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From: <sv...@va...> - 2005-10-22 12:50:51
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Author: sewardj
Date: 2005-10-22 13:50:43 +0100 (Sat, 22 Oct 2005)
New Revision: 4964
Log:
Handle a few more primops result from running Altivec code.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_translate.c 2005-10-21 12:05:05 UTC (rev 4963)
+++ trunk/memcheck/mc_translate.c 2005-10-22 12:50:43 UTC (rev 4964)
@@ -1650,7 +1650,11 @@
case Iop_ShlN16x8:
case Iop_ShlN32x4:
case Iop_ShlN64x2:
- /* Same scheme as with all other shifts. */
+ case Iop_ShlN8x16:
+ case Iop_SarN8x16:
+ /* Same scheme as with all other shifts. Note: 22 Oct 05:
+ this is wrong now, scalar shifts are done properly lazily.
+ Vector shifts should be fixed too. */
complainIfUndefined(mce, atom2);
return assignNew(mce, Ity_V128, binop(op, vatom1, atom2));
=20
@@ -1755,6 +1759,16 @@
case Iop_InterleaveHI16x8:
case Iop_InterleaveHI8x16:
return assignNew(mce, Ity_V128, binop(op, vatom1, vatom2));
+=20
+ /* Perm8x16: rearrange values in left arg using steering values
+ from right arg. So rearrange the vbits in the same way but
+ pessimise wrt steering values. */
+ case Iop_Perm8x16:
+ return mkUifUV128(
+ mce,
+ assignNew(mce, Ity_V128, binop(op, vatom1, atom2)),
+ mkPCast8x16(mce, vatom2)
+ );
=20
/* I128-bit data-steering */
case Iop_64HLto128:
@@ -2013,6 +2027,9 @@
=20
case Iop_32UtoV128:
case Iop_64UtoV128:
+ case Iop_Dup8x16:
+ case Iop_Dup16x8:
+ case Iop_Dup32x4:
return assignNew(mce, Ity_V128, unop(op, vatom));
=20
case Iop_F32toF64:=20
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