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From: <sv...@va...> - 2005-10-22 12:49:55
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Author: sewardj
Date: 2005-10-22 13:49:49 +0100 (Sat, 22 Oct 2005)
New Revision: 1424
Log:
Fill in a few missing Altivec cases:
- rename Iop_Perm to Iop_Perm8x16
- backend: handle Iop_CmpNEZ8x16
- frontend: for vperm, mask off all irrelevant parts of the steering valu=
es
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-10-22 12:46:06 UTC (rev 1423)
+++ trunk/priv/guest-ppc32/toIR.c 2005-10-22 12:49:49 UTC (rev 1424)
@@ -5977,12 +5977,18 @@
=20
case 0x2B: { // vperm (Permute, AV p218)
/* limited to two args for IR, so have to play games... */
- IRTemp a_perm =3D newTemp(Ity_V128);
- IRTemp b_perm =3D newTemp(Ity_V128);
- IRTemp mask =3D newTemp(Ity_V128);
- DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
- assign( a_perm, binop(Iop_Perm, mkexpr(vA), mkexpr(vC)) );
- assign( b_perm, binop(Iop_Perm, mkexpr(vB), mkexpr(vC)) );
+ IRTemp a_perm =3D newTemp(Ity_V128);
+ IRTemp b_perm =3D newTemp(Ity_V128);
+ IRTemp mask =3D newTemp(Ity_V128);
+ IRTemp vC_andF =3D newTemp(Ity_V128);
+ DIP("vperm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr)=
;
+ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
+ IR specifies, and also to hide irrelevant bits from
+ memcheck */
+ assign( vC_andF, binop(Iop_AndV128, mkexpr(vC),=20
+ unop(Iop_Dup8x16, mkU8(0xF))) =
);
+ assign( a_perm, binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) )=
;
+ assign( b_perm, binop(Iop_Perm8x16, mkexpr(vB), mkexpr(vC_andF)) )=
;
// mask[i8] =3D (vC[i8]_4 =3D=3D 1) ? 0xFF : 0x0
assign( mask, binop(Iop_SarN8x16,
binop(Iop_ShlN8x16, mkexpr(vC), mkU8(3)),
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-10-22 12:46:06 UTC (rev 1423)
+++ trunk/priv/host-ppc32/hdefs.c 2005-10-22 12:49:49 UTC (rev 1424)
@@ -1608,9 +1608,17 @@
addHRegUse(u, HRmRead, i->Pin.AvUnary.src);
return;
case Pin_AvBinary:
- addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst);
- addHRegUse(u, HRmRead, i->Pin.AvBinary.srcL);
- addHRegUse(u, HRmRead, i->Pin.AvBinary.srcR);
+ if (i->Pin.AvBinary.op =3D=3D Pav_XOR
+ && i->Pin.AvBinary.dst =3D=3D i->Pin.AvBinary.srcL
+ && i->Pin.AvBinary.dst =3D=3D i->Pin.AvBinary.srcR) {
+ /* reg-alloc needs to understand 'xor r,r,r' as a write of r */
+ /* (as opposed to a rite of passage :-) */
+ addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst);
+ } else {
+ addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBinary.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBinary.srcR);
+ }
return;
case Pin_AvBin8x16:
addHRegUse(u, HRmWrite, i->Pin.AvBin8x16.dst);
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-10-22 12:46:06 UTC (rev 1423)
+++ trunk/priv/host-ppc32/isel.c 2005-10-22 12:49:49 UTC (rev 1424)
@@ -2999,7 +2999,15 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_CmpNEZ8x16:
+ case Iop_CmpNEZ8x16: {
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg zero =3D newVRegV(env);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBinary(Pav_XOR, zero, zero, zero));
+ addInstr(env, PPC32Instr_AvBin8x16(Pav_CMPEQU, dst, arg, zero))=
;
+ addInstr(env, PPC32Instr_AvUnary(Pav_NOT, dst, dst));
+ return dst;
+ }
//.. case Iop_CmpNEZ16x8: {
//.. /* We can use SSE2 instructions for this. */
//.. HReg arg;
@@ -3433,7 +3441,7 @@
return dst;
}
=20
- case Iop_Perm: {
+ case Iop_Perm8x16: {
HReg dst =3D newVRegV(env);
HReg v_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg v_ctl =3D iselVecExpr(env, e->Iex.Binop.arg2);
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-10-22 12:46:06 UTC (rev 1423)
+++ trunk/priv/ir/irdefs.c 2005-10-22 12:49:49 UTC (rev 1424)
@@ -519,7 +519,7 @@
case Iop_InterleaveLO32x4: vex_printf("InterleaveLO32x4"); return;
case Iop_InterleaveLO64x2: vex_printf("InterleaveLO64x2"); return;
=20
- case Iop_Perm: vex_printf("Perm"); return;
+ case Iop_Perm8x16: vex_printf("Perm8x16"); return;
=20
default: vpanic("ppIROp(1)");
}
@@ -1574,7 +1574,7 @@
case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2:
case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8:=20
case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2:
- case Iop_Perm:
+ case Iop_Perm8x16:
BINARY(Ity_V128, Ity_V128,Ity_V128);
=20
case Iop_NotV128:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-10-22 12:46:06 UTC (rev 1423)
+++ trunk/pub/libvex_ir.h 2005-10-22 12:49:49 UTC (rev 1424)
@@ -597,8 +597,11 @@
Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4,
=20
/* PERMUTING -- copy src bytes to dst,
- as indexed by control vector bytes: dst[i] =3D src[ ctl[i] ] */
- Iop_Perm
+ as indexed by control vector bytes:
+ for i in 0 .. 15 . result[i] =3D argL[ argR[i] ]=20
+ argR[i] values may only be in the range 0 .. 15, else behaviour
+ is undefined. */
+ Iop_Perm8x16
}
IROp;
=20
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