|
From: <sv...@va...> - 2005-10-12 12:53:28
|
Author: sewardj
Date: 2005-10-12 13:53:20 +0100 (Wed, 12 Oct 2005)
New Revision: 4911
Log:
Build fixes for gcc-2.96. The system now builds and regtests with the
default gcc-2.96 on Red Hat 7.3.
Modified:
trunk/coregrind/m_translate.c
trunk/memcheck/mac_leakcheck.c
trunk/memcheck/mc_main.c
trunk/none/tests/mremap2.c
Modified: trunk/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_translate.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/coregrind/m_translate.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -68,43 +68,44 @@
LibVEX_default_VexArchInfo(vai);
=20
#if defined(VGA_x86)
- Bool have_sse1, have_sse2;
- UInt eax, ebx, ecx, edx;
+ { Bool have_sse1, have_sse2;
+ UInt eax, ebx, ecx, edx;
=20
- if (!VG_(has_cpuid)())
- /* we can't do cpuid at all. Give up. */
- return False;
+ if (!VG_(has_cpuid)())
+ /* we can't do cpuid at all. Give up. */
+ return False;
=20
- VG_(cpuid)(0, &eax, &ebx, &ecx, &edx);
- if (eax < 1)
- /* we can't ask for cpuid(x) for x > 0. Give up. */
- return False;
+ VG_(cpuid)(0, &eax, &ebx, &ecx, &edx);
+ if (eax < 1)
+ /* we can't ask for cpuid(x) for x > 0. Give up. */
+ return False;
=20
- /* get capabilities bits into edx */
- VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
+ /* get capabilities bits into edx */
+ VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
=20
- have_sse1 =3D (edx & (1<<25)) !=3D 0; /* True =3D> have sse insns */
- have_sse2 =3D (edx & (1<<26)) !=3D 0; /* True =3D> have sse2 insns */
+ have_sse1 =3D (edx & (1<<25)) !=3D 0; /* True =3D> have sse insns *=
/
+ have_sse2 =3D (edx & (1<<26)) !=3D 0; /* True =3D> have sse2 insns =
*/
=20
- VG_(have_mxcsr_x86) =3D 1;
+ VG_(have_mxcsr_x86) =3D 1;
=20
- if (have_sse2 && have_sse1) {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse2;
- return True;
- }
+ if (have_sse2 && have_sse1) {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse2;
+ return True;
+ }
=20
- if (have_sse1) {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse1;
- return True;
- }
+ if (have_sse1) {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse1;
+ return True;
+ }
=20
- {
- *vex_arch =3D VexArchX86;
- vai->subarch =3D VexSubArchX86_sse0;
- VG_(have_mxcsr_x86) =3D 0;
- return True;
+ {
+ *vex_arch =3D VexArchX86;
+ vai->subarch =3D VexSubArchX86_sse0;
+ VG_(have_mxcsr_x86) =3D 0;
+ return True;
+ }
}
=20
#elif defined(VGA_amd64)
Modified: trunk/memcheck/mac_leakcheck.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mac_leakcheck.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/memcheck/mac_leakcheck.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -83,7 +83,7 @@
static Addr* get_seg_starts ( /*OUT*/Int* n_acquired )
{
Addr* starts;
- Int n_starts, r;
+ Int n_starts, r =3D 0;
=20
n_starts =3D 1;
while (True) {
Modified: trunk/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_main.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/memcheck/mc_main.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -558,6 +558,11 @@
UWord example_a_bit,
UWord example_v_bit )
{
+ UWord a, vbits8, abits8, vbits32, v_off, a_off;
+ SecMap* sm;
+ SecMap** binder;
+ SecMap* example_dsm;
+
PROF_EVENT(150, "set_address_range_perms");
=20
/* Check the permissions make sense. */
@@ -580,35 +585,32 @@
}
}
=20
- UWord a =3D (UWord)aA;
+ a =3D (UWord)aA;
=20
# if VG_DEBUG_MEMORY >=3D 2
=20
/*------------------ debug-only case ------------------ */
- SizeT i;
+ { SizeT i;
=20
- UWord example_vbyte =3D BIT_TO_BYTE(example_v_bit);
+ UWord example_vbyte =3D BIT_TO_BYTE(example_v_bit);
=20
- tl_assert(sizeof(SizeT) =3D=3D sizeof(Addr));
+ tl_assert(sizeof(SizeT) =3D=3D sizeof(Addr));
=20
- if (0 && len >=3D 4096)
- VG_(printf)("s_a_r_p(0x%llx, %d, %d,%d)\n",=20
- (ULong)a, len, example_a_bit, example_v_bit);
+ if (0 && len >=3D 4096)
+ VG_(printf)("s_a_r_p(0x%llx, %d, %d,%d)\n",=20
+ (ULong)a, len, example_a_bit, example_v_bit);
=20
- if (len =3D=3D 0)
- return;
+ if (len =3D=3D 0)
+ return;
=20
- for (i =3D 0; i < len; i++) {
- set_abit_and_vbyte(a+i, example_a_bit, example_vbyte);
+ for (i =3D 0; i < len; i++) {
+ set_abit_and_vbyte(a+i, example_a_bit, example_vbyte);
+ }
}
=20
# else
=20
/*------------------ standard handling ------------------ */
- UWord vbits8, abits8, vbits32, v_off, a_off;
- SecMap* sm;
- SecMap** binder;
- SecMap* example_dsm;
=20
/* Decide on the distinguished secondary that we might want
to use (part of the space-compression scheme). */
@@ -778,6 +780,9 @@
static __inline__
void make_aligned_word32_writable ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off, mask;
+ SecMap* sm;
+
PROF_EVENT(300, "make_aligned_word32_writable");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -790,8 +795,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -799,14 +804,14 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the new area as uninitialised. */
((UInt*)(sm->vbyte))[v_off >> 2] =3D VGM_WORD32_INVALID;
=20
- UWord mask =3D 0x0F;
+ mask =3D 0x0F;
mask <<=3D (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */
/* mask now contains 1s where we wish to make address bits valid
(0s). */
@@ -818,6 +823,9 @@
static __inline__
void make_aligned_word32_noaccess ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off, mask;
+ SecMap* sm;
+
PROF_EVENT(310, "make_aligned_word32_noaccess");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -830,8 +838,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -839,15 +847,15 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the abandoned data as uninitialised. Probably not
necessary, but still .. */
((UInt*)(sm->vbyte))[v_off >> 2] =3D VGM_WORD32_INVALID;
=20
- UWord mask =3D 0x0F;
+ mask =3D 0x0F;
mask <<=3D (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */
/* mask now contains 1s where we wish to make address bits invalid
(1s). */
@@ -860,6 +868,9 @@
static __inline__
void make_aligned_word64_writable ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off;
+ SecMap* sm;
+
PROF_EVENT(320, "make_aligned_word64_writable");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -872,8 +883,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -881,9 +892,9 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the new area as uninitialised. */
((ULong*)(sm->vbyte))[v_off >> 3] =3D VGM_WORD64_INVALID;
@@ -897,6 +908,9 @@
static __inline__
void make_aligned_word64_noaccess ( Addr aA )
{
+ UWord a, sec_no, v_off, a_off;
+ SecMap* sm;
+
PROF_EVENT(330, "make_aligned_word64_noaccess");
=20
# if VG_DEBUG_MEMORY >=3D 2
@@ -909,8 +923,8 @@
return;
}
=20
- UWord a =3D (UWord)aA;
- UWord sec_no =3D (UWord)(a >> 16);
+ a =3D (UWord)aA;
+ sec_no =3D (UWord)(a >> 16);
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
@@ -918,9 +932,9 @@
if (EXPECTED_NOT_TAKEN(is_distinguished_sm(primary_map[sec_no])))
primary_map[sec_no] =3D copy_for_writing(primary_map[sec_no]);
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
=20
/* Paint the abandoned data as uninitialised. Probably not
necessary, but still .. */
@@ -1497,13 +1511,16 @@
VG_REGPARM(1) \
ULong nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(200, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return mc_LOADVn_slow( aA, 8, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1514,15 +1531,15 @@
return (UWord)mc_LOADVn_slow( aA, 8, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
\
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly: a is suitably aligned, */ \
@@ -1544,13 +1561,16 @@
VG_REGPARM(1) \
void nAME ( Addr aA, ULong vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(210, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 8, vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-8) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1562,15 +1582,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
\
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
&& abits =3D=3D VGM_BYTE_VALID)) { \
@@ -1595,13 +1615,16 @@
VG_REGPARM(1) \
UWord nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(220, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return (UWord)mc_LOADVn_slow( aA, 4, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1612,15 +1635,15 @@
return (UWord)mc_LOADVn_slow( aA, 4, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
abits >>=3D (a & 4); \
abits &=3D 15; \
if (EXPECTED_TAKEN(abits =3D=3D VGM_NIBBLE_VALID)) { \
@@ -1650,13 +1673,16 @@
VG_REGPARM(2) \
void nAME ( Addr aA, UWord vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; =
\
+ SecMap* sm; =
\
+ =
\
PROF_EVENT(230, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 4, (ULong)vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-4) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1668,15 +1694,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
abits >>=3D (a & 4); \
abits &=3D 15; \
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
@@ -1702,13 +1728,16 @@
VG_REGPARM(1) \
UWord nAME ( Addr aA ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; \
+ SecMap* sm; \
+ \
PROF_EVENT(240, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
return (UWord)mc_LOADVn_slow( aA, 2, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1719,15 +1748,15 @@
return (UWord)mc_LOADVn_slow( aA, 2, iS_BIGENDIAN ); \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly: a is mapped, and the */ \
/* entire word32 it lives in is addressible. */ \
@@ -1753,13 +1782,16 @@
VG_REGPARM(2) \
void nAME ( Addr aA, UWord vbytes ) \
{ \
+ UWord mask, a, sec_no, v_off, a_off, abits; \
+ SecMap* sm; \
+ \
PROF_EVENT(250, #nAME); \
\
if (VG_DEBUG_MEMORY >=3D 2) \
mc_STOREVn_slow( aA, 2, (ULong)vbytes, iS_BIGENDIAN ); \
\
- const UWord mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
- UWord a =3D (UWord)aA; \
+ mask =3D ~((0x10000-2) | ((N_PRIMARY_MAP-1) << 16)); \
+ a =3D (UWord)aA; \
\
/* If any part of 'a' indicated by the mask is 1, either */ \
/* 'a' is not naturally aligned, or 'a' exceeds the range */ \
@@ -1771,15 +1803,15 @@
return; \
} \
\
- UWord sec_no =3D (UWord)(a >> 16); \
+ sec_no =3D (UWord)(a >> 16); \
\
if (VG_DEBUG_MEMORY >=3D 1) \
tl_assert(sec_no < N_PRIMARY_MAP); \
\
- SecMap* sm =3D primary_map[sec_no]; \
- UWord v_off =3D a & 0xFFFF; \
- UWord a_off =3D v_off >> 3; \
- UWord abits =3D (UWord)(sm->abits[a_off]); \
+ sm =3D primary_map[sec_no]; \
+ v_off =3D a & 0xFFFF; \
+ a_off =3D v_off >> 3; \
+ abits =3D (UWord)(sm->abits[a_off]); \
if (EXPECTED_TAKEN(!is_distinguished_sm(sm) \
&& abits =3D=3D VGM_BYTE_VALID)) { \
/* Handle common case quickly. */ \
@@ -1802,14 +1834,17 @@
VG_REGPARM(1)
UWord MC_(helperc_LOADV1) ( Addr aA )
{
+ UWord mask, a, sec_no, v_off, a_off, abits;
+ SecMap* sm;
+
PROF_EVENT(260, "helperc_LOADV1");
=20
# if VG_DEBUG_MEMORY >=3D 2
return (UWord)mc_LOADVn_slow( aA, 1, False/*irrelevant*/ );
# else
=20
- const UWord mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
- UWord a =3D (UWord)aA;
+ mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
+ a =3D (UWord)aA;
=20
/* If any part of 'a' indicated by the mask is 1, it means 'a'
exceeds the range covered by the primary map. In which case we
@@ -1819,16 +1854,16 @@
return (UWord)mc_LOADVn_slow( aA, 1, False/*irrelevant*/ );
}
=20
- UWord sec_no =3D (UWord)(a >> 16);
+ sec_no =3D (UWord)(a >> 16);
=20
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
- UWord abits =3D (UWord)(sm->abits[a_off]);
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
+ abits =3D (UWord)(sm->abits[a_off]);
if (EXPECTED_TAKEN(abits =3D=3D VGM_BYTE_VALID)) {
/* Handle common case quickly: a is mapped, and the entire
word32 it lives in is addressible. */
@@ -1850,14 +1885,17 @@
VG_REGPARM(2)
void MC_(helperc_STOREV1) ( Addr aA, UWord vbyte )
{
+ UWord mask, a, sec_no, v_off, a_off, abits;
+ SecMap* sm;
+
PROF_EVENT(270, "helperc_STOREV1");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 1, (ULong)vbyte, False/*irrelevant*/ );
# else
=20
- const UWord mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
- UWord a =3D (UWord)aA;
+ mask =3D ~((0x10000-1) | ((N_PRIMARY_MAP-1) << 16));
+ a =3D (UWord)aA;
/* If any part of 'a' indicated by the mask is 1, it means 'a'
exceeds the range covered by the primary map. In which case we
defer to the slow-path case. */
@@ -1867,16 +1905,16 @@
return;
}
=20
- UWord sec_no =3D (UWord)(a >> 16);
+ sec_no =3D (UWord)(a >> 16);
=20
# if VG_DEBUG_MEMORY >=3D 1
tl_assert(sec_no < N_PRIMARY_MAP);
# endif
=20
- SecMap* sm =3D primary_map[sec_no];
- UWord v_off =3D a & 0xFFFF;
- UWord a_off =3D v_off >> 3;
- UWord abits =3D (UWord)(sm->abits[a_off]);
+ sm =3D primary_map[sec_no];
+ v_off =3D a & 0xFFFF;
+ a_off =3D v_off >> 3;
+ abits =3D (UWord)(sm->abits[a_off]);
if (EXPECTED_TAKEN(!is_distinguished_sm(sm)=20
&& abits =3D=3D VGM_BYTE_VALID)) {
/* Handle common case quickly: a is mapped, the entire word32 it
@@ -2505,11 +2543,11 @@
=20
static void mc_fini ( Int exitcode )
{
- MAC_(common_fini)( mc_detect_memory_leaks );
-
Int i, n_accessible_dist;
SecMap* sm;
=20
+ MAC_(common_fini)( mc_detect_memory_leaks );
+
if (VG_(clo_verbosity) > 1) {
VG_(message)(Vg_DebugMsg,
" memcheck: sanity checks: %d cheap, %d expensive",
Modified: trunk/none/tests/mremap2.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/mremap2.c 2005-10-12 11:30:43 UTC (rev 4910)
+++ trunk/none/tests/mremap2.c 2005-10-12 12:53:20 UTC (rev 4911)
@@ -100,7 +100,6 @@
int main ( void )
{
int alocal, maymove, fixed, nsi, dstpossible;
- dst_impossible =3D (char*)(&alocal) + 500 * 1000 * 1000;
int newsizes[6] =3D { 19, 20, 21, 29, 30, 31 };
=20
char* tidythis =3D NULL;
@@ -108,6 +107,8 @@
int firsttime =3D 1;
char buf[100];
=20
+ dst_impossible =3D (char*)(&alocal) + 500 * 1000 * 1000;
+
PAGE =3D sysconf(_SC_PAGESIZE);
=20
for (maymove =3D 0; maymove <=3D 1 ; maymove++) {
@@ -116,14 +117,13 @@
for (nsi =3D 0; nsi < 6; nsi++) {
for (dstpossible =3D 0; dstpossible <=3D 1; dstpossible++) {
=20
+ char* r;
int newsize =3D newsizes[nsi] * PAGE;
int flags =3D (maymove ? MREMAP_MAYMOVE : 0) |
(fixed ? MREMAP_FIXED : 0);
dst =3D dstpossible ? try_dst : dst_impossible;
src =3D setup( tidythis, tidylen );
=20
- char* r;
-
if (firsttime) {
printf("dst_possible =3D %p\n", try_dst );
printf("dst_impossible =3D %p\n", dst_impossible );
|