|
From: <sv...@va...> - 2005-10-12 11:34:37
|
Author: sewardj
Date: 2005-10-12 12:34:33 +0100 (Wed, 12 Oct 2005)
New Revision: 1419
Log:
Build fixes for gcc-2.96 (which does not allow declarations after the
first statement in a block).
Modified:
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -104,19 +104,23 @@
void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
UInt vD_idx, UInt sh, UInt dirn )
{
- vassert( vD_idx <=3D 31 );
- vassert( sh <=3D 15 );
- vassert( dirn <=3D 1 );
+ static
UChar ref[32] =3D { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F };
+ U128* pU128_src;
+ U128* pU128_dst;
+
+ vassert( vD_idx <=3D 31 );
+ vassert( sh <=3D 15 );
+ vassert( dirn <=3D 1 );
if (dirn =3D=3D 1) /* shift right */
- sh =3D 16-sh;
+ sh =3D 16-sh;
/* else shift left */
=20
- U128* pU128_src =3D (U128*)&ref[sh];
- U128* pU128_dst =3D &gst->guest_VR0 + (vD_idx*sizeof(gst->guest_VR0));
+ pU128_src =3D (U128*)&ref[sh];
+ pU128_dst =3D &gst->guest_VR0 + (vD_idx*sizeof(gst->guest_VR0));
=20
(*pU128_dst)[0] =3D (*pU128_src)[0];
(*pU128_dst)[1] =3D (*pU128_src)[1];
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/guest-ppc32/toIR.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -788,11 +788,12 @@
bit. Indexing as per getCRbit. */
static void putCRbit ( UInt bi, IRExpr* bit )
{
+ UInt n, off;
IRExpr* safe;
vassert(typeOfIRExpr(irbb->tyenv,bit) =3D=3D Ity_I32);
safe =3D binop(Iop_And32, bit, mkU32(1));
- UInt n =3D bi / 4;
- UInt off =3D bi % 4;
+ n =3D bi / 4;
+ off =3D bi % 4;
vassert(bi < 32);
if (off =3D=3D 3) {
/* This is the SO bit for this CR field */
@@ -1160,8 +1161,6 @@
/* Set the CR6 flags following an AltiVec compare operation. */
static void set_AV_CR6 ( IRExpr* result )
{
- vassert(typeOfIRExpr(irbb->tyenv,result) =3D=3D Ity_V128);
-
/* CR6[0:3] =3D {all_ones, 0, all_zeros, 0}
all_ones =3D (v[0] && v[1] && v[2] && v[3])
all_zeros =3D ~(v[0] || v[1] || v[2] || v[3])
@@ -1172,6 +1171,9 @@
IRTemp v3 =3D newTemp(Ity_V128);
IRTemp rOnes =3D newTemp(Ity_I8);
IRTemp rZeros =3D newTemp(Ity_I8);
+
+ vassert(typeOfIRExpr(irbb->tyenv,result) =3D=3D Ity_V128);
+
assign( v0, result );
assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
@@ -3274,9 +3276,7 @@
UChar flag_Rc =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
IRTemp sh_amt =3D newTemp(Ity_I8);
- IRTemp rb_b5 =3D newTemp(Ity_I32);
IRTemp Rs =3D newTemp(Ity_I32);
- IRTemp Rs_sh =3D newTemp(Ity_I32);
IRTemp Ra =3D newTemp(Ity_I32);
IRTemp Rb =3D newTemp(Ity_I32);
IRTemp sh_amt32 =3D newTemp(Ity_I32);
@@ -4924,12 +4924,12 @@
break;
=20
case 0x644: { // mtvscr (Move to VSCR, AV p130)
+ IRTemp vB =3D newTemp(Ity_V128);
if (vD_addr !=3D 0 || vA_addr !=3D 0) {
vex_printf("dis_av_procctl(PPC32)(opc2,dst)\n");
return False;
}
DIP("mtvscr v%d\n", vB_addr);
- IRTemp vB =3D newTemp(Ity_V128);
assign( vB, getVReg(vB_addr));
putSPR( PPC32_SPR_VSCR, unop(Iop_V128to32, mkexpr(vB)) );=20
break;
@@ -4966,13 +4966,13 @@
switch (opc2) {
=20
case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
- DIP("lvsl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
IRExpr** args =3D mkIRExprVec_3(mkU32(vD_addr), mkexpr(EA), mkU32(=
0));
IRDirty* d =3D unsafeIRDirty_0_N (
0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
&ppc32g_dirtyhelper_LVS,
args );
+ DIP("lvsl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
/* declare guest state effects */
d->needsBBP =3D True;
d->nFxState =3D 1;
@@ -4985,13 +4985,13 @@
break;
}
case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
- DIP("lvsr v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
IRExpr** args =3D mkIRExprVec_3(mkU32(vD_addr), mkexpr(EA), mkU32(=
1));
IRDirty* d =3D unsafeIRDirty_0_N (
0/*regparms*/,=20
"ppc32g_dirtyhelper_LVS",
&ppc32g_dirtyhelper_LVS,
args );
+ DIP("lvsr v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
/* declare guest state effects */
d->needsBBP =3D True;
d->nFxState =3D 1;
@@ -5071,9 +5071,9 @@
=20
switch (opc2) {
case 0x087: { // stvebx (Store Vector Byte Indexed, AV p131)
- DIP("stvebx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
IRTemp eb =3D newTemp(Ity_I8);
IRTemp idx =3D newTemp(Ity_I8);
+ DIP("stvebx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
assign( eb, binop(Iop_And8, mkU8(0xF),
unop(Iop_32to8, mkexpr(EA) )) );
assign( idx, binop(Iop_Shl8, binop(Iop_Sub8, mkU8(15), mkexpr(eb))=
,
@@ -5098,9 +5098,9 @@
break;
}
case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133)
- DIP("stvewx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
IRTemp eb =3D newTemp(Ity_I8);
IRTemp idx =3D newTemp(Ity_I8);
+ DIP("stvewx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
assign( EA_aligned, binop( Iop_And32, mkexpr(EA), mkU32(0xFFFFFFFC=
) ));
assign( eb, binop(Iop_And8, mkU8(0xF),
unop(Iop_32to8, mkexpr(EA_aligned) )) );
@@ -5602,6 +5602,7 @@
UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
UChar opc2 =3D toUChar((theInstr >> 0) & 0x3F); /* theInstr[0:5]=
*/
=20
+ IRTemp zeros =3D newTemp(Ity_V128);
IRTemp vA =3D newTemp(Ity_V128);
IRTemp vB =3D newTemp(Ity_V128);
IRTemp vC =3D newTemp(Ity_V128);
@@ -5614,13 +5615,11 @@
return False;
}
=20
- IRTemp zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
=20
switch (opc2) {
/* Multiply-Add */
case 0x20: { // vmhaddshs (Multiply High, Add Signed HW Saturate, AV =
p185)
- DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
IRTemp cLo =3D newTemp(Ity_V128);
@@ -5630,6 +5629,7 @@
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
IRTemp cSigns =3D newTemp(Ity_V128);
+ DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
@@ -5654,7 +5654,6 @@
break;
}
case 0x21: { // vmhraddshs (Multiply High Round, Add Signed HW Satura=
te, AV p186)
- DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
IRTemp zKonst =3D newTemp(Ity_V128);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
@@ -5665,6 +5664,7 @@
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
IRTemp cSigns =3D newTemp(Ity_V128);
+ DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
@@ -5695,7 +5695,6 @@
break;
}
case 0x22: { // vmladduhm (Multiply Low, Add Unsigned HW Modulo, AV p=
194)
- DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
IRTemp aLo =3D newTemp(Ity_V128);
IRTemp bLo =3D newTemp(Ity_V128);
IRTemp cLo =3D newTemp(Ity_V128);
@@ -5704,6 +5703,7 @@
IRTemp bHi =3D newTemp(Ity_V128);
IRTemp cHi =3D newTemp(Ity_V128);
IRTemp zHi =3D newTemp(Ity_V128);
+ DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA)=
) );
assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB)=
) );
assign( cLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vC)=
) );
@@ -5723,7 +5723,6 @@
=20
/* Multiply-Sum */
case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
- DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp zKonst =3D newTemp(Ity_V128);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
@@ -5731,6 +5730,7 @@
IRTemp odd_even =3D newTemp(Ity_V128);
IRTemp even_odd =3D newTemp(Ity_V128);
IRTemp even_even =3D newTemp(Ity_V128);
+ DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo16Ux8, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi16Ux8, mkexpr(vA), mkexpr(vB)) );
/* zKonst just used to separate the lanes out */
@@ -5754,9 +5754,9 @@
return False;
=20
case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205)
- DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
+ DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo32Ux4, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi32Ux4, mkexpr(vA), mkexpr(vB)) );
putVReg( vD_addr,
@@ -5770,9 +5770,9 @@
return False;
=20
case 0x28: { // vmsumshm (Multiply Sum Signed HW Modulo, AV p202)
- DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
IRTemp odd =3D newTemp(Ity_V128);
IRTemp even =3D newTemp(Ity_V128);
+ DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
assign( odd, binop(Iop_MulLo32Sx4, mkexpr(vA), mkexpr(vB)) );
assign( even, binop(Iop_MulHi32Sx4, mkexpr(vA), mkexpr(vB)) );
putVReg( vD_addr,
@@ -5848,8 +5848,8 @@
break;
=20
case 0x1C4: { // vsl (Shift Left, AV p239)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x7),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5858,8 +5858,8 @@
break;
}
case 0x40C: { // vslo (Shift Left by Octet, AV p243)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x78),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5886,8 +5886,8 @@
break;
=20
case 0x2C4: { // vsr (Shift Right, AV p251)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x7),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5911,8 +5911,8 @@
break;
=20
case 0x44C: { // vsro (Shift Right by Octet, AV p258)
+ IRTemp sh =3D newTemp(Ity_I8);
DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- IRTemp sh =3D newTemp(Ity_I8);
assign( sh, binop(Iop_And8, mkU8(0x78),
unop(Iop_32to8,
unop(Iop_V128to32, mkexpr(vB)))) );
@@ -5968,11 +5968,11 @@
return True;
=20
case 0x2B: { // vperm (Permute, AV p218)
- DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
/* limited to two args for IR, so have to play games... */
IRTemp a_perm =3D newTemp(Ity_V128);
IRTemp b_perm =3D newTemp(Ity_V128);
IRTemp mask =3D newTemp(Ity_V128);
+ DIP("vperma v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr=
);
assign( a_perm, binop(Iop_Perm, mkexpr(vA), mkexpr(vC)) );
assign( b_perm, binop(Iop_Perm, mkexpr(vB), mkexpr(vC)) );
// mask[i8] =3D (vC[i8]_4 =3D=3D 1) ? 0xFF : 0x0
@@ -6049,26 +6049,26 @@
=20
/* Splat */
case 0x20C: { // vspltb (Splat Byte, AV p245)
- DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
/* vD =3D Dup8x16( vB[UIMM_5] ) */
UChar sh_uimm =3D (15-UIMM_5)*8;
+ DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
putVReg( vD_addr, unop(Iop_Dup8x16,
unop(Iop_32to8, unop(Iop_V128to32,=20
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
break;
}
case 0x24C: { // vsplth (Splat Half Word, AV p246)
+ UChar sh_uimm =3D (7-UIMM_5)*16;
DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
- UChar sh_uimm =3D (7-UIMM_5)*16;
putVReg( vD_addr, unop(Iop_Dup16x8,
unop(Iop_32to16, unop(Iop_V128to32,=20
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) );
break;
}
case 0x28C: { // vspltw (Splat Word, AV p250)
- DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
/* vD =3D Dup32x4( vB[UIMM_5] ) */
UChar sh_uimm =3D (3-UIMM_5)*32;
+ DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
putVReg( vD_addr, unop(Iop_Dup32x4,
unop(Iop_V128to32,
binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm)))) );
@@ -6107,6 +6107,8 @@
UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
=20
+ IRTemp signs =3D IRTemp_INVALID;
+ IRTemp zeros =3D IRTemp_INVALID;
IRTemp vA =3D newTemp(Ity_V128);
IRTemp vB =3D newTemp(Ity_V128);
assign( vA, getVReg(vA_addr));
@@ -6142,12 +6144,12 @@
return True;
=20
case 0x10E: { // vpkshus (Pack Signed HW Unsigned Saturate, AV p221)
- DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
// This insn does a signed->unsigned saturating conversion.
// Conversion done here, then uses unsigned->unsigned vpk insn:
// =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 15) )
IRTemp vA_tmp =3D newTemp(Ity_V128);
IRTemp vB_tmp =3D newTemp(Ity_V128);
+ DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
unop(Iop_NotV128,
binop(Iop_SarN16x8,
@@ -6162,12 +6164,12 @@
return True;
}
case 0x14E: { // vpkswus (Pack Signed W Unsigned Saturate, AV p223)
- DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
// This insn does a signed->unsigned saturating conversion.
// Conversion done here, then uses unsigned->unsigned vpk insn:
// =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 31) )
IRTemp vA_tmp =3D newTemp(Ity_V128);
IRTemp vB_tmp =3D newTemp(Ity_V128);
+ DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
unop(Iop_NotV128,
binop(Iop_SarN32x4,
@@ -6194,7 +6196,6 @@
return True;
=20
case 0x30E: { // vpkpx (Pack Pixel, AV p219)
- DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
/* CAB: Worth a new primop? */
/* Using shifts to compact pixel elements, then packing them them =
*/
IRTemp a1 =3D newTemp(Ity_V128);
@@ -6205,6 +6206,7 @@
IRTemp b2 =3D newTemp(Ity_V128);
IRTemp b3 =3D newTemp(Ity_V128);
IRTemp b_tmp =3D newTemp(Ity_V128);
+ DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
assign( a1, binop(Iop_ShlN16x8,
binop(Iop_ShrN32x4, mkexpr(vA), mkU8(19)),
mkU8(10)) );
@@ -6244,8 +6246,8 @@
return False;
}
=20
- IRTemp signs =3D newTemp(Ity_V128);
- IRTemp zeros =3D newTemp(Ity_V128);
+ signs =3D newTemp(Ity_V128);
+ zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
=20
switch (opc2) {
@@ -6275,7 +6277,6 @@
break;
}
case 0x34E: { // vupkhpx (Unpack High Pixel16, AV p276)
- DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
/* CAB: Worth a new primop? */
/* Using shifts to isolate pixel elements, then expanding them */
IRTemp z0 =3D newTemp(Ity_V128);
@@ -6284,6 +6285,7 @@
IRTemp z2 =3D newTemp(Ity_V128);
IRTemp z3 =3D newTemp(Ity_V128);
IRTemp z23 =3D newTemp(Ity_V128);
+ DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
assign( z0, binop(Iop_ShlN16x8,
binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
mkU8(8)) );
@@ -6308,7 +6310,6 @@
break;
}
case 0x3CE: { // vupklpx (Unpack Low Pixel16, AV p279)
- DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
/* identical to vupkhpx, except interleaving LO */
IRTemp z0 =3D newTemp(Ity_V128);
IRTemp z1 =3D newTemp(Ity_V128);
@@ -6316,6 +6317,7 @@
IRTemp z2 =3D newTemp(Ity_V128);
IRTemp z3 =3D newTemp(Ity_V128);
IRTemp z23 =3D newTemp(Ity_V128);
+ DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
assign( z0, binop(Iop_ShlN16x8,
binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
mkU8(8)) );
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/host-ppc32/hdefs.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -1313,12 +1313,13 @@
return;
=20
case Pin_AvLdSt: {
- UChar sz =3D i->Pin.AvLdSt.sz;
+ UChar sz =3D i->Pin.AvLdSt.sz;
+ HChar* str_size;
if (i->Pin.AvLdSt.addr->tag =3D=3D Pam_IR) {
ppLoadImm(hregPPC32_GPR30(), i->Pin.AvLdSt.addr->Pam.RR.index);
vex_printf(" ; ");
}
- char* str_size =3D sz=3D=3D1 ? "eb" : sz=3D=3D2 ? "eh" : sz=3D=3D4=
? "ew" : "";
+ str_size =3D sz=3D=3D1 ? "eb" : sz=3D=3D2 ? "eh" : sz=3D=3D4 ? "ew=
" : "";
if (i->Pin.AvLdSt.isLoad)
vex_printf("lv%sx ", str_size);
else
@@ -3121,18 +3122,20 @@
vassert(sz =3D=3D 8 || sz =3D=3D 16 || sz =3D=3D 32);
=20
if (i->Pin.AvSplat.src->tag =3D=3D Pvi_Imm) {
+ Char simm5;
opc2 =3D (sz =3D=3D 8) ? 780 : (sz =3D=3D 16) ? 844 : 908; //=
8,16,32
/* expects 5-bit-signed-imm */
- Char simm5 =3D i->Pin.AvSplat.src->Pvi.Imm5s;
+ simm5 =3D i->Pin.AvSplat.src->Pvi.Imm5s;
vassert(simm5 >=3D -16 && simm5 <=3D 15);
simm5 =3D simm5 & 0x1F;
p =3D mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2 );
}
else { // Pri_Reg
+ UInt lowest_lane;
opc2 =3D (sz =3D=3D 8) ? 524 : (sz =3D=3D 16) ? 588 : 652; // =
8,16,32
vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) =3D=3D HRcVec128=
);
v_src =3D vregNo(i->Pin.AvSplat.src->Pvi.Reg);
- UInt lowest_lane =3D (128/sz)-1;
+ lowest_lane =3D (128/sz)-1;
p =3D mkFormVX( p, 4, v_dst, lowest_lane, v_src, opc2 );
}
goto done;
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-10-08 19:58:48 UTC (rev 1418)
+++ trunk/priv/host-ppc32/isel.c 2005-10-12 11:34:33 UTC (rev 1419)
@@ -761,13 +761,13 @@
*/
static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e )
{
+ HReg r_src;
HReg dst =3D newVRegV(env);
PPC32RI* ri =3D iselIntExpr_RI(env, e);
IRType ty =3D typeOfIRExpr(env->type_env,e);
UInt sz =3D (ty =3D=3D Ity_I8) ? 8 : (ty =3D=3D Ity_I16) ? 16 : =
32;
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32);
=20
- HReg r_src;
/* special case: immediate */
if (ri->tag =3D=3D Pri_Imm) {
Int simm32 =3D (Int)ri->Pri.Imm;
@@ -815,13 +815,13 @@
{
/* CAB: Perhaps faster to store r_src multiple times (sz dependent=
),
and simply load the vector? */
-
+ HReg r_aligned16;
HReg v_src =3D newVRegV(env);
PPC32AMode *am_off12;
=20
sub_from_sp( env, 32 ); // Move SP down
/* Get a 16-aligned address within our stack space */
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off12 =3D PPC32AMode_IR( 12, r_aligned16);
=20
/* Store r_src in low word of 16-aligned mem */
@@ -1295,13 +1295,14 @@
}
=20
case Iop_V128to32: {
+ HReg r_aligned16;
HReg dst =3D newVRegI(env);
HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
PPC32AMode *am_off0, *am_off12;
sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16 );
am_off12 =3D PPC32AMode_IR( 12,r_aligned16 );
=20
@@ -1802,16 +1803,14 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLT32U
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32S
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32U)) {
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-
+ PPC32RH* ri2;
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
Bool syned =3D False;
if (e->Iex.Binop.op =3D=3D Iop_CmpLT32S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE32S) {
syned =3D True;
}
-
- PPC32RH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
-
+ ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
addInstr(env, PPC32Instr_Cmp32(syned,7,r1,ri2));
=20
switch (e->Iex.Binop.op) {
@@ -2428,6 +2427,7 @@
/* V128{HI}to64 */
case Iop_V128HIto64:
case Iop_V128to64: {
+ HReg r_aligned16;
Int off =3D e->Iex.Unop.op=3D=3DIop_V128HIto64 ? 0 : 8;
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
@@ -2436,7 +2436,7 @@
sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16 );
am_offHI =3D PPC32AMode_IR( off, r_aligned16 );
am_offLO =3D PPC32AMode_IR( off+4, r_aligned16 );
@@ -3086,20 +3086,21 @@
//.. }
=20
case Iop_32UtoV128: {
+ HReg r_aligned16, r_zeros;
HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
HReg dst =3D newVRegV(env);
PPC32AMode *am_off0, *am_off4, *am_off8, *am_off12;
sub_from_sp( env, 32 ); // Move SP down
=20
/* Get a quadword aligned address within our stack space */
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16);
am_off4 =3D PPC32AMode_IR( 4, r_aligned16);
am_off8 =3D PPC32AMode_IR( 8, r_aligned16);
am_off12 =3D PPC32AMode_IR( 12, r_aligned16);
=20
- /* Store zero's */
- HReg r_zeros =3D newVRegI(env);
+ /* Store zeros */
+ r_zeros =3D newVRegI(env);
addInstr(env, PPC32Instr_LI32(r_zeros, 0x0));
addInstr(env, PPC32Instr_Store( 4, am_off0, r_zeros ));
addInstr(env, PPC32Instr_Store( 4, am_off4, r_zeros ));
@@ -3170,14 +3171,14 @@
//.. }
//..=20
case Iop_64HLtoV128: {
- HReg r3, r2, r1, r0;
+ HReg r3, r2, r1, r0, r_aligned16;
PPC32AMode *am_off0, *am_off4, *am_off8, *am_off12;
HReg dst =3D newVRegV(env);
/* do this via the stack (easy, convenient, etc) */
sub_from_sp( env, 32 ); // Move SP down
=20
// get a quadword aligned address within our stack space
- HReg r_aligned16 =3D get_sp_aligned16( env );
+ r_aligned16 =3D get_sp_aligned16( env );
am_off0 =3D PPC32AMode_IR( 0, r_aligned16);
am_off4 =3D PPC32AMode_IR( 4, r_aligned16);
am_off8 =3D PPC32AMode_IR( 8, r_aligned16);
|