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From: <sv...@va...> - 2005-09-16 07:54:42
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Author: cerion
Date: 2005-09-16 08:54:40 +0100 (Fri, 16 Sep 2005)
New Revision: 1402
Log:
More AltiVec: shifts and rotates
- vrl*, vsl*, vsr*
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-16 07:53:31 UTC (rev 1401)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-16 07:54:40 UTC (rev 1402)
@@ -5645,61 +5645,73 @@
/* Rotate */
case 0x004: // vrlb (Rotate Left Integer B, AV p234)
DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x044: // vrlh (Rotate Left Integer HW, AV p235)
DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x084: // vrlw (Rotate Left Integer W, AV p236)
DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
=20
/* Shift Left */
case 0x104: // vslb (Shift Left Integer B, AV p240)
DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x144: // vslh (Shift Left Integer HW, AV p242)
DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x184: // vslw (Shift Left Integer W, AV p244)
DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
- case 0x1C4: // vsl (Shift Left, AV p239)
+ case 0x1C4: { // vsl (Shift Left, AV p239)
DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x40C: // vslo (Shift Left by Octet, AV p243)
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x7),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
+ case 0x40C: { // vslo (Shift Left by Octet, AV p243)
DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x78),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
=20
+
/* Shift Right */
case 0x204: // vsrb (Shift Right B, AV p256)
DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x244: // vsrh (Shift Right HW, AV p257)
DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x284: // vsrw (Shift Right W, AV p259)
DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x2C4: { // vsr (Shift Right, AV p251)
DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
@@ -5713,23 +5725,29 @@
}
case 0x304: // vsrab (Shift Right Algebraic B, AV p253)
DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x344: // vsrah (Shift Right Algebraic HW, AV p254)
DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x384: // vsraw (Shift Right Algebraic W, AV p255)
DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
- case 0x44C: // vsro (Shift Right by Octet, AV p258)
+ case 0x44C: { // vsro (Shift Right by Octet, AV p258)
DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x78),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
=20
default:
vex_printf("dis_av_shift(PPC32)(opc2)\n");
@@ -6054,7 +6072,6 @@
return False;
}
=20
-
IRTemp signs =3D newTemp(Ity_V128);
IRTemp zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-16 07:53:31 UTC (rev 1401)
+++ trunk/priv/host-ppc32/isel.c 2005-09-16 07:54:40 UTC (rev 1402)
@@ -3275,13 +3275,6 @@
//.. return dst;
//.. }
=20
-//.. case Iop_QNarrow32Sx4:=20
-//.. op =3D Xsse_PACKSSD; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_QNarrow16Sx8:=20
-//.. op =3D Xsse_PACKSSW; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_QNarrow16Ux8:=20
-//.. op =3D Xsse_PACKUSW; arg1isEReg =3D True; goto do_SseReRg;
-
case Iop_AndV128: op =3D Pav_AND; goto do_AvBin;
case Iop_OrV128: op =3D Pav_OR; goto do_AvBin;
case Iop_XorV128: op =3D Pav_XOR; goto do_AvBin;
@@ -3293,27 +3286,12 @@
return dst;
}
=20
-//.. case Iop_Add8x16: op =3D Xsse_ADD8; goto do_SseReRg;
-//.. case Iop_Add64x2: op =3D Xsse_ADD64; goto do_SseReRg;
-//.. case Iop_QAdd8Sx16: op =3D Xsse_QADD8S; goto do_SseReRg;
-//.. case Iop_QAdd16Sx8: op =3D Xsse_QADD16S; goto do_SseReRg;
-//.. case Iop_QAdd8Ux16: op =3D Xsse_QADD8U; goto do_SseReRg;
-//.. case Iop_QAdd16Ux8: op =3D Xsse_QADD16U; goto do_SseReRg;
-//.. case Iop_Avg8Ux16: op =3D Xsse_AVG8U; goto do_SseReRg;
-//.. case Iop_Avg16Ux8: op =3D Xsse_AVG16U; goto do_SseReRg;
-//.. case Iop_CmpEQ8x16: op =3D Xsse_CMPEQ8; goto do_SseReRg;
-//.. case Iop_CmpEQ16x8: op =3D Xsse_CMPEQ16; goto do_SseReRg;
-//.. case Iop_CmpEQ32x4: op =3D Xsse_CMPEQ32; goto do_SseReRg;
-//.. case Iop_CmpGT8Sx16: op =3D Xsse_CMPGT8S; goto do_SseReRg;
-//.. case Iop_CmpGT16Sx8: op =3D Xsse_CMPGT16S; goto do_SseReRg;
-//.. case Iop_CmpGT32Sx4: op =3D Xsse_CMPGT32S; goto do_SseReRg;
//.. case Iop_Mul16x8: op =3D Xsse_MUL16; goto do_SseReRg;
-//.. case Iop_Sub64x2: op =3D Xsse_SUB64; goto do_SseReRg;
-//.. case Iop_QSub8Sx16: op =3D Xsse_QSUB8S; goto do_SseReRg;
-//.. case Iop_QSub16Sx8: op =3D Xsse_QSUB16S; goto do_SseReRg;
-//.. case Iop_QSub8Ux16: op =3D Xsse_QSUB8U; goto do_SseReRg;
-//.. case Iop_QSub16Ux8: op =3D Xsse_QSUB16U; goto do_SseReRg;
=20
+ case Iop_Shl8x16: op =3D Pav_SHL; goto do_AvBin8x16;
+ case Iop_Shr8x16: op =3D Pav_SHR; goto do_AvBin8x16;
+ case Iop_Sar8x16: op =3D Pav_SAR; goto do_AvBin8x16;
+ case Iop_Rotl8x16: op =3D Pav_ROTL; goto do_AvBin8x16;
case Iop_InterleaveHI8x16: op =3D Pav_MRGHI; goto do_AvBin8x16;
case Iop_InterleaveLO8x16: op =3D Pav_MRGLO; goto do_AvBin8x16;
case Iop_Add8x16: op =3D Pav_ADDUM; goto do_AvBin8x16;
@@ -3339,6 +3317,10 @@
return dst;
}
=20
+ case Iop_Shl16x8: op =3D Pav_SHL; goto do_AvBin16x8;
+ case Iop_Shr16x8: op =3D Pav_SHR; goto do_AvBin16x8;
+ case Iop_Sar16x8: op =3D Pav_SAR; goto do_AvBin16x8;
+ case Iop_Rotl16x8: op =3D Pav_ROTL; goto do_AvBin16x8;
case Iop_Narrow16Ux8: op =3D Pav_PACKUUM; goto do_AvBin16x8;
case Iop_QNarrow16Ux8: op =3D Pav_PACKUUS; goto do_AvBin16x8;
case Iop_QNarrow16Sx8: op =3D Pav_PACKSSS; goto do_AvBin16x8;
@@ -3371,6 +3353,10 @@
return dst;
}
=20
+ case Iop_Shl32x4: op =3D Pav_SHL; goto do_AvBin32x4;
+ case Iop_Shr32x4: op =3D Pav_SHR; goto do_AvBin32x4;
+ case Iop_Sar32x4: op =3D Pav_SAR; goto do_AvBin32x4;
+ case Iop_Rotl32x4: op =3D Pav_ROTL; goto do_AvBin32x4;
case Iop_Narrow32Ux4: op =3D Pav_PACKUUM; goto do_AvBin32x4;
case Iop_QNarrow32Ux4: op =3D Pav_PACKUUS; goto do_AvBin32x4;
case Iop_QNarrow32Sx4: op =3D Pav_PACKSSS; goto do_AvBin32x4;
@@ -3403,30 +3389,6 @@
return dst;
}
=20
-//.. do_SseReRg: {
-//.. HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. if (op !=3D Xsse_OR && op !=3D Xsse_AND && op !=3D Xsse_XO=
R)
-//.. REQUIRE_SSE2;
-//.. if (arg1isEReg) {
-//.. addInstr(env, mk_vMOVsd_RR(arg2, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, arg1, dst));
-//.. } else {
-//.. addInstr(env, mk_vMOVsd_RR(arg1, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, arg2, dst));
-//.. }
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_ShlN16x8: op =3D Xsse_SHL16; goto do_SseShift;
-//.. case Iop_ShlN32x4: op =3D Xsse_SHL32; goto do_SseShift;
-//.. case Iop_ShlN64x2: op =3D Xsse_SHL64; goto do_SseShift;
-//.. case Iop_SarN16x8: op =3D Xsse_SAR16; goto do_SseShift;
-//.. case Iop_SarN32x4: op =3D Xsse_SAR32; goto do_SseShift;
-//.. case Iop_ShrN16x8: op =3D Xsse_SHR16; goto do_SseShift;
-//.. case Iop_ShrN64x2: op =3D Xsse_SHR64; goto do_SseShift;
-
case Iop_ShlN8x16: op =3D Pav_SHL; goto do_AvShift8x16;
case Iop_SarN8x16: op =3D Pav_SAR; goto do_AvShift8x16;
do_AvShift8x16: {
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