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From: <sv...@va...> - 2005-09-14 21:15:47
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Author: cerion
Date: 2005-09-14 22:15:40 +0100 (Wed, 14 Sep 2005)
New Revision: 1393
Log:
implemented vaddcuw
backend:
Iop_ShrN32x4, Iop_Add32x4, Iop_CmpGT32Ux4
fixed emit_Instr::Pin_AvSplat for negative nums
fixed mk_AvDuplicateRI for imm's 16:31, -32:-17 inclusive
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-14 20:35:47 UTC (rev 1392)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-14 21:15:40 UTC (rev 1393)
@@ -5027,6 +5027,11 @@
UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
=20
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_arith(PPC32)(opc1 !=3D 0x4)\n");
return False;
@@ -5034,11 +5039,16 @@
=20
switch (opc2) {
/* Add */
- case 0x180: // vaddcuw (Add Carryout Unsigned Word, AV p136)
+ case 0x180: { // vaddcuw (Add Carryout Unsigned Word, AV p136)
DIP("vaddcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
- =20
+ /* ov =3D x >u (x+y) */
+ IRTemp sum =3D newTemp(Ity_V128);
+ assign( sum, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_ShrN32x4,
+ binop(Iop_CmpGT32Ux4, mkexpr(vA), mkexpr(s=
um)),
+ mkU8(31)) );
+ break;
+ }
case 0x000: // vaddubm (Add Unsigned Byte Modulo, AV p141)
DIP("vaddubm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
DIP(" =3D> not implemented\n");
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-14 20:35:47 UTC (rev 1392)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-14 21:15:40 UTC (rev 1393)
@@ -3126,6 +3126,7 @@
/* expects 5-bit-signed-imm */
Char simm5 =3D i->Pin.AvSplat.src->Pvi.Imm5s;
vassert(simm5 >=3D -16 && simm5 <=3D 15);
+ simm5 =3D simm5 & 0x1F;
p =3D mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2 );
}
else { // Pri_Reg
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-14 20:35:47 UTC (rev 1392)
+++ trunk/priv/host-ppc32/isel.c 2005-09-14 21:15:40 UTC (rev 1393)
@@ -780,7 +780,10 @@
HReg v2 =3D newVRegV(env);
addInstr(env, PPC32Instr_AvSplat(sz, v1, PPC32VI5s_Imm(-16))=
);
addInstr(env, PPC32Instr_AvSplat(sz, v2, PPC32VI5s_Imm(simm6=
-16)));
- addInstr(env, PPC32Instr_AvBinary(Pav_SUBUM, dst, v2, v1));
+ addInstr(env,
+ (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_SUBUM, dst, v2, v=
1) :
+ (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_SUBUM, dst, v2, v=
1)
+ : PPC32Instr_AvBin32x4(Pav_SUBUM, dst, v2, v1) )=
;
return dst;
}
if (simm6 < -16) { /* -32:-17 inclusive */
@@ -788,7 +791,10 @@
HReg v2 =3D newVRegV(env);
addInstr(env, PPC32Instr_AvSplat(sz, v1, PPC32VI5s_Imm(-16))=
);
addInstr(env, PPC32Instr_AvSplat(sz, v2, PPC32VI5s_Imm(simm6=
+16)));
- addInstr(env, PPC32Instr_AvBinary(Pav_ADDUM, dst, v2, v1));
+ addInstr(env,
+ (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_ADDUM, dst, v2, v=
1) :
+ (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_ADDUM, dst, v2, v=
1)
+ : PPC32Instr_AvBin32x4(Pav_ADDUM, dst, v2, v1) )=
;
return dst;
}
/* simplest form: -16:15 inclusive */
@@ -3335,6 +3341,17 @@
addInstr(env, PPC32Instr_AvBinary(op, dst, arg1, arg2));
return dst;
}
+
+ case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
+ case Iop_CmpGT32Ux4: op =3D Pav_CMPGTU; goto do_AvBin32x4;
+ do_AvBin32x4: {
+ HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBin32x4(op, dst, arg1, arg2));
+ return dst;
+ }
+
//.. do_SseReRg: {
//.. HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
//.. HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
@@ -3357,9 +3374,17 @@
//.. case Iop_SarN16x8: op =3D Xsse_SAR16; goto do_SseShift;
//.. case Iop_SarN32x4: op =3D Xsse_SAR32; goto do_SseShift;
//.. case Iop_ShrN16x8: op =3D Xsse_SHR16; goto do_SseShift;
-//.. case Iop_ShrN32x4: op =3D Xsse_SHR32; goto do_SseShift;
//.. case Iop_ShrN64x2: op =3D Xsse_SHR64; goto do_SseShift;
=20
+ case Iop_ShrN32x4: op =3D Pav_SHR; goto do_AvShift32x4;
+ do_AvShift32x4: {
+ HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg dst =3D newVRegV(env);
+ HReg v_shft =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_AvBin32x4(op, dst, r_src, v_shft));
+ return dst;
+ }
+
case Iop_ShrV128: op =3D Pav_SHR; goto do_AvShiftV128;
do_AvShiftV128: {
HReg dst =3D newVRegV(env);
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