|
From: <sv...@va...> - 2005-09-09 22:31:53
|
Author: sewardj
Date: 2005-09-09 23:31:49 +0100 (Fri, 09 Sep 2005)
New Revision: 1384
Log:
Typechecker cleanups (non-functional changes)
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
trunk/priv/host-x86/hdefs.c
trunk/priv/main/vex_util.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-amd64/toIR.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -5387,7 +5387,7 @@
=20
case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */
r_dst =3D (UInt)modrm - 0xD0;
- DIP("fst %%st(0),%%st(%d)\n", r_dst);
+ DIP("fst %%st(0),%%st(%u)\n", r_dst);
/* P4 manual says: "If the destination operand is a
non-empty register, the invalid-operation exception
is not generated. Hence put_ST_UNCHECKED. */
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -141,8 +141,8 @@
# define FIELD(_n) \
do { \
t =3D cr_native >> (4*(7-(_n))); \
- vex_state->guest_CR##_n##_0 =3D (UChar)(t & 1); \
- vex_state->guest_CR##_n##_321 =3D (UChar)(t & (7<<1)); \
+ vex_state->guest_CR##_n##_0 =3D toUChar(t & 1); \
+ vex_state->guest_CR##_n##_321 =3D toUChar(t & (7<<1)); \
} while (0)
=20
FIELD(0);
@@ -174,10 +174,10 @@
void LibVEX_GuestPPC32_put_XER ( UInt xer_native,
/*OUT*/VexGuestPPC32State* vex_state )
{
- vex_state->guest_XER_BC =3D (UChar)(xer_native & 0xFF);
- vex_state->guest_XER_SO =3D (UChar)((xer_native >> 31) & 0x1);
- vex_state->guest_XER_OV =3D (UChar)((xer_native >> 30) & 0x1);
- vex_state->guest_XER_CA =3D (UChar)((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_BC =3D toUChar(xer_native & 0xFF);
+ vex_state->guest_XER_SO =3D toUChar((xer_native >> 31) & 0x1);
+ vex_state->guest_XER_OV =3D toUChar((xer_native >> 30) & 0x1);
+ vex_state->guest_XER_CA =3D toUChar((xer_native >> 29) & 0x1);
}
=20
=20
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -776,7 +776,7 @@
return binop( Iop_And32,=20
binop( Iop_Shr32,=20
unop(Iop_8Uto32, getCR321(n)),
- mkU8(3-off) ),
+ mkU8(toUChar(3-off)) ),
mkU32(1) );
}
}
@@ -805,7 +805,7 @@
binop(Iop_And32, unop(Iop_8Uto32, getCR321(n)),
mkU32(~(1 << off))),
/* new value in the right place */
- binop(Iop_Shl32, safe, mkU8(off))
+ binop(Iop_Shl32, safe, mkU8(toUChar(off)))
)
)
);
@@ -879,7 +879,7 @@
if ((mask & (1 << (7-cr))) =3D=3D 0)
continue;
t =3D newTemp(Ity_I32);
- assign( t, binop(Iop_Shr32, w32, mkU8(4*(7-cr))) );
+ assign( t, binop(Iop_Shr32, w32, mkU8(toUChar(4*(7-cr)))) );
putCR0( cr, unop(Iop_32to8,=20
binop(Iop_And32, mkexpr(t), mkU32(1))) );
putCR321( cr, unop(Iop_32to8,
@@ -999,7 +999,7 @@
break;
=20
default:=20
- vex_printf("set_XER_OV: op =3D %d\n", op);
+ vex_printf("set_XER_OV: op =3D %u\n", op);
vpanic("set_XER_OV(ppc32)");
}
=20
@@ -1136,7 +1136,7 @@
break;
=20
default:=20
- vex_printf("set_XER_CA: op =3D %d\n", op);
+ vex_printf("set_XER_CA: op =3D %u\n", op);
vpanic("set_XER_CA(ppc32)");
}
=20
@@ -1450,10 +1450,10 @@
// li rD,val =3D=3D addi rD,0,val
// la disp(rA) =3D=3D addi rD,rA,disp
if ( Ra_addr =3D=3D 0 ) {
- DIP("li r%d,%d\n", Rd_addr, EXTS_SIMM);
+ DIP("li r%d,%d\n", Rd_addr, (Int)EXTS_SIMM);
assign( Rd, mkU32(EXTS_SIMM) );
} else {
- DIP("addi r%d,r%d,0x%x\n", Rd_addr, Ra_addr, SIMM_16);
+ DIP("addi r%d,r%d,0x%x\n", Rd_addr, Ra_addr, (Int)SIMM_16);
assign( Rd, binop( Iop_Add32, mkexpr(Ra), mkU32(EXTS_SIMM) ) );
}
break;
@@ -1461,7 +1461,7 @@
case 0x0F: // addis (Add Immediate Shifted, PPC32 p353)
// lis rD,val =3D=3D addis rD,0,val
if ( Ra_addr =3D=3D 0 ) {
- DIP("lis r%d,%d\n", Rd_addr, SIMM_16);
+ DIP("lis r%d,%d\n", Rd_addr, (Int)SIMM_16);
assign( Rd, mkU32(SIMM_16 << 16) );
} else {
DIP("addis r%d,r%d,0x%x\n", Rd_addr, Ra_addr, SIMM_16);
@@ -1815,7 +1815,7 @@
switch (opc1) {
case 0x0B: // cmpi (Compare Immediate, PPC32 p368)
EXTS_SIMM =3D extend_s_16to32(UIMM_16);
- DIP("cmp cr%d,r%d,%d\n", crfD, Ra_addr, EXTS_SIMM);
+ DIP("cmp cr%d,r%d,%d\n", crfD, Ra_addr, (Int)EXTS_SIMM);
putCR321( crfD, unop(Iop_32to8,
binop(Iop_CmpORD32S, mkexpr(Ra),=20
mkU32(EXTS_SIMM))) );
@@ -2166,7 +2166,7 @@
=20
switch (opc1) {
case 0x22: // lbz (Load B & Zero, PPC32 p433)
- DIP("lbz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lbz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_8Uto32,
loadBE(Ity_I8, mkexpr(EA_imm))) );
break;
@@ -2176,14 +2176,14 @@
vex_printf("dis_int_load(PPC32)(lbzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lbzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lbzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_8Uto32,
loadBE(Ity_I8, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x2A: // lha (Load HW Algebraic, PPC32 p445)
- DIP("lha r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lha r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Sto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
break;
@@ -2193,14 +2193,14 @@
vex_printf("dis_int_load(PPC32)(lhau,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)d_imm, Ra_addr);
+ DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Sto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x28: // lhz (Load HW & Zero, PPC32 p450)
- DIP("lhz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lhz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Uto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
break;
@@ -2210,14 +2210,14 @@
vex_printf("dis_int_load(PPC32)(lhzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lhzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lhzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Uto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x20: // lwz (Load W & Zero, PPC32 p460)
- DIP("lwz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lwz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, loadBE(Ity_I32, mkexpr(EA_imm)) );
break;
=20
@@ -2226,7 +2226,7 @@
vex_printf("dis_int_load(PPC32)(lwzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lwzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lwzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, loadBE(Ity_I32, mkexpr(EA_imm)) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
@@ -2351,7 +2351,7 @@
=20
switch (opc1) {
case 0x26: // stb (Store B, PPC32 p509)
- DIP("stb r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stb r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
@@ -2360,13 +2360,13 @@
vex_printf("dis_int_store(PPC32)(stbu,Ra_addr)\n");
return False;
}
- DIP("stbu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stbu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
case 0x2C: // sth (Store HW, PPC32 p522)
- DIP("sth r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("sth r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
@@ -2375,13 +2375,13 @@
vex_printf("dis_int_store(PPC32)(sthu,Ra_addr)\n");
return False;
}
- DIP("sthu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("sthu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
case 0x24: // stw (Store W, PPC32 p530)
- DIP("stw r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stw r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), mkexpr(Rs) );
break;
=20
@@ -2390,7 +2390,7 @@
vex_printf("dis_int_store(PPC32)(stwu,Ra_addr)\n");
return False;
}
- DIP("stwu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stwu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), mkexpr(Rs) );
break;
@@ -2409,13 +2409,13 @@
vex_printf("dis_int_store(PPC32)(stbux,Ra_addr)\n");
return False;
}
- DIP("stbux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stbux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
- DIP("stbx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stbx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
@@ -2424,13 +2424,13 @@
vex_printf("dis_int_store(PPC32)(sthux,Ra_addr)\n");
return False;
}
- DIP("sthux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("sthux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
case 0x197: // sthx (Store HW Indexed, PPC32 p526)
- DIP("sthx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("sthx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
@@ -2439,13 +2439,13 @@
vex_printf("dis_int_store(PPC32)(stwux,Ra_addr)\n");
return False;
}
- DIP("stwux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stwux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), mkexpr(Rs) );
break;
=20
case 0x097: // stwx (Store W Indexed, PPC32 p536)
- DIP("stwx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stwx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), mkexpr(Rs) );
break;
=20
@@ -2562,7 +2562,7 @@
unop(Iop_8Uto32,=20
loadBE(Ity_I8,=20
binop(Iop_Add32, e_EA, mkU32(i)))),=20
- mkU8(shift))=20
+ mkU8(toUChar(shift)))=20
));
shift -=3D 8;
}
@@ -2597,7 +2597,7 @@
storeBE(
binop(Iop_Add32, e_EA, mkU32(i)),
unop(Iop_32to8,
- binop(Iop_Shr32, getIReg(rS), mkU8(shift)))
+ binop(Iop_Shr32, getIReg(rS), mkU8(toUChar(shift))))
);
shift -=3D 8;
}
@@ -3650,7 +3650,7 @@
//zz return False;
=20
default:
- vex_printf("dis_proc_ctl(PPC32)(mtspr,SPR_flipped)(%d)\n",
+ vex_printf("dis_proc_ctl(PPC32)(mtspr,SPR_flipped)(%u)\n",
SPR_flipped);
return False;
}
@@ -6092,7 +6092,7 @@
}
=20
=20
- opc1 =3D ifieldOPC(theInstr);
+ opc1 =3D toUChar(ifieldOPC(theInstr));
opc2 =3D ifieldOPClo10(theInstr);
=20
#if PPC32_TOIR_DEBUG
@@ -6567,7 +6567,7 @@
/* All decode failures end up here. */
vex_printf("disInstr(ppc32): unhandled instruction: "
"0x%x\n", theInstr);
- vex_printf(" primary %d(0x%x), secondary %d(0x%x)\n",=
=20
+ vex_printf(" primary %d(0x%x), secondary %u(0x%x)\n",=
=20
opc1, opc1, opc2, opc2);
=20
#if PPC32_TOIR_DEBUG
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -435,7 +435,7 @@
if (op->Prh.Imm.syned)
vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16);
else
- vex_printf("%d", (UInt)(UShort)op->Prh.Imm.imm16);
+ vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16);
return;
case Prh_Reg:=20
ppHRegPPC32(op->Prh.Reg.reg);
@@ -1015,7 +1015,7 @@
/* generic */
vex_printf("%s ",=20
showPPC32AluOp(i->Pin.Alu32.op,
- i->Pin.Alu32.srcR->tag =3D=3D Prh_Imm=
));
+ toBool(i->Pin.Alu32.srcR->tag =3D=3D =
Prh_Imm)));
ppHRegPPC32(i->Pin.Alu32.dst);
vex_printf(",");
ppHRegPPC32(i->Pin.Alu32.srcL);
@@ -2169,7 +2169,7 @@
=20
case Pin_Alu32: {
PPC32RH* srcR =3D i->Pin.Alu32.srcR;
- Bool immR =3D srcR->tag =3D=3D Prh_Imm;
+ Bool immR =3D toBool(srcR->tag =3D=3D Prh_Imm);
UInt r_dst =3D iregNo(i->Pin.Alu32.dst);
UInt r_srcL =3D iregNo(i->Pin.Alu32.srcL);
UInt r_srcR =3D immR ? (-1)/*bogus*/ : iregNo(srcR->Prh.Reg.re=
g);
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-ppc32/isel.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -332,14 +332,16 @@
{
HReg sp =3D StackFramePtr;
vassert(n > 0 && n < 256 && (n%16) =3D=3D 0);
- addInstr(env, PPC32Instr_Alu32(Palu_ADD, sp, sp, PPC32RH_Imm(True,n))=
);
+ addInstr(env, PPC32Instr_Alu32(
+ Palu_ADD, sp, sp, PPC32RH_Imm(True,toUShort(n))));
}
=20
static void sub_from_sp ( ISelEnv* env, Int n )
{
HReg sp =3D StackFramePtr;
vassert(n > 0 && n < 256 && (n%16) =3D=3D 0);
- addInstr(env, PPC32Instr_Alu32(Palu_SUB, sp, sp, PPC32RH_Imm(True,n))=
);
+ addInstr(env, PPC32Instr_Alu32(
+ Palu_SUB, sp, sp, PPC32RH_Imm(True,toUShort(n))));
}
=20
=20
@@ -850,8 +852,8 @@
/* widen the left arg if needed */
if ((aluOp =3D=3D Palu_SHR || aluOp =3D=3D Palu_SAR)
&& (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16)) {
- PPC32RH* amt =3D PPC32RH_Imm(False, ty =3D=3D Ity_I8 ? 24 : =
16);
- HReg tmp =3D newVRegI(env);
+ PPC32RH* amt =3D PPC32RH_Imm(False, toUShort(ty =3D=3D Ity_I=
8 ? 24 : 16));
+ HReg tmp =3D newVRegI(env);
addInstr(env, PPC32Instr_Alu32(Palu_SHL, tmp, r_srcL, amt));
addInstr(env, PPC32Instr_Alu32(aluOp, tmp, tmp, amt));
r_srcL =3D tmp;
@@ -887,7 +889,7 @@
/* El-mutanto 3-way compare? */
if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S
|| e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
- Bool syned =3D e->Iex.Binop.op =3D=3D Iop_CmpORD32S;
+ Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD32S)=
;
HReg dst =3D newVRegI(env);
HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
PPC32RH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2=
);
@@ -1062,20 +1064,23 @@
case Iop_8Uto16:
case Iop_8Uto32:
case Iop_16Uto32: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt mask =3D e->Iex.Unop.op=3D=3DIop_16Uto32 ? 0xFFFF : 0xFF;
- addInstr(env, PPC32Instr_Alu32(Palu_AND,r_dst,r_src,PPC32RH_Imm=
(False,mask)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort mask =3D toUShort(e->Iex.Unop.op=3D=3DIop_16Uto32 ? 0xF=
FFF : 0xFF);
+ addInstr(env, PPC32Instr_Alu32(Palu_AND,r_dst,r_src,
+ PPC32RH_Imm(False,mask)=
));
return r_dst;
}
case Iop_8Sto16:
case Iop_8Sto32:
case Iop_16Sto32: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt amt =3D e->Iex.Unop.op=3D=3DIop_16Sto32 ? 16 : 24;
- addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_src, PPC32RH_=
Imm(False,amt)));
- addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst, PPC32RH_=
Imm(False,amt)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort amt =3D toUShort(e->Iex.Unop.op=3D=3DIop_16Sto32 ? 16 =
: 24);
+ addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_src,=20
+ PPC32RH_Imm(False,amt)=
));
+ addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst,=20
+ PPC32RH_Imm(False,amt)=
));
return r_dst;
}
case Iop_Not8:
@@ -1132,10 +1137,11 @@
}
case Iop_16HIto8:
case Iop_32HIto16: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt shift =3D e->Iex.Unop.op =3D=3D Iop_16HIto8 ? 8 : 16;
- addInstr(env, PPC32Instr_Alu32(Palu_SHR, r_dst, r_src, PPC32RH_=
Imm(False,shift)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort shift =3D toUShort(e->Iex.Unop.op =3D=3D Iop_16HIto8 ? 8=
: 16);
+ addInstr(env, PPC32Instr_Alu32(Palu_SHR, r_dst, r_src,=20
+ PPC32RH_Imm(False,shif=
t)));
return r_dst;
}
case Iop_1Uto32:
@@ -1152,8 +1158,10 @@
HReg r_dst =3D newVRegI(env);
PPC32CondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
addInstr(env, PPC32Instr_Set32(cond,r_dst));
- addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_dst, PPC32RH_=
Imm(False,31)));
- addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst, PPC32RH_=
Imm(False,31)));
+ addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_dst,=20
+ PPC32RH_Imm(False,31))=
);
+ addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst,=20
+ PPC32RH_Imm(False,31))=
);
return r_dst;
}
=20
@@ -1420,10 +1428,10 @@
i =3D (Int)u;
/* Now figure out if it's representable. */
if (!syned && u <=3D 65535) {
- return PPC32RH_Imm(False/*unsigned*/, u & 0xFFFF);
+ return PPC32RH_Imm(False/*unsigned*/, toUShort(u & 0xFFFF));
}
if (syned && i >=3D -32767 && i <=3D 32767) {
- return PPC32RH_Imm(True/*signed*/, u & 0xFFFF);
+ return PPC32RH_Imm(True/*signed*/, toUShort(u & 0xFFFF));
}
/* no luck; use the Slow Way. */
}
Modified: trunk/priv/host-x86/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-x86/hdefs.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -2221,7 +2221,7 @@
=20
/* Alternative version which works on any x86 variant. */
/* jmp fwds if !condition */
- *p++ =3D 0x70 + (i->Xin.CMov32.cond ^ 1);
+ *p++ =3D toUChar(0x70 + (i->Xin.CMov32.cond ^ 1));
*p++ =3D 0; /* # of bytes in the next bit, which we don't know yet=
*/
ptmp =3D p;
=20
@@ -2245,7 +2245,7 @@
goto bad;
}
/* Fill in the jump offset. */
- *(ptmp-1) =3D p - ptmp;
+ *(ptmp-1) =3D toUChar(p - ptmp);
goto done;
=20
break;
Modified: trunk/priv/main/vex_util.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_util.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/main/vex_util.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -106,6 +106,7 @@
/* ugly hack -- do not remove */
//extern void* malloc ( int );
//return malloc(nbytes);
+ return NULL;
} else {
nbytes =3D (nbytes + ALIGN) & ~ALIGN;
if (mode =3D=3D VexAllocModeTEMP) {
@@ -223,7 +224,7 @@
}
=20
while (1) {
- buf[bufi++] =3D '0' + (HChar)(u0 % base);
+ buf[bufi++] =3D toHChar('0' + toUInt(u0 % base));
u0 /=3D base;
if (u0 =3D=3D 0) break;
}
@@ -233,7 +234,7 @@
buf[bufi] =3D 0;
for (i =3D 0; i < bufi; i++)
if (buf[i] > '9')=20
- buf[i] +=3D ((hexcaps ? 'A' : 'a') - '9' - 1);
+ buf[i] =3D toHChar(buf[i] + (hexcaps ? 'A' : 'a') - '9' - 1);
=20
i =3D 0;
j =3D bufi-1;
@@ -374,7 +375,7 @@
}
case 'p':=20
case 'P': {
- Bool hexcaps =3D *format =3D=3D 'P';
+ Bool hexcaps =3D toBool(*format =3D=3D 'P');
ULong l =3D Ptr_to_ULong( va_arg(ap, void*) );
convert_int(intbuf, l, 16/*base*/, False/*unsigned*/, hexcap=
s);
len1 =3D len3 =3D 0;
@@ -415,7 +416,7 @@
=20
static void add_to_myprintf_buf ( HChar c )
{
- Bool emit =3D c =3D=3D '\n' || n_myprintf_buf >=3D 1000-10 /*paranoia=
*/;
+ Bool emit =3D toBool(c =3D=3D '\n' || n_myprintf_buf >=3D 1000-10 /*p=
aranoia*/);
myprintf_buf[n_myprintf_buf++] =3D c;
myprintf_buf[n_myprintf_buf] =3D 0;
if (emit) {
|