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From: <sv...@va...> - 2005-09-09 16:31:29
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Author: cerion
Date: 2005-09-09 17:31:24 +0100 (Fri, 09 Sep 2005)
New Revision: 1380
Log:
implemented Iop_64HLtoV128 in iselVecExpr_wrk
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-09 10:36:55 UTC (rev 1379)
+++ trunk/priv/host-ppc32/isel.c 2005-09-09 16:31:24 UTC (rev 1380)
@@ -2798,10 +2798,10 @@
//.. addInstr(env, X86Instr_SseConst(e->Iex.Const.con->Ico.V128, d=
st));
//.. return dst;
//.. }
-//..=20
-//.. if (e->tag =3D=3D Iex_Unop) {
-//.. switch (e->Iex.Unop.op) {
-//..=20
+
+ if (e->tag =3D=3D Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+
//.. case Iop_Not128: {
//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
//.. return do_sse_Not128(env, arg);
@@ -2970,15 +2970,15 @@
//.. add_to_esp(env, 8);
//.. return dst;
//.. }
-//..=20
-//.. default:
-//.. break;
-//.. } /* switch (e->Iex.Unop.op) */
-//.. } /* if (e->tag =3D=3D Iex_Unop) */
-//..=20
-//.. if (e->tag =3D=3D Iex_Binop) {
-//.. switch (e->Iex.Binop.op) {
-//..=20
+
+ default:
+ break;
+ } /* switch (e->Iex.Unop.op) */
+ } /* if (e->tag =3D=3D Iex_Unop) */
+
+ if (e->tag =3D=3D Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+
//.. case Iop_SetV128lo32: {
//.. HReg dst =3D newVRegV(env);
//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
@@ -3008,29 +3008,29 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_64HLtoV128: {
-//.. HReg r3, r2, r1, r0;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* esp4 =3D advance4(esp0);
-//.. X86AMode* esp8 =3D advance4(esp4);
-//.. X86AMode* esp12 =3D advance4(esp8);
-//.. HReg dst =3D newVRegV(env);
-//.. /* do this via the stack (easy, convenient, etc) */
-//.. sub_from_esp(env, 16);
-//.. /* Do the less significant 64 bits */
-//.. iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r0), esp=
0));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r1), esp=
4));
-//.. /* Do the more significant 64 bits */
-//.. iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r2), esp=
8));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r3), esp=
12));
-//.. /* Fetch result back from stack. */
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
+ case Iop_64HLtoV128: {
+ HReg r3, r2, r1, r0;
+ PPC32AMode *sp0 =3D PPC32AMode_IR(0, StackFramePtr);
+ PPC32AMode *sp4 =3D PPC32AMode_IR(4, StackFramePtr);
+ PPC32AMode *sp8 =3D PPC32AMode_IR(8, StackFramePtr);
+ PPC32AMode *sp12 =3D PPC32AMode_IR(12, StackFramePtr);
+ HReg dst =3D newVRegV(env);
+ /* do this via the stack (easy, convenient, etc) */
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ /* Do the less significant 64 bits */
+ iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_Store( 4, sp12, r0 ));
+ addInstr(env, PPC32Instr_Store( 4, sp8, r1 ));
+ /* Do the more significant 64 bits */
+ iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1);
+ addInstr(env, PPC32Instr_Store( 4, sp4, r2 ));
+ addInstr(env, PPC32Instr_Store( 4, sp0, r3 ));
+ /* Fetch result back from stack. */
+ addInstr(env, PPC32Instr_AvLdSt(True/*load*/, 16, dst, sp0));
+ add_to_sp( env, 16 ); // Reset SP
+ return dst;
+ }
+
//.. case Iop_CmpEQ32Fx4: op =3D Xsse_CMPEQF; goto do_32Fx4;
//.. case Iop_CmpLT32Fx4: op =3D Xsse_CMPLTF; goto do_32Fx4;
//.. case Iop_CmpLE32Fx4: op =3D Xsse_CMPLEF; goto do_32Fx4;
@@ -3207,12 +3207,12 @@
//.. add_to_esp(env, 16);
//.. return dst;
//.. }
-//..=20
-//.. default:
-//.. break;
-//.. } /* switch (e->Iex.Binop.op) */
-//.. } /* if (e->tag =3D=3D Iex_Binop) */
-//..=20
+
+ default:
+ break;
+ } /* switch (e->Iex.Binop.op) */
+ } /* if (e->tag =3D=3D Iex_Binop) */
+
//.. if (e->tag =3D=3D Iex_Mux0X) {
//.. HReg r8 =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
//.. HReg rX =3D iselVecExpr(env, e->Iex.Mux0X.exprX);
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