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From: <sv...@va...> - 2005-08-24 17:51:02
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Author: sewardj
Date: 2005-08-24 18:50:59 +0100 (Wed, 24 Aug 2005)
New Revision: 1360
Log:
Merge r1350, r1351, r1353 (x86 ADC Ib,AL implementation + related fixes)
Modified:
branches/VEX_3_0_BRANCH/priv/guest-amd64/toIR.c
branches/VEX_3_0_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_0_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_0_BRANCH/priv/guest-amd64/toIR.c 2005-08-24 17:45:33 U=
TC (rev 1359)
+++ branches/VEX_3_0_BRANCH/priv/guest-amd64/toIR.c 2005-08-24 17:50:59 U=
TC (rev 1360)
@@ -53,12 +53,11 @@
disInstr for details.
*/
=20
-//.. /* TODO:
-//..=20
-//.. check flag settings for cmpxchg
-//.. FUCOMI(P): what happens to A and S flags? Currently are forced
-//.. to zero.
-//..=20
+/* TODO:
+
+ All Puts to CC_OP/CC_DEP1/CC_DEP2/CC_NDEP should really be checked
+ to ensure a 64-bit value is being written.
+
//.. x87 FP Limitations:
//..=20
//.. * all arithmetic done at 64 bits
@@ -91,7 +90,8 @@
//.. bit be set by PUSHF.
//..=20
//.. This module uses global variables and so is not MT-safe (if that
-//.. should ever become relevant). */
+//.. should ever become relevant).
+*/
=20
/* Translates AMD64 code to IR. */
=20
@@ -1685,9 +1685,9 @@
mkexpr(oldcn)) );
=20
stmt( IRStmt_Put( OFFB_CC_OP, mkU64(thunkOp) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(ta1) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP2, binop(xor, mkexpr(ta2),=20
- mkexpr(oldcn)) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(ta1)) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(binop(xor, mkexpr(ta2),=20
+ mkexpr(oldcn)) =
)) );
stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) );
}
=20
@@ -1725,9 +1725,9 @@
mkexpr(oldcn)) );
=20
stmt( IRStmt_Put( OFFB_CC_OP, mkU64(thunkOp) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(ta1) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP2, binop(xor, mkexpr(ta2),=20
- mkexpr(oldcn)) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(ta1) )) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(binop(xor, mkexpr(ta2),=20
+ mkexpr(oldcn)) =
)) );
stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) );
}
=20
Modified: branches/VEX_3_0_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_0_BRANCH/priv/guest-x86/toIR.c 2005-08-24 17:45:33 UTC=
(rev 1359)
+++ branches/VEX_3_0_BRANCH/priv/guest-x86/toIR.c 2005-08-24 17:50:59 UTC=
(rev 1360)
@@ -46,7 +46,9 @@
=20
/* TODO:
=20
- check flag settings for cmpxchg
+ All Puts to CC_OP/CC_DEP1/CC_DEP2/CC_NDEP should really be checked
+ to ensure a 32-bit value is being written.
+
FUCOMI(P): what happens to A and S flags? Currently are forced
to zero.
=20
@@ -1027,9 +1029,9 @@
mkexpr(oldcn)) );
=20
stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(ta1) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP2, binop(xor, mkexpr(ta2),=20
- mkexpr(oldcn)) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1)) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2),=20
+ mkexpr(oldcn)) =
)) );
stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) );
}
=20
@@ -1063,9 +1065,9 @@
mkexpr(oldcn)) );
=20
stmt( IRStmt_Put( OFFB_CC_OP, mkU32(thunkOp) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(ta1) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP2, binop(xor, mkexpr(ta2),=20
- mkexpr(oldcn)) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto32(mkexpr(ta1) )) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto32(binop(xor, mkexpr(ta2),=20
+ mkexpr(oldcn)) =
)) );
stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldc) ) );
}
=20
@@ -10756,11 +10758,11 @@
delta =3D dis_op_imm_A( sz, False, Iop_Or8, True, delta, "or" );
break;
=20
-//-- case 0x14: /* ADC Ib, AL */
-//-- delta =3D dis_op_imm_A( 1, ADC, True, delta, "adc" );
-//-- break;
+ case 0x14: /* ADC Ib, AL */
+ delta =3D dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" );
+ break;
case 0x15: /* ADC Iv, eAX */
- delta =3D dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" );
+ delta =3D dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" );
break;
=20
//-- case 0x1C: /* SBB Ib, AL */
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