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From: <sv...@va...> - 2005-08-10 16:18:43
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Author: sewardj
Date: 2005-08-10 17:18:39 +0100 (Wed, 10 Aug 2005)
New Revision: 4372
Log:
Back out partially-committed x86 sysenter stuff on stable branch until
such time as we decide we have a coherent single vdso-related patch
which we want to push to stable.
Modified:
branches/VALGRIND_3_0_BRANCH/coregrind/m_scheduler/scheduler.c
Modified: branches/VALGRIND_3_0_BRANCH/coregrind/m_scheduler/scheduler.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_0_BRANCH/coregrind/m_scheduler/scheduler.c 2005-0=
8-10 16:17:10 UTC (rev 4371)
+++ branches/VALGRIND_3_0_BRANCH/coregrind/m_scheduler/scheduler.c 2005-0=
8-10 16:18:39 UTC (rev 4372)
@@ -772,24 +772,6 @@
"run_innerloop detected host "
"state invariant failure", trc);
=20
- case VEX_TRC_JMP_SYSENTER_X86:
- /* Do whatever simulation is appropriate for an x86 sysenter
- instruction. Note that it is critical to set this thread's
- guest_EIP to point at the code to execute after the
- sysenter, since Vex-generated code will not have set it --
- vex does not know what it should be. Vex sets the next
- address to zero, so if you don't guest_EIP, the thread will
- jump to zero afterwards and probably die as a result. */
-# if defined(VGA_x86)
- //FIXME: VG_(threads)[tid].arch.vex.guest_EIP =3D ....
- //handle_sysenter_x86(tid);
- vg_assert2(0, "VG_(scheduler), phase 3: "
- "sysenter_x86 on not yet implemented");
-# else
- vg_assert2(0, "VG_(scheduler), phase 3: "
- "sysenter_x86 on non-x86 platform?!?!");
-# endif
-
default:=20
vg_assert2(0, "VG_(scheduler), phase 3: "
"unexpected thread return code (%u)", trc);
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From: Tom H. <to...@co...> - 2005-08-10 16:26:01
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In message <200...@ja...>
sv...@va... wrote:
> Back out partially-committed x86 sysenter stuff on stable branch until
> such time as we decide we have a coherent single vdso-related patch
> which we want to push to stable.
I was just trying to find a machine to test sysenter on but it's
proving a bit tricky... I've got a P4 here with FC4 but it claims
not to have sysenter so it looks like Intel have dropped it from some
recent processors... I'm trying a PIII box now but I think the OS on
there might be too old to try and use it.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
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From: Tom H. <to...@co...> - 2005-08-10 16:32:05
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In message <yek...@de...>
Tom Hughes <to...@co...> wrote:
> In message <200...@ja...>
> sv...@va... wrote:
>
>> Back out partially-committed x86 sysenter stuff on stable branch until
>> such time as we decide we have a coherent single vdso-related patch
>> which we want to push to stable.
>
> I was just trying to find a machine to test sysenter on but it's
> proving a bit tricky... I've got a P4 here with FC4 but it claims
> not to have sysenter so it looks like Intel have dropped it from some
> recent processors... I'm trying a PIII box now but I think the OS on
> there might be too old to try and use it.
Looks like I'm out of luck... We don't seem to have any boxes running
a recent enough kernel to use sysenter that also have a processor that
supports it.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
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From: Maurice v. d. P. <gri...@ge...> - 2005-08-10 16:44:52
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On Wed, Aug 10, 2005 at 05:31:59PM +0100, Tom Hughes wrote: > Looks like I'm out of luck... We don't seem to have any boxes running > a recent enough kernel to use sysenter that also have a processor that > supports it. Could you specify what you need? I have a P3 800 (Coppermine) running Gentoo Linux with a 2.6.11 kernel. I could give you an account if that would help. Or is this about running regular regression tests? Maurice. --=20 Maurice van der Pot Gentoo Linux Developer gri...@ge... http://www.gentoo.org Creator of BiteMe! gri...@kf... http://www.kfk4ever.com |
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From: Julian S. <js...@ac...> - 2005-08-10 16:37:40
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> not to have sysenter so it looks like Intel have dropped it from some > recent processors... That sounds a bit unlikely ... when have you ever known Intel remove insns from later processors? The IA32 architecture manual page 3-763 (doc 245471) mentions it, and that was revised after P4 came out. J |
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From: Nicholas N. <nj...@cs...> - 2005-08-10 16:36:56
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On Wed, 10 Aug 2005, Tom Hughes wrote: > I've got a P4 here with FC4 but it claims not to have sysenter so it > looks like Intel have dropped it from some recent processors... Really? That doesn't sound right. Is sysenter's presence indicated by one of those CPUID (or whatever) flags? N |
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From: Tom H. <to...@co...> - 2005-08-10 16:56:47
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In message <Pin...@ch...>
Nicholas Nethercote <nj...@cs...> wrote:
> On Wed, 10 Aug 2005, Tom Hughes wrote:
>
> > I've got a P4 here with FC4 but it claims not to have sysenter so it
> > looks like Intel have dropped it from some recent processors...
>
> Really? That doesn't sound right. Is sysenter's presence indicated by
> one of those CPUID (or whatever) flags?
Yes - this is what /proc/cpuinfo says on the box in question:
processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 0
model name : Intel(R) Pentium(R) 4 CPU 1700MHz
stepping : 10
cpu MHz : 1695.248
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips : 3350.52
If it has sysenter there should be a "sep" flag in the flags list.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
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From: Maurice v. d. P. <gri...@ge...> - 2005-08-10 17:01:14
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On Wed, Aug 10, 2005 at 05:56:30PM +0100, Tom Hughes wrote: > flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mc= a cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm P4 3.0G: flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mc= a cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr P3 800M: flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mc= a cmov pat pse36 mmx fxsr sse --=20 Maurice van der Pot Gentoo Linux Developer gri...@ge... http://www.gentoo.org Creator of BiteMe! gri...@kf... http://www.kfk4ever.com |
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From: Julian S. <js...@ac...> - 2005-08-10 17:17:27
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This sounds like an oldish Northwood ... > model name : Intel(R) Pentium(R) 4 CPU 1700MHz > stepping : 10 > cpu MHz : 1695.248 > cache size : 256 KB > flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov > pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm one of which I also have, but it says this: model name : Intel(R) Pentium(R) 4 CPU 1.70GHz stepping : 8 cpu MHz : 1718.525 cache size : 256 KB flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss So there's a "sep" there. And it's an older stepping than yours. wtf?! Anybody know any headbanging-grade x86 gurus who understand this stuff? J |
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From: Tom H. <to...@co...> - 2005-08-10 18:56:52
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In message <200...@ac...>
Julian Seward <js...@ac...> wrote:
> This sounds like an oldish Northwood ...
>
> > model name : Intel(R) Pentium(R) 4 CPU 1700MHz
> > stepping : 10
> > cpu MHz : 1695.248
> > cache size : 256 KB
> > flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov
> > pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
>
> one of which I also have, but it says this:
>
> model name : Intel(R) Pentium(R) 4 CPU 1.70GHz
> stepping : 8
> cpu MHz : 1718.525
> cache size : 256 KB
> flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat
> pse36 clflush dts acpi mmx fxsr sse sse2 ss
>
> So there's a "sep" there. And it's an older stepping than yours. wtf?!
>
> Anybody know any headbanging-grade x86 gurus who understand this stuff?
It's a RedHat kernel thing - they have patched their kernels to
disable sysenter. If I query the cpuid directly it does report
support for sysenter.
Tom
--
Tom Hughes (to...@co...)
http://www.compton.nu/
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