|
From: <sv...@va...> - 2005-08-08 00:35:50
|
Author: sewardj
Date: 2005-08-08 01:35:46 +0100 (Mon, 08 Aug 2005)
New Revision: 4339
Log:
Make Valgrind work again on x86 CPUs which don't have SSE. This is a
bit of an ugly hack (see comments in m_machine.c) which is suitable
for merging into 3_0_BRANCH, but should be cleaned up once that's
done.
Modified:
trunk/coregrind/m_dispatch/dispatch-x86.S
trunk/coregrind/m_machine.c
trunk/coregrind/m_translate.c
trunk/coregrind/pub_core_machine.h
Modified: trunk/coregrind/m_dispatch/dispatch-x86.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-x86.S 2005-08-07 15:16:59 UTC (re=
v 4338)
+++ trunk/coregrind/m_dispatch/dispatch-x86.S 2005-08-08 00:35:46 UTC (re=
v 4339)
@@ -71,10 +71,12 @@
=09
/* set host SSE control word to the default mode expected=20
by VEX-generated code. */
+ cmpl $0, VG_(have_mxcsr_x86)
+ jz L1
pushl $0x1F80
ldmxcsr (%esp)
addl $4, %esp
-
+L1:
/* set dir flag to known value */
cld
=09
@@ -136,13 +138,15 @@
cmpl $0x027F, (%esp)
popl %esi /* get rid of the word without trashing %eflags */
jnz invariant_violation
+ cmpl $0, VG_(have_mxcsr_x86)
+ jz L2
pushl $0
stmxcsr (%esp)
andl $0xFFFFFFC0, (%esp) /* mask out status flags */
cmpl $0x1F80, (%esp)
popl %esi
jnz invariant_violation
- /* otherwise we're OK */
+L2: /* otherwise we're OK */
jmp run_innerloop_exit_REALLY
=20
invariant_violation:
Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c 2005-08-07 15:16:59 UTC (rev 4338)
+++ trunk/coregrind/m_machine.c 2005-08-08 00:35:46 UTC (rev 4339)
@@ -196,16 +196,36 @@
return VG_INVALID_THREADID;
}
=20
+
//////////////////////////////////////////////////////////////////
// Architecture specifics
=20
-// PPC: what is the cache line size (for dcbz etc) ?
-// This info is harvested on Linux at startup from the AT_SYSINFO
-// entries. 0 means not-yet-set.
+// PPC: what is the cache line size (for dcbz etc) ? This info is
+// harvested on Linux at startup from the AT_SYSINFO entries. 0 means
+// not-yet-set.
#if defined(VGA_ppc32)
Int VG_(cache_line_size_ppc32) =3D 0;
#endif
=20
+// X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store
+// the SSE control/status register. For most modern CPUs this will be
+// 1. It is set to 1, if possible, by m_translate.getArchAndArchInfo.
+// The value is read by m_dispatch.dispatch-x86.S, which is why it
+// is an Int rather than a Bool.
+//
+// Ugly hack: this has to start as 0 and be set to 1 in the normal
+// case, rather than the other way round, because the dispatch
+// loop needs it, and it runs before the first translation is=20
+// made. Yet it is the act of making that first translation which
+// causes getArchAndArchInfo to set this value to its final value.
+// So it is necessary to start this value off at 0 as only that
+// guarantees that the dispatch loop will not SIGILL on its first
+// attempt.
+#if defined(VGA_x86)
+Int VG_(have_mxcsr_x86) =3D 0;
+#endif
+
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
Modified: trunk/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_translate.c 2005-08-07 15:16:59 UTC (rev 4338)
+++ trunk/coregrind/m_translate.c 2005-08-08 00:35:46 UTC (rev 4339)
@@ -35,6 +35,7 @@
#include "pub_core_cpuid.h"
#include "pub_core_machine.h" // For VG_(cache_line_size_ppc32)
// and VG_(get_SP)
+ // and VG_(have_mxcsr_x86)
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
@@ -53,7 +54,7 @@
/*------------------------------------------------------------*/
=20
// Returns the architecture and auxiliary information, or indicates
-// that this subarchitecture is unable to run Valgrind Returns False
+// that this subarchitecture is unable to run Valgrind. Returns False
// to indicate we cannot proceed further.
=20
static Bool getArchAndArchInfo( /*OUT*/VexArch* vex_arch,=20
@@ -64,7 +65,7 @@
LibVEX_default_VexArchInfo(vai);
=20
#if defined(VGA_x86)
- Bool have_sse0, have_sse1, have_sse2;
+ Bool have_sse1, have_sse2;
UInt eax, ebx, ecx, edx;
=20
if (!VG_(has_cpuid)())
@@ -79,31 +80,30 @@
/* get capabilities bits into edx */
VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
=20
- have_sse0 =3D (edx & (1<<24)) !=3D 0; /* True =3D> have fxsave/fxrsto=
r */
have_sse1 =3D (edx & (1<<25)) !=3D 0; /* True =3D> have sse insns */
have_sse2 =3D (edx & (1<<26)) !=3D 0; /* True =3D> have sse2 insns */
=20
- if (have_sse2 && have_sse1 && have_sse0) {
+ VG_(have_mxcsr_x86) =3D 1;
+
+ if (have_sse2 && have_sse1) {
*vex_arch =3D VexArchX86;
vai->subarch =3D VexSubArchX86_sse2;
return True;
}
=20
- if (have_sse1 && have_sse0) {
+ if (have_sse1) {
*vex_arch =3D VexArchX86;
vai->subarch =3D VexSubArchX86_sse1;
return True;
}
=20
- if (have_sse0) {
+ {
*vex_arch =3D VexArchX86;
vai->subarch =3D VexSubArchX86_sse0;
+ VG_(have_mxcsr_x86) =3D 0;
return True;
}
=20
- /* we need at least SSE state to operate. */
- return False;
-
#elif defined(VGA_amd64)
vg_assert(VG_(has_cpuid)());
*vex_arch =3D VexArchAMD64;
@@ -459,7 +459,7 @@
VG_(printf)("\n");
VG_(printf)("valgrind: fatal error: unsupported CPU.\n");
VG_(printf)(" Supported CPUs are:\n");
- VG_(printf)(" * x86 with SSE (Pentium III or above, "
+ VG_(printf)(" * x86 (practically any; Pentium-I or above), "
"AMD Athlon or above)\n");
VG_(printf)(" * AMD Athlon64/Opteron\n");
VG_(printf)(" * PowerPC with Altivec\n");
Modified: trunk/coregrind/pub_core_machine.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_machine.h 2005-08-07 15:16:59 UTC (rev 4338)
+++ trunk/coregrind/pub_core_machine.h 2005-08-08 00:35:46 UTC (rev 4339)
@@ -71,9 +71,11 @@
# error Unknown arch
#endif
=20
+
// Offsets for the Vex state
#define VG_O_STACK_PTR (offsetof(VexGuestArchState, VG_STACK_PTR)=
)
=20
+
// Architecture specifics
=20
// PPC: what is the cache line size (for dcbz etc) ?
@@ -83,6 +85,13 @@
extern Int VG_(cache_line_size_ppc32);
#endif
=20
+// X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store
+// the SSE control/status register.=20
+#if defined(VGA_x86)
+extern Int VG_(have_mxcsr_x86);
+#endif
+
+
#endif // __PUB_CORE_MACHINE_H
=20
/*--------------------------------------------------------------------*/
|