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From: <sv...@va...> - 2005-08-07 14:49:28
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Author: sewardj
Date: 2005-08-07 15:49:27 +0100 (Sun, 07 Aug 2005)
New Revision: 4337
Log:
Valgrind-side stub for dealing with x86 sysenter artefacts from Vex.
Does not do anything yet.
Modified:
trunk/coregrind/m_scheduler/scheduler.c
Modified: trunk/coregrind/m_scheduler/scheduler.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_scheduler/scheduler.c 2005-08-06 18:07:17 UTC (rev =
4336)
+++ trunk/coregrind/m_scheduler/scheduler.c 2005-08-07 14:49:27 UTC (rev =
4337)
@@ -792,6 +792,24 @@
"run_innerloop detected host "
"state invariant failure", trc);
=20
+ case VEX_TRC_JMP_SYSENTER_X86:
+ /* Do whatever simulation is appropriate for an x86 sysenter
+ instruction. Note that it is critical to set this thread's
+ guest_EIP to point at the code to execute after the
+ sysenter, since Vex-generated code will not have set it --
+ vex does not know what it should be. Vex sets the next
+ address to zero, so if you don't guest_EIP, the thread will
+ jump to zero afterwards and probably die as a result. */
+# if defined(VGA_x86)
+ //FIXME: VG_(threads)[tid].arch.vex.guest_EIP =3D ....
+ //handle_sysenter_x86(tid);
+ vg_assert2(0, "VG_(scheduler), phase 3: "
+ "sysenter_x86 on not yet implemented");
+# else
+ vg_assert2(0, "VG_(scheduler), phase 3: "
+ "sysenter_x86 on non-x86 platform?!?!");
+# endif
+
default:=20
vg_assert2(0, "VG_(scheduler), phase 3: "
"unexpected thread return code (%u)", trc);
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