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From: <sv...@va...> - 2005-07-01 21:16:52
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Author: cerion
Date: 2005-07-01 22:16:10 +0100 (Fri, 01 Jul 2005)
New Revision: 1245
Log:
Implemented altivec load: lvx - xfontsel runs now (tool=3Dnone)
plus a little cleaning of toIR.c
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-07-01 18:56:33 UTC (rev 1244)
+++ trunk/priv/guest-ppc32/toIR.c 2005-07-01 21:16:10 UTC (rev 1245)
@@ -653,16 +653,13 @@
return IRExpr_Get( vectorGuestRegOffset(archreg), Ity_V128 );
}
=20
-#if 0
/* Ditto, but write to a reg instead. */
-/* apparently unused, jrs 2005-06-30 */
static void putVReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 32);
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_V128);
stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) );
}
-#endif
=20
static void assign ( IRTemp dst, IRExpr* e )
{
@@ -903,6 +900,7 @@
break;
=20
case PPC32_SPR_CTR:
+ vassert(mask =3D=3D 0xFFFFFFFF); // Only ever need whole reg
assign( val, IRExpr_Get(OFFB_CTR, Ity_I32) );
break;
=20
@@ -1011,9 +1009,6 @@
/* Write masked src to the given reg */
static void putReg_masked ( PPC32SPR reg, IRExpr* src, UInt mask )
{
- IRTemp src_mskd =3D newTemp(Ity_I32);
- IRTemp reg_old =3D newTemp(Ity_I32);
-
vassert( reg < PPC32_SPR_MAX );
vassert( typeOfIRExpr(irbb->tyenv,src ) =3D=3D Ity_I32 );
=20
@@ -1036,10 +1031,10 @@
case PPC32_SPR_XER:
// Bits 7-28 are 'Reserved'. Ignoring writes these bits.
// (They may be written to, but reading them gives zero or undefin=
ed)
- assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0xE000007F)) =
);
- assign( reg_old, getReg_masked( PPC32_SPR_XER, (~mask & 0xE000007F=
) ) );
stmt( IRStmt_Put( OFFB_XER,
- binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
+ binop(Iop_Or32,
+ binop(Iop_And32, src, mkU32(mask & 0xE000007F)),
+ getReg_masked( PPC32_SPR_XER, (~mask & 0xE000007F) =
))));
break;
=20
case PPC32_SPR_CR: {
@@ -1052,7 +1047,7 @@
binop(Iop_And32, src, mkU32(mask & 0xF0000000)),
getReg_masked( PPC32_SPR_CR, (~mask & 0xF0000000=
) ))));
}
- if (mask & 0xFFFFFFF) { // CR fields 0 t o6:
+ if (mask & 0x0FFFFFFF) { // CR fields 0 to 6:
stmt( IRStmt_Put( OFFB_CR0to6,
binop(Iop_Or32,
binop(Iop_And32, src, mkU32(mask & 0x0FFFFFFF)),
@@ -1099,6 +1094,7 @@
break;
=20
case PPC32_SPR_VRSAVE:
+ vassert(mask =3D=3D 0xFFFFFFFF); // Only ever need whole reg
stmt( IRStmt_Put( OFFB_VRSAVE, src ) );
break;
=20
@@ -1106,10 +1102,10 @@
//CAB: There are only 2 valid bits in VSCR - maybe split into two vars..=
.
=20
// All other bits are 'Reserved'. Ignoring writes to these bits.
- assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0x00010001)) =
);
- assign( reg_old, getReg_masked( PPC32_SPR_VSCR, (~mask & 0x0001000=
1) ) );
stmt( IRStmt_Put( OFFB_VSCR,
- binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
+ binop(Iop_Or32,
+ binop(Iop_And32, src, mkU32(mask & 0x00010001)),
+ getReg_masked( PPC32_SPR_VSCR, (~mask & 0x00010001)=
))));
break;
}
=20
@@ -2685,7 +2681,10 @@
putReg_field( PPC32_SPR_CR, mkexpr(tmp), (7-crfD_addr) );
} else {
assign( crbA, getReg_bit( PPC32_SPR_CR, (31-crbA_addr) ) );
- assign( crbB, getReg_bit( PPC32_SPR_CR, (31-crbB_addr) ) );
+ if (crbA_addr =3D=3D crbB_addr)
+ assign( crbB, mkexpr(crbA) );
+ else
+ assign( crbB, getReg_bit( PPC32_SPR_CR, (31-crbB_addr) ) );
=20
switch (opc2) {
case 0x101: // crand (Cond Reg AND, PPC32 p372)
@@ -4450,11 +4449,18 @@
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
+ IRTemp EA =3D newTemp(Ity_I32);
+ IRTemp EA_aligned =3D newTemp(Ity_I32);
+
if (opc1 !=3D 0x1F || b0 !=3D 0) {
vex_printf("dis_av_load(PPC32)(instr)\n");
return False;
}
=20
+ assign( EA, binop(Iop_Add32,
+ ((rA_addr =3D=3D 0) ? mkU32(0) : getIReg(rA_addr)),
+ getIReg(rB_addr) ));
+
switch (opc2) {
=20
case 0x006: // lvsl (Load Vector for Shift Left, AV p123)
@@ -4484,8 +4490,9 @@
=20
case 0x067: // lvx (Load Vector Indexed, AV p127)
DIP("lvx v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( EA_aligned, binop( Iop_And32, mkexpr(EA), mkU32(0xFFFFFFF0=
) ));
+ putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_aligned)) );
+ break;
=20
case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
// XXX: lvxl gives explicit control over cache block replacement
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-07-01 18:56:33 UTC (rev 1244)
+++ trunk/priv/host-ppc32/isel.c 2005-07-01 21:16:10 UTC (rev 1245)
@@ -2816,13 +2816,15 @@
return dst;
}
=20
-//.. if (e->tag =3D=3D Iex_LDle) {
-//.. HReg dst =3D newVRegV(env);
-//.. X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
-//.. addInstr(env, X86Instr_SseLdSt( True/*load*/, dst, am ));
-//.. return dst;
-//.. }
-//..=20
+ if (e->tag =3D=3D Iex_Load) {
+ PPC32AMode* am_addr;
+ HReg v_dst =3D newVRegV(env);
+ vassert(e->Iex.Load.ty =3D=3D Ity_V128);
+ am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ addInstr(env, PPC32Instr_AvLdSt( True/*load*/, 16, v_dst, am_addr)=
);
+ return v_dst;
+ }
+
//.. if (e->tag =3D=3D Iex_Const) {
//.. HReg dst =3D newVRegV(env);
//.. vassert(e->Iex.Const.con->tag =3D=3D Ico_V128);
@@ -3274,7 +3276,7 @@
ppIRStmt(stmt);
vex_printf("\n");
}
- =20
+
switch (stmt->tag) {
=20
/* --------- STORE --------- */
@@ -3339,12 +3341,12 @@
addInstr(env, PPC32Instr_Store( 4, am_addr4, rLo ));
return;
}
-//.. if (ty =3D=3D Ity_V128) {
-//.. HReg vec =3D iselVecExpr(env, stmt->Ist.Put.data);
-//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, am));
-//.. return;
-//.. }
+ if (ty =3D=3D Ity_V128) {
+ HReg v_src =3D iselVecExpr(env, stmt->Ist.Put.data);
+ PPC32AMode* am_addr =3D PPC32AMode_IR(stmt->Ist.Put.offset, Gu=
estStatePtr);
+ addInstr(env, PPC32Instr_AvLdSt(False/*store*/, 16, v_src, am_a=
ddr));
+ return;
+ }
//.. if (ty =3D=3D Ity_F32) {
//.. HReg f32 =3D iselFltExpr(env, stmt->Ist.Put.data);
//.. X86AMode* am =3D X86AMode_IR(stmt->Ist.Put.offset, hregX8=
6_EBP());
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