|
From: <sv...@va...> - 2005-07-01 18:56:36
|
Author: cerion
Date: 2005-07-01 19:56:33 +0100 (Fri, 01 Jul 2005)
New Revision: 1244
Log:
Cleaned up read/write register functions, wrt XER, and fixed a bug for wr=
ite to VSCR.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-07-01 18:44:52 UTC (rev 1243)
+++ trunk/priv/guest-ppc32/toIR.c 2005-07-01 18:56:33 UTC (rev 1244)
@@ -907,9 +907,9 @@
break;
=20
case PPC32_SPR_XER:
- vassert((mask & 0xF000007F) =3D=3D mask); // Only valid bits of xe=
r
- // actually, bit28 not valid, but sometimes asked for anyway - alw=
ays 0:
- mask =3D mask & ~(1<<28);
+ // Bits 7-28 are 'Reserved'. Always return zero for these bits.
+ // (They may be written to, but reading them gives zero or undefin=
ed)
+ mask =3D mask & 0xE000007F;
assign( val, IRExpr_Get(OFFB_XER, Ity_I32) );
break;
=20
@@ -955,7 +955,6 @@
mask =3D mask & 0x00010001;
assign( val, IRExpr_Get(OFFB_VSCR, Ity_I32) );
break;
- break;
=20
default:
vpanic("getReg(ppc32)");
@@ -972,12 +971,7 @@
static IRExpr* getReg ( PPC32SPR reg )
{
vassert( reg < PPC32_SPR_MAX );
- switch (reg) {
- case PPC32_SPR_XER:
- return getReg_masked( reg, 0xE000007F ); // Only valid bits of xer
- default:
- return getReg_masked( reg, 0xFFFFFFFF );
- }
+ return getReg_masked( reg, 0xFFFFFFFF );
}
=20
/* Get a right-shifted nibble from given reg[field_idx]
@@ -1040,12 +1034,10 @@
break;
=20
case PPC32_SPR_XER:
- vassert((mask & 0xF000007F) =3D=3D mask); // Only valid bits of xe=
r
- // actually, bit28 not valid, but sometimes asked for anyway - alw=
ays 0:
- mask =3D mask & ~(1<<28);
- assign( src_mskd, binop(Iop_And32, src, mkU32(mask)) );
+ // Bits 7-28 are 'Reserved'. Ignoring writes these bits.
+ // (They may be written to, but reading them gives zero or undefin=
ed)
+ assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0xE000007F)) =
);
assign( reg_old, getReg_masked( PPC32_SPR_XER, (~mask & 0xE000007F=
) ) );
-
stmt( IRStmt_Put( OFFB_XER,
binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
break;
@@ -1100,6 +1092,10 @@
)
);
}
+
+ /*
+ Ignore all other writes
+ */
break;
=20
case PPC32_SPR_VRSAVE:
@@ -1111,15 +1107,10 @@
=20
// All other bits are 'Reserved'. Ignoring writes to these bits.
assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0x00010001)) =
);
- assign( reg_old, getReg_masked( PPC32_SPR_XER, (~mask & 0x00010001=
) ) );
+ assign( reg_old, getReg_masked( PPC32_SPR_VSCR, (~mask & 0x0001000=
1) ) );
stmt( IRStmt_Put( OFFB_VSCR,
binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
break;
-
- /*
- Ignore all other writes
- */
- break;
}
=20
default:
@@ -1132,15 +1123,7 @@
{
vassert( typeOfIRExpr(irbb->tyenv,src ) =3D=3D Ity_I32 );
vassert( reg < PPC32_SPR_MAX );
-
- switch (reg) {
- case PPC32_SPR_XER:
- putReg_masked( reg, src, 0xE000007F ); // Only valid bits of xer
- break;
- default:
- putReg_masked( reg, src, 0xFFFFFFFF );
- break;
- }
+ putReg_masked( reg, src, 0xFFFFFFFF );
}
=20
/* Write least-significant nibble of src to reg[field_idx] */
|