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From: <sv...@va...> - 2005-07-01 18:44:57
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Author: cerion
Date: 2005-07-01 19:44:52 +0100 (Fri, 01 Jul 2005)
New Revision: 1243
Log:
Fixed a couple of bugs relating to condition register reading/writing, an=
d conditional register logic
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-07-01 18:41:01 UTC (rev 1242)
+++ trunk/priv/guest-ppc32/toIR.c 2005-07-01 18:44:52 UTC (rev 1243)
@@ -838,7 +838,7 @@
xer_so =3D getReg_bit( PPC32_SPR_XER, SHIFT_XER_SO );
=20
// =3D> Delaying calculating result until needed...
- stmt( IRStmt_Put( OFFB_CC_OP, mkU32(0) ));
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU32(0)/*calc from DEP1,DEP2*/ ));
stmt( IRStmt_Put( OFFB_CC_DEP1, result ));
stmt( IRStmt_Put( OFFB_CC_DEP2, xer_so ));
}
@@ -914,13 +914,16 @@
break;
=20
case PPC32_SPR_CR:
- if (mask & 0xF0000000) {
+ if ((mask & 0xF0000000) =3D=3D mask) { // CR7 only
// Call helper function to calculate latest CR7 from thunk:
- // ... and OR it with CR0to6
+ assign( val, mk_ppc32g_calculate_cr7() );
+ }
+ else if ((mask & 0x0FFFFFFF) =3D=3D mask) { // CR0to6 only
+ assign( val, IRExpr_Get(OFFB_CR0to6, Ity_I32) );
+ }
+ else { // Both
assign( val, binop(Iop_Or32, mk_ppc32g_calculate_cr7(),
IRExpr_Get(OFFB_CR0to6, Ity_I32)) );
- } else {
- assign( val, IRExpr_Get(OFFB_CR0to6, Ity_I32) );
}
break;
=20
@@ -1048,21 +1051,21 @@
break;
=20
case PPC32_SPR_CR: {
- if (mask & 0xF0000000) { // CR 7:
- /* Write exactly the given flags to field CR7
- Set the flags thunk OP=3D1, DEP1=3Dflags, DEP2=3D0(unused). =
*/
-
- // =3D> Delaying calculation until needed...
- stmt( IRStmt_Put( OFFB_CC_OP, mkU32(1) ) );
- stmt( IRStmt_Put( OFFB_CC_DEP1, src ) ); // masked in hel=
per.
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) ) );
+ if (mask & 0xF0000000) { // CR field 7:
+ /* Set the CR7 flags thunk */
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU32(1)/*set imm value DEP1*/ =
) );
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0)/*=3Dunused*/ ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1,
+ binop(Iop_Or32,
+ binop(Iop_And32, src, mkU32(mask & 0xF0000000)),
+ getReg_masked( PPC32_SPR_CR, (~mask & 0xF0000000=
) ))));
}
- // CR 0 to 6:
- assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0x0FFFFFFF)) =
);
- assign( reg_old, getReg_masked( PPC32_SPR_CR, (~mask & 0x0FFFFFFF)=
) );
-
- stmt( IRStmt_Put( OFFB_CR0to6,
- binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
+ if (mask & 0xFFFFFFF) { // CR fields 0 t o6:
+ stmt( IRStmt_Put( OFFB_CR0to6,
+ binop(Iop_Or32,
+ binop(Iop_And32, src, mkU32(mask & 0x0FFFFFFF)),
+ getReg_masked( PPC32_SPR_CR, (~mask & 0x0FFFFFFF=
) ))));
+ }
break;
}
=20
@@ -1097,6 +1100,7 @@
)
);
}
+ break;
=20
case PPC32_SPR_VRSAVE:
stmt( IRStmt_Put( OFFB_VRSAVE, src ) );
@@ -2744,7 +2748,7 @@
return False;
}
=20
- putReg_masked( PPC32_SPR_CR, mkexpr(crbD), 1<<(31-crbD_addr) );
+ putReg_bit( PPC32_SPR_CR, mkexpr(crbD), (31-crbD_addr) );
}
return True;
}
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