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From: <sv...@va...> - 2005-05-18 11:47:54
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Author: sewardj
Date: 2005-05-18 12:47:47 +0100 (Wed, 18 May 2005)
New Revision: 1200
Modified:
trunk/priv/guest-amd64/toIR.c
Log:
Handle XCHG rAX, reg for 32-bit regs as well as 64-bit regs. I'm not
sure this is right -- the AMD64 docs are very difficult to interpret
on the subtle point of precisely what is and isn't to be regarded as a
no-op.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-18 10:22:47 UTC (rev 1199)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-18 11:47:47 UTC (rev 1200)
@@ -6916,15 +6916,22 @@
IRType ty =3D szToITy(sz);
IRTemp t1 =3D newTemp(ty);
IRTemp t2 =3D newTemp(ty);
- vassert(sz =3D=3D 8);
+ vassert(sz =3D=3D 4 || sz =3D=3D 8);
vassert(regLo3 < 8);
- assign( t1, getIReg64(R_RAX) );
- assign( t2, getIRegRexB(8,pfx, regLo3) );
- putIReg64( R_RAX, mkexpr(t2) );
- putIRegRexB(8, pfx, regLo3, mkexpr(t1) );
+ if (sz =3D=3D 8) {
+ assign( t1, getIReg64(R_RAX) );
+ assign( t2, getIRegRexB(8, pfx, regLo3) );
+ putIReg64( R_RAX, mkexpr(t2) );
+ putIRegRexB(8, pfx, regLo3, mkexpr(t1) );
+ } else {
+ assign( t1, getIReg32(R_RAX) );
+ assign( t2, getIRegRexB(4, pfx, regLo3) );
+ putIReg32( R_RAX, mkexpr(t2) );
+ putIRegRexB(4, pfx, regLo3, mkexpr(t1) );
+ }
DIP("xchg%c %s, %s\n",=20
nameISize(sz), nameIRegRAX(sz),=20
- nameIRegRexB(8,pfx, regLo3));
+ nameIRegRexB(sz,pfx, regLo3));
}
=20
=20
@@ -12746,9 +12753,15 @@
break;
=20
case 0x90: /* XCHG eAX,eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- DIP("nop\n");
- break;
+ /* detect and handle NOPs specially */
+ if (/* F2/F3 probably change meaning completely */
+ !haveF2orF3(pfx)
+ /* If REX.B is 1, we're not exchanging rAX with itself */
+ && getRexB(pfx)=3D=3D0 ) {
+ DIP("nop\n");
+ break;
+ }
+ /* else fall through to normal case. */
case 0x91: /* XCHG rAX,rCX */
case 0x92: /* XCHG rAX,rDX */
case 0x93: /* XCHG rAX,rBX */
@@ -12756,8 +12769,13 @@
case 0x95: /* XCHG rAX,rBP */
case 0x96: /* XCHG rAX,rSI */
case 0x97: /* XCHG rAX,rDI */
+
+ /* guard against mutancy */
if (haveF2orF3(pfx)) goto decode_failure;
- if (sz !=3D 8) goto decode_failure; /* temp hack */
+
+ /* sz =3D=3D 2 could legitimately happen, but we don't handle it y=
et */
+ if (sz =3D=3D 2) goto decode_failure; /* awaiting test case */
+
codegen_xchg_rAX_Reg ( pfx, sz, opc - 0x90 );
break;
=20
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