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From: <sv...@va...> - 2005-05-07 01:01:34
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Author: sewardj
Date: 2005-05-07 02:01:24 +0100 (Sat, 07 May 2005)
New Revision: 1169
Modified:
trunk/priv/guest-amd64/toIR.c
Log:
More x87 instructions.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-06 16:30:21 UTC (rev 1168)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-07 01:01:24 UTC (rev 1169)
@@ -4405,10 +4405,10 @@
fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, Fal=
se );
break;
=20
-//.. case 1: /* FMUL single-real */
-//.. fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64=
, False );
-//.. break;
-//..=20
+ case 1: /* FMUL single-real */
+ fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, Fal=
se );
+ break;
+
//.. case 2: /* FCOM single-real */
//.. DIP("fcoms %s\n", dis_buf);
//.. /* This forces C1 to zero, which isn't right. */
@@ -4439,23 +4439,23 @@
//.. ));
//.. fp_pop();
//.. break; =20
-//..=20
-//.. case 4: /* FSUB single-real */
-//.. fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64=
, False );
-//.. break;
=20
+ case 4: /* FSUB single-real */
+ fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, Fal=
se );
+ break;
+
case 5: /* FSUBR single-real */
fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64,=
False );
break;
=20
-//.. case 6: /* FDIV single-real */
-//.. fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64=
, False );
-//.. break;
-//..=20
-//.. case 7: /* FDIVR single-real */
-//.. fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_Di=
vF64, False );
-//.. break;
+ case 6: /* FDIV single-real */
+ fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, Fal=
se );
+ break;
=20
+ case 7: /* FDIVR single-real */
+ fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64,=
False );
+ break;
+
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
vex_printf("first_opcode =3D=3D 0xD8\n");
@@ -4508,9 +4508,9 @@
fp_do_op_ST_ST ( "sub", Iop_SubF64, modrm - 0xE0, 0, Fals=
e );
break;
=20
-//.. case 0xE8 ... 0xEF: /* FSUBR %st(?),%st(0) */
-//.. fp_do_oprev_ST_ST ( "subr", Iop_SubF64, modrm - 0xE8=
, 0, False );
-//.. break;
+ case 0xE8 ... 0xEF: /* FSUBR %st(?),%st(0) */
+ fp_do_oprev_ST_ST ( "subr", Iop_SubF64, modrm - 0xE8, 0, =
False );
+ break;
=20
case 0xF0 ... 0xF7: /* FDIV %st(?),%st(0) */
fp_do_op_ST_ST ( "div", Iop_DivF64, modrm - 0xF0, 0, Fals=
e );
@@ -4890,12 +4890,12 @@
//.. get_ST(1), get_ST(0)));
//.. fp_pop();
//.. break;
-//..=20
-//.. case 0xFA: /* FSQRT */
-//.. DIP("fsqrt\n");
-//.. put_ST_UNCHECKED(0, unop(Iop_SqrtF64, get_ST(0)));
-//.. break;
-//..=20
+
+ case 0xFA: /* FSQRT */
+ DIP("fsqrt\n");
+ put_ST_UNCHECKED(0, unop(Iop_SqrtF64, get_ST(0)));
+ break;
+
//.. case 0xFB: { /* FSINCOS */
//.. IRTemp a1 =3D newTemp(Ity_F64);
//.. assign( a1, get_ST(0) );
@@ -5263,14 +5263,14 @@
=20
switch (gregLO3ofRM(modrm)) {
=20
-//.. case 0: /* FADD double-real */
-//.. fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64=
, True );
-//.. break;
-//..=20
-//.. case 1: /* FMUL double-real */
-//.. fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64=
, True );
-//.. break;
-//..=20
+ case 0: /* FADD double-real */
+ fp_do_op_mem_ST_0 ( addr, "add", dis_buf, Iop_AddF64, Tru=
e );
+ break;
+
+ case 1: /* FMUL double-real */
+ fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, Tru=
e );
+ break;
+
//.. case 2: /* FCOM double-real */
//.. DIP("fcoml %s\n", dis_buf);
//.. /* This forces C1 to zero, which isn't right. */
@@ -5299,23 +5299,23 @@
//.. ));
//.. fp_pop();
//.. break; =20
-//..=20
-//.. case 4: /* FSUB double-real */
-//.. fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64=
, True );
-//.. break;
=20
+ case 4: /* FSUB double-real */
+ fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, Tru=
e );
+ break;
+
case 5: /* FSUBR double-real */
fp_do_oprev_mem_ST_0 ( addr, "subr", dis_buf, Iop_SubF64,=
True );
break;
=20
-//.. case 6: /* FDIV double-real */
-//.. fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64=
, True );
-//.. break;
-//..=20
-//.. case 7: /* FDIVR double-real */
-//.. fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_Di=
vF64, True );
-//.. break;
+ case 6: /* FDIV double-real */
+ fp_do_op_mem_ST_0 ( addr, "div", dis_buf, Iop_DivF64, Tru=
e );
+ break;
=20
+ case 7: /* FDIVR double-real */
+ fp_do_oprev_mem_ST_0 ( addr, "divr", dis_buf, Iop_DivF64,=
True );
+ break;
+
default:
vex_printf("unhandled opc_aux =3D 0x%2x\n", gregLO3ofRM(m=
odrm));
vex_printf("first_opcode =3D=3D 0xDC\n");
@@ -5339,14 +5339,14 @@
fp_do_oprev_ST_ST ( "subr", Iop_SubF64, 0, modrm - 0xE0, =
False );
break;
=20
-//.. case 0xE8 ... 0xEF: /* FSUB %st(0),%st(?) */
-//.. fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8,=
False );
-//.. break;
-//..=20
-//.. case 0xF0 ... 0xF7: /* FDIVR %st(0),%st(?) */
-//.. fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0=
xF0, False );
-//.. break;
+ case 0xE8 ... 0xEF: /* FSUB %st(0),%st(?) */
+ fp_do_op_ST_ST ( "sub", Iop_SubF64, 0, modrm - 0xE8, Fals=
e );
+ break;
=20
+ case 0xF0 ... 0xF7: /* FDIVR %st(0),%st(?) */
+ fp_do_oprev_ST_ST ( "divr", Iop_DivF64, 0, modrm - 0xF0, =
False );
+ break;
+
case 0xF8 ... 0xFF: /* FDIV %st(0),%st(?) */
fp_do_op_ST_ST ( "div", Iop_DivF64, 0, modrm - 0xF8, Fals=
e );
break;
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