|
From: <sv...@va...> - 2005-05-05 12:06:01
|
Author: sewardj
Date: 2005-05-05 13:05:54 +0100 (Thu, 05 May 2005)
New Revision: 1162
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/host-amd64/hdefs.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
Log:
Play a few more rounds of the SSE game on amd64.
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/guest-amd64/toIR.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -9164,12 +9164,13 @@
//.. goto after_sse_decoders;
//..=20
//.. insn =3D (UChar*)&guest_code[delta];
-//..=20
-//.. /* 66 0F 58 =3D ADDPD -- add 32Fx4 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "addpd", Iop_Add=
64Fx2 );
-//.. goto decode_success;
-//.. }
+
+ /* 66 0F 58 =3D ADDPD -- add 32Fx4 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "addpd", Iop_Add64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 58 =3D ADDSD -- add 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x58=
) {
@@ -9893,21 +9894,21 @@
goto decode_success;
}
=20
-//.. /* 66 0F 29 =3D MOVAPD -- move from G (xmm) to E (mem or xmm). *=
/
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x29) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. /* fall through; awaiting test case */
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. storeLE( mkexpr(addr), getXMMReg(gregOfRM(modrm)) );
-//.. DIP("movapd %s,%s\n", nameXMMReg(gregOfRM(modrm)),
-//.. dis_buf );
-//.. delta +=3D 2+alen;
-//.. goto decode_success;
-//.. }
-//.. }
-//..=20
+ /* 66 0F 29 =3D MOVAPD -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x29=
) {
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ /* fall through; awaiting test case */
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movapd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta +=3D 2+alen;
+ goto decode_success;
+ }
+ }
+
//.. /* 66 0F 6E =3D MOVD from r/m32 to xmm, zeroing high 3/4 of xmm.=
*/
//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x6E) {
//.. modrm =3D getUChar(delta+2);
@@ -10028,42 +10029,42 @@
//.. /* fall through, apparently no mem case for this insn */
//.. }
//.. }
-//..=20
-//.. /* 66 0F 16 =3D MOVHPD -- move from mem to high half of XMM. */
-//.. /* These seems identical to MOVHPS. This instruction encoding i=
s
-//.. completely crazy. */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x16) {
-//.. modrm =3D getUChar(delta+2);
-//.. if (epartIsReg(modrm)) {
-//.. /* fall through; apparently reg-reg is not possible */
-//.. } else {
-//.. addr =3D disAMode ( &alen, sorb, delta+2, dis_buf );
-//.. delta +=3D 2+alen;
-//.. putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
-//.. loadLE(Ity_I64, mkexpr(addr)) );
-//.. DIP("movhpd %s,%s\n", dis_buf,=20
-//.. nameXMMReg( gregOfRM(modrm) ));
-//.. goto decode_success;
-//.. }
-//.. }
-//..=20
-//.. /* 66 0F 17 =3D MOVHPD -- move from high half of XMM to mem. */
-//.. /* Again, this seems identical to MOVHPS. */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x17) {
-//.. if (!epartIsReg(insn[2])) {
-//.. delta +=3D 2;
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. delta +=3D alen;
-//.. storeLE( mkexpr(addr),=20
-//.. getXMMRegLane64( gregOfRM(insn[2]),
-//.. 1/*upper lane*/ ) );
-//.. DIP("movhpd %s,%s\n", nameXMMReg( gregOfRM(insn[2]) ),
-//.. dis_buf);
-//.. goto decode_success;
-//.. }
-//.. /* else fall through */
-//.. }
=20
+ /* 66 0F 16 =3D MOVHPD -- move from mem to high half of XMM. */
+ /* These seems identical to MOVHPS. This instruction encoding is
+ completely crazy. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x16=
) {
+ modrm =3D getUChar(delta+2);
+ if (epartIsReg(modrm)) {
+ /* fall through; apparently reg-reg is not possible */
+ } else {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movhpd %s,%s\n", dis_buf,=20
+ nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ goto decode_success;
+ }
+ }
+
+ /* 66 0F 17 =3D MOVHPD -- move from high half of XMM to mem. */
+ /* Again, this seems identical to MOVHPS. */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x17=
) {
+ if (!epartIsReg(insn[2])) {
+ delta +=3D 2;
+ addr =3D disAMode ( &alen, pfx, delta, dis_buf, 0 );
+ delta +=3D alen;
+ storeLE( mkexpr(addr),=20
+ getXMMRegLane64( gregOfRexRM(pfx,insn[2]),
+ 1/*upper lane*/ ) );
+ DIP("movhpd %s,%s\n", nameXMMReg( gregOfRexRM(pfx,insn[2]) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
/* 66 0F 12 =3D MOVLPD -- move from mem to low half of XMM. */
/* Identical to MOVLPS ? */
if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x12=
) {
@@ -10082,23 +10083,23 @@
}
}
=20
-//.. /* 66 0F 13 =3D MOVLPD -- move from low half of XMM to mem. */
-//.. /* Identical to MOVLPS ? */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x13) {
-//.. if (!epartIsReg(insn[2])) {
-//.. delta +=3D 2;
-//.. addr =3D disAMode ( &alen, sorb, delta, dis_buf );
-//.. delta +=3D alen;
-//.. storeLE( mkexpr(addr),=20
-//.. getXMMRegLane64( gregOfRM(insn[2]),=20
-//.. 0/*lower lane*/ ) );
-//.. DIP("movlpd %s, %s\n", nameXMMReg( gregOfRM(insn[2]) ),
-//.. dis_buf);
-//.. goto decode_success;
-//.. }
-//.. /* else fall through */
-//.. }
-//..=20
+ /* 66 0F 13 =3D MOVLPD -- move from low half of XMM to mem. */
+ /* Identical to MOVLPS ? */
+ if (have66noF2noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x13=
) {
+ modrm =3D getUChar(delta+2);
+ if (!epartIsReg(modrm)) {
+ addr =3D disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
+ delta +=3D 2+alen;
+ storeLE( mkexpr(addr),=20
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),=20
+ 0/*lower lane*/ ) );
+ DIP("movlpd %s, %s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+
//.. /* 66 0F 50 =3D MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(=
E) to
//.. 2 lowest bits of ireg(G) */
//.. if (insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x50) {
@@ -10237,11 +10238,12 @@
}
}
=20
-//.. /* 66 0F 59 =3D MULPD -- mul 64Fx2 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x59) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "mulpd", Iop_Mul=
64Fx2 );
-//.. goto decode_success;
-//.. }
+ /* 66 0F 59 =3D MULPD -- mul 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x59) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "mulpd", Iop_Mul64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 59 =3D MULSD -- mul 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && sz =3D=3D 4
@@ -10321,11 +10323,12 @@
goto decode_success;
}
=20
-//.. /* 66 0F 5C =3D SUBPD -- sub 64Fx2 from R/M to R */
-//.. if (sz =3D=3D 2 && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C) {
-//.. delta =3D dis_SSE_E_to_G_all( sorb, delta+2, "subpd", Iop_Sub=
64Fx2 );
-//.. goto decode_success;
-//.. }
+ /* 66 0F 5C =3D SUBPD -- sub 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz =3D=3D 2=20
+ && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C) {
+ delta =3D dis_SSE_E_to_G_all( pfx, delta+2, "subpd", Iop_Sub64Fx2 =
);
+ goto decode_success;
+ }
=20
/* F2 0F 5C =3D SUBSD -- sub 64F0x2 from R/M to R */
if (haveF2no66noF3(pfx) && insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0x5C=
) {
@@ -11836,11 +11839,12 @@
goto decode_failure;
}
=20
-//.. /* ------------------------ opl imm, A ----------------- */
-//..=20
-//.. case 0x04: /* ADD Ib, AL */
-//.. delta =3D dis_op_imm_A( 1, Iop_Add8, True, delta, "add" );
-//.. break;
+ /* ------------------------ opl imm, A ----------------- */
+
+ case 0x04: /* ADD Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta =3D dis_op_imm_A( 1, Iop_Add8, True, delta, "add" );
+ break;
case 0x05: /* ADD Iv, eAX */
if (haveF2orF3(pfx)) goto decode_failure;
delta =3D dis_op_imm_A(sz, Iop_Add8, True, delta, "add" );
Modified: trunk/priv/host-amd64/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/hdefs.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -966,15 +966,15 @@
vassert(op !=3D Asse_MOV);
return i;
}
-//.. AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp op, HReg src, HReg dst=
) {
-//.. AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag =3D Xin_Sse64Fx2;
-//.. i->Xin.Sse64Fx2.op =3D op;
-//.. i->Xin.Sse64Fx2.src =3D src;
-//.. i->Xin.Sse64Fx2.dst =3D dst;
-//.. vassert(op !=3D Xsse_MOV);
-//.. return i;
-//.. }
+AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp op, HReg src, HReg dst ) {
+ AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag =3D Ain_Sse64Fx2;
+ i->Ain.Sse64Fx2.op =3D op;
+ i->Ain.Sse64Fx2.src =3D src;
+ i->Ain.Sse64Fx2.dst =3D dst;
+ vassert(op !=3D Asse_MOV);
+ return i;
+}
AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i =3D LibVEX_Alloc(sizeof(AMD64Instr));
i->tag =3D Ain_Sse64FLo;
@@ -1279,12 +1279,12 @@
vex_printf(",");
ppHRegAMD64(i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. vex_printf("%spd ", showAMD64SseOp(i->Xin.Sse64Fx2.op));
-//.. ppHRegAMD64(i->Xin.Sse64Fx2.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ vex_printf("%spd ", showAMD64SseOp(i->Ain.Sse64Fx2.op));
+ ppHRegAMD64(i->Ain.Sse64Fx2.src);
+ vex_printf(",");
+ ppHRegAMD64(i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
vex_printf("%ssd ", showAMD64SseOp(i->Ain.Sse64FLo.op));
ppHRegAMD64(i->Ain.Sse64FLo.src);
@@ -1537,15 +1537,15 @@
addHRegUse(u, unary ? HRmWrite : HRmModify,=20
i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. vassert(i->Xin.Sse64Fx2.op !=3D Xsse_MOV);
-//.. unary =3D i->Xin.Sse64Fx2.op =3D=3D Xsse_RCPF
-//.. || i->Xin.Sse64Fx2.op =3D=3D Xsse_RSQRTF
-//.. || i->Xin.Sse64Fx2.op =3D=3D Xsse_SQRTF;
-//.. addHRegUse(u, HRmRead, i->Xin.Sse64Fx2.src);
-//.. addHRegUse(u, unary ? HRmWrite : HRmModify,=20
-//.. i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ vassert(i->Ain.Sse64Fx2.op !=3D Asse_MOV);
+ unary =3D i->Ain.Sse64Fx2.op =3D=3D Asse_RCPF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_RSQRTF
+ || i->Ain.Sse64Fx2.op =3D=3D Asse_SQRTF;
+ addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
+ addHRegUse(u, unary ? HRmWrite : HRmModify,=20
+ i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
vassert(i->Ain.Sse64FLo.op !=3D Asse_MOV);
unary =3D toBool( i->Ain.Sse64FLo.op =3D=3D Asse_RCPF
@@ -1721,10 +1721,10 @@
mapReg(m, &i->Ain.Sse32FLo.src);
mapReg(m, &i->Ain.Sse32FLo.dst);
return;
-//.. case Xin_Sse64Fx2:
-//.. mapReg(m, &i->Xin.Sse64Fx2.src);
-//.. mapReg(m, &i->Xin.Sse64Fx2.dst);
-//.. return;
+ case Ain_Sse64Fx2:
+ mapReg(m, &i->Ain.Sse64Fx2.src);
+ mapReg(m, &i->Ain.Sse64Fx2.dst);
+ return;
case Ain_Sse64FLo:
mapReg(m, &i->Ain.Sse64FLo.src);
mapReg(m, &i->Ain.Sse64FLo.dst);
@@ -3100,30 +3100,33 @@
*p++ =3D toUChar(xtra & 0xFF);
goto done;
=20
-//.. case Xin_Sse64Fx2:
-//.. xtra =3D 0;
-//.. *p++ =3D 0x66;
-//.. *p++ =3D 0x0F;
-//.. switch (i->Xin.Sse64Fx2.op) {
-//.. case Xsse_ADDF: *p++ =3D 0x58; break;
+ case Ain_Sse64Fx2:
+ xtra =3D 0;
+ *p++ =3D 0x66;
+ *p++ =3D clearWBit(
+ rexAMode_R( vreg2ireg(i->Ain.Sse64Fx2.dst),
+ vreg2ireg(i->Ain.Sse64Fx2.src) ));
+ *p++ =3D 0x0F;
+ switch (i->Ain.Sse64Fx2.op) {
+ case Asse_ADDF: *p++ =3D 0x58; break;
//.. case Xsse_DIVF: *p++ =3D 0x5E; break;
//.. case Xsse_MAXF: *p++ =3D 0x5F; break;
//.. case Xsse_MINF: *p++ =3D 0x5D; break;
-//.. case Xsse_MULF: *p++ =3D 0x59; break;
+ case Asse_MULF: *p++ =3D 0x59; break;
//.. case Xsse_RCPF: *p++ =3D 0x53; break;
//.. case Xsse_RSQRTF: *p++ =3D 0x52; break;
//.. case Xsse_SQRTF: *p++ =3D 0x51; break;
-//.. case Xsse_SUBF: *p++ =3D 0x5C; break;
+ case Asse_SUBF: *p++ =3D 0x5C; break;
//.. case Xsse_CMPEQF: *p++ =3D 0xC2; xtra =3D 0x100; break;
//.. case Xsse_CMPLTF: *p++ =3D 0xC2; xtra =3D 0x101; break;
//.. case Xsse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
-//.. default: goto bad;
-//.. }
-//.. p =3D doAMode_R(p, fake(vregNo(i->Xin.Sse64Fx2.dst)),
-//.. fake(vregNo(i->Xin.Sse64Fx2.src)) );
-//.. if (xtra & 0x100)
-//.. *p++ =3D (UChar)(xtra & 0xFF);
-//.. goto done;
+ default: goto bad;
+ }
+ p =3D doAMode_R(p, vreg2ireg(i->Ain.Sse64Fx2.dst),
+ vreg2ireg(i->Ain.Sse64Fx2.src) );
+ if (xtra & 0x100)
+ *p++ =3D (UChar)(xtra & 0xFF);
+ goto done;
=20
case Ain_Sse32FLo:
xtra =3D 0;
@@ -3144,7 +3147,7 @@
case Asse_SUBF: *p++ =3D 0x5C; break;
//.. case Xsse_CMPEQF: *p++ =3D 0xC2; xtra =3D 0x100; break;
case Asse_CMPLTF: *p++ =3D 0xC2; xtra =3D 0x101; break;
-//.. case Xsse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
+ case Asse_CMPLEF: *p++ =3D 0xC2; xtra =3D 0x102; break;
default: goto bad;
}
p =3D doAMode_R(p, vreg2ireg(i->Ain.Sse32FLo.dst),
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/hdefs.h 2005-05-05 12:05:54 UTC (rev 1162)
@@ -393,7 +393,7 @@
Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg *=
/
Ain_Sse32Fx4, /* SSE binary, 32Fx4 */
Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */
-//.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */
+ Ain_Sse64Fx2, /* SSE binary, 64Fx2 */
Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */
Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */
Ain_SseCMov, /* SSE conditional move */
@@ -620,15 +620,15 @@
HReg src;
HReg dst;
} Sse32FLo;
-//.. struct {
-//.. X86SseOp op;
-//.. HReg src;
-//.. HReg dst;
-//.. } Sse64Fx2;
struct {
AMD64SseOp op;
HReg src;
HReg dst;
+ } Sse64Fx2;
+ struct {
+ AMD64SseOp op;
+ HReg src;
+ HReg dst;
} Sse64FLo;
struct {
AMD64SseOp op;
@@ -691,7 +691,7 @@
extern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* );
extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg );
-//.. extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg );
+extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg =
dst );
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-05-05 12:05:11 UTC (rev 1161)
+++ trunk/priv/host-amd64/isel.c 2005-05-05 12:05:54 UTC (rev 1162)
@@ -3272,26 +3272,25 @@
//.. case Iop_CmpEQ64Fx2: op =3D Xsse_CMPEQF; goto do_64Fx2;
//.. case Iop_CmpLT64Fx2: op =3D Xsse_CMPLTF; goto do_64Fx2;
//.. case Iop_CmpLE64Fx2: op =3D Xsse_CMPLEF; goto do_64Fx2;
-//.. case Iop_Add64Fx2: op =3D Xsse_ADDF; goto do_64Fx2;
+ case Iop_Add64Fx2: op =3D Asse_ADDF; goto do_64Fx2;
//.. case Iop_Div64Fx2: op =3D Xsse_DIVF; goto do_64Fx2;
//.. case Iop_Max64Fx2: op =3D Xsse_MAXF; goto do_64Fx2;
//.. case Iop_Min64Fx2: op =3D Xsse_MINF; goto do_64Fx2;
-//.. case Iop_Mul64Fx2: op =3D Xsse_MULF; goto do_64Fx2;
-//.. case Iop_Sub64Fx2: op =3D Xsse_SUBF; goto do_64Fx2;
-//.. do_64Fx2:
-//.. {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse64Fx2(op, argR, dst));
-//.. return dst;
-//.. }
+ case Iop_Mul64Fx2: op =3D Asse_MULF; goto do_64Fx2;
+ case Iop_Sub64Fx2: op =3D Asse_SUBF; goto do_64Fx2;
+ do_64Fx2:
+ {
+ HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(argL, dst));
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
+ return dst;
+ }
=20
//.. case Iop_CmpEQ32F0x4: op =3D Xsse_CMPEQF; goto do_32F0x4;
case Iop_CmpLT32F0x4: op =3D Asse_CMPLTF; goto do_32F0x4;
-//.. case Iop_CmpLE32F0x4: op =3D Xsse_CMPLEF; goto do_32F0x4;
+ case Iop_CmpLE32F0x4: op =3D Asse_CMPLEF; goto do_32F0x4;
case Iop_Add32F0x4: op =3D Asse_ADDF; goto do_32F0x4;
case Iop_Div32F0x4: op =3D Asse_DIVF; goto do_32F0x4;
case Iop_Max32F0x4: op =3D Asse_MAXF; goto do_32F0x4;
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