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From: <sv...@va...> - 2005-04-27 11:55:19
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Author: sewardj
Date: 2005-04-27 12:55:08 +0100 (Wed, 27 Apr 2005)
New Revision: 1150
Modified:
trunk/priv/host-amd64/isel.c
Log:
Handle various more primops, and reorganise iselCondCode_wrk in line
with similar reorg on x86 side.
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-04-27 11:53:23 UTC (rev 1149)
+++ trunk/priv/host-amd64/isel.c 2005-04-27 11:55:08 UTC (rev 1150)
@@ -781,7 +781,7 @@
MatchInfo mi;
DECLARE_PATTERN(p_8Uto64);
DECLARE_PATTERN(p_16Uto64);
- DECLARE_PATTERN(p_1Uto8_32to1_64to32);
+ DECLARE_PATTERN(p_1Uto8_64to1);
//.. DECLARE_PATTERN(p_32to1_then_1Uto8);
=20
IRType ty =3D typeOfIRExpr(env->type_env,e);
@@ -1127,20 +1127,7 @@
=20
/* --------- UNARY OP --------- */
case Iex_Unop: {
- /* 32Uto64(16Uto32(expr16)) */
- DEFINE_PATTERN(p_16Uto64,
- unop(Iop_32Uto64, unop(Iop_16Uto32, bind(0)) ) );
- if (matchIRExpr(&mi,p_16Uto64,e)) {
- IRExpr* expr16 =3D mi.bindee[0];
- HReg dst =3D newVRegI(env);
- HReg src =3D iselIntExpr_R(env, expr16);
- addInstr(env, mk_iMOVsd_RR(src,dst) );
- addInstr(env, AMD64Instr_Sh64(Ash_SHL, 48, AMD64RM_Reg(dst)));
- addInstr(env, AMD64Instr_Sh64(Ash_SHR, 48, AMD64RM_Reg(dst)));
- return dst;
- }
-
- /* 32Uto64(8Uto32(expr16)) */
+ /* 32Uto64(8Uto32(expr8)) */
DEFINE_PATTERN(p_8Uto64,
unop(Iop_32Uto64, unop(Iop_8Uto32, bind(0)) ) );
if (matchIRExpr(&mi,p_8Uto64,e)) {
@@ -1153,11 +1140,10 @@
return dst;
}
=20
- /* 1Uto8(32to1(64to32(expr64))) */
- DEFINE_PATTERN(p_1Uto8_32to1_64to32,
- unop(Iop_1Uto8,=20
- unop(Iop_32to1, unop(Iop_64to32, bind(0)))));
- if (matchIRExpr(&mi,p_1Uto8_32to1_64to32,e)) {
+ /* 1Uto8(64to1(expr64)) */
+ DEFINE_PATTERN( p_1Uto8_64to1,
+ unop(Iop_1Uto8, unop(Iop_64to1, bind(0))) );
+ if (matchIRExpr(&mi,p_1Uto8_64to1,e)) {
IRExpr* expr64 =3D mi.bindee[0];
HReg dst =3D newVRegI(env);
HReg src =3D iselIntExpr_R(env, expr64);
@@ -1207,22 +1193,30 @@
return rLo; /* and abandon rHi */
}
case Iop_8Uto16:
- case Iop_8Uto32:
+// case Iop_8Uto32:
+ case Iop_8Uto64:
+ case Iop_16Uto64:
case Iop_16Uto32: {
- HReg dst =3D newVRegI(env);
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt mask =3D e->Iex.Unop.op=3D=3DIop_16Uto32 ? 0xFFFF : 0xF=
F;
+ HReg dst =3D newVRegI(env);
+ HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ Bool srcIs16 =3D e->Iex.Unop.op=3D=3DIop_16Uto32
+ || e->Iex.Unop.op=3D=3DIop_16Uto64;
+ UInt mask =3D srcIs16 ? 0xFFFF : 0xFF;
addInstr(env, mk_iMOVsd_RR(src,dst) );
addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
AMD64RMI_Imm(mask), dst));
return dst;
}
case Iop_8Sto16:
+ case Iop_8Sto64:
case Iop_8Sto32:
- case Iop_16Sto32: {
- HReg dst =3D newVRegI(env);
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt amt =3D e->Iex.Unop.op=3D=3DIop_16Sto32 ? 48 : 56;
+ case Iop_16Sto32:
+ case Iop_16Sto64: {
+ HReg dst =3D newVRegI(env);
+ HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ Bool srcIs16 =3D e->Iex.Unop.op=3D=3DIop_16Sto32
+ || e->Iex.Unop.op=3D=3DIop_16Sto64;
+ UInt amt =3D srcIs16 ? 48 : 56;
addInstr(env, mk_iMOVsd_RR(src,dst) );
addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, AMD64RM_Reg(dst)=
));
addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, AMD64RM_Reg(dst)=
));
@@ -1264,6 +1258,7 @@
Ash_SHR, shift, AMD64RM_Reg(dst)));
return dst;
}
+ case Iop_1Uto64:
case Iop_1Uto32:
case Iop_1Uto8: {
HReg dst =3D newVRegI(env);
@@ -1304,6 +1299,16 @@
AMD64RMI_Reg(tmp), dst));
return dst;
}
+ case Iop_Neg8:
+ case Iop_Neg16:
+ case Iop_Neg32:
+ case Iop_Neg64: {
+ HReg dst =3D newVRegI(env);
+ HReg reg =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, mk_iMOVsd_RR(reg,dst));
+ addInstr(env, AMD64Instr_Unary64(Aun_NEG,AMD64RM_Reg(dst)));
+ return dst;
+ }
=20
case Iop_V128to32: {
HReg dst =3D newVRegI(env);
@@ -1347,7 +1352,9 @@
=20
case Iop_16to8:
case Iop_32to8:
+ case Iop_64to8:
case Iop_32to16:
+ case Iop_64to16:
case Iop_64to32:
/* These are no-ops. */
return iselIntExpr_R(env, e->Iex.Unop.arg);
@@ -1749,6 +1756,15 @@
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) =3D=3D Ity_I1);
=20
+ /* var */
+ if (e->tag =3D=3D Iex_Tmp) {
+ HReg r64 =3D lookupIRTemp(env, e->Iex.Tmp.tmp);
+ HReg dst =3D newVRegI(env);
+ addInstr(env, mk_iMOVsd_RR(r64,dst));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
+ return Acc_NZ;
+ }
+
//.. /* Constant 1:Bit */
//.. if (e->tag =3D=3D Iex_Const && e->Iex.Const.con->Ico.U1 =3D=3D T=
rue) {
//.. HReg r;
@@ -1765,16 +1781,11 @@
return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
}
=20
- /* 32to1(64to32(32Uto64(1Uto32(expr1))))
- -- the casts are pointless, ignore them */
- DEFINE_PATTERN(
- p_1Uto64_then_64to1,
- unop(Iop_32to1,
- unop(Iop_64to32,
- unop(Iop_32Uto64,
- unop(Iop_1Uto32,
- bind(0)))))
- );
+ /* --- patterns rooted at: 64to1 --- */
+
+ /* 64to1(1Uto64(expr1)) =3D=3D> expr1 */
+ DEFINE_PATTERN( p_1Uto64_then_64to1,
+ unop(Iop_64to1, unop(Iop_1Uto64, bind(0))) );
if (matchIRExpr(&mi,p_1Uto64_then_64to1,e)) {
IRExpr* expr1 =3D mi.bindee[0];
return iselCondCode(env, expr1);
@@ -1796,16 +1807,49 @@
//.. return iselCondCode(env, expr1);
//.. }
=20
- /* pattern: 32to1(64to32(expr64)) */
- DEFINE_PATTERN(p_32to1_64to32,=20
- unop(Iop_32to1,unop(Iop_64to32, bind(0)))
- );
- if (matchIRExpr(&mi,p_32to1_64to32,e)) {
- AMD64RM* rm =3D iselIntExpr_RM(env, mi.bindee[0]);
+ /* 64to1 */
+ if (e->tag =3D=3D Iex_Unop && e->Iex.Unop.op =3D=3D Iop_64to1) {
+ AMD64RM* rm =3D iselIntExpr_RM(env, e->Iex.Unop.arg);
addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(1),rm));
return Acc_NZ;
}
=20
+ /* --- patterns rooted at: CmpNEZ8 --- */
+
+ /* CmpNEZ8(x) */
+ if (e->tag =3D=3D Iex_Unop=20
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ8) {
+ HReg r =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, AMD64Instr_Test64(AMD64RI_Imm(0xFF),AMD64RM_Reg(r)))=
;
+ return Acc_NZ;
+ }
+
+ /* --- patterns rooted at: CmpNEZ32 --- */
+
+ /* CmpNEZ32(x) */
+ if (e->tag =3D=3D Iex_Unop=20
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ32) {
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg tmp =3D newVRegI(env);
+ AMD64RMI* rmi2 =3D AMD64RMI_Imm(0);
+ addInstr(env, AMD64Instr_MovZLQ(r1,tmp));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,tmp));
+ return Acc_NZ;
+ }
+
+ /* --- patterns rooted at: CmpNEZ64 --- */
+
+ /* CmpNEZ64(x) */
+ if (e->tag =3D=3D Iex_Unop=20
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ AMD64RMI* rmi2 =3D AMD64RMI_Imm(0);
+ addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,r1));
+ return Acc_NZ;
+ }
+
+ /* --- patterns rooted at: Cmp{EQ,NE}{8,16,32} --- */
+
/* CmpEQ8 / CmpNE8 */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ8
@@ -1853,39 +1897,10 @@
switch (e->Iex.Binop.op) {
case Iop_CmpEQ32: return Acc_Z;
case Iop_CmpNE32: return Acc_NZ;
- default: vpanic("iselCondCode(amd64): CmpXX8");
+ default: vpanic("iselCondCode(amd64): CmpXX32");
}
}
=20
-
-//.. /* CmpEQ16 / CmpNE16 */
-//.. if (e->tag =3D=3D Iex_Binop=20
-//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ16
-//.. || e->Iex.Binop.op =3D=3D Iop_CmpNE16)) {
-//.. HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi2 =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//.. HReg r =3D newVRegI(env);
-//.. addInstr(env, mk_iMOVsd_RR(r1,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND,X86RMI_Imm(0xFFFF),r))=
;
-//.. switch (e->Iex.Binop.op) {
-//.. case Iop_CmpEQ16: return Xcc_Z;
-//.. case Iop_CmpNE16: return Xcc_NZ;
-//.. default: vpanic("iselCondCode(x86): CmpXX16");
-//.. }
-//.. }
-
- /* CmpNE32(1Sto32(b), 0) =3D=3D> b */
- {
- DECLARE_PATTERN(p_CmpNE32_1Sto32);
- DEFINE_PATTERN(
- p_CmpNE32_1Sto32,
- binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
- if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
- return iselCondCode(env, mi.bindee[0]);
- }
- }
-
/* Cmp*64*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ64
@@ -1956,15 +1971,6 @@
//.. }
//.. }
=20
- /* var */
- if (e->tag =3D=3D Iex_Tmp) {
- HReg r64 =3D lookupIRTemp(env, e->Iex.Tmp.tmp);
- HReg dst =3D newVRegI(env);
- addInstr(env, mk_iMOVsd_RR(r64,dst));
- addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
- return Acc_NZ;
- }
-
ppIRExpr(e);
vpanic("iselCondCode(amd64)");
}
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