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From: <sv...@va...> - 2005-04-23 22:42:33
|
Author: sewardj
Date: 2005-04-23 23:42:27 +0100 (Sat, 23 Apr 2005)
New Revision: 3546
Modified:
trunk/NOTES.txt
trunk/coregrind/amd64/core_arch.h
trunk/coregrind/x86/core_arch.h
trunk/include/amd64/tool_arch.h
trunk/include/x86/tool_arch.h
trunk/memcheck/mac_shared.h
Log:
Allow memcheck to take account of VGA_STACK_REDZONE_SIZE -- that is,
account for the fact that on amd64 (really, on amd64-linux) the area
up to 128 bytes below the stack pointer is accessible. This meant
moving the definitions of VGA_STACK_REDZONE_SIZE to tool-visible
places.
Modified: trunk/NOTES.txt
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/NOTES.txt 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/NOTES.txt 2005-04-23 22:42:27 UTC (rev 3546)
@@ -1,4 +1,14 @@
=20
+23 Apr 05 (memcheck-on-amd64 notes)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+If a thread is given an initial stack with address range [lo .. hi],
+we need to tell memcheck that the area [lo - VGA_STACK_REDZONE_SIZE
+.. hi] is valid, rather than just [lo .. hi] as has been the case on
+x86-only systems. However, am not sure where to look for the=20
+call into memcheck that states the new stack area.
+
+
9 Apr 05 (starting work on memcheck for 32/64-bit and big/little endian)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* get rid of memcheck/mc_asm.h and include/tool_asm.h. I think=20
Modified: trunk/coregrind/amd64/core_arch.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/amd64/core_arch.h 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/coregrind/amd64/core_arch.h 2005-04-23 22:42:27 UTC (rev 3546)
@@ -76,9 +76,6 @@
asm("movq %%rbp, %0" : "=3Dr" (lval)); \
} while (0)
=20
-// On AMD64, it's ok to access up to 128 bytes below %rsp.
-// The signal handler needs to know this.
-#define VGA_STACK_REDZONE_SIZE 128
=20
/* ---------------------------------------------------------------------
Architecture-specific part of a ThreadState
Modified: trunk/coregrind/x86/core_arch.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/x86/core_arch.h 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/coregrind/x86/core_arch.h 2005-04-23 22:42:27 UTC (rev 3546)
@@ -76,10 +76,6 @@
asm("movl %%ebp, %0" : "=3Dr" (ebp)); \
} while (0)
=20
-// On X86, any access below %esp is illegal.
-// The signal handler needs to know this.
-#define VGA_STACK_REDZONE_SIZE 0
-
//extern const Char VG_(helper_wrapper_before)[]; /* in dispatch.S */
//extern const Char VG_(helper_wrapper_return)[]; /* in dispatch.S */
=20
Modified: trunk/include/amd64/tool_arch.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/include/amd64/tool_arch.h 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/include/amd64/tool_arch.h 2005-04-23 22:42:27 UTC (rev 3546)
@@ -30,15 +30,20 @@
#ifndef __AMD64_TOOL_ARCH_H
#define __AMD64_TOOL_ARCH_H
=20
-/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
-/*=3D=3D=3D Registers, etc =
=3D=3D=3D*/
-/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
=20
-#define VGA_REGPARM(n)
+#define VGA_REGPARM(n) /* */
=20
+
#define VGA_MIN_INSTR_SIZE 1
#define VGA_MAX_INSTR_SIZE 16
=20
+
+/* How many bytes below the stack pointer are validly addressible?
+ On amd64, the answer is: 128.
+*/
+#define VGA_STACK_REDZONE_SIZE 128
+
+
#endif // __AMD64_TOOL_ARCH_H
=20
/*--------------------------------------------------------------------*/
Modified: trunk/include/x86/tool_arch.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/include/x86/tool_arch.h 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/include/x86/tool_arch.h 2005-04-23 22:42:27 UTC (rev 3546)
@@ -30,16 +30,20 @@
#ifndef __X86_TOOL_ARCH_H
#define __X86_TOOL_ARCH_H
=20
-/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
-/*=3D=3D=3D Registers, etc =
=3D=3D=3D*/
-/*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D*/
=20
#define VGA_REGPARM(n) __attribute__((regparm(n)))
=20
+
#define VGA_MIN_INSTR_SIZE 1
#define VGA_MAX_INSTR_SIZE 16
=20
=20
+/* How many bytes below the stack pointer are validly addressible?
+ On x86, the answer is: none.
+*/
+#define VGA_STACK_REDZONE_SIZE 0
+
+
#endif // __X86_TOOL_ARCH_H
=20
/*--------------------------------------------------------------------*/
Modified: trunk/memcheck/mac_shared.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mac_shared.h 2005-04-23 22:38:38 UTC (rev 3545)
+++ trunk/memcheck/mac_shared.h 2005-04-23 22:42:27 UTC (rev 3546)
@@ -437,163 +437,163 @@
factoring, rather than eg. using function pointers. =20
*/
=20
-#define SP_UPDATE_HANDLERS(ALIGNED4_NEW, ALIGNED4_DIE, \
- ALIGNED8_NEW, ALIGNED8_DIE, \
- UNALIGNED_NEW, UNALIGNED_DIE) \
- \
-void VGA_REGPARM(1) MAC_(new_mem_stack_4)(Addr new_SP) \
-{ \
- PROF_EVENT(110, "new_mem_stack_4"); \
- if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_NEW ( new_SP ); \
- } else { \
- UNALIGNED_NEW ( new_SP, 4 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(die_mem_stack_4)(Addr new_SP) \
-{ \
- PROF_EVENT(120, "die_mem_stack_4"); \
- if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_DIE ( new_SP-4 ); \
- } else { \
- UNALIGNED_DIE ( new_SP-4, 4 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(new_mem_stack_8)(Addr new_SP) \
-{ \
- PROF_EVENT(111, "new_mem_stack_8"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_NEW ( new_SP ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_NEW ( new_SP ); \
- ALIGNED4_NEW ( new_SP+4 ); \
- } else { \
- UNALIGNED_NEW ( new_SP, 8 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(die_mem_stack_8)(Addr new_SP) \
-{ \
- PROF_EVENT(121, "die_mem_stack_8"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_DIE ( new_SP-8 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_DIE ( new_SP-8 ); \
- ALIGNED4_DIE ( new_SP-4 ); \
- } else { \
- UNALIGNED_DIE ( new_SP-8, 8 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(new_mem_stack_12)(Addr new_SP) \
-{ \
- PROF_EVENT(112, "new_mem_stack_12"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_NEW ( new_SP ); \
- ALIGNED4_NEW ( new_SP+8 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_NEW ( new_SP ); \
- ALIGNED8_NEW ( new_SP+4 ); \
- } else { \
- UNALIGNED_NEW ( new_SP, 12 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(die_mem_stack_12)(Addr new_SP) \
-{ \
- PROF_EVENT(122, "die_mem_stack_12"); \
- /* Note the -12 in the test */ \
- if (VG_IS_8_ALIGNED(new_SP-12)) { \
- ALIGNED8_DIE ( new_SP-12 ); \
- ALIGNED4_DIE ( new_SP-4 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_DIE ( new_SP-12 ); \
- ALIGNED8_DIE ( new_SP-8 ); \
- } else { \
- UNALIGNED_DIE ( new_SP-12, 12 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(new_mem_stack_16)(Addr new_SP) \
-{ \
- PROF_EVENT(113, "new_mem_stack_16"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_NEW ( new_SP ); \
- ALIGNED8_NEW ( new_SP+8 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_NEW ( new_SP ); \
- ALIGNED8_NEW ( new_SP+4 ); \
- ALIGNED4_NEW ( new_SP+12 ); \
- } else { \
- UNALIGNED_NEW ( new_SP, 16 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(die_mem_stack_16)(Addr new_SP) \
-{ \
- PROF_EVENT(123, "die_mem_stack_16"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_DIE ( new_SP-16 ); \
- ALIGNED8_DIE ( new_SP-8 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_DIE ( new_SP-16 ); \
- ALIGNED8_DIE ( new_SP-12 ); \
- ALIGNED4_DIE ( new_SP-4 ); \
- } else { \
- UNALIGNED_DIE ( new_SP-16, 16 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(new_mem_stack_32)(Addr new_SP) \
-{ \
- PROF_EVENT(114, "new_mem_stack_32"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_NEW ( new_SP ); \
- ALIGNED8_NEW ( new_SP+8 ); \
- ALIGNED8_NEW ( new_SP+16 ); \
- ALIGNED8_NEW ( new_SP+24 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_NEW ( new_SP ); \
- ALIGNED8_NEW ( new_SP+4 ); \
- ALIGNED8_NEW ( new_SP+12 ); \
- ALIGNED8_NEW ( new_SP+20 ); \
- ALIGNED4_NEW ( new_SP+28 ); \
- } else { \
- UNALIGNED_NEW ( new_SP, 32 ); \
- } \
-} \
- \
-void VGA_REGPARM(1) MAC_(die_mem_stack_32)(Addr new_SP) \
-{ \
- PROF_EVENT(124, "die_mem_stack_32"); \
- if (VG_IS_8_ALIGNED(new_SP)) { \
- ALIGNED8_DIE ( new_SP-32 ); \
- ALIGNED8_DIE ( new_SP-24 ); \
- ALIGNED8_DIE ( new_SP-16 ); \
- ALIGNED8_DIE ( new_SP- 8 ); \
- } else if (VG_IS_4_ALIGNED(new_SP)) { \
- ALIGNED4_DIE ( new_SP-32 ); \
- ALIGNED8_DIE ( new_SP-28 ); \
- ALIGNED8_DIE ( new_SP-20 ); \
- ALIGNED8_DIE ( new_SP-12 ); \
- ALIGNED4_DIE ( new_SP-4 ); \
- } else { \
- UNALIGNED_DIE ( new_SP-32, 32 ); \
- } \
-} \
- \
-void MAC_(new_mem_stack) ( Addr a, SizeT len ) \
-{ \
- PROF_EVENT(115, "new_mem_stack"); \
- UNALIGNED_NEW ( a, len ); \
-} \
- \
-void MAC_(die_mem_stack) ( Addr a, SizeT len ) \
-{ \
- PROF_EVENT(125, "die_mem_stack"); \
- UNALIGNED_DIE ( a, len ); \
+#define SP_UPDATE_HANDLERS(ALIGNED4_NEW, ALIGNED4_DIE, \
+ ALIGNED8_NEW, ALIGNED8_DIE, \
+ UNALIGNED_NEW, UNALIGNED_DIE) \
+ \
+void VGA_REGPARM(1) MAC_(new_mem_stack_4)(Addr new_SP) \
+{ \
+ PROF_EVENT(110, "new_mem_stack_4"); \
+ if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ } else { \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP, 4 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(die_mem_stack_4)(Addr new_SP) \
+{ \
+ PROF_EVENT(120, "die_mem_stack_4"); \
+ if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4 ); \
+ } else { \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4, 4 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(new_mem_stack_8)(Addr new_SP) \
+{ \
+ PROF_EVENT(111, "new_mem_stack_8"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+4 ); \
+ } else { \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP, 8 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(die_mem_stack_8)(Addr new_SP) \
+{ \
+ PROF_EVENT(121, "die_mem_stack_8"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-8 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-8 ); \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4 ); \
+ } else { \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-8, 8 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(new_mem_stack_12)(Addr new_SP) \
+{ \
+ PROF_EVENT(112, "new_mem_stack_12"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+8 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+4 ); \
+ } else { \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP, 12 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(die_mem_stack_12)(Addr new_SP) \
+{ \
+ PROF_EVENT(122, "die_mem_stack_12"); \
+ /* Note the -12 in the test */ \
+ if (VG_IS_8_ALIGNED(new_SP-12)) { \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-12 ); \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-12 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-8 ); \
+ } else { \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-12, 12 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(new_mem_stack_16)(Addr new_SP) \
+{ \
+ PROF_EVENT(113, "new_mem_stack_16"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+8 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+4 ); \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+12 ); \
+ } else { \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP, 16 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(die_mem_stack_16)(Addr new_SP) \
+{ \
+ PROF_EVENT(123, "die_mem_stack_16"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-16 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-8 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-16 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-12 ); \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4 ); \
+ } else { \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-16, 16 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(new_mem_stack_32)(Addr new_SP) \
+{ \
+ PROF_EVENT(114, "new_mem_stack_32"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+8 ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+16 ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+24 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+4 ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+12 ); \
+ ALIGNED8_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+20 ); \
+ ALIGNED4_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP+28 ); \
+ } else { \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + new_SP, 32 ); \
+ } \
+} \
+ \
+void VGA_REGPARM(1) MAC_(die_mem_stack_32)(Addr new_SP) \
+{ \
+ PROF_EVENT(124, "die_mem_stack_32"); \
+ if (VG_IS_8_ALIGNED(new_SP)) { \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-32 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-24 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-16 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP- 8 ); \
+ } else if (VG_IS_4_ALIGNED(new_SP)) { \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-32 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-28 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-20 ); \
+ ALIGNED8_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-12 ); \
+ ALIGNED4_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-4 ); \
+ } else { \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + new_SP-32, 32 ); \
+ } \
+} \
+ \
+void MAC_(new_mem_stack) ( Addr a, SizeT len ) \
+{ \
+ PROF_EVENT(115, "new_mem_stack"); \
+ UNALIGNED_NEW ( -VGA_STACK_REDZONE_SIZE + a, len ); \
+} \
+ \
+void MAC_(die_mem_stack) ( Addr a, SizeT len ) \
+{ \
+ PROF_EVENT(125, "die_mem_stack"); \
+ UNALIGNED_DIE ( -VGA_STACK_REDZONE_SIZE + a, len ); \
}
=20
#endif /* __MAC_SHARED_H */
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