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From: <sv...@va...> - 2005-04-20 22:57:14
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Author: sewardj
Date: 2005-04-20 23:57:11 +0100 (Wed, 20 Apr 2005)
New Revision: 1132
Modified:
trunk/priv/host-amd64/isel.c
Log:
Fix some more insn selection cases required by Memcheck.
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-04-19 23:06:11 UTC (rev 1131)
+++ trunk/priv/host-amd64/isel.c 2005-04-20 22:57:11 UTC (rev 1132)
@@ -87,12 +87,12 @@
//.. {
//.. return IRExpr_Const(IRConst_U64(i));
//.. }
-//..=20
-//.. static IRExpr* mkU32 ( UInt i )
-//.. {
-//.. return IRExpr_Const(IRConst_U32(i));
-//.. }
=20
+static IRExpr* mkU32 ( UInt i )
+{
+ return IRExpr_Const(IRConst_U32(i));
+}
+
static IRExpr* bind ( Int binder )
{
return IRExpr_Binder(binder);
@@ -1284,15 +1284,16 @@
}
//.. case Iop_1Sto8:
//.. case Iop_1Sto16:
-//.. case Iop_1Sto32: {
-//.. /* could do better than this, but for now ... */
-//.. HReg dst =3D newVRegI(env);
-//.. X86CondCode cond =3D iselCondCode(env, e->Iex.Unop.arg)=
;
-//.. addInstr(env, X86Instr_Set32(cond,dst));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, X86RM_Reg(dst)=
));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, X86RM_Reg(dst)=
));
-//.. return dst;
-//.. }
+//.. case Iop_1Sto32:
+ case Iop_1Sto64: {
+ /* could do better than this, but for now ... */
+ HReg dst =3D newVRegI(env);
+ AMD64CondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
+ addInstr(env, AMD64Instr_Set64(cond,dst));
+ addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, AMD64RM_Reg(dst))=
);
+ addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, AMD64RM_Reg(dst))=
);
+ return dst;
+ }
case Iop_Ctz64: {
/* Count trailing zeroes, implemented by amd64 'bsfq' */
HReg dst =3D newVRegI(env);
@@ -1798,23 +1799,23 @@
return Acc_NZ;
}
=20
-//.. /* CmpEQ8 / CmpNE8 */
-//.. if (e->tag =3D=3D Iex_Binop=20
-//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ8
-//.. || e->Iex.Binop.op =3D=3D Iop_CmpNE8)) {
-//.. HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi2 =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//.. HReg r =3D newVRegI(env);
-//.. addInstr(env, mk_iMOVsd_RR(r1,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND,X86RMI_Imm(0xFF),r));
-//.. switch (e->Iex.Binop.op) {
-//.. case Iop_CmpEQ8: return Xcc_Z;
-//.. case Iop_CmpNE8: return Xcc_NZ;
-//.. default: vpanic("iselCondCode(x86): CmpXX8");
-//.. }
-//.. }
-//..=20
+ /* CmpEQ8 / CmpNE8 */
+ if (e->tag =3D=3D Iex_Binop=20
+ && (e->Iex.Binop.op =3D=3D Iop_CmpEQ8
+ || e->Iex.Binop.op =3D=3D Iop_CmpNE8)) {
+ HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ AMD64RMI* rmi2 =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+ HReg r =3D newVRegI(env);
+ addInstr(env, mk_iMOVsd_RR(r1,r));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
+ addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));
+ switch (e->Iex.Binop.op) {
+ case Iop_CmpEQ8: return Acc_Z;
+ case Iop_CmpNE8: return Acc_NZ;
+ default: vpanic("iselCondCode(amd64): CmpXX8");
+ }
+ }
+
//.. /* CmpEQ16 / CmpNE16 */
//.. if (e->tag =3D=3D Iex_Binop=20
//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ16
@@ -1831,18 +1832,18 @@
//.. default: vpanic("iselCondCode(x86): CmpXX16");
//.. }
//.. }
-//..=20
-//.. /* CmpNE32(1Sto32(b), 0) =3D=3D> b */
-//.. {
-//.. DECLARE_PATTERN(p_CmpNE32_1Sto32);
-//.. DEFINE_PATTERN(
-//.. p_CmpNE32_1Sto32,
-//.. binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
-//.. if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
-//.. return iselCondCode(env, mi.bindee[0]);
-//.. }
-//.. }
=20
+ /* CmpNE32(1Sto32(b), 0) =3D=3D> b */
+ {
+ DECLARE_PATTERN(p_CmpNE32_1Sto32);
+ DEFINE_PATTERN(
+ p_CmpNE32_1Sto32,
+ binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
+ if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
+ return iselCondCode(env, mi.bindee[0]);
+ }
+ }
+
/* Cmp*64*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ64
@@ -3612,7 +3613,7 @@
return;
=20
retty =3D typeOfIRTemp(env->type_env, d->tmp);
- if (retty =3D=3D Ity_I64) {
+ if (retty =3D=3D Ity_I64 || retty =3D=3D Ity_I32) {
/* The returned value is in %rax. Park it in the register
associated with tmp. */
HReg dst =3D lookupIRTemp(env, d->tmp);
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