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From: <sv...@va...> - 2005-04-04 02:52:19
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Author: njn
Date: 2005-04-04 03:52:16 +0100 (Mon, 04 Apr 2005)
New Revision: 3518
Modified:
trunk/cachegrind/cg_main.c
Log:
Remove the x86-specific is_valid_data_size() test. Also, make any dataSi=
ze
greater than MIN_LINE_SIZE equal to MIN_LINE_SIZE. This makes the
x86/fpu-28-108 regression test pass.
Modified: trunk/cachegrind/cg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/cg_main.c 2005-04-04 02:48:32 UTC (rev 3517)
+++ trunk/cachegrind/cg_main.c 2005-04-04 02:52:16 UTC (rev 3518)
@@ -493,13 +493,6 @@
}
}
=20
-// XXX: very x86-specific...
-static Bool is_valid_data_size(Int data_size)
-{
- return (4 =3D=3D data_size || 2 =3D=3D data_size || 1 =3D=3D data_si=
ze ||=20
- 8 =3D=3D data_size || 10 =3D=3D data_size || MIN_LINE_SIZE =3D=
=3D data_size);
-}
-
static Bool loadStoreAddrsMatch(IRExpr* loadAddrExpr, IRExpr* storeAddrE=
xpr)
{
// I'm assuming that for 'modify' instructions, that Vex always makes
@@ -545,6 +538,11 @@
(instrLen >=3D VGA_MIN_INSTR_SIZE &&=20
instrLen <=3D VGA_MAX_INSTR_SIZE) );
=20
+ // Large (eg. 28B, 108B, 512B on x86) data-sized instructions will be
+ // done inaccurately, but they're very rare and this avoids errors fr=
om
+ // hitting more than two cache lines in the simulation.
+ if (dataSize > MIN_LINE_SIZE) dataSize =3D MIN_LINE_SIZE;
+
// Setup 1st arg: instr_info node's address
// Believed to be 64-bit clean
do_details(i_node, bbSeenBefore, instrAddr, instrLen, dataSize );
@@ -560,7 +558,6 @@
=20
} else if (loadAddrExpr && !storeAddrExpr) {
// load
- tl_assert( is_valid_data_size(dataSize) );
tl_assert( isIRAtom(loadAddrExpr) );
helperName =3D "log_1I_1Dr_cache_access";
helperAddr =3D &log_1I_1Dr_cache_access;
@@ -570,7 +567,6 @@
=20
} else if (!loadAddrExpr && storeAddrExpr) {
// store
- tl_assert( is_valid_data_size(dataSize) );
tl_assert( isIRAtom(storeAddrExpr) );
helperName =3D "log_1I_1Dw_cache_access";
helperAddr =3D &log_1I_1Dw_cache_access;
@@ -580,7 +576,6 @@
=20
} else {
tl_assert( loadAddrExpr && storeAddrExpr );
- tl_assert( is_valid_data_size(dataSize) );
tl_assert( isIRAtom(loadAddrExpr) );
tl_assert( isIRAtom(storeAddrExpr) );
=20
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