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From: <sv...@va...> - 2005-12-30 15:04:34
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Author: sewardj
Date: 2005-12-30 15:04:29 +0000 (Fri, 30 Dec 2005)
New Revision: 1520
Log:
Apparently "sync" has an undocumented relative called "lwsync". Sigh.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2005-12-30 03:39:14 UTC (rev 1519)
+++ trunk/priv/guest-ppc/toIR.c 2005-12-30 15:04:29 UTC (rev 1520)
@@ -4511,18 +4511,38 @@
break;
}
=20
- case 0x256: // sync (Synchronize, PPC32 p543)
- if (b11to25 !=3D 0 || b0 !=3D 0) {
- vex_printf("dis_memsync(ppc)(sync,b11to25|b0)\n");
+ case 0x256: // sync (Synchronize, PPC32 p543),=20
+ // also lwsync, which appears to be undocumented
+ /* http://sources.redhat.com/ml/binutils/2000-12/msg00311.html
+
+ The PowerPC architecture used in IBM chips has expanded
+ the sync instruction into two variants: lightweight sync
+ and heavyweight sync. The original sync instruction is
+ the new heavyweight sync and lightweight sync is a strict
+ subset of the heavyweight sync functionality. This allows
+ the programmer to specify a less expensive operation on
+ high-end systems when the full sync functionality is not
+ necessary.
+
+ The basic "sync" mnemonic now utilizes an operand. "sync"
+ without an operand now becomes a extended mnemonic for
+ heavyweight sync. Processors without the lwsync
+ instruction will not decode the L field and will perform a
+ heavyweight sync. Everything is backward compatible.
+
+ sync =3D sync 0
+ lwsync =3D sync 1
+ */
+ if ((b11to25 !=3D 0/*sync*/ && b11to25 !=3D 1024/*lwsync*/) || =
b0 !=3D 0) {
+ vex_printf("dis_memsync(ppc)(sync/lwsync,b11to25|b0)\n");
return False;
}
- DIP("sync\n");
+ DIP("%ssync\n", b11to25 =3D=3D 1024 ? "lw" : "");
/* Insert a memory fence. It's sometimes important that these
are carried through to the generated code. */
stmt( IRStmt_MFence() );
break;
=20
-
/* 64bit Memsync */
case 0x054: // ldarx (Load DWord and Reserve Indexed, PPC64 p473)
if (b0 !=3D 0) {
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From: Paul M. <pa...@sa...> - 2005-12-31 00:06:49
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sv...@va... writes: > Apparently "sync" has an undocumented relative called "lwsync". Sigh. Not undocumented - it's in Book II of the PowerPC architecture, which you can get from http://www-128.ibm.com/developerworks/eserver/library/es-archguide-v2.html Paul. |