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From: Carl L. <ca...@so...> - 2018-02-28 00:40:46
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=9afb136f591c59bfb138e5b141ca59fe0d9e04af commit 9afb136f591c59bfb138e5b141ca59fe0d9e04af Author: Carl Love <ca...@us...> Date: Tue Feb 27 17:52:01 2018 -0600 PPC64, Missing tests for mtvsrwa, mtvrwa, mtvrd, and mtfprd. Add the missing tests to none/tests/ppc64/test_isa_2_07_part1.c. Update the expected output file with the new test outputs. Diff: --- none/tests/ppc64/jm_vec_isa_2_07.stdout.exp | 42 ++++++++++++++++++++++++++++- none/tests/ppc64/test_isa_2_07_part1.c | 42 ++++++++++++++++++++++++++++- 2 files changed, 82 insertions(+), 2 deletions(-) diff --git a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp index 40d32d6..76fd4d5 100644 --- a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp +++ b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp @@ -48,6 +48,46 @@ mtfprwa: 00000000 => 0000000000000000 mtfprwa: 00000000 => 0000000000000000 mtfprwa: ffffffff => ffffffffffffffff +mtvsrwa: 05060708 => 0000000005060708 +mtvsrwa: 0e0d0e0f => 000000000e0d0e0f +mtvsrwa: f5f6f7f8 => fffffffff5f6f7f8 +mtvsrwa: fefdfeff => fffffffffefdfeff +mtvsrwa: ffffffff => ffffffffffffffff +mtvsrwa: 00000000 => 0000000000000000 +mtvsrwa: 00000000 => 0000000000000000 +mtvsrwa: 00000000 => 0000000000000000 +mtvsrwa: ffffffff => ffffffffffffffff + +mtfprd: 0102030405060708 => 0000000000000000 +mtfprd: 090a0b0c0e0d0e0f => 0000000000000000 +mtfprd: f1f2f3f4f5f6f7f8 => 0000000000000000 +mtfprd: f9fafbfcfefdfeff => 0000000000000000 +mtfprd: 00007fffffffffff => 0000000000000000 +mtfprd: ffff000000000000 => 0000000000000000 +mtfprd: 0000800000000000 => 0000000000000000 +mtfprd: 0000000000000000 => 0000000000000000 +mtfprd: ffffffffffffffff => 0000000000000000 + +mtvrwa: 05060708 => 0000000005060708 +mtvrwa: 0e0d0e0f => 000000000e0d0e0f +mtvrwa: f5f6f7f8 => fffffffff5f6f7f8 +mtvrwa: fefdfeff => fffffffffefdfeff +mtvrwa: ffffffff => ffffffffffffffff +mtvrwa: 00000000 => 0000000000000000 +mtvrwa: 00000000 => 0000000000000000 +mtvrwa: 00000000 => 0000000000000000 +mtvrwa: ffffffff => ffffffffffffffff + +mtvrd: 0102030405060708 => 0102030405060708 +mtvrd: 090a0b0c0e0d0e0f => 090a0b0c0e0d0e0f +mtvrd: f1f2f3f4f5f6f7f8 => f1f2f3f4f5f6f7f8 +mtvrd: f9fafbfcfefdfeff => f9fafbfcfefdfeff +mtvrd: 00007fffffffffff => 00007fffffffffff +mtvrd: ffff000000000000 => ffff000000000000 +mtvrd: 0000800000000000 => 0000800000000000 +mtvrd: 0000000000000000 => 0000000000000000 +mtvrd: ffffffffffffffff => ffffffffffffffff + vaddudm: 0102030405060708 @@ 0102030405060708 ==> 020406080a0c0e10 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 121416181c1a1c1e vaddudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f2f4f6f8fafcff00 @@ -1277,4 +1317,4 @@ vsubeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @ vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000 -All done. Tested 66 different instructions +All done. Tested 70 different instructions diff --git a/none/tests/ppc64/test_isa_2_07_part1.c b/none/tests/ppc64/test_isa_2_07_part1.c index 201fa88..6009bb3 100644 --- a/none/tests/ppc64/test_isa_2_07_part1.c +++ b/none/tests/ppc64/test_isa_2_07_part1.c @@ -403,18 +403,41 @@ static void test_mtvsrwz (void) __asm__ __volatile__ ("mtvsrwz %x0,%1" : "=ws" (vec_out) : "r" (r14)); }; +static void test_mtvsrwa (void) +{ + __asm__ __volatile__ ("mtvsrwa %x0,%1" : "=d" (vec_out) : "r" (r14)); +}; static void test_mtfprwa (void) { __asm__ __volatile__ ("mtfprwa %x0,%1" : "=d" (vec_out) : "r" (r14)); }; +static void test_mtvrwa (void) +{ + __asm__ __volatile__ ("mtvrwa %0,%1" : "=v" (vec_out) : "r" (r14)); +}; + +static void test_mtvrd (void) +{ + __asm__ __volatile__ ("mtvrd %0,%1" : "=v" (vec_out) : "r" (r14)); +}; + +static void test_mtfprd (void) +{ + __asm__ __volatile__ ("mtfprd %0,%1" : "=v" (vec_out) : "r" (r14)); +}; + static test_t tests_move_ops_spe[] = { { &test_mfvsrd , "mfvsrd" }, { &test_mfvsrwz , "mfvsrwz" }, { &test_mtvsrd , "mtvsrd" }, { &test_mtvsrwz , "mtvsrwz" }, { &test_mtfprwa , "mtfprwa" }, + { &test_mtvsrwa , "mtvsrwa" }, + { &test_mtfprd , "mtfprd" }, + { &test_mtvrwa , "mtvrwa" }, + { &test_mtvrd , "mtvrd" }, { NULL, NULL } }; @@ -1255,7 +1278,12 @@ static special_t special_move_ops[] = { &mtvs, }, { - "mtfprwa", /* (extended mnemonic for mtvsrwa) move from scalar to vector reg with twoâs-complement */ + "mtvsrwa", /* mtvsrwa move from scalar to vector reg */ + &mtvs2s, + }, + { + "mtfprwa", /* (extended mnemonic for mtvsrwa) move from scalar to vector + reg */ &mtvs2s, }, { @@ -1265,6 +1293,18 @@ static special_t special_move_ops[] = { { "mtvsrwz", /* move from scalar to vector reg word */ &mtvs2s, + }, + { + "mtvrwa", /* (extended mnemonic for mtvsrwa) move to vsr word */ + &mtvs2s, + }, + { + "mtvrd", /* (extended mnemonic for mtvsrd) move to vsr double word */ + &mtvs, + }, + { + "mtfprd", /* (extended mnemonic for mtvsrd) move to float word */ + &mtvs, } }; |
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From: Peter B. <be...@vn...> - 2018-02-28 23:36:00
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On 2/27/18 6:40 PM, Carl Love wrote:
> +static void test_mtvsrwa (void)
> +{
> + __asm__ __volatile__ ("mtvsrwa %x0,%1" : "=d" (vec_out) : "r" (r14));
> +};
The mtvsrwa instruction writes a VSX register and you correctly use %x0
to write its reg number, but you should also use the "=ws" constraint
instead of "=d". You won't get an error, but you're forcing the inline
asm to only use FP regs (a subset of VSX regs).
> +static void test_mtfprd (void)
> +{
> + __asm__ __volatile__ ("mtfprd %0,%1" : "=v" (vec_out) : "r" (r14));
> +};
The mtfprd writes a FP register, so you need to use the "=d" constraint
instead of "=v". The assembler won't give an error since the reg numbers
are the same (0-31), but unless you got really lucky, this should have
led to a runtime error (ie, value not what you expected).
Peter
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From: Carl L. <ce...@us...> - 2018-03-01 22:07:50
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Peter:
Thanks for the input on the incorrect register constraints for the new
tests. I have committed a fix for them.
commit 839b244af27d6b7d27001c10ed308c485fecd3a8
Author: Carl Love <ca...@us...>
Date: Thu Mar 1 13:50:56 2018 -0600
PPC64, Fix tests for mtvsrwa and mtfprd.
Fix the register constraints for the vtvsrwa and mtfprd instructions
in test_isa_2_07_part2.c. Update the expected output in
none/tests/jm_vec_isa_2_07.stdout.exp.
Carl Love
-----------------------------------------------
On Wed, 2018-02-28 at 16:34 -0600, Peter Bergner wrote:
> On 2/27/18 6:40 PM, Carl Love wrote:
> > +static void test_mtvsrwa (void)
> > +{
> > + __asm__ __volatile__ ("mtvsrwa %x0,%1" : "=d" (vec_out) : "r"
> > (r14));
> > +};
>
> The mtvsrwa instruction writes a VSX register and you correctly use
> %x0
> to write its reg number, but you should also use the "=ws" constraint
> instead of "=d". You won't get an error, but you're forcing the
> inline
> asm to only use FP regs (a subset of VSX regs).
>
>
>
>
> > +static void test_mtfprd (void)
> > +{
> > + __asm__ __volatile__ ("mtfprd %0,%1" : "=v" (vec_out) : "r"
> > (r14));
> > +};
>
> The mtfprd writes a FP register, so you need to use the "=d"
> constraint
> instead of "=v". The assembler won't give an error since the reg
> numbers
> are the same (0-31), but unless you got really lucky, this should
> have
> led to a runtime error (ie, value not what you expected).
>
>
> Peter
>
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