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From: Carl E. L. <ce...@li...> - 2012-01-20 16:39:40
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Valgrind Community:
Since we have agreed to implement the DFP support by adding the three
DFP types, I will probably need to have two Iops for reinterpreting the
DFP type as an integer. Specifically we should include the Iops
Iop_ReinterpD64asI64 and Iop_ReinterpI64asD64.
In the preliminary implementation that I did, I used the F64 and F128
types to hold the DFP values. Then when I needed to do bit
manipulations I would reinterpret the F64 as and I64 do the bit
operations and then reinterpret the I64 result as F64.
I was thinking of some ways I could get around adding the DFP
reinterpret Iops by fetching the DFP value as a binary floating point
value so I could use the existing F64 to I64 and I64 to F64 reinterpret
Iops but it would really make the code ugly. I would rather not go this
route.
Carl Love
> Date: Thu, 19 Jan 2012 15:37:24 -0800
> From: "Carl E. Love" <ce...@li...>
> Subject: [Valgrind-developers] Version 2, Proposal to add Iops for DFP
> support
> To: Julian Seward <js...@ac...>,
> val...@li...
> Cc: ce...@us...
> Message-ID: <132...@oc...>
> Content-Type: text/plain; charset="UTF-8"
>
>
> Valgrind Community:
>
> The following is version 2 of the proposal to add Iops to Valgrind to support
> the Power and s390 Decimal Floating Point (DFP) instructions. The following
> proposal includes adding 28 new DFP Iops to support operations on 32-bit,
> 64-bit and 128-bit DFP numbers. The goal is to define a minimal set of Iops
> that are needed to support these two architectures and hopefully any future
> architectures that add support for DFP. Three new types will be added to
> Valgrind to support these Iops, D32, D64 and D128 for the 32-bit, 64-bit and
> 128-bit DFP values. The proposed DFP support will not extend the existing
> exception support in Valgrind. The exception support will be the same as the
> current binary floating point support.
>
> The Instruction Set Architecture (ISA) for s390(Z-series) can be found at:
> http://w3.ibm.com/jct03001pt/wps/myportal, click on the link to the document
> SA22-7832-08.pdf. The DFP instructions are described in chapter 20. Note, you
> will need to obtain a free IBM login to get to the document. Follow the
> instructions on the web page. If you have trouble getting to the document,
> use the "feedback" link to let them know.
>
> The POWER 7 ISA an be found at:
> http://www.power.org/home Then under community at work, click on the link
> "Power ISA v2.06 Now Available". The DFP instructions are found in book I,
> chapter 5.
>
> The s390 architecture has a few instructions that may require the introduction
> of additional Iops to support these instructions. The specifics of how to
> handle these s390 specific instructions by introducing additional Iops, helper
> functions, or by emulating them with existing Iops has not been decided.
> These instructions are not part of the base set of Iops required by both POWER
> and s390. The discussion of how to support these s390 specific instructions has
> been deferred until the s390 support is implemented. The names of these
> Iops are left as "To Be Determined" (TBD) at the time the s3990 support is
> added. They are called out here for completeness of all the Iops that may
> need to be added for s390 DFP support. The need for the additional Iops is
> mentioned in this proposal for completeness sake. The decision on the Iops
> is deferred until the s390 support is added.
>
> The list of proposed DFP Iops will be used as a basis to implement the POWER7
> and s390 DFP instruction support. Note that some of the POWER7 and s390
> instructions can be implemented using one or more of the new DFP Iops and the
> existing integer and binary floating point Iops. The instructions that can be
> implemented using the existing Iops and new DFP Iops have not been explicitly
> listed in this proposal.
>
> I have done a proof of concept implementation for the POWER DFP instruction
> support in Valgrind. The implementation was intended to validate that the
> proposed DFP Iops are sufficient for at least the POWER architecture. I will
> be working on revising the proof of concept implementation for POWER to
> make it consistent with this version of the proposal and any additional changes
> the community agrees on. I hope to post the code for inclusion into Valgrind
> in the near future.
>
>
> Notation Description
> ---------------------------------------------------------------------------
> DFP: Decimal Floating Point type (D32, D64 or D128). The term is
> used to distinguish the value from the traditional binary
> floating point type.
>
> D32: 32-bit decimal floating point type. These values use F64
> registers.
>
> D64: 64-bit decimal floating point type. These values use F64
> registers.
>
> D128: 128-bit decimal floating point type. These values use a pair
> of two 64 bit floating point registers (F64). The instruction
> only references the first register of the register pair. The
> second register is implied.
>
> Quantization: Rounding a number to a specified exponent is referred to as
> quantizing a number. For example, the U.S. specifies a dollar
> amount with at most two fractional digits, for example $12.98.
> When doing a computation involving money, the quantization
> instruction would be used to round the result to two fractional
> digits.
>
> Note, POWER 7 and s390 use two floating point registers to hold the 128-bit
> DFP value. The D32 and D64 values are also stored in the floating point
> registers.
>
> The IEEE 754-2008 specification adds four more rounding modes for DFP that are
> not supported by the binary floating point numbers. A new rounding mode
> designator will be introduced for DFP to support all of the specified DFP
> rounding modes.
>
> IRRoundingModeDFP(I32): Indicates the I32 argument is used to hold the
> bits that specify the rounding mode to be used
> by the instruction. The possible rounding modes
> are:
> - Round to nearest, ties to even
> - Round toward Zero
> - Round toward +infinity
> - Round toward -infinity
> - Round to Nearest, Ties away from 0
> - Round to Nearest, Ties toward 0
> - Round to away from Zero
> - Round to Prepare for Shorter Precision
>
>
> Summary of proposed Iops
> ----------------------------------------------------------------------------
>
> ARITHMETIC INSTRUCTIONS
> -----------------------
> IRRoundingModeDFP(I32) X D64 X D64 -> D64
> Iop_AddD64, Iop_SubD64, Iop_MulD64, Iop_DivD64
>
> IRRoundingModeDFP(I32) X D128 X D128 -> D128
> Iop_AddD128, Iop_SubD128, Iop_MulD128, Iop_DivD128
>
>
> FORMAT CONVERSION INSTRUCTIONS
> ------------------------------
> D32 -> D64
> Iop_D32toD64
>
> D64 -> D128
> Iop_D64toD128
>
> IRRoundingModeDFP(I32) x D64 -> D32
> Iop_D64toD32
>
> IRRoundingModeDFP(I32) x D128 -> D64
> Iop_D128toD64
>
> IRRoundingModeDFP(I32) x I64 -> D64
> Iop_I64StoD64
>
> IRRoundingModeDFP(I32) x D64 -> I64
> Iop_D64toI64S
>
> Additional format conversion Iops for converting to/from the DFP and
> binary floating point formats may need to be added later for s390 support.
>
>
> ROUNDING INSTRUCTIONS
> -----------------------
> IRRoundingModeDFP(I32) x D64 -> D64
> Iop_RoundD64toInt
>
> IRRoundingModeDFP(I32) x D128 -> D128
> Iop_RoundD128toInt
>
>
> COMPARE INSTRUCTIONS
> -----------------------
> D64 x D64 -> IRCmpD64Result(I32)
> Iop_CmpD64
>
> D128 x D128 -> IRCmpD64Result(I32)
> Iop_CmpD128
>
>
> QUANTIZE AND ROUND INSTRUCTIONS
> -------------------------------
> IRRoundingModeDFP(I32) x D64 x D64 -> D64
> Iop_QuantizeD64
>
> IRRoundingModeDFP(I32) x D128 x D128 -> D128
> Iop_QuantizeD128
>
> IRRoundingModeDFP(I32) x D64 x D64 -> D64
> Iop_SignificanceRoundD64
>
> IRRoundingModeDFP(I32) x D128 x D128 -> D128
> Iop_SignificanceRoundD128
>
>
> EXTRACT AND INSERT INSTRUCTIONS
> -------------------------------
> D64 -> I32
> Iop_ExtractExpD64
>
> D128 -> I32
> Iop_ExtractExpD128
>
> I32 x I64 -> D64
> Iop_InsertExpD64
>
> I32 x I128 -> D128
> Iop_InsertExpD128
>
>
> SHIFT SIGNIFICAND INSTRUCTIONS
> -------------------------------
> D64 x U8 -> D64
> Iop_ShlD64, Iop_ShrD64
>
> D128 x U8 -> D128
> Iop_ShlD128, Iop_ShrD128
>
>
>
> This section gives the detailed mapping of the proposed DFP Iops to the
> corresponding POWER and s390 instruction. The POWER and s390 instructions are
> listed in their respective Instruction Set Architecture documents referenced
> at the beginning of this proposal. The POWER and s390 instructions that can
> be implemented using a sequence of Iops are not listed.
>
>
> ARITHMETIC INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
> Iop_AddD64 IRRoundingModeDFP(I32) X D64 X D64 -> D64
> ADTR dadd
> ADTRA Add two 64-bit DFP numbers. If both operands
> are finite numbers, they are added
> algebraically, forming an intermediate
> sum. The intermediate sum, if nonzero, is
> rounded to the operand format and the rounded
> value is then placed at the result location.
> The ADTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the ADTR.
>
> Iop_AddD128 IRRoundingModeDFP(I32) X D128 X D128 -> D128
> AXTR daddq
> AXTRA Add two 128-bit DFP numbers If both operands
> are finite numbers, they are added
> algebraically, forming an intermediate sum. The
> intermediate sum, if nonzero, is rounded to the
> operand format and the rounded value is then
> placed at the result location.
> The AXTRA instruction has a field to specify
> the desired rounding mode.
>
> Iop_SubD64 IRRoundingModeDFP(I32) X D64 X D64 -> D64
> SDTR dsub
> SDTRA
> The execution of SUBTRACT is identical to that
> of ADD, except that the second operand, if
> numeric, participates in the operation with
> its sign bit inverted.
> The SXTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the SDTR.
>
> Iop_SubD128 IRRoundingModeDFP(I32) X D128 X D128 -> D128
> SXTR dsubq
> SXTRA
> The execution of SUBTRACT is identical to that
> of ADD, except that the second operand, if
> numeric, participates in the operation with
> its sign bit inverted.
> The SXTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the SXTRA.
>
> Iop_MulD64 IRRoundingModeDFP(I32) X D64 X D64 -> D64
> MDTR dmul
> MDTRA
> If both source operands are finite numbers,
> they are multiplied to form an intermediate
> product. The intermediate product is rounded
> to the target format.
> The MDTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the MDTR.
>
> Iop_MulD128 IRRoundingModeDFP(I32) X D128 X D128 -> D128
> MXTR dmulq
> MXTRA
> If both source operands are finite numbers,
> they are multiplied to form an intermediate
> product. The intermediate product is rounded
> to the target format.
> The MXTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the MXTR.
>
> Iop_DivD64 IRRoundingModeDFP(I32) X D64 X D64 -> D64
> DDTR ddiv
> DDTRA
> If divisor is nonzero and both the dividend and
> divisor are finite numbers, the first operand
> is divided by the second operand to form an
> intermediate quotient. The intermediate
> quotient, if nonzero, is rounded to the target
> format.
> The MDTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the MDTR.
>
> Iop_DivD128 IRRoundingModeDFP(I32) X D128 X D128 -> D128
> DXTR ddivq
> DXTRA
> If divisor is nonzero and both the dividend and
> divisor are finite numbers, the first operand
> is divided by the second operand to form an
> intermediate quotient. The intermediate
> quotient, if nonzero, is rounded to the target
> format.
> The DXTRA instruction has a field to specify
> the desired rounding mode but is otherwise
> identical to the MXTR.
>
>
>
> FORMAT CONVERSION INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
> TBD
> PFPO
> The PFPO instruction operation is specified by
> the code in general purpose register 0 and the
> condition code is set to indicate the result.
> The operations that can be specified for this
> instruction include a large list of format
> conversions to/from various sizes of DFP
> operands and various sizes of Hexadecimal
> floating point and Binary floating point
> formats.
>
> Additional Iops to support these conversions
> on s390 may be needed. The decision on which
> Iops are needed will be deferred to when the
> s390 support is added.
>
> Iop_D32toD64 D32 -> D64
> LDETR dctdp
> The 32-bit DFP source operand is converted into
> a 64-bit DFP result.
>
> Iop_D64toD128 D64 -> D128
> LXETR dctqpq
> The 64-bit DFP source operand is
> converted into a 128-bit DFP result.
>
> Iop_D64toD32 IRRoundingModeDFP(I32) x D64 -> D64
> LEDTR drsp
> The 64-bit DFP source operand is rounded to a
> DFP 32-bit value, according to the rounding
> mode.
>
> Iop_D128toD64 IRRoundingModeDFP(I32) x D128 -> D64
> LDXTR drdpq
> The 128-bit DFP source operand is rounded,
> according to the rounding mode.
>
> Iop_I64StoD64 IRRoundingModeDFP(I32) x I64 -> D64
> CDGTR dcffix
> CDGTRA
> The 64-bit signed binary-integer in the second
> source operand is converted into a 64-bit DFP
> result using the rounding mode specified in
> the first operand.
>
> Iop_D64toI64S IRRoundingModeDFP(I32) x D64 -> I64
> CGDTR dctfix
> CGDTRA
> The 64-bit DFP source operand is rounded to a
> signed integer, according to the rounding mode
> specified by the first operand, and converted
> into a signed 64-bit integer result with
> the same sign as the source.
>
>
> May need new Iop IRRoundingModeDFP(I32) x D64 -> I64
> TBD CLGDTR
> The 64-bit DFP source operand is rounded to a
> signed integer, according to the rounding mode
> specified by the first operand, and converted
> into a signed 64-bit binary integer result with
> the same sign as the source.
>
> Possible implementation: the 64-bit DFP source
> operand is rounded into a 64-bit signed integer
> using the existing instruction Iop_D64toI64.
>
> Defer decision on adding a new Iop until the
> s390 implementation is started.
>
> May need new Iop IRRoundingModeDFP(I32) x D64 -> I32
> TBD CLFDTR
> The 64-bit DFP source operand is rounded to a
> signed integer, according to the rounding mode
> specified by the first operand, and converted
> into a signed 32-bit integer result with
> the same sign as the source.
>
> Possible implementation: the 64-bit DFP source
> operand is rounded into a 64-bit signed integer
> using the existing instruction Iop_D64toI64,
> then Iop_64to32 convert to a signed 32-bit
> integer.
>
> Defer decision on adding a new Iop until the
> s390 implementation is started.
>
> May need new Iop IRRoundingModeDFP(I32) x D128 -> I64
> TBD CLGXTR
> The 128-bit DFP source operand is rounded to a
> signed integer, according to the rounding mode
> specified by the first operand, and converted
> into a signed 64-bit integer result with
> the same sign as the source.
>
> Possible implementation: the 128-bit DFP source
> operand is rounded into a 64-bit DFP with the
> Iop_RoundD128toD64 instruction, 64-bit DFP is
> rounded to a 64-bit signed integer using the
> existing instruction Iop_D64toI64.
>
> Defer decision on adding a new Iop until the
> s390 implementation is started.
>
> May need new Iop IRRoundingModeDFP(I32) x D128 -> I32
> TBD CLFXTR
> The 128-bit DFP source operand is rounded to a
> signed integer, according to the rounding mode
> specified by the first operand, and converted
> into a signed 32-bit integer result with
> the same sign as the source.
>
> Possible implementation: the 128-bit DFP source
> operand is rounded into a 64-bit DFP with the
> Iop_RoundD128toD64 instruction,the 64-bit DFP
> is then converted to a 64-bit signed integer
> using the existing instruction Iop_D64toI64,
> then Iop_64to32 convert to a signed 32-bit
> integer.
>
> Defer decision on adding a new Iop until the
> s390 implementation is started.
>
>
> ROUNDING INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
> Iop_RoundD64toInt IRRoundingModeDFP(I32) x D64 -> D64
> FIDTR drintx
> The D64 operand, if a finite number, is rounded
> to an integer value in the same DFP format.
>
> Iop_RoundD128toInt IRRoundingModeDFP(I32) x D128 -> D128
> FIXTR drintxq
> The D128 operand, if a finite number, is
> rounded to a binary integer value, in the
> same DFP format.
>
>
> COMPARE INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
>
> Iop_CmpD64 D64 x D64 -> IRCmpF64Result(I32)
> dcmpo
> dcmpu
> Perform the comparison, as specified in the
> instruction. The instruction sets the platform
> condition codes. The condition codes for the
> virtual machine need to be updated based on the
> result in this platform specific condition code
> register.
>
> Iop_CmpD128 D128 x D128 -> IRCmpF64Result(I32)
> dcmpoq
> dcmpuq
> Perform the comparison, as specified in the
> instruction. The instruction sets the platform
> condition codes. The condition codes for the
> virtual machine need to be updated based on the
> result in this platform specific condition code
> register.
>
>
> QUANTIZE AND ROUND INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
>
> Iop_QuantizeD64 IRRoundingModeDFP(I32) x D64 x D64 -> D64
> dqua
> The second D64 operand is converted and
> rounded to the form with the same exponent
> as that of the first DFP operand. The result
> is placed in the result operand.
>
> Iop_QuantizeD128 IRRoundingModeDFP(I32) x D128 x D128-> D128
> dquaq
> The second D128 operand is converted and
> rounded to the form with the same exponent
> as that of the first DFP operand. The
> result is placed in the result operand.
>
> Iop_SignificanceRoundD64 IRRoundingModeDFP(I32) x D64 x D64 -> D64
> RRDTR drrnd
> The second D64 operand is rounded to the
> significance specified by the first D64
> operand as specified by the rounding mode.
>
> Iop_SignificanceRoundD128 IRRoundingModeDFP(I32) x D128 x D128 -> D128
> RRXTR drrndq
> The second D128 operand is rounded to the
> significance specified by the first D128
> operand as specified by the rounding mode.
>
> EXTRACT AND INSERT INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
> Iop_ExtractExpD64 D64 -> I32
> EEDTR dxex
> The exponent of the D64 operand is extracted.
> The extracted exponent is converted and stored
> in the floating point register as a signed
> 32-bit binary integer format.
>
>
> Iop_ExtractExpD128 D128 -> I32
> EEXTR dxexq
> The exponent of the D128 operand is extracted.
> The extracted exponent is converted and stored
> in the floating point register as a signed
> 32-bit binary integer.
>
> Iop_InsertExpD64 I32 x I64 -> D64
> IEDTR diex
> The exponent is specified by the first I32
> operand the signed significand is given by the
> second I64 value. The result is a D64 value
> consisting of the specified significand and
> exponent whose sign is that of the specified
> significand.
>
> Iop_InsertExpD128 I32 x I128 -> D128
> IEXTR diexq
> The exponent is specified by the first I32
> operand the signed significand is given by the
> second I128 value. The result is a D128 value
> consisting of the specified significand and
> exponent whose sign is that of the specified
> significand.
>
>
> SHIFT SIGNIFICAND INSTRUCTIONS
> Iop s390 Power Description of instruction, implementation
> opcode opcode details
> -------------------------------------------------------------------------------
> Iop_ShlD64 D64 x U8 -> D64
> SLDT dscli
> The D32 or D64 significand is shifted left by
> the number of digits specified by the U8
> operand. Digits shifted out of the leftmost
> digit are lost. Zeros are supplied to the
> vacated positions on the right. The sign of
> the result is the same as the sign of the D64
> operand.
>
> Iop_ShlD128 D128 x U8 -> D128
> SLDT dscliq
> The D128 significand is shifted left by the
> number of digits specified by the U8 operand.
> Digits shifted out of the leftmost digit are
> lost. Zeros are supplied to the vacated
> positions on the right. The sign of the result
> is the same as the sign of the D128 operand.
>
> Iop_ShrD64 D64 x U8 -> D64
> SLDT dscri
> The D32 or D64 significand is shifted right by
> the number of digits specified by the U8
> operand. Digits shifted out of the right most
> digit are lost. Zeros are supplied to the
> vacated positions on the left. The sign of the
> result is the same as the sign of the D64
> operand.
>
> Iop_ShrD128 D128 x U8 -> D128
> SLDT dscriq
> The D128 significand is shifted right by the
> number of digits specified by the U8 operand.
> Digits shifted out of the right most digit are
> lost. Zeros are supplied to the vacated
> positions on the left. The sign of the result
> is the same as the sign of the D128 operand.
>
>
> Thank you for your time and effort to review this proposal.
>
> Carl Love
>
>
>
>
>
> ------------------------------
>
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> End of Valgrind-developers Digest, Vol 68, Issue 80
> ***************************************************
>
>
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