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From: Nicholas N. <nj...@ca...> - 2004-10-13 11:30:38
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CVS commit by nethercote:
Add a new CPUID cache configuration for more recent Pentiums.
M +1 -0 cg_arch.c 1.2
--- valgrind/cachegrind/x86/cg_arch.c #1.1:1.2
@@ -126,4 +126,5 @@ Int Intel_cache_info(Int level, cache_t*
/* These are sectored, whatever that means */
+ case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */
case 0x66: *D1c = (cache_t) { 8, 4, 64 }; break; /* sectored */
case 0x67: *D1c = (cache_t) { 16, 4, 64 }; break; /* sectored */
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From: Dirk M. <mu...@kd...> - 2005-07-28 16:48:11
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SVN commit 439682 by mueller:
backport -r4210 to valgrind-2.4:
Add a CPUID case, thanks to Josef W.
M +1 -0 cg_arch.c =20
--- trunk/valgrind/cachegrind/x86/cg_arch.c #439681:439682
@@ -153,6 +153,7 @@
case 0x7a: *L2c =3D (cache_t) { 256, 8, 64 }; L2_found =3D True;=
break;
case 0x7b: *L2c =3D (cache_t) { 512, 8, 64 }; L2_found =3D True;=
break;
case 0x7c: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
+ case 0x7d: *L2c =3D (cache_t) { 2048, 8, 64 }; L2_found =3D True;=
break;
case 0x7e: *L2c =3D (cache_t) { 256, 8, 128 }; L2_found =3D True;=
break;
=20
case 0x81: *L2c =3D (cache_t) { 128, 8, 32 }; L2_found =3D True;=
break;
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From: Dirk M. <mu...@kd...> - 2005-07-28 16:49:59
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SVN commit 439684 by mueller:
backport -r4286 from valgrind-3.0:=20
Ignore prefetch information when decoding Intel cache details. Patch
from Josef Weidendorfer <Jos...@gm...>.
M +4 -0 cg_arch.c =20
--- trunk/valgrind/cachegrind/x86/cg_arch.c #439683:439684
@@ -164,6 +164,10 @@
case 0x86: *L2c =3D (cache_t) { 512, 4, 64 }; L2_found =3D True;=
break;
case 0x87: *L2c =3D (cache_t) { 1024, 8, 64 }; L2_found =3D True;=
break;
=20
+ /* Ignore prefetch information */
+ case 0xf0: case 0xf1:
+ break;
+
default:
VG_(message)(Vg_DebugMsg,=20
"warning: Unknown Intel cache config value "
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