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From: Paul F. <pa...@so...> - 2023-01-11 20:44:06
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8fcc813468554b23c04d8db64f425b299df06ad0 commit 8fcc813468554b23c04d8db64f425b299df06ad0 Author: Paul Floyd <pj...@wa...> Date: Wed Jan 11 21:42:41 2023 +0100 Bug 241072 List tools in --help output Diff: --- NEWS | 1 + coregrind/m_main.c | 3 +++ none/tests/cmdline1.stdout.exp | 5 +++-- none/tests/cmdline2.stdout.exp | 5 +++-- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/NEWS b/NEWS index 041ff5ba65..f2a380863b 100644 --- a/NEWS +++ b/NEWS @@ -76,6 +76,7 @@ than mailing the developers (or mailing lists) directly -- bugs that are not entered into bugzilla tend to get forgotten about or ignored. 170510 Don't warn about ioctl of size 0 without direction hint +241072 List tools in --help output 327548 false positive while destroying mutex 351857 confusing error message about valid command line option 392331 Spurious lock not held error from inside pthread_cond_timedwait diff --git a/coregrind/m_main.c b/coregrind/m_main.c index c966873e26..27ec451433 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -87,6 +87,9 @@ static void usage_NORETURN ( int need_help ) "\n" " tool-selection option, with default in [ ]:\n" " --tool=<name> use the Valgrind tool named <name> [memcheck]\n" +" available tools are:\n" +" memcheck cachegrind callgrind helgrind drd\n" +" massif dhat lackey none exp-bbv\n" "\n" " basic user options for all Valgrind tools, with defaults in [ ]:\n" " -h --help show this message\n" diff --git a/none/tests/cmdline1.stdout.exp b/none/tests/cmdline1.stdout.exp index de5fcd819a..c0e71fa576 100644 --- a/none/tests/cmdline1.stdout.exp +++ b/none/tests/cmdline1.stdout.exp @@ -2,6 +2,9 @@ usage: valgrind [options] prog-and-args tool-selection option, with default in [ ]: --tool=<name> use the Valgrind tool named <name> [memcheck] + available tools are: + memcheck cachegrind callgrind helgrind drd + massif dhat lackey none exp-bbv basic user options for all Valgrind tools, with defaults in [ ]: -h --help show this message @@ -31,8 +34,6 @@ usage: valgrind [options] prog-and-args --log-fd=<number> log messages to file descriptor [2=stderr] --log-file=<file> log messages to <file> --log-socket=ipaddr:port log messages to socket ipaddr:port - --enable-debuginfod=no|yes query debuginfod servers for missing - debuginfo [yes] user options for Valgrind tools that report errors: --xml=yes emit error output in XML (some tools only) diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp index d810cc7fa3..c19fa72597 100644 --- a/none/tests/cmdline2.stdout.exp +++ b/none/tests/cmdline2.stdout.exp @@ -2,6 +2,9 @@ usage: valgrind [options] prog-and-args tool-selection option, with default in [ ]: --tool=<name> use the Valgrind tool named <name> [memcheck] + available tools are: + memcheck cachegrind callgrind helgrind drd + massif dhat lackey none exp-bbv basic user options for all Valgrind tools, with defaults in [ ]: -h --help show this message @@ -31,8 +34,6 @@ usage: valgrind [options] prog-and-args --log-fd=<number> log messages to file descriptor [2=stderr] --log-file=<file> log messages to <file> --log-socket=ipaddr:port log messages to socket ipaddr:port - --enable-debuginfod=no|yes query debuginfod servers for missing - debuginfo [yes] user options for Valgrind tools that report errors: --xml=yes emit error output in XML (some tools only) |
|
From: Andreas A. <ar...@so...> - 2023-01-11 15:47:53
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d6073d34d46bf33488b1df43980284ba557617e7 commit d6073d34d46bf33488b1df43980284ba557617e7 Author: Andreas Arnez <ar...@li...> Date: Wed Oct 26 19:45:30 2022 +0200 s390: Add test for short/extended vector float insns Several issues with vector floating point instructions have gone unnoticed due to a lack of test coverage in this area. Add a test case that improves the coverage, particuarly when dealing with short and extended floating point formats. Diff: --- .gitignore | 1 + none/tests/s390x/Makefile.am | 3 +- none/tests/s390x/vec2_float.c | 419 +++++++++++++++++++++++++++++++++ none/tests/s390x/vec2_float.stderr.exp | 2 + none/tests/s390x/vec2_float.stdout.exp | 389 ++++++++++++++++++++++++++++++ none/tests/s390x/vec2_float.vgtest | 2 + tests/s390x_features.c | 2 +- 7 files changed, 816 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 66a221fb49..b422b173e2 100644 --- a/.gitignore +++ b/.gitignore @@ -2032,6 +2032,7 @@ /none/tests/s390x/vector_float /none/tests/s390x/misc3 /none/tests/s390x/vec2 +/none/tests/s390x/vec2_float # /none/tests/scripts/ /none/tests/scripts/*.dSYM diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index ca38db935c..d8f9e4b894 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -20,7 +20,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \ spechelper-icm-1 spechelper-icm-2 spechelper-tmll \ spechelper-tm laa vector lsc2 ppno vector_string vector_integer \ vector_float add-z14 sub-z14 mul-z14 bic \ - misc3 vec2 + misc3 vec2 vec2_float if BUILD_DFP_TESTS INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo @@ -75,3 +75,4 @@ vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5 vector_integer_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 vector_float_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 vec2_CFLAGS = $(AM_CFLAGS) -march=z13 +vec2_float_CFLAGS = $(AM_CFLAGS) -march=z13 diff --git a/none/tests/s390x/vec2_float.c b/none/tests/s390x/vec2_float.c new file mode 100644 index 0000000000..3dc4798708 --- /dev/null +++ b/none/tests/s390x/vec2_float.c @@ -0,0 +1,419 @@ +#include <stdio.h> + +#define VECTOR __attribute__ ((vector_size (16))) + +typedef unsigned int VECTOR u2_v; +typedef unsigned long VECTOR u3_v; +typedef unsigned long VECTOR u4_v; /* avoid 128-bit integers */ +typedef float VECTOR f2_v; +typedef double VECTOR f3_v; +typedef long double VECTOR f4_v; + +#define INF (1./0.) +#define NAN (0./0.) + +static const u2_v vec_u2_a = { -1, 0x7ffffff0, 42, 0 }; +static const u2_v vec_u2_b = { 0x7fffff80, 1, 1000, -0x7caffe }; +static const u2_v vec_u2_c = { 0x7fffff, 0x70000000, -10000, 0xffff }; +static const u2_v vec_u2_e = { 0x7fffffff, 0x8000000, 0, 42 }; + +static const f2_v vec_f2_a = { 16777215., -16777215., 42.5, 10000. }; +static const f2_v vec_f2_b = { 4., 3., 42.5, 1. }; +static const f2_v vec_f2_c = { 0., INF, -0., -INF }; +static const f2_v vec_f2_d = { -16777214., 16777214., -23., -9999. }; +static const f2_v vec_f2_e = { NAN, -NAN, NAN, -NAN }; + +static const f3_v vec_f3_a = { (double) ((1UL << 52) - 1), -16777215. }; +static const f3_v vec_f3_b = { 0.1, 3. }; +static const f3_v vec_f3_c = { -0., INF }; +static const f3_v vec_f3_e = { NAN, -NAN }; + +static const f4_v vec_f4_a = { 16777215.0L }; +static const f4_v vec_f4_b = { 4.0L }; +static const f4_v vec_f4_c = { INF }; +static const f4_v vec_f4_d = { -23.0 }; +static const f4_v vec_f4_e = { NAN }; + +static const u3_v vec_ini = { 0x0112233445566778, 0x899aabbccddeeff0 }; + +/* -- Dump a vector depending on FP format and single-element control -- */ + +static void dump_cc(int cc) +{ + if (cc) { + printf(" cc=%d", cc); + } + putchar('\n'); +} + +static void dump_vu2(u2_v u) +{ + printf("\t%d | %d | %d | %d", u[0], u[1], u[2], u[3]); +} + +static void dump_wu2(u2_v u) +{ + printf("\t%d | - | - | -", u[0]); +} + +static void dump_wu4(u4_v u) +{ + if (u[0] == 0) { + printf("\t%ld", u[1]); + } else if (u[0] == -1) { + printf("\t-%ld", -u[1]); + } else { + printf("\t0x%016lx%016lx", u[0], u[1]); + } +} + +static void dump_vf2(f2_v v) +{ + printf("\t%a | %a | %a | %a", v[0], v[1], v[2], v[3]); +} + +static void dump_ef2(f2_v v) +{ + printf("\t%a | - | %a | -", v[0], v[2]); +} + +static void dump_vf3(f3_v v) +{ + printf("\t%a | %a", v[0], v[1]); +} + +static void dump_wf3(f3_v v) +{ + printf("\t%a | -", v[0]); +} + +static void dump_wf2(f2_v v) +{ + printf("\t%a | - | - | -", v[0]); +} + +static void dump_wf4(f4_v v) +{ + printf("\t%La", v[0]); +} + +/* -- Vector unary operators -- */ + +#define TEST_EXEC(opc1,opc2,fmt,ty1,ty2,insn,m3,m4,m5) \ + do { \ + puts(#insn); \ + test_##insn##_##m3##_##m4##_##m5(vec_##ty2##_a); \ + test_##insn##_##m3##_##m4##_##m5(vec_##ty2##_b); \ + test_##insn##_##m3##_##m4##_##m5(vec_##ty2##_c); \ + test_##insn##_##m3##_##m4##_##m5(vec_##ty2##_e); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,fmt,ty1,ty2,insn,m3,m4,m5) \ + static void test_##insn##_##m3##_##m4##_##m5(ty2##_v a) \ + { \ + ty1##_v out = (ty1##_v) vec_ini; \ + int cc = -1; \ + __asm__( \ + "cr 0,0\n\t" \ + ".insn vrr,0x" #opc1 "00000000" #opc2 ",%[out],%[a],0," \ + #m3 "," #m4 "," #m5 "\n\t" \ + "ipm %[cc]\n\t" \ + "srl %[cc],28" \ + : [cc]"=d" (cc), [out]"+v" (out) \ + : [a]"v" (a) \ + : "cc"); \ + dump_##fmt##ty1(out); \ + dump_cc(cc); \ + } + +#define INSNS \ + XTEST(e7,c0, v,u2, f2, vclfeb, 2,4,0); \ + XTEST(e7,c0, w,u2, f2, wclfeb, 2,12,0); \ + XTEST(e7,c1, v,f2, u2, vcelfb, 2,4,0); \ + XTEST(e7,c1, w,f2, u2, wcelfb, 2,12,0); \ + XTEST(e7,c2, v,u2, f2, vcfeb, 2,4,0); \ + XTEST(e7,c2, w,u2, f2, wcfeb, 2,12,0); \ + XTEST(e7,c3, v,f2, u2, vcefb, 2,4,0); \ + XTEST(e7,c3, w,f2, u2, wcefb, 2,12,0); \ + XTEST(e7,c4, v,f3, f2, vldeb, 2,0,0); \ + XTEST(e7,c4, w,f3, f2, wldeb, 2,8,0); \ + XTEST(e7,c4, w,f4, f3, wflld, 3,8,0); \ + XTEST(e7,c5, e,f2, f3, vledb, 3,4,0); \ + XTEST(e7,c5, w,f2, f3, wledb, 3,12,0); \ + XTEST(e7,c5, w,f3, f4, wflrx, 4,12,0); \ + XTEST(e7,c7, v,f2, f2, vfisb, 2,0,0); \ + XTEST(e7,c7, w,f2, f2, wfisb, 2,8,0); \ + XTEST(e7,c7, w,f4, f4, wfixb, 4,8,0); \ + XTEST(e7,cc, v,f2, f2, vflcsb, 2,0,0); \ + XTEST(e7,cc, w,f2, f2, wflcsb, 2,8,0); \ + XTEST(e7,cc, w,f4, f4, wflcxb, 4,8,0); \ + XTEST(e7,cc, v,f2, f2, vflnsb, 2,0,1); \ + XTEST(e7,cc, w,f2, f2, wflnsb, 2,8,1); \ + XTEST(e7,cc, w,f4, f4, wflnxb, 4,8,1); \ + XTEST(e7,cc, v,f2, f2, vflpsb, 2,0,2); \ + XTEST(e7,cc, w,f2, f2, wflpsb, 2,8,2); \ + XTEST(e7,cc, w,f4, f4, wflpxb, 4,8,2); \ + XTEST(e7,ce, v,f2, f2, vfsqsb, 2,0,0); \ + XTEST(e7,ce, w,f2, f2, wfsqsb, 2,8,0); \ + XTEST(e7,ce, w,f4, f4, wfsqxb, 4,8,0); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_unops() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE +#undef TEST_EXEC + +/* -- Vector binary operators -- */ + +#define TEST_EXEC(opc1,opc2,fmt,ty1,insn,m4,m5,m6) \ + do { \ + puts(#insn); \ + test_##insn##_##m4##_##m5##_##m6(vec_f##m4##_a, vec_f##m4##_b); \ + test_##insn##_##m4##_##m5##_##m6(vec_f##m4##_b, vec_f##m4##_a); \ + test_##insn##_##m4##_##m5##_##m6(vec_f##m4##_a, vec_f##m4##_c); \ + test_##insn##_##m4##_##m5##_##m6(vec_f##m4##_d, vec_f##m4##_e); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,fmt,ty1,insn,m4,m5,m6) \ + static void test_##insn##_##m4##_##m5##_##m6(f##m4##_v a, f##m4##_v b) \ + { \ + ty1##_v out = (ty1##_v) vec_ini; \ + int cc = -1; \ + __asm__( \ + "cr 0,0\n\t" \ + ".insn vrr,0x" #opc1 "00000000" #opc2 ",%[out],%[a],%[b]," \ + #m4 "," #m5 "," #m6 "\n\t" \ + "ipm %[cc]\n\t" \ + "srl %[cc],28" \ + : [cc]"=d" (cc), [out] "+v" (out) \ + : [a] "v" (a), [b] "v" (b) \ + : "cc"); \ + dump_##fmt##ty1(out); \ + dump_cc(cc); \ + } + +#define INSNS \ + XTEST(e7,e2, v,f2, vfssb, 2,0,0); \ + XTEST(e7,e2, w,f2, wfssb, 2,8,0); \ + XTEST(e7,e2, w,f4, wfsxb, 4,8,0); \ + XTEST(e7,e3, v,f2, vfasb, 2,0,0); \ + XTEST(e7,e3, w,f2, wfasb, 2,8,0); \ + XTEST(e7,e3, w,f4, wfaxb, 4,8,0); \ + XTEST(e7,e5, v,f2, vfdsb, 2,0,0); \ + XTEST(e7,e5, w,f2, wfdsb, 2,8,0); \ + XTEST(e7,e5, w,f4, wfdxb, 4,8,0); \ + XTEST(e7,e7, v,f2, vfmsb, 2,0,0); \ + XTEST(e7,e7, w,f2, wfmsb, 2,8,0); \ + XTEST(e7,e7, w,f4, wfmxb, 4,8,0); \ + XTEST(e7,e8, v,u2, vfcesb, 2,0,0); \ + XTEST(e7,e8, w,u2, wfcesb, 2,8,0); \ + XTEST(e7,e8, w,u4, wfcexb, 4,8,0); \ + XTEST(e7,e8, v,u2, vfcesbs, 2,0,1); \ + XTEST(e7,e8, w,u2, wfcesbs, 2,8,1); \ + XTEST(e7,e8, w,u4, wfcexbs, 4,8,1); \ + XTEST(e7,ea, v,u2, vfchesb, 2,0,0); \ + XTEST(e7,ea, w,u2, wfchesb, 2,8,0); \ + XTEST(e7,ea, w,u4, wfchexb, 4,8,0); \ + XTEST(e7,ea, v,u2, vfchesbs, 2,0,1); \ + XTEST(e7,ea, w,u2, wfchesbs, 2,8,1); \ + XTEST(e7,ea, w,u4, wfchexbs, 4,8,1); \ + XTEST(e7,ee, v,f2, vfminsb, 2,0,0); \ + XTEST(e7,ee, w,f2, wfminsb, 2,8,0); \ + XTEST(e7,ee, w,f4, wfminxb, 4,8,0); \ + XTEST(e7,ef, v,f2, vfmaxsb, 2,0,0); \ + XTEST(e7,ef, w,f2, wfmaxsb, 2,8,0); \ + XTEST(e7,ef, w,f4, wfmaxxb, 4,8,0); \ + XTEST(e7,eb, v,u2, vfchsb, 2,0,0); \ + XTEST(e7,eb, w,u2, wfchsb, 2,8,0); \ + XTEST(e7,eb, w,u4, wfchxb, 4,8,0); \ + XTEST(e7,eb, v,u2, vfchsbs, 2,0,1); \ + XTEST(e7,eb, w,u2, wfchsbs, 2,8,1); \ + XTEST(e7,eb, w,u4, wfchxbs, 4,8,1); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_binops() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE +#undef TEST_EXEC + +/* -- Vector ternary operators -- */ + +#define TEST_EXEC(opc1,opc2,fmt,ty,insn,m5,m6) \ + do { \ + puts(#insn); \ + test_##insn##_##m5##_##m6(vec_##ty##_a, vec_##ty##_b, vec_##ty##_c); \ + test_##insn##_##m5##_##m6(vec_##ty##_b, vec_##ty##_a, vec_##ty##_d); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,fmt,ty,insn,m5,m6) \ + static void test_##insn##_##m5##_##m6(ty##_v a, ty##_v b, ty##_v c) \ + { \ + ty##_v out = (ty##_v) vec_ini; \ + int cc = -1; \ + register ty##_v my_c __asm__("v7") = c; \ + __asm__( \ + "cr 0,0\n\t" \ + ".insn vrr,0x" #opc1 "000" #m6 "0000" #opc2 ",%[out],%[a]," \ + "%[b],7," #m5 ",0\n\t" \ + "ipm %[cc]\n\t" \ + "srl %[cc],28" \ + : [cc]"=d" (cc), [out] "+v" (out) \ + : [a] "v" (a), [b] "v" (b), [c] "v" (my_c) \ + : "cc"); \ + dump_##fmt##ty(out); \ + dump_cc(cc); \ + } + +#define INSNS \ + XTEST(e7,8e, v,f2, vfmssb, 0,2); \ + XTEST(e7,8e, w,f2, wfmssb, 8,2); \ + XTEST(e7,8e, w,f4, wfmsxb, 8,4); \ + XTEST(e7,8f, v,f2, vfmasb, 0,2); \ + XTEST(e7,8f, w,f2, wfmasb, 8,2); \ + XTEST(e7,8f, w,f4, wfmaxb, 8,4); \ + XTEST(e7,9e, v,f2, vfnmssb, 0,2); \ + XTEST(e7,9e, w,f2, wfnmssb, 8,2); \ + XTEST(e7,9e, w,f4, wfnmsxb, 8,4); \ + XTEST(e7,9f, v,f2, vfnmasb, 0,2); \ + XTEST(e7,9f, w,f2, wfnmasb, 8,2); \ + XTEST(e7,9f, w,f4, wfnmaxb, 8,4); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_ternops() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE +#undef TEST_EXEC + +/* -- Vector scalar compare operators -- */ + +#define TEST_EXEC(opc1,opc2,ty,insn,m3,m4) \ + do { \ + puts(#insn); \ + test_##insn##_##m3##_##m4(vec_##ty##_a, vec_##ty##_b); \ + test_##insn##_##m3##_##m4(vec_##ty##_b, vec_##ty##_a); \ + test_##insn##_##m3##_##m4(vec_##ty##_c, vec_##ty##_c); \ + test_##insn##_##m3##_##m4(vec_##ty##_a, vec_##ty##_e); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,ty,insn,m3,m4) \ + static void test_##insn##_##m3##_##m4(ty##_v a, ty##_v b) \ + { \ + int cc = -1; \ + __asm__( \ + "cr 0,0\n\t" \ + ".insn vrr,0x" #opc1 "00000000" #opc2 ",%[a],%[b],0," \ + #m3 "," #m4 ",0\n\t" \ + "ipm %[cc]\n\t" \ + "srl %[cc],28" \ + : [cc]"=d" (cc) \ + : [a]"v" (a), [b]"v" (b) \ + : "cc"); \ + printf("\tcc=%d\n", cc); \ + } + +#define INSNS \ + XTEST(e7,cb, f2, wfcsb, 2,0); \ + XTEST(e7,cb, f4, wfcxb, 4,0); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_scalar_compares() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE +#undef TEST_EXEC + +/* -- Vector FP test data class -- */ + +#define TEST_EXEC(opc1,opc2,fmt,ty1,ty2,insn,i3,m4,m5) \ + do { \ + puts(#insn); \ + test_##insn##_##m3##_##m4(vec_##ty2##_a); \ + test_##insn##_##m3##_##m4(vec_##ty2##_b); \ + test_##insn##_##m3##_##m4(vec_##ty2##_c); \ + test_##insn##_##m3##_##m4(vec_##ty2##_d); \ + test_##insn##_##m3##_##m4(vec_##ty2##_e); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,fmt,ty1,ty2,insn,i3,m4,m5) \ + static void test_##insn##_##m3##_##m4(ty2##_v a) \ + { \ + ty1##_v out = (ty1##_v) vec_ini; \ + int cc = -1; \ + __asm__( \ + "cr 0,0\n\t" \ + ".insn vri,0x" #opc1 "00000000" #opc2 ",%[out],%[a]," \ + #i3 "," #m4 "," #m5 "\n\t" \ + "ipm %[cc]\n\t" \ + "srl %[cc],28" \ + : [cc]"=d" (cc), [out]"+v" (out) \ + : [a]"v" (a) \ + : "cc"); \ + dump_##fmt##ty1(out); \ + dump_cc(cc); \ + } + +#define INSNS \ + XTEST(e7,4a, v,u2,f2, vftcisb, 0x864,2,0); \ + XTEST(e7,4a, w,u2,f2, wftcisb, 0x520,2,8); \ + XTEST(e7,4a, w,u4,f4, wftcixb, 0x3c0,4,0); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_vftci() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE +#undef TEST_EXEC + + +int main() +{ + test_all_unops(); + test_all_binops(); + test_all_ternops(); + test_all_scalar_compares(); + test_all_vftci(); + return 0; +} diff --git a/none/tests/s390x/vec2_float.stderr.exp b/none/tests/s390x/vec2_float.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/s390x/vec2_float.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/vec2_float.stdout.exp b/none/tests/s390x/vec2_float.stdout.exp new file mode 100644 index 0000000000..e021f08a35 --- /dev/null +++ b/none/tests/s390x/vec2_float.stdout.exp @@ -0,0 +1,389 @@ +vclfeb + 16777215 | 0 | 42 | 10000 + 4 | 3 | 42 | 1 + 0 | -1 | 0 | 0 + 0 | 0 | 0 | 0 +wclfeb + 16777215 | - | - | - + 4 | - | - | - + 0 | - | - | - + 0 | - | - | - +vcelfb + 0x1p+32 | 0x1p+31 | 0x1.5p+5 | 0x0p+0 + 0x1.fffffep+30 | 0x1p+0 | 0x1.f4p+9 | 0x1.ff06ap+31 + 0x1.fffffcp+22 | 0x1.cp+30 | 0x1.ffffb2p+31 | 0x1.fffep+15 + 0x1p+31 | 0x1p+27 | 0x0p+0 | 0x1.5p+5 +wcelfb + 0x1p+32 | - | - | - + 0x1.fffffep+30 | - | - | - + 0x1.fffffcp+22 | - | - | - + 0x1p+31 | - | - | - +vcfeb + 16777215 | -16777215 | 42 | 10000 + 4 | 3 | 42 | 1 + 0 | 2147483647 | 0 | -2147483648 + -2147483648 | -2147483648 | -2147483648 | -2147483648 +wcfeb + 16777215 | - | - | - + 4 | - | - | - + 0 | - | - | - + -2147483648 | - | - | - +vcefb + -0x1p+0 | 0x1p+31 | 0x1.5p+5 | 0x0p+0 + 0x1.fffffep+30 | 0x1p+0 | 0x1.f4p+9 | -0x1.f2bff8p+22 + 0x1.fffffcp+22 | 0x1.cp+30 | -0x1.388p+13 | 0x1.fffep+15 + 0x1p+31 | 0x1p+27 | 0x0p+0 | 0x1.5p+5 +wcefb + -0x1p+0 | - | - | - + 0x1.fffffep+30 | - | - | - + 0x1.fffffcp+22 | - | - | - + 0x1p+31 | - | - | - +vldeb + 0x1.fffffep+23 | 0x1.54p+5 + 0x1p+2 | 0x1.54p+5 + 0x0p+0 | -0x0p+0 + nan | nan +wldeb + 0x1.fffffep+23 | - + 0x1p+2 | - + 0x0p+0 | - + nan | - +wflld + 0x1.ffffffffffffep+51 + 0x1.999999999999ap-4 + -0x0p+0 + nan +vledb + 0x1p+52 | - | -0x1.fffffep+23 | - + 0x1.99999ap-4 | - | 0x1.8p+1 | - + -0x0p+0 | - | inf | - + nan | - | -nan | - +wledb + 0x1p+52 | - | - | - + 0x1.99999ap-4 | - | - | - + -0x0p+0 | - | - | - + nan | - | - | - +wflrx + 0x1.fffffep+23 | - + 0x1p+2 | - + inf | - + nan | - +vfisb + 0x1.fffffep+23 | -0x1.fffffep+23 | 0x1.5p+5 | 0x1.388p+13 + 0x1p+2 | 0x1.8p+1 | 0x1.5p+5 | 0x1p+0 + 0x0p+0 | inf | -0x0p+0 | -inf + nan | -nan | nan | -nan +wfisb + 0x1.fffffep+23 | - | - | - + 0x1p+2 | - | - | - + 0x0p+0 | - | - | - + nan | - | - | - +wfixb + 0x1.fffffep+23 + 0x1p+2 + inf + nan +vflcsb + -0x1.fffffep+23 | 0x1.fffffep+23 | -0x1.54p+5 | -0x1.388p+13 + -0x1p+2 | -0x1.8p+1 | -0x1.54p+5 | -0x1p+0 + -0x0p+0 | -inf | 0x0p+0 | inf + -nan | nan | -nan | nan +wflcsb + -0x1.fffffep+23 | - | - | - + -0x1p+2 | - | - | - + -0x0p+0 | - | - | - + -nan | - | - | - +wflcxb + -0x1.fffffep+23 + -0x1p+2 + -inf + -nan +vflnsb + -0x1.fffffep+23 | -0x1.fffffep+23 | -0x1.54p+5 | -0x1.388p+13 + -0x1p+2 | -0x1.8p+1 | -0x1.54p+5 | -0x1p+0 + -0x0p+0 | -inf | -0x0p+0 | -inf + -nan | -nan | -nan | -nan +wflnsb + -0x1.fffffep+23 | - | - | - + -0x1p+2 | - | - | - + -0x0p+0 | - | - | - + -nan | - | - | - +wflnxb + -0x1.fffffep+23 + -0x1p+2 + -inf + -nan +vflpsb + 0x1.fffffep+23 | 0x1.fffffep+23 | 0x1.54p+5 | 0x1.388p+13 + 0x1p+2 | 0x1.8p+1 | 0x1.54p+5 | 0x1p+0 + 0x0p+0 | inf | 0x0p+0 | inf + nan | nan | nan | nan +wflpsb + 0x1.fffffep+23 | - | - | - + 0x1p+2 | - | - | - + 0x0p+0 | - | - | - + nan | - | - | - +wflpxb + 0x1.fffffep+23 + 0x1p+2 + inf + nan +vfsqsb + 0x1.fffffep+11 | nan | 0x1.a13a9cp+2 | 0x1.9p+6 + 0x1p+1 | 0x1.bb67aep+0 | 0x1.a13a9cp+2 | 0x1p+0 + 0x0p+0 | inf | -0x0p+0 | nan + nan | -nan | nan | -nan +wfsqsb + 0x1.fffffep+11 | - | - | - + 0x1p+1 | - | - | - + 0x0p+0 | - | - | - + nan | - | - | - +wfsqxb + 0x1.fffffeffffffbfffffdfffffecp+11 + 0x1p+1 + inf + nan +vfssb + 0x1.fffff6p+23 | -0x1.000002p+24 | 0x0p+0 | 0x1.3878p+13 + -0x1.fffff6p+23 | 0x1.000002p+24 | 0x0p+0 | -0x1.3878p+13 + 0x1.fffffep+23 | -inf | 0x1.54p+5 | inf + nan | -nan | nan | -nan +wfssb + 0x1.fffff6p+23 | - | - | - + -0x1.fffff6p+23 | - | - | - + 0x1.fffffep+23 | - | - | - + nan | - | - | - +wfsxb + 0x1.fffff6p+23 + -0x1.fffff6p+23 + -inf + nan +vfasb + 0x1.000004p+24 | -0x1.fffff8p+23 | 0x1.54p+6 | 0x1.3888p+13 + 0x1.000004p+24 | -0x1.fffff8p+23 | 0x1.54p+6 | 0x1.3888p+13 + 0x1.fffffep+23 | inf | 0x1.54p+5 | -inf + nan | -nan | nan | -nan +wfasb + 0x1.000004p+24 | - | - | - + 0x1.000004p+24 | - | - | - + 0x1.fffffep+23 | - | - | - + nan | - | - | - +wfaxb + 0x1.000003p+24 + 0x1.000003p+24 + inf + nan +vfdsb + 0x1.fffffep+21 | -0x1.555554p+22 | 0x1p+0 | 0x1.388p+13 + 0x1.000002p-22 | -0x1.800002p-23 | 0x1p+0 | 0x1.a36e2ep-14 + inf | -0x0p+0 | -inf | -0x0p+0 + nan | -nan | nan | -nan +wfdsb + 0x1.fffffep+21 | - | - | - + 0x1.000002p-22 | - | - | - + inf | - | - | - + nan | - | - | - +wfdxb + 0x1.fffffep+21 + 0x1.000001000001000001000001p-22 + 0x0p+0 + nan +vfmsb + 0x1.fffffep+25 | -0x1.7ffffep+25 | 0x1.c39p+10 | 0x1.388p+13 + 0x1.fffffep+25 | -0x1.7ffffep+25 | 0x1.c39p+10 | 0x1.388p+13 + 0x0p+0 | -inf | -0x0p+0 | -inf + nan | -nan | nan | -nan +wfmsb + 0x1.fffffep+25 | - | - | - + 0x1.fffffep+25 | - | - | - + 0x0p+0 | - | - | - + nan | - | - | - +wfmxb + 0x1.fffffep+25 + 0x1.fffffep+25 + inf + nan +vfcesb + 0 | 0 | -1 | 0 + 0 | 0 | -1 | 0 + 0 | 0 | 0 | 0 + 0 | 0 | 0 | 0 +wfcesb + 0 | - | - | - + 0 | - | - | - + 0 | - | - | - + 0 | - | - | - +wfcexb + 0 + 0 + 0 + 0 +vfcesbs + 0 | 0 | -1 | 0 cc=1 + 0 | 0 | -1 | 0 cc=1 + 0 | 0 | 0 | 0 cc=3 + 0 | 0 | 0 | 0 cc=3 +wfcesbs + 0 | - | - | - cc=3 + 0 | - | - | - cc=3 + 0 | - | - | - cc=3 + 0 | - | - | - cc=3 +wfcexbs + 0 cc=3 + 0 cc=3 + 0 cc=3 + 0 cc=3 +vfchesb + -1 | 0 | -1 | -1 + 0 | -1 | -1 | 0 + -1 | 0 | -1 | -1 + 0 | 0 | 0 | 0 +wfchesb + -1 | - | - | - + 0 | - | - | - + -1 | - | - | - + 0 | - | - | - +wfchexb + -1 + 0 + 0 + 0 +vfchesbs + -1 | 0 | -1 | -1 cc=1 + 0 | -1 | -1 | 0 cc=1 + -1 | 0 | -1 | -1 cc=1 + 0 | 0 | 0 | 0 cc=3 +wfchesbs + -1 | - | - | - + 0 | - | - | - cc=3 + -1 | - | - | - + 0 | - | - | - cc=3 +wfchexbs + -1 + 0 cc=3 + 0 cc=3 + 0 cc=3 +vfminsb + 0x1p+2 | -0x1.fffffep+23 | 0x1.54p+5 | 0x1p+0 + 0x1p+2 | -0x1.fffffep+23 | 0x1.54p+5 | 0x1p+0 + 0x0p+0 | -0x1.fffffep+23 | -0x0p+0 | -inf + -0x1.fffffcp+23 | 0x1.fffffcp+23 | -0x1.7p+4 | -0x1.3878p+13 +wfminsb + 0x1p+2 | - | - | - + 0x1p+2 | - | - | - + 0x0p+0 | - | - | - + -0x1.fffffcp+23 | - | - | - +wfminxb + 0x1p+2 + 0x1p+2 + 0x1.fffffep+23 + -0x1.7p+4 +vfmaxsb + 0x1.fffffep+23 | 0x1.8p+1 | 0x1.54p+5 | 0x1.388p+13 + 0x1.fffffep+23 | 0x1.8p+1 | 0x1.54p+5 | 0x1.388p+13 + 0x1.fffffep+23 | inf | 0x1.54p+5 | 0x1.388p+13 + -0x1.fffffcp+23 | 0x1.fffffcp+23 | -0x1.7p+4 | -0x1.3878p+13 +wfmaxsb + 0x1.fffffep+23 | - | - | - + 0x1.fffffep+23 | - | - | - + 0x1.fffffep+23 | - | - | - + -0x1.fffffcp+23 | - | - | - +wfmaxxb + 0x1.fffffep+23 + 0x1.fffffep+23 + inf + -0x1.7p+4 +vfchsb + -1 | 0 | 0 | -1 + 0 | -1 | 0 | 0 + -1 | 0 | -1 | -1 + 0 | 0 | 0 | 0 +wfchsb + -1 | - | - | - + 0 | - | - | - + -1 | - | - | - + 0 | - | - | - +wfchxb + -1 + 0 + 0 + 0 +vfchsbs + -1 | 0 | 0 | -1 cc=1 + 0 | -1 | 0 | 0 cc=1 + -1 | 0 | -1 | -1 cc=1 + 0 | 0 | 0 | 0 cc=3 +wfchsbs + -1 | - | - | - + 0 | - | - | - cc=3 + -1 | - | - | - + 0 | - | - | - cc=3 +wfchxbs + -1 + 0 cc=3 + 0 cc=3 + 0 cc=3 +vfmssb + 0x1.fffffep+25 | -inf | 0x1.c39p+10 | inf + 0x1.3ffffep+26 | -0x1.fffffep+25 | 0x1.c95p+10 | 0x1.387cp+14 +wfmssb + 0x1.fffffep+25 | - | - | - + 0x1.3ffffep+26 | - | - | - +wfmsxb + -inf + 0x1.000004cp+26 +vfmasb + 0x1.fffffep+25 | inf | 0x1.c39p+10 | -inf + 0x1.8p+25 | -0x1p+25 | 0x1.bddp+10 | 0x1p+0 +wfmasb + 0x1.fffffep+25 | - | - | - + 0x1.8p+25 | - | - | - +wfmaxb + inf + 0x1.fffff28p+25 +vfnmssb + -0x1.fffffep+25 | inf | -0x1.c39p+10 | -inf + -0x1.3ffffep+26 | 0x1.fffffep+25 | -0x1.c95p+10 | -0x1.387cp+14 +wfnmssb + -0x1.fffffep+25 | - | - | - + -0x1.3ffffep+26 | - | - | - +wfnmsxb + inf + -0x1.000004cp+26 +vfnmasb + -0x1.fffffep+25 | -inf | -0x1.c39p+10 | inf + -0x1.8p+25 | 0x1p+25 | -0x1.bddp+10 | -0x1p+0 +wfnmasb + -0x1.fffffep+25 | - | - | - + -0x1.8p+25 | - | - | - +wfnmaxb + -inf + -0x1.fffff28p+25 +wfcsb + cc=2 + cc=1 + cc=0 + cc=3 +wfcxb + cc=2 + cc=1 + cc=0 + cc=3 +vftcisb + 0 | 0 | 0 | 0 cc=3 + 0 | 0 | 0 | 0 cc=3 + -1 | -1 | 0 | 0 cc=1 + 0 | 0 | 0 | 0 cc=3 + 0 | -1 | 0 | -1 cc=1 +wftcisb + 0 | - | - | - cc=3 + 0 | - | - | - cc=3 + 0 | - | - | - cc=3 + -1 | - | - | - + 0 | - | - | - cc=3 +wftcixb + -1 + -1 + 0 cc=3 + -1 + 0 cc=3 diff --git a/none/tests/s390x/vec2_float.vgtest b/none/tests/s390x/vec2_float.vgtest new file mode 100644 index 0000000000..1f92d59ece --- /dev/null +++ b/none/tests/s390x/vec2_float.vgtest @@ -0,0 +1,2 @@ +prog: vec2_float +prereq: test -e vec2_float && ../../../tests/s390x_features s390x-vx2 diff --git a/tests/s390x_features.c b/tests/s390x_features.c index e7939c4635..6a45199c9d 100644 --- a/tests/s390x_features.c +++ b/tests/s390x_features.c @@ -273,7 +273,7 @@ static int go(char *feature, char *cpu) } else if (strcmp(feature, "s390x-mi3") == 0 ) { match = facilities[0] & FAC_BIT(61); } else if (strcmp(feature, "s390x-vx2") == 0 ) { - match = facilities[2] & FAC_BIT(20); + match = (GET_HWCAP() & 0x800) && (facilities[2] & FAC_BIT(20)); } else { return 2; // Unrecognised feature. } |
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From: Andreas A. <ar...@so...> - 2023-01-11 15:47:48
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4f4cd4b8d5ec13ef92d97b0e9a9e0053e8bd094e commit 4f4cd4b8d5ec13ef92d97b0e9a9e0053e8bd094e Author: Andreas Arnez <ar...@li...> Date: Thu Dec 8 13:39:25 2022 +0100 s390: Add z16 support to ecag testcase The testcase 'none/tests/s390x/ecag' requires expected output from any machine it runs on. This is missing for z16, so add it. Diff: --- none/tests/s390x/Makefile.am | 1 + none/tests/s390x/ecag.stdout.exp-z16 | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index d8f9e4b894..2a22aefac2 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -41,6 +41,7 @@ EXTRA_DIST = \ $(addsuffix .vgtest,$(INSN_TESTS)) \ ecag.stdout.exp-z10ec ecag.stdout.exp-z196 ecag.stdout.exp-zec12 \ ecag.stdout.exp-z13 ecag.stdout.exp-z14 ecag.stdout.exp-z15 \ + ecag.stdout.exp-z16 \ op00.stderr.exp1 op00.stderr.exp2 op00.vgtest \ fixbr.vgtest fixbr.stderr.exp fixbr.stdout.exp \ fpext.vgtest fpext.stderr.exp fpext.stdout.exp \ diff --git a/none/tests/s390x/ecag.stdout.exp-z16 b/none/tests/s390x/ecag.stdout.exp-z16 new file mode 100644 index 0000000000..e3f1af306b --- /dev/null +++ b/none/tests/s390x/ecag.stdout.exp-z16 @@ -0,0 +1,21 @@ +L1 topology: separate data and instruction; private +L1 cache line size data: 256 +L1 cache line size insn: 256 +L1 total cachesize data: 131072 +L1 total cachesize insn: 131072 +L1 set. assoc. data: 8 +L1 set. assoc. insn: 8 +L2 topology: unified data and instruction; private +L2 cache line size data: 256 +L2 cache line size insn: 256 +L2 total cachesize data: 33554432 +L2 total cachesize insn: 33554432 +L2 set. assoc. data: 16 +L2 set. assoc. insn: 16 +L3 topology: unified data and instruction; shared +L3 cache line size data: 256 +L3 cache line size insn: 256 +L3 total cachesize data: 268435456 +L3 total cachesize insn: 268435456 +L3 set. assoc. data: 128 +L3 set. assoc. insn: 128 |
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From: Andreas A. <ar...@so...> - 2023-01-11 15:47:37
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1b8dcec1b4b9e086894378f819eb3f12044b0b0a commit 1b8dcec1b4b9e086894378f819eb3f12044b0b0a Author: Andreas Arnez <ar...@li...> Date: Thu Dec 1 15:20:21 2022 +0100 s390: Stop CC clobbering by VFMIN and VFMAX Valgrind's implementation of the VFMIN and VFMAX instructions clobbers the condition code, which is wrong. Stop doing that. Diff: --- VEX/priv/guest_s390_toIR.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 3ef104fcd9..250daeca13 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -19382,7 +19382,6 @@ s390_irgen_VFMIN(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5); IRDirty* d; - IRTemp cc = newTemp(Ity_I64); s390x_vec_op_details_t details = { .serialized = 0ULL }; details.op = S390_VEC_OP_VFMIN; @@ -19393,7 +19392,7 @@ s390_irgen_VFMIN(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) details.m5 = m5; details.m6 = m6; - d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op", + d = unsafeIRDirty_0_N(0, "s390x_dirtyhelper_vec_op", &s390x_dirtyhelper_vec_op, mkIRExprVec_2(IRExpr_GSPTR(), mkU64(details.serialized))); @@ -19413,7 +19412,6 @@ s390_irgen_VFMIN(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - s390_cc_set(cc); return "vfmin"; } @@ -19425,7 +19423,6 @@ s390_irgen_VFMAX(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5); IRDirty* d; - IRTemp cc = newTemp(Ity_I64); s390x_vec_op_details_t details = { .serialized = 0ULL }; details.op = S390_VEC_OP_VFMAX; @@ -19436,7 +19433,7 @@ s390_irgen_VFMAX(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) details.m5 = m5; details.m6 = m6; - d = unsafeIRDirty_1_N(cc, 0, "s390x_dirtyhelper_vec_op", + d = unsafeIRDirty_0_N(0, "s390x_dirtyhelper_vec_op", &s390x_dirtyhelper_vec_op, mkIRExprVec_2(IRExpr_GSPTR(), mkU64(details.serialized))); @@ -19456,7 +19453,6 @@ s390_irgen_VFMAX(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - s390_cc_set(cc); return "vfmax"; } |
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From: Andreas A. <ar...@so...> - 2023-01-11 15:47:32
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=73ab2978f8bfb5becc4bc7356228a117292ca51f commit 73ab2978f8bfb5becc4bc7356228a117292ca51f Author: Andreas Arnez <ar...@li...> Date: Thu Dec 1 11:02:12 2022 +0100 s390: Un-swap implementations of VFCH and VFCHE When running under Valgrind, the VFCH instruction behaves like VFCHE, and vice versa. Fix this. Diff: --- VEX/priv/host_s390_defs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index ac5ca6cbe8..c811dc5b80 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -11709,9 +11709,9 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn) case S390_VEC_FLOAT_COMPARE_EQUAL: return s390_emit_VFCE(buf, v1, v2, v3, s390_getM_from_size(size), 0, 0); case S390_VEC_FLOAT_COMPARE_LESS_OR_EQUAL: - return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0); - case S390_VEC_FLOAT_COMPARE_LESS: return s390_emit_VFCHE(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0); + case S390_VEC_FLOAT_COMPARE_LESS: + return s390_emit_VFCH(buf, v1, v3, v2, s390_getM_from_size(size), 0, 0); default: goto fail; |
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From: Andreas A. <ar...@so...> - 2023-01-11 15:47:28
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e05f55c77c4a330283778cfea042b6b18312e23d commit e05f55c77c4a330283778cfea042b6b18312e23d Author: Andreas Arnez <ar...@li...> Date: Wed Nov 30 19:15:53 2022 +0100 s390: Fix VFMA, VFMS, VFNMA, and VFNMS for 128-bit FP When trying to execute any of the vector float multiply-and-add family instructions, Valgrind panics with the message "Iex_Qop with F128 data". So far all F128 operations were implemented with instructions that operate on FP register pairs. However, such instructions don't exist for Iop_MAddF128 and Iop_MSubF128, so they must be implemented with vector instructions instead. This was missed when emitting them in "guest_s390_toIR.c". Add the missing support. This also involves adding a few new features to host_s390_defs: * a new vector operation S390_VEC_INIT_FROM_FPRS * the capability to move the left half of a VR to an FPR * S390_VEC_FLOAT_MADD/_MSUB for 128-bit sizes Diff: --- VEX/priv/host_s390_defs.c | 15 ++++++++++++--- VEX/priv/host_s390_defs.h | 1 + VEX/priv/host_s390_isel.c | 46 ++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 57 insertions(+), 5 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 239d9d2997..ac5ca6cbe8 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -8356,6 +8356,7 @@ s390_insn_as_string(const s390_insn *insn) case S390_VEC_PWSUM_DW: op = "v-vpwsumdw"; break; case S390_VEC_PWSUM_QW: op = "v-vpwsumqw"; break; case S390_VEC_INIT_FROM_GPRS: op = "v-vinitfromgprs"; break; + case S390_VEC_INIT_FROM_FPRS: op = "v-vinitfromfprs"; break; case S390_VEC_FLOAT_ADD: op = "v-vfloatadd"; break; case S390_VEC_FLOAT_SUB: op = "v-vfloatsub"; break; case S390_VEC_FLOAT_MUL: op = "v-vfloatmul"; break; @@ -8772,6 +8773,9 @@ s390_insn_move_emit(UChar *buf, const s390_insn *insn) return s390_emit_LGDRw(buf, dst, src); } } + if (dst_class == HRcFlt64 && src_class == HRcVec128) { + return s390_emit_VLR(buf, dst, src); + } /* A move between floating point registers and general purpose registers of different size should never occur and indicates an error elsewhere. */ @@ -11692,6 +11696,8 @@ s390_insn_vec_binop_emit(UChar *buf, const s390_insn *insn) return s390_emit_VSUMQ(buf, v1, v2, v3, s390_getM_from_size(size)); case S390_VEC_INIT_FROM_GPRS: return s390_emit_VLVGP(buf, v1, v2, v3); + case S390_VEC_INIT_FROM_FPRS: + return s390_emit_VMRH(buf, v1, v2, v3, 3); case S390_VEC_FLOAT_ADD: return s390_emit_VFA(buf, v1, v2, v3, s390_getM_from_size(size), 0); case S390_VEC_FLOAT_SUB: @@ -11722,6 +11728,7 @@ static UChar * s390_insn_vec_triop_emit(UChar *buf, const s390_insn *insn) { s390_vec_triop_t tag = insn->variant.vec_triop.tag; + UChar size = insn->size; UChar v1 = hregNumber(insn->variant.vec_triop.dst); UChar v2 = hregNumber(insn->variant.vec_triop.op1); UChar v3 = hregNumber(insn->variant.vec_triop.op2); @@ -11729,13 +11736,15 @@ s390_insn_vec_triop_emit(UChar *buf, const s390_insn *insn) switch (tag) { case S390_VEC_PERM: { - vassert(insn->size == 16); + vassert(size == 16); return s390_emit_VPERM(buf, v1, v2, v3, v4); } case S390_VEC_FLOAT_MADD: - return s390_emit_VFMA(buf, v1, v2, v3, v4, 0, 3); + return s390_emit_VFMA(buf, v1, v2, v3, v4, 0, + s390_getM_from_size(size)); case S390_VEC_FLOAT_MSUB: - return s390_emit_VFMS(buf, v1, v2, v3, v4, 0, 3); + return s390_emit_VFMS(buf, v1, v2, v3, v4, 0, + s390_getM_from_size(size)); default: goto fail; } diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h index dc116106ef..375cc8402a 100644 --- a/VEX/priv/host_s390_defs.h +++ b/VEX/priv/host_s390_defs.h @@ -402,6 +402,7 @@ typedef enum { S390_VEC_PWSUM_QW, S390_VEC_INIT_FROM_GPRS, + S390_VEC_INIT_FROM_FPRS, S390_VEC_FLOAT_ADD, S390_VEC_FLOAT_SUB, S390_VEC_FLOAT_MUL, diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 32c209edb5..3ae7c07c07 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -2153,8 +2153,47 @@ s390_isel_float128_expr_wrk(HReg *dst_hi, HReg *dst_lo, ISelEnv *env, vpanic("Iex_Get with F128 data"); /* --------- 4-ary OP --------- */ - case Iex_Qop: - vpanic("Iex_Qop with F128 data"); + case Iex_Qop: { + IRQop *qop = expr->Iex.Qop.details; + s390_vec_triop_t vecop; + HReg op1_hi, op1_lo, op2_hi, op2_lo, op3_hi, op3_lo; + HReg dst, dstv_lo, op1, op2, op3; + + s390_isel_float128_expr(&op1_hi, &op1_lo, env, qop->arg2); + s390_isel_float128_expr(&op2_hi, &op2_lo, env, qop->arg3); + s390_isel_float128_expr(&op3_hi, &op3_lo, env, qop->arg4); + + /* Cannot carry out with FPRs; move operands to VRs instead. */ + op1 = newVRegV(env); + op2 = newVRegV(env); + op3 = newVRegV(env); + dst = newVRegV(env); + dstv_lo = newVRegV(env); + addInstr(env, s390_insn_vec_binop(8, S390_VEC_INIT_FROM_FPRS, + op1, op1_hi, op1_lo)); + addInstr(env, s390_insn_vec_binop(8, S390_VEC_INIT_FROM_FPRS, + op2, op2_hi, op2_lo)); + addInstr(env, s390_insn_vec_binop(8, S390_VEC_INIT_FROM_FPRS, + op3, op3_hi, op3_lo)); + + switch (qop->op) { + case Iop_MAddF128: vecop = S390_VEC_FLOAT_MADD; break; + case Iop_MSubF128: vecop = S390_VEC_FLOAT_MSUB; break; + default: + goto irreducible; + } + + set_bfp_rounding_mode_in_fpc(env, qop->arg1); + addInstr(env, s390_insn_vec_triop(16, vecop, dst, op1, op2, op3)); + addInstr(env, s390_insn_vec_binop(8, S390_VEC_MERGEL, dstv_lo, dst, dst)); + + /* Move result to destination FPRs. */ + *dst_hi = newVRegF(env); + *dst_lo = newVRegF(env); + addInstr(env, s390_insn_move(8, *dst_hi, dst)); + addInstr(env, s390_insn_move(8, *dst_lo, dstv_lo)); + return; + } /* --------- TERNARY OP --------- */ case Iex_Triop: { @@ -4797,6 +4836,9 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr) } } + case Iex_Qop: { + } + /* --------- MULTIPLEX --------- */ case Iex_ITE: { IRExpr *cond_expr = expr->Iex.ITE.cond; |
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From: Andreas A. <ar...@so...> - 2023-01-11 15:47:25
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6da4025b59253312a24eb2650190a4fcd8f2e634 commit 6da4025b59253312a24eb2650190a4fcd8f2e634 Author: Andreas Arnez <ar...@li...> Date: Thu Oct 13 14:29:08 2022 +0200 Bug 460356 -- s390: Fix code generation for Iop_Sqrt32Fx4 There is no instruction selector for Iop_Sqrt32Fx4, leading to Valgrind panicking with the message: s390_isel_vec_expr: cannot reduce tree Fix this. Diff: --- NEWS | 1 + VEX/priv/host_s390_isel.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/NEWS b/NEWS index fb3b05fa9d..041ff5ba65 100644 --- a/NEWS +++ b/NEWS @@ -85,6 +85,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 444488 Use glibc.pthread.stack_cache_size tunable 444568 drd/tests/pth_barrier_thr_cr fails on Fedora 38 459476 vgdb: allow address reuse to avoid "address already in use" errorsuse" errors +460356 s390: Sqrt32Fx4 -- cannot reduce tree 462830 WARNING: unhandled amd64-freebsd syscall: 474 463027 broken check for MPX instruction support in assembler diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index f037255cb8..32c209edb5 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -4552,6 +4552,10 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr) goto Iop_VV_wrk; } + case Iop_Sqrt32Fx4: + size = 4; + vec_unop = S390_VEC_FLOAT_SQRT; + goto Iop_irrm_V_wrk; case Iop_Sqrt64Fx2: size = 8; vec_unop = S390_VEC_FLOAT_SQRT; |
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From: Mark W. <ma...@kl...> - 2023-01-11 15:01:33
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Hi Philippe, On Wed, 2023-01-11 at 11:50 +0100, Philippe Waroquiers wrote: > On Tue, 2023-01-10 at 14:40 +0100, Mark Wielaard wrote: > > Does that look correct? > Yes, the approach looks correct to me (but I did not test the patch). > > I think it would be good to put a specific comment for the new filter patterns to > indicate that these are to remove the loading error messages when running > in a .vg_in_place/not installed setup. > because a missing file looks frightening :). Thanks. Added comments and pushed. Hopefully this fixes some failures seen on the nightly builders. (It does fix the gdb_server tests on my local setup) Cheers, Mark |
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From: Mark W. <ma...@so...> - 2023-01-11 14:46:57
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c5d52a4056f6d732622278d1f65c4f8090533880 commit c5d52a4056f6d732622278d1f65c4f8090533880 Author: Mark Wielaard <ma...@kl...> Date: Wed Jan 11 15:44:27 2023 +0100 gdbserver tests filter out uninstalled python scripts warnings Filter out loading error messages when python scripts haven't been installed yet (running against vg-in-place) Diff: --- gdbserver_tests/filter_gdb.in | 5 +++++ gdbserver_tests/filter_vgdb.in | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in index 03f26dc860..28f807d09e 100755 --- a/gdbserver_tests/filter_gdb.in +++ b/gdbserver_tests/filter_gdb.in @@ -18,6 +18,11 @@ cat > $PATTERNFILE <<EOF # delete messages produced by valgrind python code loading. /Loaded.*valgrind-monitor.py$/d /Type "help valgrind" for more info\.$/d +# and remove loading error messages when python scripts haven't +# been installed yet (running against vg-in-place) +/warning: Missing auto-load script.*/d +/of file .*vgpreload.*so.*/d +/Use.*info auto-load python-scripts.*/d # delete messages produced when GDB auto-load denies loading python code. # Note that the first pattern is also present in filter_vgdb.in diff --git a/gdbserver_tests/filter_vgdb.in b/gdbserver_tests/filter_vgdb.in index fb5c484bf8..bd593d91c9 100755 --- a/gdbserver_tests/filter_vgdb.in +++ b/gdbserver_tests/filter_vgdb.in @@ -32,6 +32,11 @@ $SED -e '/_exit.c: Inappropriate ioctl for device\./d' | # filter python loading denied error message (see also filter_gdb.in) $SED -e '/warning: File .*valgrind-monitor.py.*declined.*/d' | +# and remove loading error messages when python scripts haven't +# been installed yet (running against vg-in-place) +$SED -e '/warning: Missing auto-load script.*/d' | +$SED -e '/of file .*vgpreload.*so.*/d' | +$SED -e '/Use.*info auto-load python-scripts.*/d' | # and filter out any remaining empty lines $SED -e '/^$/d' |
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From: Philippe W. <phi...@sk...> - 2023-01-11 10:50:41
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On Tue, 2023-01-10 at 14:40 +0100, Mark Wielaard wrote: > Hi, > > On Mon, 2023-01-09 at 08:53 +0100, Paul Floyd wrote: > > Unfortunately I think that there is a problem on FreeBSD. As already > > said there is an issue on a clean system when running in the build > > directory. Because the auto-load uses VG_LIBDIR which is based on the > > configure -prefix rather than the in-place location the scripts won't > > load if you haven't done a make install. > > > > The same should hold for the nightly tests. The script does a make / > > make check / make install and then a make regtest in the build dir. > > So that should work. > > > > I also see that several of the Linux nightlies also have failures. > > This issue seems indeed that you get warnings like: > > warning: Missing auto-load script at offset 0 in section .debug_gdb_scripts > of file /home/mark/src/valgrind/./.in_place/vgpreload_core-amd64-linux.so. > Use `info auto-load python-scripts [REGEXP]' to list them. > > Unless you explicitly installed valgrind-monitor.py in the VG_LIBDIR > path. > > The following filters help with that: > > diff --git a/gdbserver_tests/filter_gdb.in b/gdbserver_tests/filter_gdb.in > index 03f26dc86..b70dc5201 100755 > --- a/gdbserver_tests/filter_gdb.in > +++ b/gdbserver_tests/filter_gdb.in > @@ -18,6 +18,9 @@ cat > $PATTERNFILE <<EOF > # delete messages produced by valgrind python code loading. > /Loaded.*valgrind-monitor.py$/d > /Type "help valgrind" for more info\.$/d > +/warning: Missing auto-load script.*/d > +/of file .*vgpreload.*so.*/d > +/Use.*info auto-load python-scripts.*/d > > > # delete messages produced when GDB auto-load denies loading python code. > # Note that the first pattern is also present in filter_vgdb.in > diff --git a/gdbserver_tests/filter_vgdb.in b/gdbserver_tests/filter_vgdb.in > index fb5c484bf..13e9a344e 100755 > --- a/gdbserver_tests/filter_vgdb.in > +++ b/gdbserver_tests/filter_vgdb.in > @@ -32,6 +32,9 @@ $SED -e '/_exit.c: Inappropriate ioctl for device\./d' | > > > # filter python loading denied error message (see also filter_gdb.in) > $SED -e '/warning: File .*valgrind-monitor.py.*declined.*/d' | > +$SED -e '/warning: Missing auto-load script.*/d' | > +$SED -e '/of file .*vgpreload.*so.*/d' | > +$SED -e '/Use.*info auto-load python-scripts.*/d' | > > > # and filter out any remaining empty lines > $SED -e '/^$/d' > > Does that look correct? Yes, the approach looks correct to me (but I did not test the patch). I think it would be good to put a specific comment for the new filter patterns to indicate that these are to remove the loading error messages when running in a .vg_in_place/not installed setup. because a missing file looks frightening :). Thanks Philippe |