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From: Paul F. <pj...@wa...> - 2021-09-23 19:05:42
|
On 9/22/21 1:02 PM, Mark Wielaard wrote: > Hi, > > I would like to propose we do a valgrind 3.18.0 release next month. > There have been various useful changes since 3.17.0 for power10, s390x > z15 updates, arm64 v8.2, glibc 2.34 updates (which are really needed, > without them things simply break). > > I have backported most of the above improvements to the Fedora valgrind > package (mainly because Fedora 35 has already switched to glibc 2.34), > but that contains 25 patches now (where the power10 and z15 backports > count as just one, so it is more like 35 patches), which is not ideal. > > There is also the DWARF reader speedup patch: > https://bugs.kde.org/show_bug.cgi?id=442061 > which I would really like to see go in because it really helps startup > time (especially with distros that use debuginfod, which valgrind now > also supports). > > I propose to do the release on October 15. So we have some time to go > over the open bugs and see which really should get resolved before > then. Please do respond if you have bugs/patches that really deserve to > be resolved before the 3.18.0 release. Hi Mark I have FreeBSD support that I'd like to add. I'll refresh the patches in bugzilla. Not much has changed, but there has been at least one merge conflict since I last generated the patches. A+ Paul |
|
From: Julian S. <se...@so...> - 2021-09-23 13:47:34
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e3f6c6610401ce4dfd87efe54ac87cdaa0b0f9bd commit e3f6c6610401ce4dfd87efe54ac87cdaa0b0f9bd Author: Julian Seward <js...@ac...> Date: Thu Sep 23 15:46:21 2021 +0200 amd64: add spec rules for: S/NS after ADDL, S after ADDQ. Diff: --- VEX/priv/guest_amd64_helpers.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c index af2ddc29c5..9d61e7a0fd 100644 --- a/VEX/priv/guest_amd64_helpers.c +++ b/VEX/priv/guest_amd64_helpers.c @@ -1092,6 +1092,7 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, /*---------------- ADDQ ----------------*/ + /* 4, */ if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondZ)) { /* long long add, then Z --> test (dst+src == 0) */ return unop(Iop_1Uto64, @@ -1100,8 +1101,22 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, mkU64(0))); } + /* 8, */ + if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondS)) { + /* long long add, then S (negative) + --> (dst+src)[63] + --> ((dst + src) >>u 63) & 1 + */ + return binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(63)), + mkU64(1)); + } + /*---------------- ADDL ----------------*/ + /* 0, */ if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondO)) { /* This is very commonly generated by Javascript JITs, for the idiom "do a 32-bit add and jump to out-of-line code if @@ -1127,6 +1142,32 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, } + /* 8, 9 */ + if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondS)) { + /* long add, then S (negative) + --> (dst+src)[31] + --> ((dst +64 src) >>u 31) & 1 + Pointless to narrow the args to 32 bit before the add. */ + return binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(31)), + mkU64(1)); + } + if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondNS)) { + /* long add, then NS (not negative) + --> (dst+src)[31] ^ 1 + --> (((dst +64 src) >>u 31) & 1) ^ 1 + Pointless to narrow the args to 32 bit before the add. */ + return binop(Iop_Xor64, + binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(31)), + mkU64(1)), + mkU64(1)); + } + /*---------------- SUBQ ----------------*/ /* 0, */ |