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From: Carl L. <ca...@so...> - 2021-09-30 23:13:56
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bcbfa9e9006aa377a4ed19919af9be6e4ac19267 commit bcbfa9e9006aa377a4ed19919af9be6e4ac19267 Author: Carl Love <ce...@us...> Date: Tue Sep 28 20:58:22 2021 +0000 fix compiler print format warnings in test_isa_3_0.c GCC fixed the compiler warnings long long types. Add explicit casts so gcc will not generate compile warnings. Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_0.c | 151 ++++++++++++++++++++++++---------------- 2 files changed, 92 insertions(+), 60 deletions(-) diff --git a/NEWS b/NEWS index ef36395dea..8f62518401 100644 --- a/NEWS +++ b/NEWS @@ -63,6 +63,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 443178 Powerpc, test jm-mfspr expected output needs to be updated. 443179 Need new test for the lxvx and stxvx instructions on ISA 2.07 and ISA 3.0 systems. +443180 The subnormal test and the ISA 3.0 test generate compiler warnings. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c index cf9df8ac9c..6eca370a39 100644 --- a/none/tests/ppc64/test_isa_3_0.c +++ b/none/tests/ppc64/test_isa_3_0.c @@ -2633,8 +2633,8 @@ static void testfunction_vector_absolute (const char* instruction_name, printf("%s xa:%016lx %016lx xb:%016lx %016lx ", instruction_name, - vec_xa[1],vec_xa[0], - vec_xb[1],vec_xb[0] + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0] ); printf(" => "); @@ -2644,7 +2644,8 @@ static void testfunction_vector_absolute (const char* instruction_name, GET_CR(cr); - printf(" xt:%016lx %016lx (%08x)\n", vec_xt[1], vec_xt[0], cr); + printf(" xt:%016lx %016lx (%08x)\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], cr); } if (verbose) printf("\n"); } @@ -2673,9 +2674,9 @@ static void testfunction_vector_xxpermute (const char* instruction_name, printf("%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx] => ", instruction_name, - vec_xa[1], vec_xa[0], - vec_xt[1], vec_xt[0], - vec_xb[1], vec_xb[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xt[1], (unsigned long)vec_xt[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0]); SET_CR_ZERO; @@ -2683,14 +2684,15 @@ static void testfunction_vector_xxpermute (const char* instruction_name, GET_CR(cr); - printf(" %016lx %016lx (%08x)\n", vec_xt[1], vec_xt[0], cr); + printf(" %016lx %016lx (%08x)\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], cr); #if defined (DEBUG_VECTOR_PERMUTE) printf("DEBUG:%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx]\n", ignore_name, - vec_xa[1], vec_xa[0], - vec_xt[1], vec_xt[0], - vec_xb[1], vec_xb[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xt[1], (unsigned long)vec_xt[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0]); #endif } if (verbose) printf("\n"); @@ -2719,13 +2721,13 @@ static void testfunction_vector_logical_one (const char* instruction_name, printf("%s xa:%016lx %016lx xt:%016lx %016lx => ", instruction_name, - vec_xa[1], vec_xa[0], - vec_xt[1], vec_xt[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xt[1], (unsigned long)vec_xt[0]); (*test_function)(); printf(" xt:%016lx %016lx\n", - vec_xt[1], vec_xt[0]); + (unsigned long)vec_xt[1], (unsigned long)vec_xt[0]); } } if (verbose) printf("\n"); @@ -2752,7 +2754,7 @@ static void testfunction_gpr_vector_logical_one (const char* instruction_name, printf("%s rt xt:%016lx %016lx => ", instruction_name, - vec_xa[1], vec_xa[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0]); (*test_function)(); @@ -2786,9 +2788,9 @@ static void testfunction_vector_logical_four (const char* instruction_name, printf("%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx] => ", instruction_name, - vec_xa[1], vec_xa[0], - vec_xb[1], vec_xb[0], - vec_xc[1], vec_xc[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0], + (unsigned long)vec_xc[1], (unsigned long)vec_xc[0]); SET_CR_ZERO; @@ -2796,7 +2798,8 @@ static void testfunction_vector_logical_four (const char* instruction_name, GET_CR(cr); - printf(" %016lx %016lx (%08x)\n", vec_xt[1], vec_xt[0], cr); + printf(" %016lx %016lx (%08x)\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], cr); } } @@ -2827,8 +2830,8 @@ void testfunction_vector_insert_or_extract_immediate (const char* instruction_na * suppress output for those cases per the global variable. */ for (x_index = 0; x_index < 16 ; x_index++) { - vec_xb[0] = (unsigned long) vsxargs[i]; - vec_xb[1] = (unsigned long) vsxargs[i+1]; + vec_xb[0] = (unsigned long)vsxargs[i]; + vec_xb[1] = (unsigned long)vsxargs[i+1]; /* Run each test against all zeros and then all ones, * This is intended to help any bitfield changes stand out. @@ -2844,10 +2847,12 @@ void testfunction_vector_insert_or_extract_immediate (const char* instruction_na if (!insert_extract_error) { printf("%s %016lx %016lx [%d] (into%s) => ", - instruction_name, vec_xb[1], vec_xb[0], x_index, + instruction_name, (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0], x_index, (t == 0 ? " zeros" : " ones") ); - printf("%016lx %016lx\n", vec_xt[1], vec_xt[0]); + printf("%016lx %016lx\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); } } } @@ -2871,11 +2876,13 @@ static void testfunction_vector_immediate (const char * instruction_name, vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff; printf("%s %016lx %016lx [%2x] => ", - instruction_name, vec_xt[1], vec_xt[0], x_splat); + instruction_name, (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], x_splat); (*test_function)(); - printf("%016lx %016lx\n", vec_xt[1], vec_xt[0]); + printf("%016lx %016lx\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); } } } @@ -2906,13 +2913,15 @@ static void testfunction_vector_loadstore (const char* instruction_name, initialize_buffer(buffer_pattern); printf("%s ", instruction_name); - printf("%016lx %016lx ", vec_xt[1], vec_xt[0]); + printf("%016lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dump_small_buffer(); printf(" =>\n"); (*test_function)(); - printf(" %016lx %016lx ", vec_xt[1], vec_xt[0]); + printf(" %016lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dump_small_buffer(); printf("\n"); } @@ -2943,12 +2952,14 @@ static void testfunction_vectorscalar_move_tofrom (const char * instruction_name vec_xt[1] = pattern[v%PATTERN_SIZE]; printf("%s ", instruction_name); - printf("%016lx %016lx %lx %016lx ", vec_xt[1], vec_xt[0], + printf("%016lx %016lx %lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], (long unsigned)r14, (long unsigned)r15 ); (*test_function)(); - printf("=> %016lx %016lx %lx %016lx", vec_xt[1], vec_xt[0], + printf("=> %016lx %016lx %lx %016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], (long unsigned)r14, (long unsigned)r15 ); printf("\n"); } @@ -2998,7 +3009,8 @@ static void testfunction_vector_scalar_loadstore_length (const char* instruction initialize_buffer(buffer_pattern); printf("%s ", instruction_name); - printf("%016lx %016lx ", vec_xt[1], vec_xt[0] ); + printf("%016lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0] ); if (uses_bits_0to7(instruction_name)) { printf(" 0x%2lx ", (long unsigned)r15>>56 ); @@ -3029,8 +3041,8 @@ static void testfunction_vector_scalar_loadstore_length (const char* instruction vec_xt[1] &= 0xFFFFFFFF00000000; } - printf("=> %016lx %016lx & %16lx", vec_xt[1], vec_xt[0], - (long unsigned)r15 ); + printf("=> %016lx %016lx & %16lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0], (long unsigned)r15 ); dump_small_buffer(); printf("\n"); @@ -3052,7 +3064,8 @@ static void testfunction_vector_count_bytes (const char* instruction_name, r14 = 0; printf("%s ", instruction_name); - printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r14); + printf("%016lx %016lx %2d ", (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0], (unsigned)r14); (*test_function)(); @@ -3074,7 +3087,8 @@ static void testfunction_vector_extract (const char* instruction_name, r14 = 0; printf("%s ", instruction_name); - printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r15); + printf("%016lx %016lx %2d ", (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0], (unsigned)r15); (*test_function)(); @@ -3096,11 +3110,13 @@ static void testfunction_vector_extend_sign (const char* instruction_name, vec_xt = (vector unsigned long){0, 0}; printf("%s ", instruction_name); - printf("%016lx %016lx ", vec_xb[1], vec_xb[0]); + printf("%016lx %016lx ",(unsigned long) vec_xb[1], + (unsigned long)vec_xb[0]); (*test_function)(); - printf("=> %016lx %016lx\n", vec_xt[1], vec_xt[0]); + printf("=> %016lx %016lx\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); } } @@ -3210,7 +3226,8 @@ static inline void testfunction_bcd_setup_inputs(const char * instruction_name, static inline void testfunction_bcd_display_outputs(const char * instruction_name) { - printf(" xt:%016lx %016lx", vec_xt[1], vec_xt[0] ); + printf(" xt:%016lx %016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0] ); if (convert_to_zoned(instruction_name)) { /* convert to zoned */ @@ -3276,7 +3293,8 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name, vec_xt = (vector unsigned long){0, 0}; printf("%s ", instruction_name); - printf("%016lx %016lx ", vec_xb[1], vec_xb[0]); + printf("%016lx %016lx ", (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0]); SET_FPSCR_ZERO @@ -3284,7 +3302,8 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name, GET_FPSCR(local_fpscr); - printf("=> %016lx %016lx", vec_xt[1], vec_xt[0]); + printf("=> %016lx %016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dissect_fpscr(local_fpscr); printf("\n"); } @@ -3330,12 +3349,13 @@ testfunction_vector_scalar_compare_double (const char* instruction_name, SET_FPSCR_ZERO if (instruction_only_uses_dword0_inputs(instruction_name)) { printf("%s %016lx %016lx", - instruction_name, vec_xa[1], vec_xb[1]); + instruction_name, (unsigned long)vec_xa[1], + (unsigned long)vec_xb[1]); } else { printf("%s %016lx %016lx %016lx %016lx", instruction_name, - vec_xa[1], vec_xa[0], - vec_xb[1], vec_xb[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0]); } if (verbose) printf(" cr#%d ", x_index); @@ -3345,7 +3365,8 @@ testfunction_vector_scalar_compare_double (const char* instruction_name, (*test_function)(); if (instruction_only_uses_dword0_inputs(instruction_name)) { - printf("%016lx %016lx", vec_xt[1], vec_xt[0]); + printf("%016lx %016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); } dissect_fpscr(local_fpscr); @@ -3397,14 +3418,16 @@ testfunction_vector_scalar_data_class (const char* instruction_name, if (dcmx_match || (verbose>2)) { printf("%s %016lx, %016lx ", - instruction_name, vec_xb[1], vec_xb[0]); + instruction_name, (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0]); print_dcmx_field(x_index); if (dcmx_match) printf(" => Match. "); - printf(" %016lx, %016lx ", vec_xt[1], vec_xt[0]); + printf(" %016lx, %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dissect_cr_rn(local_cr,3); dissect_fpscr_dcmx_indicator(local_fpscr); @@ -3412,9 +3435,11 @@ testfunction_vector_scalar_data_class (const char* instruction_name, } printf("%s %016lx, %016lx => ", - instruction_name, vec_xb[1], vec_xb[0]); + instruction_name, (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0]); - printf(" %016lx, %016lx\n", vec_xt[1], vec_xt[0]); + printf(" %016lx, %016lx\n", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); } } } @@ -3444,8 +3469,8 @@ static void testfunction_vector_scalar_compare_quads (const char* instruction_na */ printf("%s %016lx%016lx %016lx%016lx (cr#%d) => ", instruction_name, - vec_xa[1], vec_xa[0], - vec_xb[1], vec_xb[0], + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0], x_index); SET_CR_ZERO @@ -3482,7 +3507,7 @@ static void testfunction_vector_scalar_rounding_quads (const char* instruction_n printf("%s %016lx%016lx (R=%x) (RMC=%x) => ", instruction_name, - vec_xb[1], vec_xb[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0], (x_index & 0x4) >> 2, x_index & 0x3); SET_CR_ZERO @@ -3492,7 +3517,8 @@ static void testfunction_vector_scalar_rounding_quads (const char* instruction_n GET_FPSCR(local_fpscr); - printf("%016lx%016lx", vec_xt[1], vec_xt[0]); + printf("%016lx%016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dissect_fpscr(local_fpscr); printf("\n"); } @@ -3525,15 +3551,16 @@ static void testfunction_vector_three_special (const char* instruction_name, SET_FPSCR_ZERO; printf("%s %016lx%016lx %016lx%016lx %016lx%016lx => ", instruction_name, - vec_xa[1], vec_xa[0], - vec_xb[1], vec_xb[0], - vec_xt[1], vec_xt[0]); + (unsigned long)vec_xa[1], (unsigned long)vec_xa[0], + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0], + (unsigned long)vec_xt[1], (unsigned long)vec_xt[0]); (*test_function)(); GET_FPSCR(local_fpscr); - printf(" %016lx%016lx", vec_xt[1], vec_xt[0]); + printf(" %016lx%016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); dissect_fpscr(local_fpscr); printf("\n"); } @@ -3579,7 +3606,7 @@ static void testfunction_vector_scalar_two_double(const char* instruction_name, binary16_float_vsxargs[(nb_float_vsxargs - 1) - i ] << 48 }; printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ", - vec_xb[1], vec_xb[0]); + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0]); } else if (uses_single_precision_input(instruction_name)) { vec_xb = (vector unsigned long) { @@ -3589,7 +3616,7 @@ static void testfunction_vector_scalar_two_double(const char* instruction_name, binary32_float_vsxargs[nb_float_vsxargs - 1 - j ] << 32 }; printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ", - vec_xb[1], vec_xb[0]); + (unsigned long)vec_xb[1], (unsigned long)vec_xb[0]); } else { /* uses double */ r14 = binary64_float_vsxargs[i]; @@ -3599,7 +3626,8 @@ static void testfunction_vector_scalar_two_double(const char* instruction_name, vec_xt = (vector unsigned long){0, 0}; - printf("%016lx %016lx ", vec_xb[1], vec_xb[0] ); + printf("%016lx %016lx ", (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0] ); if ((verbose > 2) && uses_double_precision_input(instruction_name)) { dissect_binary64_float(vec_xb[1]); @@ -3612,7 +3640,8 @@ static void testfunction_vector_scalar_two_double(const char* instruction_name, (*test_function)(); GET_FPSCR(local_fpscr); - printf(" %016lx %016lx", vec_xt[1], vec_xt[0]); + printf(" %016lx %016lx", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); if ((verbose > 2) && uses_half_precision_output(instruction_name)) { dissect_double_as_16s(vec_xt[1]); @@ -3834,12 +3863,14 @@ static void testfunction_bcd_misc (const char* instruction_name, if (short_circuit) continue; printf("%s ", instruction_name); - printf("xa:%016lx %016lx ", vec_xa[1], vec_xa[0]); + printf("xa:%016lx %016lx ", (unsigned long)vec_xa[1], + (unsigned long)vec_xa[0]); if (!shift_or_truncate_instruction) dissect_packed_decimal_sign(xa_sign); - printf(" xb:%016lx %016lx ", vec_xb[1], vec_xb[0]); + printf(" xb:%016lx %016lx ", (unsigned long)vec_xb[1], + (unsigned long)vec_xb[0]); if (convert_from_zoned(instruction_name)) { /* convert from zoned */ |
|
From: Carl L. <ca...@so...> - 2021-09-30 23:13:51
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ef411515d9c63b29af24f712f7d53800d912230a commit ef411515d9c63b29af24f712f7d53800d912230a Author: Carl Love <ce...@us...> Date: Tue Sep 28 19:54:49 2021 +0000 Fix compiler warnings for subnormal_test.c GCC fixed the compiler warnings long long types. Add explicit casts so gcc will not generate compile warnings. Diff: --- none/tests/ppc64/subnormal_test.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/none/tests/ppc64/subnormal_test.c b/none/tests/ppc64/subnormal_test.c index 00a0ad8d16..6e033706fe 100644 --- a/none/tests/ppc64/subnormal_test.c +++ b/none/tests/ppc64/subnormal_test.c @@ -75,6 +75,13 @@ void do_tests( void ) { vector unsigned long srcA, srcB, srcC, arg_list[NUM_ARGS], dst; int i, j, k; + srcA[0] = 0; // initialize to remove compiler warnings + srcA[1] = 0; + srcB[0] = 0; // initialize to remove compiler warnings + srcB[1] = 0; + srcC[0] = 0; // initialize to remove compiler warnings + srcC[1] = 0; + arg_list[0][0] = 0x8000012480000124ULL; arg_list[0][1] = 0x8000012480000124ULL; @@ -124,7 +131,8 @@ void do_tests( void ) { srcA[0] = arg_list[i][0]; srcA[1] = arg_list[i][1]; - printf ("srcA = 0x%016lx 0x%016lx\n\n", srcA[1], srcA[0]); + printf ("srcA = 0x%016lx 0x%016lx\n\n", (unsigned long)srcA[1], + (unsigned long) srcA[0]); __asm__ __volatile__ ("vcfsx %0,%1,31" : "=v" (dst): "v" (srcA)); printf (" vcfsx(srcA) result = "); print_vector_elements(dst); @@ -165,7 +173,7 @@ void do_tests( void ) { number. Square root can't generate a subnormal result. */ __asm__ __volatile__ ("vrsqrtefp %0,%1" : "=v" (dst): "v" (srcA)); printf (" vrsqrtefp(srcA) result = 0x%016lx 0x%016lx\n\n", - dst[1], dst[0]); + (unsigned long) dst[1], (unsigned long) dst[0]); for ( j = START_j; j < STOP_j; j++) { srcB[0] = arg_list[j][0]; @@ -173,7 +181,8 @@ void do_tests( void ) { dst[0] = 0xFFFFFFFFFFFFFFFF; dst[1] = 0xFFFFFFFFFFFFFFFF; - printf ("srcB = 0x%016lx 0x%016lx\n\n", srcB[1], srcB[0]); + printf ("srcB = 0x%016lx 0x%016lx\n\n", (unsigned long) srcB[1], + (unsigned long) srcB[0]); __asm__ __volatile__ ("vaddfp %0,%1,%2" : "=v" (dst): "v" (srcA), "v" (srcB)); printf (" vaddfp(srcA,srcB) result = "); print_vector_elements(dst); @@ -214,7 +223,8 @@ void do_tests( void ) { dst[0] = 0xFFFFFFFFFFFFFFFF; dst[1] = 0xFFFFFFFFFFFFFFFF; - printf ("srcC = 0x%016lx 0x%016lx\n\n", srcC[1], srcC[0]); + printf ("srcC = 0x%016lx 0x%016lx\n\n", (unsigned long) srcC[1], + (unsigned long) srcC[0]); __asm__ __volatile__ ("vmaddfp %0,%1,%2,%3" : "=v" (dst): "v" (srcA), "v" (srcC), "v" (srcB)); printf("i=%d, j=%d, k=%d ", i, j, k); @@ -263,9 +273,9 @@ int main() __asm__ __volatile__ ("mfvscr %0" : "=v"(vreg)); #ifdef VGP_ppc64le_linux - printf("vscr set to 0x%lx\n", vreg[0]); + printf("vscr set to 0x%lx\n", (unsigned long) vreg[0]); #else - printf("vscr set to 0x%lx\n", vreg[1]); + printf("vscr set to 0x%lx\n", (unsigned long) vreg[1]); #endif do_tests(); @@ -289,9 +299,9 @@ int main() __asm__ __volatile__ ("mfvscr %0" : "=v"(vreg)); #ifdef VGP_ppc64le_linux - printf("vscr set to 0x%lx\n", vreg[0]); + printf("vscr set to 0x%lx\n", (unsigned long) vreg[0]); #else - printf("vscr set to 0x%lx\n", vreg[1]); + printf("vscr set to 0x%lx\n", (unsigned long) vreg[1]); #endif do_tests(); |
|
From: Carl L. <ca...@so...> - 2021-09-30 23:13:47
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=9c22ad00249c1a6739afb2eed1db0a6fb846978c commit 9c22ad00249c1a6739afb2eed1db0a6fb846978c Author: Carl Love <ce...@us...> Date: Tue Sep 28 18:00:35 2021 +0000 Fixes for the lxvx and stxvx instructions The lxvx and stxvx tests are moved into their own separate tests. Add the expec files for the new test. Update the expected results for the altivec test. Diff: --- NEWS | 2 + none/tests/ppc64/Makefile.am | 18 +- .../tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE | 328 +++++++++---------- none/tests/ppc64/test_lxvx_stxvx.c | 355 +++++++++++++++++++++ none/tests/ppc64/test_lxvx_stxvx.stderr.exp | 2 + none/tests/ppc64/test_lxvx_stxvx.stdout.exp-p8 | 245 ++++++++++++++ none/tests/ppc64/test_lxvx_stxvx.stdout.exp-p9 | 245 ++++++++++++++ none/tests/ppc64/test_lxvx_stxvx.vgtest | 2 + 8 files changed, 1031 insertions(+), 166 deletions(-) diff --git a/NEWS b/NEWS index d4601281ee..ef36395dea 100644 --- a/NEWS +++ b/NEWS @@ -61,6 +61,8 @@ are not entered into bugzilla tend to get forgotten about or ignored. 443033 Add support for the ISA 3.0 mcrxrx instruction 443034 Sraw, srawi, srad, sradi, mfs 443178 Powerpc, test jm-mfspr expected output needs to be updated. +443179 Need new test for the lxvx and stxvx instructions on ISA 2.07 and + ISA 3.0 systems. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 4fae9f7dd4..b709f3ef49 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -67,7 +67,8 @@ EXTRA_DIST = \ scv_test.stderr.exp scv_test.stdout.exp scv_test.vgtest \ test_copy_paste.stderr.exp test_copy_paste.stdout.exp \ test_copy_paste.vgtest \ - test_mcrxrx.vgtest test_mcrxrx.stderr.exp test_mcrxrx.stdout.exp + test_mcrxrx.vgtest test_mcrxrx.stderr.exp test_mcrxrx.stdout.exp \ + test_lxvx_stxvx.vgtest test_lxvx_stxvx.stderr.exp test_lxvx_stxvx.stdout.exp-p8 test_lxvx_stxvx.stdout.exp-p9 check_PROGRAMS = \ @@ -83,7 +84,7 @@ check_PROGRAMS = \ test_tm test_touch_tm data-cache-instructions \ std_reg_imm \ twi_tdi tw_td power6_bcmp scv_test \ - test_mcrxrx + test_mcrxrx test_lxvx_stxvx # lmw, stmw, lswi, lswx, stswi, stswx compile (and run) only on big endian. if VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX @@ -231,6 +232,18 @@ test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG test_mcrxrx_CFLAGS = $(AM_FLAGS) -Winline -Wall -O -g -mregnames @FLAG_M64@ $(ISA_3_00_FLAG) +# ISA 2.06 and 2.07 the lxvx, stxvx instructions are nmemonics for the BE +# instructions lxvd2x and stxvd2x +# They are real endian aware instruction in ISA 3.0. + +if HAS_ISA_3_00 +test_lxvx_stxvx_CFLAGS = $(AM_FLAGS) -Winline -Wall -O -g -mregnames \ + @FLAG_M64@ $(ISA_2_07_FLAG) $(BUILD_FLAGS_ISA_3_00) +else + test_lxvx_stxvx_CFLAGS = $(AM_FLAGS) -Winline -Wall -O -g -mregnames \ + @FLAG_M64@ $(ISA_2_07_FLAG) $(BUILD_FLAGS_ISA_2_07) +endif + test_isa_2_06_part3_LDADD = -lm test_dfp1_LDADD = -lm test_dfp2_LDADD = -lm @@ -243,4 +256,5 @@ test_tm_LDADD = -lm test_touch_tm_LDADD = -lm test_isa_3_0_LDADD = -lm test_mcrxrx_LDADD = -lm +test_lxvx_stxvx_LDADD = -lm diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE index e5d53aa4bf..e91c033853 100644 --- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE +++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE @@ -52498,125 +52498,125 @@ All done. Tested 129 different instructions ppc vector load/store: Test instruction group [ppc vector load/store] lxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] -lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] -lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] -lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] -lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] +lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => + 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] +lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => + ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] +lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => + 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] @@ -52994,113 +52994,113 @@ stxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555 stxvx 0000000000000000 0000000000000000 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => 0000000000000000 0000000000000000 [ 0000000000000000 0000000000000000 0000000000000000 ffffffffffffffff ] stxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 5555555555555555 0000000000000000 ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 5555555555555555 0000000000000000 ] stxvx 0102010201020102 0102030405060708 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0000000000000000 ffffffffffffffff ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0000000000000000 ffffffffffffffff ] stxvx 0102010201020102 0102030405060708 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 ffffffffffffffff 0001020304050607 ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 ffffffffffffffff 0001020304050607 ] stxvx 0102010201020102 0102030405060708 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0001020304050607 5555555555555555 ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0001020304050607 5555555555555555 ] stxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 5555555555555555 0000000000000000 ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 5555555555555555 0000000000000000 ] stxvx 0102010201020102 0102030405060708 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0000000000000000 ffffffffffffffff ] + 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0000000000000000 ffffffffffffffff ] stxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 5555555555555555 0000000000000000 ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 5555555555555555 0000000000000000 ] stxvx 8899aabbccddeeff 0011223344556677 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0000000000000000 ffffffffffffffff ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0000000000000000 ffffffffffffffff ] stxvx 8899aabbccddeeff 0011223344556677 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 ffffffffffffffff 0001020304050607 ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff ffffffffffffffff 0001020304050607 ] stxvx 8899aabbccddeeff 0011223344556677 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0001020304050607 5555555555555555 ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0001020304050607 5555555555555555 ] stxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 5555555555555555 0000000000000000 ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 5555555555555555 0000000000000000 ] stxvx 8899aabbccddeeff 0011223344556677 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0000000000000000 ffffffffffffffff ] + 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0000000000000000 ffffffffffffffff ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 5555555555555555 0000000000000000 ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 5555555555555555 0000000000000000 ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0000000000000000 ffffffffffffffff ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0000000000000000 ffffffffffffffff ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 ffffffffffffffff 0001020304050607 ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 ffffffffffffffff 0001020304050607 ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0001020304050607 5555555555555555 ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0001020304050607 5555555555555555 ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 5555555555555555 0000000000000000 ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 5555555555555555 0000000000000000 ] stxvx 7060504030201000 f0e0d0c0b0a09080 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0000000000000000 ffffffffffffffff ] + 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0000000000000000 ffffffffffffffff ] stxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 5555555555555555 0000000000000000 ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 5555555555555555 0000000000000000 ] stxvx 0000100800001010 0000100000001002 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0000000000000000 ffffffffffffffff ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0000000000000000 ffffffffffffffff ] stxvx 0000100800001010 0000100000001002 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 ffffffffffffffff 0001020304050607 ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 ffffffffffffffff 0001020304050607 ] stxvx 0000100800001010 0000100000001002 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0001020304050607 5555555555555555 ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0001020304050607 5555555555555555 ] stxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 5555555555555555 0000000000000000 ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 5555555555555555 0000000000000000 ] stxvx 0000100800001010 0000100000001002 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0000000000000000 ffffffffffffffff ] + 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0000000000000000 ffffffffffffffff ] stxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 5555555555555555 0000000000000000 ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 5555555555555555 0000000000000000 ] stxvx 0010100800101010 0010100000101002 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0000000000000000 ffffffffffffffff ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0000000000000000 ffffffffffffffff ] stxvx 0010100800101010 0010100000101002 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 ffffffffffffffff 0001020304050607 ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 ffffffffffffffff 0001020304050607 ] stxvx 0010100800101010 0010100000101002 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0001020304050607 5555555555555555 ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0001020304050607 5555555555555555 ] stxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 5555555555555555 0000000000000000 ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 5555555555555555 0000000000000000 ] stxvx 0010100800101010 0010100000101002 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0000000000000000 ffffffffffffffff ] + 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0000000000000000 ffffffffffffffff ] stxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 5555555555555555 0000000000000000 ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 5555555555555555 0000000000000000 ] stxvx 00001c0800001c10 00001c0000001c02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0000000000000000 ffffffffffffffff ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0000000000000000 ffffffffffffffff ] stxvx 00001c0800001c10 00001c0000001c02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 ffffffffffffffff 0001020304050607 ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 ffffffffffffffff 0001020304050607 ] stxvx 00001c0800001c10 00001c0000001c02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0001020304050607 5555555555555555 ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0001020304050607 5555555555555555 ] stxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 5555555555555555 0000000000000000 ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 5555555555555555 0000000000000000 ] stxvx 00001c0800001c10 00001c0000001c02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0000000000000000 ffffffffffffffff ] + 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0000000000000000 ffffffffffffffff ] stxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 5555555555555555 0000000000000000 ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 5555555555555555 0000000000000000 ] stxvx 00101c0800101c10 00101c0000101c02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0000000000000000 ffffffffffffffff ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0000000000000000 ffffffffffffffff ] stxvx 00101c0800101c10 00101c0000101c02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 ffffffffffffffff 0001020304050607 ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 ffffffffffffffff 0001020304050607 ] stxvx 00101c0800101c10 00101c0000101c02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0001020304050607 5555555555555555 ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0001020304050607 5555555555555555 ] stxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 5555555555555555 0000000000000000 ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 5555555555555555 0000000000000000 ] stxvx 00101c0800101c10 00101c0000101c02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0000000000000000 ffffffffffffffff ] + 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0000000000000000 ffffffffffffffff ] stxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 5555555555555555 0000000000000000 ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 5555555555555555 0000000000000000 ] stxvx 00001f0800001f10 00001f0000001f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0000000000000000 ffffffffffffffff ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ] stxvx 00001f0800001f10 00001f0000001f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 ffffffffffffffff 0001020304050607 ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 ffffffffffffffff 0001020304050607 ] stxvx 00001f0800001f10 00001f0000001f02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0001020304050607 5555555555555555 ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0001020304050607 5555555555555555 ] stxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 5555555555555555 0000000000000000 ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 5555555555555555 0000000000000000 ] stxvx 00001f0800001f10 00001f0000001f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0000000000000000 ffffffffffffffff ] + 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ] stxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 5555555555555555 0000000000000000 ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ] stxvx 00101f0800101f10 00101f0000101f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0000000000000000 ffffffffffffffff ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ] stxvx 00101f0800101f10 00101f0000101f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 ffffffffffffffff 0001020304050607 ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 ffffffffffffffff 0001020304050607 ] stxvx 00101f0800101f10 00101f0000101f02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0001020304050607 5555555555555555 ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0001020304050607 5555555555555555 ] stxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 5555555555555555 0000000000000000 ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ] stxvx 00101f0800101f10 00101f0000101f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] => - 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0000000000000000 ffffffffffffffff ] + 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ] stxvh8x 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => 0000000000000000 0000000000000000 [ 0000000000000000 0000000000000000 5555555555555555 0000000000000000 ] diff --git a/none/tests/ppc64/test_lxvx_stxvx.c b/none/tests/ppc64/test_lxvx_stxvx.c new file mode 100644 index 0000000000..e4525d46e1 --- /dev/null +++ b/none/tests/ppc64/test_lxvx_stxvx.c @@ -0,0 +1,355 @@ +/* + * test_lxvx_stxvx.c: + * + * The lxvx and stxvx instructions were extended mnemonics + * of the lxvd2x and stxvd2x instructions, which are Big-Endian + * by design in ISA 2.07 and earlier. + * Beginning with ISA 3.0 these are unique instructions and + * are endian aware. + * Tests of those instructions must be aware of which + * ISA level the code is being compiled to. + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License V2 + * as published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdio.h> +#include <stdint.h> + +#ifdef HAS_ISA_2_07 +#include <assert.h> +#include <ctype.h> // isspace +#include <stdlib.h> +#include <string.h> +#include <unistd.h> // getopt +#include <altivec.h> // vector +#include <malloc.h> // memalign + +#undef DEBUG_VECTOR_PERMUTE +static int verbose = 0; + +typedef uint64_t HWord_t; + +/* Define a small memory range used to test load-from and store-to vsx */ +#define BUFFER_SIZE 4 +#define MAX_BUFFER_PATTERNS 6 +unsigned long buffer[BUFFER_SIZE]; + +static void dump_small_buffer(void) { + int x; + + printf("[ "); + + for (x = 0; x < BUFFER_SIZE; x++) + printf("%016lx ", buffer[x] ); + + printf("]"); +} + +static void initialize_buffer(int t) +{ + int x; + + for (x = 0; x < BUFFER_SIZE; x++) + /* Don't want each of the 32-bit chunks to be identical. Loads of a + * byte from the wrong 32-bit chuck are not detectable if the chunks + * are identical. + */ + switch((t+x)%BUFFER_SIZE) { + case 0: + buffer[x] = 0xffffffffffffffff; + break; + case 1: + buffer[x] = 0x0001020304050607; + break; + case 2: + buffer[x] = 0x5555555555555555; + break; + case 3: + buffer[x] = 0x0000000000000000; + break; + case 4: + buffer[x] = 0x5a05a05a05a05a05; + break; + case 5: + buffer[x] = 0x0102030405060708; + break; + default: + buffer[x] = 0x1010101010101010; + break; + } +} + +#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7" + +#define SET_CR(_arg) \ + __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR ); + +#define SET_CR_ZERO \ + SET_CR(0) + +#define GET_CR(_lval) \ + __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) ) + +#define GET_XER(_lval) \ + __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) ) + +#define SET_CR_ZERO \ + SET_CR(0) + +/* a table of exponent values for use in the float precision tests. */ +unsigned long exponent_table[] = { +#ifdef EXHAUSTIVE_TESTS + 0x0000, /* +/-0 or +/-DENormalized, depending on associated mantissa. */ + 0x1a, /* within NORmalized for 16,32,64,128-bit. */ + 0x1f, /* +/-INF or +/-NaN for 16bit, NORmalized for 32,64,128 */ + 0xff, /* +/-INF or +/-NaN for 32bit, NORmalized for 64,128 */ + 0x7ff, /* +/-INF or +/-NaN for 32 and 64bit, NORmalized for 128 */ + 0x7fff, /* +/-INF or +/-NaN for 128bit. */ +#else + 0x0000, /* +/-0 or +/-DENormalized, depending on associated mantissa. */ + 0xff, /* +/-INF or +/-NaN for 32bit, NORmalized for 64,128 */ + 0x7ff, /* +/-INF or +/-NaN for 32 and 64bit, NORmalized for 128 */ + 0x7fff, /* +/-INF or +/-NaN for 128bit. */ +#endif +}; +#define MAX_EXPONENTS (sizeof(exponent_table) / sizeof(unsigned long)) + +unsigned long nb_float_vsxargs; + +#define MAX_FLOAT_VSX_ARRAY_SIZE (((MAX_EXPONENTS * MAX_MANTISSAS) * 2 + 1) * 2) + +static unsigned long * vsxargs = NULL; +unsigned long nb_vargs; + +#define MAX_VSX_ARRAY_SIZE 42 + +static void build_vsx_table (void) +{ + long i = 0; + // A VSX register is 128-bits wide. + // We build contents here using pairs of 64-bit longs. + // Permutes work against two (non-paired) VSX regs, so these are + // also grouped by twos. + vsxargs = memalign(16, MAX_VSX_ARRAY_SIZE * sizeof(unsigned long)); +#ifdef EXHAUSTIVE_TESTS + vsxargs[i++] = 0x0000000000000000UL; vsxargs[i++] = 0x0000000000000000UL; + vsxargs[i++] = 0x0102030405060708UL; vsxargs[i++] = 0x0102010201020102UL; + + vsxargs[i++] = 0xaaaaaaaaaaaaaaaaUL; vsxargs[i++] = 0xaaaaaaaaaaaaaaaaUL; + vsxargs[i++] = 0x5555555555555555UL; vsxargs[i++] = 0x5555555555555555UL; + + vsxargs[i++] = 0x08090a0b0c0d0e0fUL; vsxargs[i++] = 0x0102010201020102UL; + vsxargs[i++] = 0xf0f1f2f3f4f5f6f7UL; vsxargs[i++] = 0xf8f9fafbfcfdfeffUL; + + vsxargs[i++] = 0x7ea1a5a7abadb0baUL; vsxargs[i++] = 0x070d111d1e555e70UL; + vsxargs[i++] = 0xe5e7ecedeff0f1faUL; vsxargs[i++] = 0xbeb1c0caced0dbdeUL; + + vsxargs[i++] = 0x00115e7eadbabec0UL; vsxargs[i++] = 0xced0deede5ecef00UL; + vsxargs[i++] = 0x00111e7ea5abadb1UL; vsxargs[i++] = 0xbecad0deedeffe00UL; + + vsxargs[i++] = 0x0011223344556677UL; vsxargs[i++] = 0x8899aabbccddeeffUL; + vsxargs[i++] = 0xf0e0d0c0b0a09080UL; vsxargs[i++] = 0x7060504030201000UL; +#else + vsxargs[i++] = 0x0000000000000000UL; vsxargs[i++] = 0x0000000000000000UL; + vsxargs[i++] = 0x0102030405060708UL; vsxargs[i++] = 0x0102010201020102UL; + + vsxargs[i++] = 0x0011223344556677UL; vsxargs[i++] = 0x8899aabbccddeeffUL; + vsxargs[i++] = 0xf0e0d0c0b0a09080UL; vsxargs[i++] = 0x7060504030201000UL; +#endif + + // these next three groups are specific for vector rotate tests. + // bits 11:15,19:23,27:31 of each 32-bit word contain mb,me,sh values. + vsxargs[i++] = 0x0000100000001002ULL; vsxargs[i++] = 0x0000100800001010ULL; + vsxargs[i++] = 0x0010100000101002ULL; vsxargs[i++] = 0x0010100800101010ULL; + + // vector rotate special... + vsxargs[i++] = 0x00001c0000001c02ULL; vsxargs[i++] = 0x00001c0800001c10ULL; + vsxargs[i++] = 0x00101c0000101c02ULL; vsxargs[i++] = 0x00101c0800101c10ULL; + + // vector rotate special... + vsxargs[i++] = 0x00001f0000001f02ULL; vsxargs[i++] = 0x00001f0800001f10ULL; + vsxargs[i++] = 0x00101f0000101f02ULL; vsxargs[i++] = 0x00101f0800101f10ULL; + + nb_vargs = i; +} + +#define VERBOSE_FUNCTION_CALLOUT \ + if (verbose) \ + printf("Test Harness Function: %s\n", __FUNCTION__); + +/* XXXX these must all be callee-save regs! */ +register HWord_t r14 __asm__ ("r14"); +register HWord_t r15 __asm__ ("r15"); +register HWord_t r16 __asm__ ("r16"); +register HWord_t r17 __asm__ ("r17"); +register double f14 __asm__ ("fr14"); +register double f15 __asm__ ("fr15"); + +/* globals used for vector tests */ +static vector unsigned long vec_xt; + +/* globals for the condition register fields. These are used to + * capture the condition register values immediately after the + * instruction under test is tested. + * This is to help prevent other test overhead, switch statements, + * compares, what-not from interfering. + */ +unsigned long local_cr; +unsigned long local_fpscr; +unsigned long local_xer; +volatile unsigned int cr_value; + +/* global for holding the DFP values */ +//dfp_val_t dfp_value; + +/* individual instruction tests */ +typedef void (*test_func_t) (void); +struct test_list_t { + test_func_t func; + const char *name; +}; +typedef struct test_list_t test_list_t; + +/* vector splat value */ +volatile int x_splat; +//volatile int dfp_significance; + +/* groups of instruction tests, calling individual tests */ +typedef void (*test_group_t) (const char *name, test_func_t func, + unsigned int test_flags); + +enum test_flags { + unused = 0, + /* Nb arguments */ +}; + +static void test_lxvx(void) { + __asm__ __volatile__ ("lxvx %x0, 14, 15" : "=wa" (vec_xt)); +} + + +static void test_stxvx(void) { + __asm__ __volatile__ ("stxvx %x0, 14, 15" :: "wa" (vec_xt)); +} + +static test_list_t testgroup_vector_loadstore[] = { + { &test_lxvx , "lxvx" }, + { &test_stxvx , "stxvx" }, + { NULL , NULL }, +}; + +/* table containing all of the instruction groups */ +struct test_group_table_t { + test_list_t *tests; + const char *name; + unsigned int flags; +}; + +typedef struct test_group_table_t test_group_table_t; + +static test_group_table_t all_tests[] = { + { + testgroup_vector_loadstore, + "ppc vector load/store", + 0, + }, + { NULL, NULL, 0x00000000, }, +}; + +static void testfunction_vector_loadstore (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags) { + /* exercises vector loads from memory, and vector stores from memory. + * <load or store instruction> XS, RA, RB + * For these tests, RA will be zero. + * EA is then, simply, RB. */ + int i; + int buffer_pattern; + + VERBOSE_FUNCTION_CALLOUT + + for (i = 0; i < nb_vargs; i += 2) { + + vec_xt = (vector unsigned long){vsxargs[i], vsxargs[i+1]}; + r14 = 0; + r15 = (unsigned long) & buffer; + + for (buffer_pattern = 0; buffer_pattern < MAX_BUFFER_PATTERNS; + buffer_pattern++) { + + /* set patterns on both ends */ + initialize_buffer(buffer_pattern); + + printf("%s ", instruction_name); + printf("%016lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); + dump_small_buffer(); + printf(" =>\n"); + + (*test_function)(); + + printf("\t\t\t\t%016lx %016lx ", (unsigned long)vec_xt[1], + (unsigned long)vec_xt[0]); + dump_small_buffer(); + printf("\n"); + } + } +} + +typedef struct insn_sel_flags_t_struct { + unsigned int cr; +} insn_sel_flags_t; + +static void do_tests ( insn_sel_flags_t seln_flags) +{ + test_group_t group_function; + int n = 0; + int j = 0; + int i = 0; + + test_list_t *tests; + + printf("%s:\n", all_tests[i].name); + group_function = &testfunction_vector_loadstore; + tests = all_tests[i].tests; + + for (j = 0; tests[j].name != NULL; j++) { + (*group_function)(tests[j].name, tests[j].func, 0); + printf("\n"); + n++; + } + printf("\n"); + n++; + + if (verbose) printf("\n"); + + printf("All done. Tested %d different instructions\n", n); +} +#endif + +int main (int argc, char **argv) +{ +#ifdef HAS_ISA_2_07 + insn_sel_flags_t flags; + + build_vsx_table(); + + do_tests( flags ); +#else + printf("HAS_ISA_2_07 not detected.\n"); +#endif + return 0; +} + diff --git a/none/tests/ppc64/test_lxvx_stxvx.stderr.exp b/none/tests/ppc64/test_lxvx_stxvx.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_lxvx_stxvx.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_lxvx_stxvx.stdout.exp-p8 b/none/tests/ppc64/test_lxvx_stxvx.stdout.exp-p8 new file mode 100644 index 0000000000..f7b9225dc0 --- /dev/null +++ b/none/tests/ppc64/test_lxvx_stxvx.stdout.exp-p8 @@ -0,0 +1,245 @@ +ppc vector load/store: +lxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] => + ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] +lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555... [truncated message content] |
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From: Carl L. <ca...@so...> - 2021-09-30 23:09:11
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f1d6dec60148d1ca7dc660f98e39ff31a9bfb5a0 commit f1d6dec60148d1ca7dc660f98e39ff31a9bfb5a0 Author: Carl Love <ce...@us...> Date: Tue Sep 28 15:49:10 2021 +0000 Fix tests for mfspr Split out the mfspr tests into a separate test using command line option "-M". The value in the LR and CTR registers changed. It appears the changes are due to changes in the test program jm-insns.c. Splinting these instructions out will help to minimize the size of future updates when the test program changes. Diff: --- NEWS | 1 + none/tests/ppc32/Makefile.am | 1 + none/tests/ppc32/jm-insns.c | 37 +++++++++++++++++++++++++---- none/tests/ppc32/jm-mfspr.stderr.exp | 2 ++ none/tests/ppc32/jm-mfspr.stdout.exp | 13 ++++++++++ none/tests/ppc32/jm-mfspr.vgtest | 1 + none/tests/ppc64/Makefile.am | 2 ++ none/tests/ppc64/jm-int_other.stdout.exp-LE | 13 +--------- none/tests/ppc64/jm-mfspr.stderr.exp | 2 ++ none/tests/ppc64/jm-mfspr.stdout.exp | 13 ++++++++++ none/tests/ppc64/jm-mfspr.stdout.exp-ALT | 13 ++++++++++ none/tests/ppc64/jm-mfspr.vgtest | 1 + 12 files changed, 82 insertions(+), 17 deletions(-) diff --git a/NEWS b/NEWS index 73edd71920..d4601281ee 100644 --- a/NEWS +++ b/NEWS @@ -60,6 +60,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 443031 Gcc -many change requires explicit .machine directives 443033 Add support for the ISA 3.0 mcrxrx instruction 443034 Sraw, srawi, srad, sradi, mfs +443178 Powerpc, test jm-mfspr expected output needs to be updated. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am index 2ca067d486..187cab74f7 100644 --- a/none/tests/ppc32/Makefile.am +++ b/none/tests/ppc32/Makefile.am @@ -16,6 +16,7 @@ EXTRA_DIST = \ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \ jm-vmx.vgtest \ + jm-mfspr.stderr.exp jm-mfspr.stdout.exp jm-mfspr.vgtest \ jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \ mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \ diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index e452fe0f31..7c35823c69 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -382,6 +382,7 @@ enum test_flags { PPC_FALTIVEC = 0x00050000, PPC_MISC = 0x00060000, PPC_SH_ALGEBRAIC = 0x00070000, + PPC_MFSPR = 0x00080000, PPC_FAMILY = 0x000F0000, /* Flags: these may be combined, so use separate bitfields. */ PPC_CR = 0x01000000, @@ -1444,13 +1445,17 @@ static test_t tests_il_ops_spe_sh[] = { #endif // #ifdef __powerpc64__ { NULL, NULL, }, }; +static test_t tests_il_ops_mfspr[] = { + { &test_mfspr , " mfspr", }, + { &test_mtspr , " mtspr", }, + { NULL, NULL, }, +}; + static test_t tests_il_ops_spe[] = { { &test_rlwimi , " rlwimi", }, { &test_rlwinm , " rlwinm", }, { &test_rlwnm , " rlwnm", }, { &test_mfcr , " mfcr", }, - { &test_mfspr , " mfspr", }, - { &test_mtspr , " mtspr", }, #ifdef __powerpc64__ { &test_rldcl , " rldcl", }, { &test_rldcr , " rldcr", }, @@ -4037,6 +4042,11 @@ static test_table_t all_tests[] = { "PPC integer logical insns with one arg with flags update", 0x01010201, }, + { + tests_il_ops_mfspr , + "PPC mfspr instructions", + 0x00080207, + }, { tests_il_ops_spe , "PPC logical insns with special forms", @@ -5776,7 +5786,11 @@ static test_loop_t int_sh_algebraic[] = { &test_int_special, }; -static test_loop_t int_loops[] = { +static test_loop_t int_mfspr[] = { + &test_int_special, +}; + + static test_loop_t int_loops[] = { &test_int_one_arg, &test_int_two_args, &test_int_three_args, @@ -7513,7 +7527,7 @@ static int check_name (const char* name, const char *filter, typedef struct insn_sel_flags_t_struct { int one_arg, two_args, three_args; int arith, logical, compare, ldst; - int integer, floats, p405, altivec, faltivec, misc, sh_algebraic; + int integer, floats, p405, altivec, faltivec, misc, sh_algebraic, mfspr; int cr; } insn_sel_flags_t; @@ -7554,6 +7568,7 @@ static void do_tests ( insn_sel_flags_t seln_flags, (family == PPC_ALTIVEC && !seln_flags.altivec) || (family == PPC_MISC && !seln_flags.misc) || (family == PPC_SH_ALGEBRAIC && !seln_flags.sh_algebraic) || + (family == PPC_MFSPR && !seln_flags.mfspr) || (family == PPC_FALTIVEC && !seln_flags.faltivec)) continue; /* Check flags update */ @@ -7570,6 +7585,9 @@ static void do_tests ( insn_sel_flags_t seln_flags, case PPC_SH_ALGEBRAIC: loop = &int_sh_algebraic[0]; break; + case PPC_MFSPR: + loop = &int_mfspr[0]; + break; case PPC_MISC: loop = &misc_loops[0]; break; @@ -7678,6 +7696,7 @@ static void usage (void) "\t-a: test altivec instructions\n" "\t-m: test miscellaneous instructions\n" "\t-s: test shift algebraic (sraw, srawi, srad, sradi) instructions\n" + "\t-M: test mfspr instructions\n" "\t-A: test all (int, fp, altivec) instructions\n" "\t-v: be verbose\n" "\t-h: display this help and exit\n" @@ -7712,6 +7731,7 @@ int main (int argc, char **argv) flags.faltivec = 0; flags.cr = -1; flags.sh_algebraic = 0; + flags.mfspr = 0; while ((c = getopt(argc, argv, "123t:f:n:r:uvh")) != -1) { switch (c) { @@ -7815,6 +7835,7 @@ int main (int argc, char **argv) flags.altivec = 1; flags.faltivec = 1; flags.algebraic = 1; + flags.mfspr = 1; } // Default cr update if (flags.cr == -1) @@ -7851,10 +7872,11 @@ int main (int argc, char **argv) flags.altivec = 0; flags.faltivec = 0; flags.sh_algebraic = 0; + flags.mfspr = 0; // Flags flags.cr = 2; - while ((c = getopt(argc, argv, "ilcLfmsahvA")) != -1) { + while ((c = getopt(argc, argv, "ilcLfmMsahvA")) != -1) { switch (c) { case 'i': flags.arith = 1; @@ -7864,6 +7886,10 @@ int main (int argc, char **argv) flags.logical = 1; flags.sh_algebraic = 1; break; + case 'M': + flags.logical = 1; + flags.mfspr = 1; + break; case 'l': flags.logical = 1; flags.integer = 1; @@ -7956,6 +7982,7 @@ int main (int argc, char **argv) printf(" altivec = %d\n", flags.altivec); printf(" faltivec = %d\n", flags.faltivec); printf(" sh_algebraic = %d\n", flags.sh_algebraic); + printf(" mfspr = %d\n", flags.mfspr); printf(" cr update: \n"); printf(" cr = %d\n", flags.cr); printf("\n"); diff --git a/none/tests/ppc32/jm-mfspr.stderr.exp b/none/tests/ppc32/jm-mfspr.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc32/jm-mfspr.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/jm-mfspr.stdout.exp b/none/tests/ppc32/jm-mfspr.stdout.exp new file mode 100644 index 0000000000..bfab0acbbf --- /dev/null +++ b/none/tests/ppc32/jm-mfspr.stdout.exp @@ -0,0 +1,13 @@ +PPC mfspr instructions: + mfspr 1 (00000000) -> mtxer -> mfxer => 00000000 + mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f + mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f + mfspr 8 (00000000) -> mtlr -> mflr => 00000000 + mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f + mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff + mfspr 9 (00000000) -> mtctr -> mfctr => 00000000 + mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f + mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff + + +All done. Tested 2 different instructions diff --git a/none/tests/ppc32/jm-mfspr.vgtest b/none/tests/ppc32/jm-mfspr.vgtest new file mode 100644 index 0000000000..07ea056e41 --- /dev/null +++ b/none/tests/ppc32/jm-mfspr.vgtest @@ -0,0 +1 @@ +prog: jm-insns -M diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 1f40d94ca3..4fae9f7dd4 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -12,6 +12,8 @@ EXTRA_DIST = \ jm-int-sh_algebraic.stdout.exp-LE \ jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 \ jm-int-sh_algebraic.vgtest \ + jm-mfspr.stderr.exp jm-mfspr.stdout.exp jm-mfspr.stdout.exp-ALT \ + jm-mfspr.vgtest \ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \ jm-int_other.stdout.exp-LE \ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \ diff --git a/none/tests/ppc64/jm-int_other.stdout.exp-LE b/none/tests/ppc64/jm-int_other.stdout.exp-LE index 08fac66165..f7dc3675b3 100644 --- a/none/tests/ppc64/jm-int_other.stdout.exp-LE +++ b/none/tests/ppc64/jm-int_other.stdout.exp-LE @@ -617,17 +617,6 @@ PPC logical insns with special forms: mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000) mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000) - mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000 - mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f - mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f - mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000 - mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def - mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff - mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000 - mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def - mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff - - rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000) rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000) rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000) @@ -3859,4 +3848,4 @@ PPC integer store insns with three register args: stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000) stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000) -All done. Tested 123 different instructions +All done. Tested 121 different instructions diff --git a/none/tests/ppc64/jm-mfspr.stderr.exp b/none/tests/ppc64/jm-mfspr.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/jm-mfspr.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/jm-mfspr.stdout.exp b/none/tests/ppc64/jm-mfspr.stdout.exp new file mode 100644 index 0000000000..f9cc36fd33 --- /dev/null +++ b/none/tests/ppc64/jm-mfspr.stdout.exp @@ -0,0 +1,13 @@ +PPC mfspr instructions: + mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000 + mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f + mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f + mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000 + mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def + mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff + mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000 + mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def + mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff + + +All done. Tested 2 different instructions diff --git a/none/tests/ppc64/jm-mfspr.stdout.exp-ALT b/none/tests/ppc64/jm-mfspr.stdout.exp-ALT new file mode 100644 index 0000000000..7801fac6c4 --- /dev/null +++ b/none/tests/ppc64/jm-mfspr.stdout.exp-ALT @@ -0,0 +1,13 @@ +PPC mfspr instructions: + mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000 + mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f + mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f + mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000 + mfspr 8 (be991def) -> mtlr -> mflr => 0000001cbe991def + mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff + mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000 + mfspr 9 (be991def) -> mtctr -> mfctr => 0000001cbe991def + mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff + + +All done. Tested 2 different instructions diff --git a/none/tests/ppc64/jm-mfspr.vgtest b/none/tests/ppc64/jm-mfspr.vgtest new file mode 100644 index 0000000000..07ea056e41 --- /dev/null +++ b/none/tests/ppc64/jm-mfspr.vgtest @@ -0,0 +1 @@ +prog: jm-insns -M |
|
From: Carl L. <ca...@so...> - 2021-09-30 22:53:55
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a9f41e0c0b18763a18a1a2abad7981bbd299b235 commit a9f41e0c0b18763a18a1a2abad7981bbd299b235 Author: Carl Love <ce...@us...> Date: Thu Sep 9 23:10:07 2021 +0000 fix sraw, srawi, srad, sradi instructions For ISA 3.0 and beyond, the instructions also write the XER register. Split the instructions out to a new command line option so we can create an ISA 2.07 expect file, ISA 3.0 LE and ISA 3.0 BE expect file. The new command line option is "-s" to just run just these four instructions. Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 28 ++++- none/tests/ppc32/Makefile.am | 2 + none/tests/ppc32/jm-insns.c | 81 +++++++++++-- none/tests/ppc32/jm-int-sh_algebraic.stderr.exp | 2 + none/tests/ppc32/jm-int-sh_algebraic.stdout.exp | 45 +++++++ none/tests/ppc32/jm-int-sh_algebraic.vgtest | 1 + none/tests/ppc32/jm-int_other.stdout.exp | 47 +------- none/tests/ppc64/Makefile.am | 4 + none/tests/ppc64/jm-int-sh_algebraic.stderr.exp | 2 + none/tests/ppc64/jm-int-sh_algebraic.stdout.exp | 85 ++++++++++++++ none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE | 85 ++++++++++++++ .../ppc64/jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 | 85 ++++++++++++++ none/tests/ppc64/jm-int-sh_algebraic.vgtest | 1 + none/tests/ppc64/jm-int_other.stdout.exp | 129 +-------------------- none/tests/ppc64/jm-int_other.stdout.exp-LE | 118 +------------------ 16 files changed, 412 insertions(+), 304 deletions(-) diff --git a/NEWS b/NEWS index ef1fce7baf..73edd71920 100644 --- a/NEWS +++ b/NEWS @@ -59,6 +59,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 442061 very slow execution under Fedora 34 (readdwarf3) 443031 Gcc -many change requires explicit .machine directives 443033 Add support for the ISA 3.0 mcrxrx instruction +443034 Sraw, srawi, srad, sradi, mfs To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 3dab201476..5d9f6b84a2 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -11499,7 +11499,7 @@ static Bool dis_memsync ( UInt prefix, UInt theInstr ) /* Integer Shift Instructions */ -static Bool dis_int_shift ( UInt prefix, UInt theInstr ) +static Bool dis_int_shift ( UInt prefix, UInt theInstr, UInt allow_isa_3_0 ) { /* X-Form, XS-Form */ UChar opc1 = ifieldOPC(theInstr); @@ -11575,11 +11575,16 @@ static Bool dis_int_shift ( UInt prefix, UInt theInstr ) mkexpr(sh_amt)) ) ); assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */True) ); + /* Set CA bit */ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAW, mkexpr(rA), mkWidenFrom32(ty, mkexpr(rS_lo32), True), mkWidenFrom32(ty, mkexpr(sh_amt), True ), mkWidenFrom32(ty, getXER_CA_32(), True) ); + + if (allow_isa_3_0) + /* copy CA to CA32 */ + putXER_CA32( unop(Iop_32to8, getXER_CA_32())); break; } @@ -11597,11 +11602,16 @@ static Bool dis_int_shift ( UInt prefix, UInt theInstr ) mkU8(sh_imm)) ); } + /* Set CA bit */ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAWI, mkexpr(rA), mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True), mkSzImm(ty, sh_imm), mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) ); + + if (allow_isa_3_0) + /* copy CA to CA32 */ + putXER_CA32( unop(Iop_32to8, getXER_CA_32())); break; case 0x218: // srw (Shift Right Word, PPC32 p508) @@ -11672,9 +11682,14 @@ static Bool dis_int_shift ( UInt prefix, UInt theInstr ) mkU64(63), mkexpr(sh_amt)) )) ); + /* Set CA bit */ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAD, mkexpr(rA), mkexpr(rS), mkexpr(sh_amt), mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) ); + + if (allow_isa_3_0) + /* copy CA to CA32 */ + putXER_CA32( unop(Iop_32to8, getXER_CA_32())); break; } @@ -11685,11 +11700,16 @@ static Bool dis_int_shift ( UInt prefix, UInt theInstr ) flag_rC ? ".":"", rA_addr, rS_addr, sh_imm); assign( rA, binop(Iop_Sar64, getIReg(rS_addr), mkU8(sh_imm)) ); + /* Set CA bit */ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRADI, mkexpr(rA), getIReg(rS_addr), mkU64(sh_imm), mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) ); + + if (allow_isa_3_0) + /* copy CA to CA32 */ + putXER_CA32( unop(Iop_32to8, getXER_CA_32())); break; case 0x21B: // srd (Shift Right DWord, PPC64 p574) @@ -37453,7 +37473,8 @@ DisResult disInstr_PPC_WRK ( /* Integer Shift Instructions */ case 0x018: case 0x318: case 0x338: // slw, sraw, srawi case 0x218: // srw - if (dis_int_shift( prefix, theInstr )) goto decode_success; + if (dis_int_shift( prefix, theInstr, allow_isa_3_0 )) + goto decode_success; goto decode_failure; /* 64bit Integer Shift Instructions */ @@ -37461,7 +37482,8 @@ DisResult disInstr_PPC_WRK ( case 0x33A: case 0x33B: // sradi case 0x21B: // srd if (!mode64) goto decode_failure; - if (dis_int_shift( prefix, theInstr )) goto decode_success; + if (dis_int_shift( prefix, theInstr, allow_isa_3_0 )) + goto decode_success; goto decode_failure; /* Integer Load Instructions */ diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am index 11697c99a4..2ca067d486 100644 --- a/none/tests/ppc32/Makefile.am +++ b/none/tests/ppc32/Makefile.am @@ -9,6 +9,8 @@ EXTRA_DIST = \ bug139050-ppc32.stdout.exp bug139050-ppc32.stderr.exp \ bug139050-ppc32.vgtest \ ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \ + jm-int-sh_algebraic.stderr.exp jm-int-sh_algebraic.stdout.exp \ + jm-int-sh_algebraic.vgtest \ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \ diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index 3a169933f8..e452fe0f31 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -381,6 +381,7 @@ enum test_flags { PPC_ALTIVEC = 0x00040000, PPC_FALTIVEC = 0x00050000, PPC_MISC = 0x00060000, + PPC_SH_ALGEBRAIC = 0x00070000, PPC_FAMILY = 0x000F0000, /* Flags: these may be combined, so use separate bitfields. */ PPC_CR = 0x01000000, @@ -886,6 +887,14 @@ static void test_srd (void) } #endif // #ifdef __powerpc64__ +static test_t tests_il_ops_two_sh[] = { + { &test_sraw , " sraw", }, +#ifdef __powerpc64__ + { &test_srad , " srad", }, +#endif // #ifdef __powerpc64__ + { NULL, NULL, }, +}; + static test_t tests_il_ops_two[] = { { &test_and , " and", }, { &test_andc , " andc", }, @@ -896,11 +905,9 @@ static test_t tests_il_ops_two[] = { { &test_orc , " orc", }, { &test_xor , " xor", }, { &test_slw , " slw", }, - { &test_sraw , " sraw", }, { &test_srw , " srw", }, #ifdef __powerpc64__ { &test_sld , " sld", }, - { &test_srad , " srad", }, { &test_srd , " srd", }, #endif // #ifdef __powerpc64__ { NULL, NULL, }, @@ -978,6 +985,14 @@ static void test_srd_ (void) } #endif // #ifdef __powerpc64__ +static test_t tests_ilr_ops_two_sh[] = { + { &test_sraw_ , " sraw.", }, +#ifdef __powerpc64__ + { &test_srad_ , " srad.", }, +#endif // #ifdef __powerpc64__ + { NULL, NULL, }, +}; + static test_t tests_ilr_ops_two[] = { { &test_and_ , " and.", }, { &test_andc_ , " andc.", }, @@ -988,11 +1003,9 @@ static test_t tests_ilr_ops_two[] = { { &test_orc_ , " orc.", }, { &test_xor_ , " xor.", }, { &test_slw_ , " slw.", }, - { &test_sraw_ , " sraw.", }, { &test_srw_ , " srw.", }, #ifdef __powerpc64__ { &test_sld_ , " sld.", }, - { &test_srad_ , " srad.", }, { &test_srd_ , " srd.", }, #endif // #ifdef __powerpc64__ { NULL, NULL, }, @@ -1424,11 +1437,17 @@ extern void test_sradi (void); ASSEMBLY_FUNC("test_sradi", "sradi 17, 14, 0"); #endif // #ifdef __powerpc64__ +static test_t tests_il_ops_spe_sh[] = { + { &test_srawi , " srawi", }, +#ifdef __powerpc64__ + { &test_sradi , " sradi", }, +#endif // #ifdef __powerpc64__ + { NULL, NULL, }, +}; static test_t tests_il_ops_spe[] = { { &test_rlwimi , " rlwimi", }, { &test_rlwinm , " rlwinm", }, { &test_rlwnm , " rlwnm", }, - { &test_srawi , " srawi", }, { &test_mfcr , " mfcr", }, { &test_mfspr , " mfspr", }, { &test_mtspr , " mtspr", }, @@ -1439,7 +1458,6 @@ static test_t tests_il_ops_spe[] = { { &test_rldicl , " rldicl", }, { &test_rldicr , " rldicr", }, { &test_rldimi , " rldimi", }, - { &test_sradi , " sradi", }, #endif // #ifdef __powerpc64__ { NULL, NULL, }, }; @@ -1489,11 +1507,17 @@ extern void test_sradi_ (void); ASSEMBLY_FUNC("test_sradi_", "sradi. 17, 14, 0"); #endif // #ifdef __powerpc64__ +static test_t tests_ilr_ops_spe_sh[] = { + { &test_srawi_ , " srawi.", }, +#ifdef __powerpc64__ + { &test_sradi_ , " sradi.", }, +#endif // #ifdef __powerpc64__ + { NULL, NULL, }, +}; static test_t tests_ilr_ops_spe[] = { { &test_rlwimi_ , " rlwimi.", }, { &test_rlwinm_ , " rlwinm.", }, { &test_rlwnm_ , " rlwnm.", }, - { &test_srawi_ , " srawi.", }, { &test_mcrf , " mcrf", }, { &test_mcrxr , " mcrxr", }, { &test_mtcrf , " mtcrf", }, @@ -1504,7 +1528,6 @@ static test_t tests_ilr_ops_spe[] = { { &test_rldicl_ , " rldicl.", }, { &test_rldicr_ , " rldicr.", }, { &test_rldimi_ , " rldimi.", }, - { &test_sradi_ , " sradi.", }, #endif // #ifdef __powerpc64__ { NULL, NULL, }, }; @@ -3944,11 +3967,21 @@ static test_table_t all_tests[] = { "PPC integer logical insns with two args", 0x00010202, }, + { + tests_il_ops_two_sh , + "PPC integer shift algebraic two args", + 0x00070202, + }, { tests_ilr_ops_two , "PPC integer logical insns with two args with flags update", 0x01010202, }, + { + tests_ilr_ops_two_sh , + "PPC integer shift algebraic two args with flags update", + 0x01070202, + }, { tests_icr_ops_two , "PPC integer compare insns (two args)", @@ -4009,11 +4042,21 @@ static test_table_t all_tests[] = { "PPC logical insns with special forms", 0x00010207, }, + { + tests_il_ops_spe_sh , + "PPC shift algebraic with special forms", + 0x00070207, + }, { tests_ilr_ops_spe , "PPC logical insns with special forms with flags update", 0x01010207, }, + { + tests_ilr_ops_spe_sh , + "PPC shift algebraic with special forms with flags update", + 0x01070207, + }, { tests_ild_ops_two_i16 , "PPC integer load insns\n with one register + one 16 bits immediate args with flags update", @@ -5728,6 +5771,11 @@ static void test_int_st_three_regs (const char* name, /* Used in do_tests, indexed by flags->nb_args Elements correspond to enum test_flags::num args */ +static test_loop_t int_sh_algebraic[] = { + &test_int_two_args, + &test_int_special, +}; + static test_loop_t int_loops[] = { &test_int_one_arg, &test_int_two_args, @@ -7465,7 +7513,7 @@ static int check_name (const char* name, const char *filter, typedef struct insn_sel_flags_t_struct { int one_arg, two_args, three_args; int arith, logical, compare, ldst; - int integer, floats, p405, altivec, faltivec, misc; + int integer, floats, p405, altivec, faltivec, misc, sh_algebraic; int cr; } insn_sel_flags_t; @@ -7505,6 +7553,7 @@ static void do_tests ( insn_sel_flags_t seln_flags, (family == PPC_405 && !seln_flags.p405) || (family == PPC_ALTIVEC && !seln_flags.altivec) || (family == PPC_MISC && !seln_flags.misc) || + (family == PPC_SH_ALGEBRAIC && !seln_flags.sh_algebraic) || (family == PPC_FALTIVEC && !seln_flags.faltivec)) continue; /* Check flags update */ @@ -7518,6 +7567,9 @@ static void do_tests ( insn_sel_flags_t seln_flags, case PPC_INTEGER: loop = &int_loops[nb_args - 1]; break; + case PPC_SH_ALGEBRAIC: + loop = &int_sh_algebraic[0]; + break; case PPC_MISC: loop = &misc_loops[0]; break; @@ -7625,6 +7677,7 @@ static void usage (void) "\t-f: test floating point instructions\n" "\t-a: test altivec instructions\n" "\t-m: test miscellaneous instructions\n" + "\t-s: test shift algebraic (sraw, srawi, srad, sradi) instructions\n" "\t-A: test all (int, fp, altivec) instructions\n" "\t-v: be verbose\n" "\t-h: display this help and exit\n" @@ -7658,6 +7711,7 @@ int main (int argc, char **argv) flags.altivec = 0; flags.faltivec = 0; flags.cr = -1; + flags.sh_algebraic = 0; while ((c = getopt(argc, argv, "123t:f:n:r:uvh")) != -1) { switch (c) { @@ -7760,6 +7814,7 @@ int main (int argc, char **argv) flags.p405 = 1; flags.altivec = 1; flags.faltivec = 1; + flags.algebraic = 1; } // Default cr update if (flags.cr == -1) @@ -7795,15 +7850,20 @@ int main (int argc, char **argv) flags.p405 = 0; flags.altivec = 0; flags.faltivec = 0; + flags.sh_algebraic = 0; // Flags flags.cr = 2; - while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) { + while ((c = getopt(argc, argv, "ilcLfmsahvA")) != -1) { switch (c) { case 'i': flags.arith = 1; flags.integer = 1; break; + case 's': + flags.logical = 1; + flags.sh_algebraic = 1; + break; case 'l': flags.logical = 1; flags.integer = 1; @@ -7895,6 +7955,7 @@ int main (int argc, char **argv) printf(" p405 = %d\n", flags.p405); printf(" altivec = %d\n", flags.altivec); printf(" faltivec = %d\n", flags.faltivec); + printf(" sh_algebraic = %d\n", flags.sh_algebraic); printf(" cr update: \n"); printf(" cr = %d\n", flags.cr); printf("\n"); diff --git a/none/tests/ppc32/jm-int-sh_algebraic.stderr.exp b/none/tests/ppc32/jm-int-sh_algebraic.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc32/jm-int-sh_algebraic.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc32/jm-int-sh_algebraic.stdout.exp b/none/tests/ppc32/jm-int-sh_algebraic.stdout.exp new file mode 100644 index 0000000000..796d39a3f4 --- /dev/null +++ b/none/tests/ppc32/jm-int-sh_algebraic.stdout.exp @@ -0,0 +1,45 @@ +PPC integer shift algebraic two args: + sraw 00000000, 00000000 => 00000000 (00000000 00000000) + sraw 00000000, 000f423f => 00000000 (00000000 00000000) + sraw 00000000, ffffffff => 00000000 (00000000 00000000) + sraw 000f423f, 00000000 => 000f423f (00000000 00000000) + sraw 000f423f, 000f423f => 00000000 (00000000 00000000) + sraw 000f423f, ffffffff => 00000000 (00000000 00000000) + sraw ffffffff, 00000000 => ffffffff (00000000 00000000) + sraw ffffffff, 000f423f => ffffffff (00000000 20000000) + sraw ffffffff, ffffffff => ffffffff (00000000 20000000) + +PPC integer shift algebraic two args with flags update: + sraw. 00000000, 00000000 => 00000000 (20000000 00000000) + sraw. 00000000, 000f423f => 00000000 (20000000 00000000) + sraw. 00000000, ffffffff => 00000000 (20000000 00000000) + sraw. 000f423f, 00000000 => 000f423f (40000000 00000000) + sraw. 000f423f, 000f423f => 00000000 (20000000 00000000) + sraw. 000f423f, ffffffff => 00000000 (20000000 00000000) + sraw. ffffffff, 00000000 => ffffffff (80000000 00000000) + sraw. ffffffff, 000f423f => ffffffff (80000000 20000000) + sraw. ffffffff, ffffffff => ffffffff (80000000 20000000) + +PPC shift algebraic with special forms: + srawi 00000000, 00000000 => 00000000 (00000000 00000000) + srawi 00000000, 000f423f => 00000000 (00000000 00000000) + srawi 00000000, ffffffff => 00000000 (00000000 00000000) + srawi 000f423f, 00000000 => 000f423f (00000000 00000000) + srawi 000f423f, 000f423f => 000f423f (00000000 00000000) + srawi 000f423f, ffffffff => 000f423f (00000000 00000000) + srawi ffffffff, 00000000 => ffffffff (00000000 00000000) + srawi ffffffff, 000f423f => ffffffff (00000000 00000000) + srawi ffffffff, ffffffff => ffffffff (00000000 00000000) + +PPC shift algebraic with special forms with flags update: + srawi. 00000000, 00000000 => 00000000 (20000000 00000000) + srawi. 00000000, 000f423f => 00000000 (20000000 00000000) + srawi. 00000000, ffffffff => 00000000 (20000000 00000000) + srawi. 000f423f, 00000000 => 000f423f (40000000 00000000) + srawi. 000f423f, 000f423f => 000f423f (40000000 00000000) + srawi. 000f423f, ffffffff => 000f423f (40000000 00000000) + srawi. ffffffff, 00000000 => ffffffff (80000000 00000000) + srawi. ffffffff, 000f423f => ffffffff (80000000 00000000) + srawi. ffffffff, ffffffff => ffffffff (80000000 00000000) + +All done. Tested 4 different instructions diff --git a/none/tests/ppc32/jm-int-sh_algebraic.vgtest b/none/tests/ppc32/jm-int-sh_algebraic.vgtest new file mode 100644 index 0000000000..cc660fcbfb --- /dev/null +++ b/none/tests/ppc32/jm-int-sh_algebraic.vgtest @@ -0,0 +1 @@ +prog: jm-insns -s diff --git a/none/tests/ppc32/jm-int_other.stdout.exp b/none/tests/ppc32/jm-int_other.stdout.exp index 577ddd12ca..989647f7c5 100644 --- a/none/tests/ppc32/jm-int_other.stdout.exp +++ b/none/tests/ppc32/jm-int_other.stdout.exp @@ -89,16 +89,6 @@ PPC integer logical insns with two args: slw ffffffff, 000f423f => 00000000 (00000000 00000000) slw ffffffff, ffffffff => 00000000 (00000000 00000000) - sraw 00000000, 00000000 => 00000000 (00000000 00000000) - sraw 00000000, 000f423f => 00000000 (00000000 00000000) - sraw 00000000, ffffffff => 00000000 (00000000 00000000) - sraw 000f423f, 00000000 => 000f423f (00000000 00000000) - sraw 000f423f, 000f423f => 00000000 (00000000 00000000) - sraw 000f423f, ffffffff => 00000000 (00000000 00000000) - sraw ffffffff, 00000000 => ffffffff (00000000 00000000) - sraw ffffffff, 000f423f => ffffffff (00000000 20000000) - sraw ffffffff, ffffffff => ffffffff (00000000 20000000) - srw 00000000, 00000000 => 00000000 (00000000 00000000) srw 00000000, 000f423f => 00000000 (00000000 00000000) srw 00000000, ffffffff => 00000000 (00000000 00000000) @@ -200,16 +190,6 @@ PPC integer logical insns with two args with flags update: slw. ffffffff, 000f423f => 00000000 (20000000 00000000) slw. ffffffff, ffffffff => 00000000 (20000000 00000000) - sraw. 00000000, 00000000 => 00000000 (20000000 00000000) - sraw. 00000000, 000f423f => 00000000 (20000000 00000000) - sraw. 00000000, ffffffff => 00000000 (20000000 00000000) - sraw. 000f423f, 00000000 => 000f423f (40000000 00000000) - sraw. 000f423f, 000f423f => 00000000 (20000000 00000000) - sraw. 000f423f, ffffffff => 00000000 (20000000 00000000) - sraw. ffffffff, 00000000 => ffffffff (80000000 00000000) - sraw. ffffffff, 000f423f => ffffffff (80000000 20000000) - sraw. ffffffff, ffffffff => ffffffff (80000000 20000000) - srw. 00000000, 00000000 => 00000000 (20000000 00000000) srw. 00000000, 000f423f => 00000000 (20000000 00000000) srw. 00000000, ffffffff => 00000000 (20000000 00000000) @@ -537,28 +517,10 @@ PPC logical insns with special forms: rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000) rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000) - srawi 00000000, 0 => 00000000 (00000000 00000000) - srawi 00000000, 31 => 00000000 (00000000 00000000) - srawi 000f423f, 0 => 000f423f (00000000 00000000) - srawi 000f423f, 31 => 00000000 (00000000 00000000) - srawi ffffffff, 0 => ffffffff (00000000 00000000) - srawi ffffffff, 31 => ffffffff (00000000 20000000) - mfcr (00000000) => 00000000 (00000000 00000000) mfcr (000f423f) => 000f423f (000f423f 00000000) mfcr (ffffffff) => ffffffff (ffffffff 00000000) - mfspr 1 (00000000) -> mtxer -> mfxer => 00000000 - mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f - mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f - mfspr 8 (00000000) -> mtlr -> mflr => 00000000 - mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f - mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff - mfspr 9 (00000000) -> mtctr -> mfctr => 00000000 - mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f - mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff - - PPC logical insns with special forms with flags update: rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000) rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000) @@ -647,13 +609,6 @@ PPC logical insns with special forms with flags update: rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000) rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000) - srawi. 00000000, 0 => 00000000 (20000000 00000000) - srawi. 00000000, 31 => 00000000 (20000000 00000000) - srawi. 000f423f, 0 => 000f423f (40000000 00000000) - srawi. 000f423f, 31 => 00000000 (20000000 00000000) - srawi. ffffffff, 0 => ffffffff (80000000 00000000) - srawi. ffffffff, 31 => ffffffff (80000000 20000000) - mcrf 0, 0 (00000000) => (00000000 00000000) mcrf 0, 7 (00000000) => (00000000 00000000) mcrf 7, 0 (00000000) => (00000000 00000000) @@ -966,4 +921,4 @@ PPC integer store insns with three register args: stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000) stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000) -All done. Tested 92 different instructions +All done. Tested 86 different instructions diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index bf95bfe418..1f40d94ca3 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -8,6 +8,10 @@ noinst_HEADERS = ppc64_helpers.h isa_3_1_helpers.h isa_3_1_register_defines.h EXTRA_DIST = \ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \ jm-int.stdout.exp-LE-ISA3_0 \ + jm-int-sh_algebraic.stderr.exp jm-int-sh_algebraic.stdout.exp \ + jm-int-sh_algebraic.stdout.exp-LE \ + jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 \ + jm-int-sh_algebraic.vgtest \ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \ jm-int_other.stdout.exp-LE \ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \ diff --git a/none/tests/ppc64/jm-int-sh_algebraic.stderr.exp b/none/tests/ppc64/jm-int-sh_algebraic.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/jm-int-sh_algebraic.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp new file mode 100644 index 0000000000..68345a843c --- /dev/null +++ b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp @@ -0,0 +1,85 @@ +PPC integer shift algebraic two args: + sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + + srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + +PPC integer shift algebraic two args with flags update: + sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + + srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + +PPC shift algebraic with special forms: + srawi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srawi 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (00000000 00000000) + srawi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + + sradi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sradi 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) + sradi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + +PPC shift algebraic with special forms with flags update: + srawi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srawi. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (80000000 00000000) + srawi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + + sradi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sradi. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) + sradi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + +All done. Tested 8 different instructions diff --git a/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE new file mode 100644 index 0000000000..68345a843c --- /dev/null +++ b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE @@ -0,0 +1,85 @@ +PPC integer shift algebraic two args: + sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + + srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) + srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) + +PPC integer shift algebraic two args with flags update: + sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + + srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) + srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) + +PPC shift algebraic with special forms: + srawi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srawi 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (00000000 00000000) + srawi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + + sradi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sradi 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) + sradi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + +PPC shift algebraic with special forms with flags update: + srawi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srawi. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (80000000 00000000) + srawi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + + sradi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sradi. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) + sradi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + +All done. Tested 8 different instructions diff --git a/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 new file mode 100644 index 0000000000..fedbb5ead1 --- /dev/null +++ b/none/tests/ppc64/jm-int-sh_algebraic.stdout.exp-LE-ISA3_0 @@ -0,0 +1,85 @@ +PPC integer shift algebraic two args: + sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20040000) + sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20040000) + sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20040000) + sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20040000) + + srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20040000) + srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20040000) + +PPC integer shift algebraic two args with flags update: + sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20040000) + sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20040000) + sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20040000) + sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20040000) + + srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20040000) + srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20040000) + +PPC shift algebraic with special forms: + srawi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + srawi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + srawi 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (00000000 00000000) + srawi 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (00000000 00000000) + srawi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + srawi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + + sradi 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) + sradi 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) + sradi 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000) + sradi 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) + sradi ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) + sradi ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) + +PPC shift algebraic with special forms with flags update: + srawi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + srawi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + srawi. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, 0000001cbe991def => ffffffffbe991def (80000000 00000000) + srawi. 0000001cbe991def, ffffffffffffffff => ffffffffbe991def (80000000 00000000) + srawi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + srawi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + + sradi. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) + sradi. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) + sradi. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000) + sradi. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) + sradi. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) + sradi. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) + +All done. Tested 8 different instructions diff --git a/none/tests/ppc64/jm-int-sh_algebraic.vgtest b/none/tests/ppc64/jm-int-sh_algebraic.vgtest new file mode 100644 index 0000000000..cc660fcbfb --- /dev/null +++ b/none/tests/ppc64/jm-int-sh_algebraic.vgtest @@ -0,0 +1 @@ +prog: jm-insns -s diff --git a/none/tests/ppc64/jm-int_other.stdout.exp b/none/tests/ppc64/jm-int_other.stdout.exp index 6deb0d0ddd..72760c299d 100644 --- a/none/tests/ppc64/jm-int_other.stdout.exp +++ b/none/tests/ppc64/jm-int_other.stdout.exp @@ -89,16 +89,6 @@ PPC integer logical insns with two args: slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) - sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) - sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) - sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) - sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) - sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000) - sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000) - sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) - sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) - sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) - srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) @@ -119,16 +109,6 @@ PPC integer logical insns with two args: sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) - srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) - srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) - srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) - srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) - srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) - srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) - srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) - srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) - srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) - srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) @@ -230,16 +210,6 @@ PPC integer logical insns with two args with flags update: slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) - sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) - sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) - sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) - sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) - sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000) - sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000) - sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) - sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) - sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) - srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) @@ -260,16 +230,6 @@ PPC integer logical insns with two args with flags update: sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) - srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) - srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) - srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) - srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) - srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) - srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) - srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) - srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) - srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) - srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) @@ -653,28 +613,10 @@ PPC logical insns with special forms: rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000) rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000) - srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000) - srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000) - srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000) - srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000) - srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000) - srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000) - mfcr (0000000000000000) => 0000000000000000 (00000000 00000000) mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000) mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000) - mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000 - mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f - mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f - mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000 - mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def - mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff - mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000 - mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def - mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff - - rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000) rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000) rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000) @@ -2061,37 +2003,6 @@ PPC logical insns with special forms: rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000) rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000) - sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000) - sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000) - sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000) - sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000) - sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000) - sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000) - sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000) - sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000) - sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000) - sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000) - sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000) - sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000) - sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000) - sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000) - sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000) - PPC logical insns with special forms with flags update: rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000) rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000) @@ -2180,13 +2091,6 @@ PPC logical insns with special forms with flags update: rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000) rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000) - srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000) - srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000) - srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000) - srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000) - srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000) - srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000) - mcrf 0, 0 (0000000000000000) => (00000000 00000000) mcrf 0, 7 (0000000000000000) => (00000000 00000000) mcrf 7, 0 (0000000000000000) => (00000000 00000000) @@ -3725,37 +3629,6 @@ PPC logical insns with special forms with flags update: rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000) rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000) - sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000) - sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000) - sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000) - sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000) - sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000) - sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000) - sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000) - sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000) - sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000) - sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000) - sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000) - sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000) - sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000) - sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000) - sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000) - PPC integer load insns with one register + one 16 bits immediate args with flags update: lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) @@ -3975,4 +3848,4 @@ PPC integer store insns with three register args: stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000) stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000) -All done. Tested 131 different instructions +All done. Tested 121 different instructions diff --git a/none/tests/ppc64/jm-int_other.stdout.exp-LE b/none/tests/ppc64/jm-int_other.stdout.exp-LE index 5cc903dffd..08fac66165 100644 --- a/none/tests/ppc64/jm-int_other.stdout.exp-LE +++ b/none/tests/ppc64/jm-int_other.stdout.exp-LE @@ -89,16 +89,6 @@ PPC integer logical insns with two args: slw ffffffffffffffff, 0000001cbe991def => 00000000000000... [truncated message content] |
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From: Carl L. <ca...@so...> - 2021-09-30 22:49:59
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a3c3f5394a77c641de19df1b59a7f544e5e0470a commit a3c3f5394a77c641de19df1b59a7f544e5e0470a Author: Carl Love <ce...@us...> Date: Wed Sep 29 21:20:30 2021 +0000 New test for the ISA 3.0 mcrxrx instruction. Add new test. Diff: --- NEWS | 1 + none/tests/ppc64/Makefile.am | 9 ++- none/tests/ppc64/test_mcrxrx.c | 113 ++++++++++++++++++++++++++++++++ none/tests/ppc64/test_mcrxrx.stderr.exp | 2 + none/tests/ppc64/test_mcrxrx.stdout.exp | 16 +++++ none/tests/ppc64/test_mcrxrx.vgtest | 2 + 6 files changed, 141 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 161441e167..ef1fce7baf 100644 --- a/NEWS +++ b/NEWS @@ -58,6 +58,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 441534 Update the expected output for test_isa_3_1_VRT. 442061 very slow execution under Fedora 34 (readdwarf3) 443031 Gcc -many change requires explicit .machine directives +443033 Add support for the ISA 3.0 mcrxrx instruction To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 1e5398575f..bf95bfe418 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -60,7 +60,8 @@ EXTRA_DIST = \ test_darn_inst.stdout.exp test_darn_inst.vgtest \ scv_test.stderr.exp scv_test.stdout.exp scv_test.vgtest \ test_copy_paste.stderr.exp test_copy_paste.stdout.exp \ - test_copy_paste.vgtest + test_copy_paste.vgtest \ + test_mcrxrx.vgtest test_mcrxrx.stderr.exp test_mcrxrx.stdout.exp check_PROGRAMS = \ @@ -75,7 +76,8 @@ check_PROGRAMS = \ subnormal_test test_darn_inst test_copy_paste \ test_tm test_touch_tm data-cache-instructions \ std_reg_imm \ - twi_tdi tw_td power6_bcmp scv_test + twi_tdi tw_td power6_bcmp scv_test \ + test_mcrxrx # lmw, stmw, lswi, lswx, stswi, stswx compile (and run) only on big endian. if VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX @@ -221,6 +223,8 @@ subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_1_FLAG) \ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_1) +test_mcrxrx_CFLAGS = $(AM_FLAGS) -Winline -Wall -O -g -mregnames @FLAG_M64@ $(ISA_3_00_FLAG) + test_isa_2_06_part3_LDADD = -lm test_dfp1_LDADD = -lm test_dfp2_LDADD = -lm @@ -232,4 +236,5 @@ test_isa_2_07_part2_LDADD = -lm test_tm_LDADD = -lm test_touch_tm_LDADD = -lm test_isa_3_0_LDADD = -lm +test_mcrxrx_LDADD = -lm diff --git a/none/tests/ppc64/test_mcrxrx.c b/none/tests/ppc64/test_mcrxrx.c new file mode 100644 index 0000000000..50aa40239e --- /dev/null +++ b/none/tests/ppc64/test_mcrxrx.c @@ -0,0 +1,113 @@ +/* + * Valgrind testcase for mcrxrx. + * This is a power9 (isa 3.0) instruction that copies + * OV,OV32,CA,CA32 fields from the XER and places them + * into a specified field of the CR. */ + +#include <stdio.h> +#include <string.h> +#include <unistd.h> + +unsigned long long current_cr; +unsigned long long current_xer; + +inline static void dissect_cr_field (unsigned long long full_cr, int offset) { + int mask; + int crfield; + mask = 0xf << (offset*4); + crfield = full_cr & mask; + crfield = crfield >> 4*offset; + + if (crfield & 0x01) printf("(LT)"); else printf(" - "); + if (crfield & 0x02) printf("(GT)"); else printf(" - "); + if (crfield & 0x04) printf("(EQ)"); else printf(" - "); + if (crfield & 0x08) printf("(SO)"); else printf(" - "); +} + +/* dissect_xer helpers */ +static char * xer_strings[] = { + " 0-RSVD", " 1-RSVD", " 2-RSVD", " 3-RSVD", " 4-RSVD", " 5-RSVD", " 6-RSVD", + " 7-RSVD", " 8-RSVD", " 9-RSVD", "10-RSVD", "11-RSVD", "12-RSVD", "13-RSVD", + "14-RSVD", "15-RSVD", "16-RSVD", "17-RSVD", "18-RSVD", "19-RSVD", + "20-RSVD", "21-RSVD", "22-RSVD", "23-RSVD", "24-RSVD", "25-RSVD", + "26-RSVD", "27-RSVD", "28-RSVD", "29-RSVD", "30-RSVD", "31-RSVD", + /* 32 */ "SO", "OV", "CA", + /* 35 */ "35-RSVD", "36-RSVD", "37-RSVD", "38-RSVD", "39-RSVD", + /* 40 */ "40-RSVD", "41-RSVD", "42-RSVD", "43-RSVD", + /* 44 */ "OV32", "CA32", + /* 46 */ "46-RSVD", "47-RSVD", "48-RSVD", "49-RSVD", "50-RSVD", "51-RSVD", + "52-RSVD", "53-RSVD", "54-RSVD", "55-RSVD", "56-RSVD", + /* 57:63 # bytes transferred by a Load/Store String Indexed instruction. */ + "LSI/SSI-0", "LSI/SSI-1", "LSI/SSI-2", "LSI/SSI-3", + "LSI/SSI-4", "LSI/SSI-5", "LSI/SSI-6", +}; + +/* Dissect the XER register contents. +*/ +static void dissect_xer_raw(unsigned long local_xer) { + int i; + long mybit; + char mystr[30]; + strcpy(mystr,""); + for (i = 0; i <= 63; i++) { + mybit = 1ULL << (63 - i); /* compensate for reversed bit numbering. */ + if (mybit & local_xer) { + strcat(mystr,xer_strings[i]); + strcat(mystr," "); + } + } + printf(" %16s",mystr); +} + +int main (int argc, char **argv) +{ +#if HAS_ISA_3_00 + /* init xer to zero. */ + unsigned long long Rx = 0; + __asm__ __volatile__ ("mtxer %0" : : "r" (Rx) :"xer"); + + /* iterate over each of the interesting fields in the xer + * OV,CA,OV32,CA32. Build a field with those bits set, and + * push that into the XER (mtxer). */ + unsigned long long i18,i19,i29,i30; + for (i30=0; i30<2; i30++) { // iterate OV + for (i29=0; i29<2; i29++) { // iterate CA + for (i19=0; i19<2; i19++) { // iterate OV32 + for (i18=0; i18<2; i18++) { // iterate CA32 + Rx = i18 << 18; + Rx += i19 << 19; + Rx += i29 << 29; + Rx += i30 << 30; + + printf("mcrxrx "); + + /* move 'Rx' value into the xer. */ + __asm__ __volatile__ ("mtxer %0" : : "r" (Rx) :"xer"); + + /* Retrieve the XER and print it. */ + __asm__ __volatile__ ("mfxer %0" : "=b"(current_xer) ); + + /* Moving the xer contents to the CR field # 2 + * using the mcrxr instruction. */ + __asm__ __volatile__ (".machine push;" \ + ".machine power9;" \ + "mcrxrx 2;" \ + ".machine pop;" ); + + /* Copy the cr into a reg so we can print it.. */ + __asm__ __volatile__ ("mfcr %0" : "=b"(current_cr) ); + + dissect_xer_raw(current_xer); + printf(" => "); + dissect_cr_field(current_cr,5); + printf("\n"); + } + } + } + } +#else + printf("HAS_ISA_3_00 not detected.\n"); +#endif + return 0; +} + diff --git a/none/tests/ppc64/test_mcrxrx.stderr.exp b/none/tests/ppc64/test_mcrxrx.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_mcrxrx.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_mcrxrx.stdout.exp b/none/tests/ppc64/test_mcrxrx.stdout.exp new file mode 100644 index 0000000000..c9ad72e6d1 --- /dev/null +++ b/none/tests/ppc64/test_mcrxrx.stdout.exp @@ -0,0 +1,16 @@ +mcrxrx => - - - - +mcrxrx CA32 => (LT) - - - +mcrxrx OV32 => - - (EQ) - +mcrxrx OV32 CA32 => (LT) - (EQ) - +mcrxrx CA => - (GT) - - +mcrxrx CA CA32 => (LT)(GT) - - +mcrxrx CA OV32 => - (GT)(EQ) - +mcrxrx CA OV32 CA32 => (LT)(GT)(EQ) - +mcrxrx OV => - - - (SO) +mcrxrx OV CA32 => (LT) - - (SO) +mcrxrx OV OV32 => - - (EQ)(SO) +mcrxrx OV OV32 CA32 => (LT) - (EQ)(SO) +mcrxrx OV CA => - (GT) - (SO) +mcrxrx OV CA CA32 => (LT)(GT) - (SO) +mcrxrx OV CA OV32 => - (GT)(EQ)(SO) +mcrxrx OV CA OV32 CA32 => (LT)(GT)(EQ)(SO) diff --git a/none/tests/ppc64/test_mcrxrx.vgtest b/none/tests/ppc64/test_mcrxrx.vgtest new file mode 100644 index 0000000000..6713503d5b --- /dev/null +++ b/none/tests/ppc64/test_mcrxrx.vgtest @@ -0,0 +1,2 @@ +prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00 +prog: test_mcrxrx |
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From: Carl L. <ca...@so...> - 2021-09-30 22:49:54
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7bd75320a0ba995be90e469fe4f26f4a925875b9 commit 7bd75320a0ba995be90e469fe4f26f4a925875b9 Author: Carl Love <ce...@us...> Date: Thu Sep 9 19:06:00 2021 +0000 Add support for the mcrxrx instruction. The mcrxrx instruction was introduced in ISA 3.0. It was missed when the ISA 3.0 support was added to Valgrind. The mcrxr instruction is not supported on ISA 3.0 and beyond. The instructions both do a move to the condition register however the mcrxrx moves [OV|OV32|CA|CA32]. Where the mcrxr instruction moves XER[32:35] (S0, OV, and CA bits) to the CR. Diff: --- VEX/priv/guest_ppc_toIR.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index e30e431581..3dab201476 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -11929,6 +11929,35 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt prefix, UInt theInstr ) break; } + case 0x240: { // mcrxrx (Move to Cond Register from XER) + IRTemp OV = newTemp(Ity_I32); + IRTemp CA = newTemp(Ity_I32); + IRTemp OV32 = newTemp(Ity_I32); + IRTemp CA32 = newTemp(Ity_I32); + IRTemp tmp = newTemp(Ity_I32); + + if (b21to22 != 0 || b11to20 != 0) { + vex_printf("dis_proc_ctl(ppc)(mcrxrx,b21to22|b11to20)\n"); + return False; + } + DIP("mcrxrx crf%d\n", crfD); + /* Move OV, OV32, CA, CA32 to condition register field BF */ + assign( OV, binop( Iop_Shl32, getXER_OV_32(), mkU8( 3 ) )); + assign( CA, binop( Iop_Shl32, getXER_CA_32(), mkU8( 1 ) )); + assign( OV32, binop( Iop_Shl32, getXER_OV32_32(), mkU8( 2 ) )); + assign( CA32, getXER_CA32_32() ); + + /* Put [OV | OV32 | CA | CA32] into the condition code register */ + assign( tmp, + binop( Iop_Or32, + binop( Iop_Or32, mkexpr ( OV ), mkexpr ( OV32 ) ), + binop( Iop_Or32, mkexpr ( CA ), mkexpr ( CA32 ) ) + ) ); + + putGST_field( PPC_GST_CR, mkexpr( tmp ), crfD ); + break; + } + case 0x013: // b11to20==0: mfcr (Move from Cond Register, PPC32 p467) // b20==1 & b11==0: mfocrf (Move from One CR Field) @@ -37514,6 +37543,7 @@ DisResult disInstr_PPC_WRK ( case 0x200: case 0x013: case 0x153: // mcrxr, mfcr, mfspr case 0x173: case 0x090: case 0x1D3: // mftb, mtcrf, mtspr case 0x220: // mcrxrt + case 0x240: // mcrxrx if (dis_proc_ctl( abiinfo, prefix, theInstr )) goto decode_success; goto decode_failure; |
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From: Carl L. <ca...@so...> - 2021-09-30 22:33:25
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7d2cec7f247809f08ce2e93a1a81ce333c6c244b commit 7d2cec7f247809f08ce2e93a1a81ce333c6c244b Author: Carl Love <ce...@us...> Date: Tue Sep 14 19:36:24 2021 +0000 Fixes for mcrxr instruction Add .machine directives to ensure the mcrxr instruction is assembled for power 6. The instruction is not supported on later platforms. Diff: --- NEWS | 1 + none/tests/ppc32/jm-insns.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index 3e570c7de6..161441e167 100644 --- a/NEWS +++ b/NEWS @@ -57,6 +57,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 441512 Remove a unneeded / unnecessary prefix check. 441534 Update the expected output for test_isa_3_1_VRT. 442061 very slow execution under Fedora 34 (readdwarf3) +443031 Gcc -many change requires explicit .machine directives To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index 5316ce318d..3a169933f8 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -1460,7 +1460,8 @@ extern void test_mcrf (void); ASSEMBLY_FUNC("test_mcrf", "mcrf 0, 0"); extern void test_mcrxr (void); -ASSEMBLY_FUNC("test_mcrxr", "mcrxr 0"); +ASSEMBLY_FUNC("test_mcrxr", ".machine push; .machine power6;" \ + "mcrxr 0; .machine pop"); extern void test_mtcrf (void); ASSEMBLY_FUNC("test_mtcrf", "mtcrf 0, 14"); |
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From: Carl L. <ca...@so...> - 2021-09-30 22:33:16
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=518a2d59ac49fd4cd206912d95da76c1631d439c commit 518a2d59ac49fd4cd206912d95da76c1631d439c Author: Carl Love <ce...@us...> Date: Wed Sep 8 22:01:05 2021 +0000 Fix dfp tests. Due to changes between the compiler and linker, we need to add .machine arguments to configure file to properly detect the availability of the dfp instructions. Add print statement if HAS_DFP is not enabled to make it easier to determine when HAS_DFP is not enabled. Diff: --- configure.ac | 14 ++++++++++---- none/tests/ppc32/test_dfp1.c | 2 ++ none/tests/ppc32/test_dfp2.c | 2 ++ none/tests/ppc32/test_dfp3.c | 2 ++ none/tests/ppc32/test_dfp4.c | 2 ++ none/tests/ppc32/test_dfp5.c | 2 ++ none/tests/ppc64/test_dfp1.vgtest | 2 +- none/tests/ppc64/test_dfp2.vgtest | 2 +- none/tests/ppc64/test_dfp3.vgtest | 2 +- none/tests/ppc64/test_dfp4.vgtest | 2 +- none/tests/ppc64/test_dfp5.vgtest | 2 +- 11 files changed, 25 insertions(+), 9 deletions(-) diff --git a/configure.ac b/configure.ac index 463e05f172..27400ad1e5 100755 --- a/configure.ac +++ b/configure.ac @@ -1563,14 +1563,17 @@ AM_CONDITIONAL([HAS_VSX], [test x$ac_compiler_supports_vsx_flag = xyes \ -a x$HWCAP_HAS_VSX = xyes ]) # DFP (Decimal Float) +# The initial DFP support was added in Power 6. The dcffix instruction +# support was added in Power 7. AC_MSG_CHECKING([that assembler knows DFP]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ #ifdef __s390__ __asm__ __volatile__("adtr 1, 2, 3") #else - __asm__ __volatile__("dadd 1, 2, 3"); - __asm__ __volatile__("dcffix 1, 2"); +__asm__ __volatile__(".machine power7;\n" \ + "dadd 1, 2, 3;\n" \ + "dcffix 1, 2"); #endif ]])], [ ac_asm_have_dfp=yes @@ -1582,13 +1585,16 @@ AC_MSG_RESULT([no]) AC_MSG_CHECKING([that compiler knows -mhard-dfp switch]) safe_CFLAGS=$CFLAGS CFLAGS="-mhard-dfp -Werror" + +# The dcffix instruction is Power 7 AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ #ifdef __s390__ __asm__ __volatile__("adtr 1, 2, 3") #else - __asm__ __volatile__("dadd 1, 2, 3"); - __asm__ __volatile__("dcffix 1, 2"); + __asm__ __volatile__(".machine power7;\n" \ + "dadd 1, 2, 3;\n" \ + "dcffix 1, 2"); #endif ]])], [ ac_compiler_have_dfp=yes diff --git a/none/tests/ppc32/test_dfp1.c b/none/tests/ppc32/test_dfp1.c index baf18419c7..a08f5dff8c 100644 --- a/none/tests/ppc32/test_dfp1.c +++ b/none/tests/ppc32/test_dfp1.c @@ -497,6 +497,8 @@ int main() { i++; } +#else + printf("HAS_DFP not detected.\n"); #endif // HAS_DFP return 0; } diff --git a/none/tests/ppc32/test_dfp2.c b/none/tests/ppc32/test_dfp2.c index 1563fb32b8..9ec325d6df 100644 --- a/none/tests/ppc32/test_dfp2.c +++ b/none/tests/ppc32/test_dfp2.c @@ -668,6 +668,8 @@ int main(int argc, char ** argv, char ** envp) { i++; } +#else + printf("HAS_DFP not detected.\n"); #endif // HAS_DFP return 0; } diff --git a/none/tests/ppc32/test_dfp3.c b/none/tests/ppc32/test_dfp3.c index f8596de38f..cb99538cd0 100644 --- a/none/tests/ppc32/test_dfp3.c +++ b/none/tests/ppc32/test_dfp3.c @@ -1256,6 +1256,8 @@ int main() { i++; } +#else + printf("HAS_DFP not detected.\n"); #endif // HAS_DFP return 0; } diff --git a/none/tests/ppc32/test_dfp4.c b/none/tests/ppc32/test_dfp4.c index bce9130f70..0aa3a5adb2 100644 --- a/none/tests/ppc32/test_dfp4.c +++ b/none/tests/ppc32/test_dfp4.c @@ -636,6 +636,8 @@ int main() { i++; } +#else + printf("HAS_DFP not detected.\n"); #endif // HAS_DFP return 0; } diff --git a/none/tests/ppc32/test_dfp5.c b/none/tests/ppc32/test_dfp5.c index 9af94b81f9..4c6e1fc8f5 100644 --- a/none/tests/ppc32/test_dfp5.c +++ b/none/tests/ppc32/test_dfp5.c @@ -605,6 +605,8 @@ int main() { i++; } +#else + printf("HAS_DFP not detected.\n"); #endif // HAS_DFP return 0; } diff --git a/none/tests/ppc64/test_dfp1.vgtest b/none/tests/ppc64/test_dfp1.vgtest index 71af5fa640..1939c55ec4 100644 --- a/none/tests/ppc64/test_dfp1.vgtest +++ b/none/tests/ppc64/test_dfp1.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap dfp +prereq: ../../../tests/check_ppc64_auxv_cap dfp && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: test_dfp1 diff --git a/none/tests/ppc64/test_dfp2.vgtest b/none/tests/ppc64/test_dfp2.vgtest index 23a1f00ede..7c3ce6fa6a 100644 --- a/none/tests/ppc64/test_dfp2.vgtest +++ b/none/tests/ppc64/test_dfp2.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap dfp +prereq: ../../../tests/check_ppc64_auxv_cap dfp && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: test_dfp2 diff --git a/none/tests/ppc64/test_dfp3.vgtest b/none/tests/ppc64/test_dfp3.vgtest index e806e85e21..cd5ac995b6 100644 --- a/none/tests/ppc64/test_dfp3.vgtest +++ b/none/tests/ppc64/test_dfp3.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap dfp +prereq: ../../../tests/check_ppc64_auxv_cap dfp && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: test_dfp3 diff --git a/none/tests/ppc64/test_dfp4.vgtest b/none/tests/ppc64/test_dfp4.vgtest index 7688eb8ac9..24e639d38b 100644 --- a/none/tests/ppc64/test_dfp4.vgtest +++ b/none/tests/ppc64/test_dfp4.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap dfp +prereq: ../../../tests/check_ppc64_auxv_cap dfp && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: test_dfp4 diff --git a/none/tests/ppc64/test_dfp5.vgtest b/none/tests/ppc64/test_dfp5.vgtest index 0c905d8d9e..4e79f4f10a 100644 --- a/none/tests/ppc64/test_dfp5.vgtest +++ b/none/tests/ppc64/test_dfp5.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap dfp +prereq: ../../../tests/check_ppc64_auxv_cap dfp && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: test_dfp5 |
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From: Carl L. <ca...@so...> - 2021-09-30 22:33:11
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=475916cbd37611dcf510c2249c74ff6e31894023 commit 475916cbd37611dcf510c2249c74ff6e31894023 Author: Carl Love <ce...@us...> Date: Tue Sep 14 21:43:49 2021 +0000 Add .machine directives for the darn instruction Diff: --- VEX/priv/guest_ppc_helpers.c | 9 ++++++--- configure.ac | 2 +- none/tests/ppc64/test_darn_inst.c | 9 ++++++--- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 54318b6d5c..0ae3a5aa17 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -2429,11 +2429,14 @@ ULong darn_dirty_helper ( UInt L ) # if defined (HAS_DARN) if ( L == 0) - __asm__ __volatile__("darn %0,0" : "=r"(val)); + __asm__ __volatile__(".machine push; .machine power9;" \ + "darn %0,0; .machine pop;" : "=r"(val)); else if (L == 1) - __asm__ __volatile__("darn %0,1" : "=r"(val)); + __asm__ __volatile__(".machine push; .machine power9;" \ + "darn %0,1; .machine pop;" : "=r"(val)); else if (L == 2) - __asm__ __volatile__("darn %0,2" : "=r"(val)); + __asm__ __volatile__(".machine push; .machine power9;" + "darn %0,2; .machine pop;" : "=r"(val)); # endif return val; diff --git a/configure.ac b/configure.ac index d755b0248b..463e05f172 100755 --- a/configure.ac +++ b/configure.ac @@ -1693,7 +1693,7 @@ AC_MSG_CHECKING([that assembler knows darn instruction ]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ - __asm__ __volatile__("darn 1,0 "); + __asm__ __volatile__(".machine power9; darn 1,0 "); ]])], [ ac_asm_have_darn_inst=yes AC_MSG_RESULT([yes]) diff --git a/none/tests/ppc64/test_darn_inst.c b/none/tests/ppc64/test_darn_inst.c index cd72fac14a..b591a8146d 100644 --- a/none/tests/ppc64/test_darn_inst.c +++ b/none/tests/ppc64/test_darn_inst.c @@ -19,19 +19,22 @@ int main() /* The random number instruction returns 0xFFFFFFFFFFFFFFFFULL on error and an unsigned 64-bit value between 0 and 0xFFFFFFFFFFFFFFFEULL on success. */ - __asm__ __volatile__ ("darn %0,0" : "=r" (rand)); + __asm__ __volatile__ (".machine push; .machine power9;" \ + "darn %0,0; .machine pop" : "=r" (rand)); if (rand == ERROR) { success = FALSE; printf ("Error darn 0 result = 0%llx not in expected range.\n", rand); } - __asm__ __volatile__ ("darn %0,1" : "=r" (rand)); + __asm__ __volatile__ (".machine push; .machine power9;" \ + "darn %0,1; .machine pop" : "=r" (rand)); if (rand == ERROR) { success = FALSE; printf ("Error darn 1 result = 0%llx not in expected range.\n", rand); } - __asm__ __volatile__ ("darn %0,2" : "=r" (rand)); + __asm__ __volatile__ (".machine push; .machine power9;" \ + "darn %0,2; .machine pop" : "=r" (rand)); if (rand == ERROR) { success = FALSE; printf ("Error darn 2 result = 0%llx not in expected range.\n", rand); |
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From: Carl L. <ca...@so...> - 2021-09-30 22:33:09
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e23c2a2291071d1443ff9c6dbce5bbfe2c4cdd7c commit e23c2a2291071d1443ff9c6dbce5bbfe2c4cdd7c Author: Carl Love <ce...@us...> Date: Fri Sep 17 00:33:14 2021 +0000 Fixes to add .machine directives for assembly instructions Diff: --- VEX/priv/guest_ppc_helpers.c | 4 +++- configure.ac | 9 ++++++--- none/tests/ppc64/Makefile.am | 2 +- none/tests/ppc64/scv_test.c | 3 ++- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 689aa8f34e..54318b6d5c 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -1899,7 +1899,9 @@ static Double conv_f16_to_double( ULong input ) __attribute__ ((aligned (64))) ULong src; __attribute__ ((aligned (64))) Double result; src = input; - __asm__ __volatile__ ("xscvhpdp %x0,%x1" : "=wa" (result) : "wa" (src)); + __asm__ __volatile__ (".machine push;\n" ".machine power9;\n" \ + "xscvhpdp %x0,%x1 ;\n .machine pop" \ + : "=wa" (result) : "wa" (src) ); return result; # else return 0.0; diff --git a/configure.ac b/configure.ac index 81f2e23497..d755b0248b 100755 --- a/configure.ac +++ b/configure.ac @@ -1658,7 +1658,8 @@ AC_MSG_CHECKING([that assembler knows ISA 3.00 ]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ - __asm__ __volatile__("cnttzw 1,2 "); +__asm__ __volatile__ (".machine power9;\n" \ + "cnttzw 1,3; \n" ); ]])], [ # guest_ppc_helpers.c needs the HAS_ISA_3_OO to enable copy, paste, # cpabort support @@ -1677,7 +1678,8 @@ AC_MSG_CHECKING([that assembler knows xscvhpdp ]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ - __asm__ __volatile__("xscvhpdp 1,2 "); +__asm__ __volatile__ (".machine power9;\n" \ + "xscvhpdp 1,2;\n" ); ]])], [ ac_asm_have_xscvhpdp=yes AC_MSG_RESULT([yes]) @@ -1704,7 +1706,8 @@ AC_MSG_RESULT([no]) AC_MSG_CHECKING([that assembler knows ISA 3.1 ]) AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ - __asm__ __volatile__("brh 1,2 "); +__asm__ __volatile__ (".machine power10;\n" \ + "brh 1,2;\n "); ]])], [ ac_asm_have_isa_3_1=yes AC_MSG_RESULT([yes]) diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 15e90ebfdb..1e5398575f 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -147,7 +147,7 @@ HTM_FLAG = endif if HAS_ISA_3_00 -BUILD_FLAGS_ISA_3_00 = -mcpu=power8 +BUILD_FLAGS_ISA_3_00 = -mcpu=power9 ISA_3_00_FLAG = -DHAS_ISA_3_00 else BUILD_FLAGS_ISA_3_00 = diff --git a/none/tests/ppc64/scv_test.c b/none/tests/ppc64/scv_test.c index 39bf82aa20..5c8df226f4 100644 --- a/none/tests/ppc64/scv_test.c +++ b/none/tests/ppc64/scv_test.c @@ -19,7 +19,8 @@ register long int r8 __asm__ ("r8"); \ r0=name; \ __asm__ __volatile__ \ - ("scv 0\n\t" \ + (".machine power9\n" \ + "scv 0\n\t" \ "0:" \ : "=&r" (r0), \ "=&r" (r3), "=&r" (r4), "=&r" (r5), \ |
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From: Carl L. <ca...@so...> - 2021-09-30 22:33:01
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a63e9c28b53f20ce1c4bdc0b81da59957a17f4f0 commit a63e9c28b53f20ce1c4bdc0b81da59957a17f4f0 Author: Tulio Magno Quites Machado Filho <tu...@li...> Date: Fri Aug 20 19:07:09 2021 -0300 powerpc: Add .machine directives for scv, copy, paste, cpabort instructions GCC is no longer passing the "-many" flag to the assembler. So, the inline assembly instructions statements need to use the .machine directives for the specific platform. (gcc commit e154242724b084380e3221df7c08fcdbd8460674 ; "[RS6000] Don't pass -many to the assembler". Hardware sync instruction (hwsync) added after the copy, paste and cpabort instructions to improve the reliability of the test. Diff: --- Makefile.all.am | 4 ++-- VEX/priv/guest_ppc_helpers.c | 15 ++++++++++++--- coregrind/m_syscall.c | 4 ++++ none/tests/ppc64/Makefile.am | 4 ++-- none/tests/ppc64/test_copy_paste.c | 25 ++++++++++++++++++------- 5 files changed, 38 insertions(+), 14 deletions(-) diff --git a/Makefile.all.am b/Makefile.all.am index 1b66f82ea4..06b23c99e0 100644 --- a/Makefile.all.am +++ b/Makefile.all.am @@ -126,9 +126,9 @@ AM_CFLAGS_BASE = \ # Power ISA flag for use by guest_ppc_helpers.c if HAS_XSCVHPDP if HAS_DARN -ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN +ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN -DHAS_ISA_3_00 else -ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP +ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_ISA_3_00 endif else ISA_3_0_BUILD_FLAG = diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 87f094c670..689aa8f34e 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -3170,13 +3170,22 @@ UInt copy_paste_abort_dirty_helper(UInt addr, UInt op) { UInt cr; if (op == COPY_INST) - __asm__ __volatile__ ("copy 0,%0" :: "r" (addr)); + __asm__ __volatile__ (".machine push;\n" + ".machine power9;\n" + "copy 0,%0;\n" + ".machine pop" :: "r" (addr)); else if (op == PASTE_INST) - __asm__ __volatile__ ("paste. 0,%0" :: "r" (addr)); + __asm__ __volatile__ (".machine push;\n" + ".machine power9;\n" + "paste. 0,%0\n" + ".machine pop" :: "r" (addr)); else if (op == CPABORT_INST) - __asm__ __volatile__ ("cpabort"); + __asm__ __volatile__ (".machine push;\n" + ".machine power9;\n" + "cpabort\n" + ".machine pop"); else /* Unknown operation */ diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c index 80e2af4397..c12632d366 100644 --- a/coregrind/m_syscall.c +++ b/coregrind/m_syscall.c @@ -599,7 +599,11 @@ asm( " ld 4, 16(3)\n" /* sc arg 2 */ " ld 0, 0(3)\n" /* sc number */ " ld 3, 8(3)\n" /* sc arg 1 */ + +" .machine push\n" +" .machine \"power9\"\n" " scv 0\n" +" .machine pop\n" " ld 5,-16(1)\n" /* reacquire argblock ptr (r5 is caller-save) */ " std 3,0(5)\n" /* argblock[0] = r3 */ diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 9527cdf1e8..15e90ebfdb 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -218,8 +218,8 @@ test_isa_3_1_AT_CFLAGS = $(test_isa_3_1_CFLAGS) subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) -test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) +test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_1_FLAG) \ + @FLAG_M64@ $(BUILD_FLAGS_ISA_3_1) test_isa_2_06_part3_LDADD = -lm test_dfp1_LDADD = -lm diff --git a/none/tests/ppc64/test_copy_paste.c b/none/tests/ppc64/test_copy_paste.c index dc5f42c1a0..339ff8b6f7 100644 --- a/none/tests/ppc64/test_copy_paste.c +++ b/none/tests/ppc64/test_copy_paste.c @@ -1,5 +1,9 @@ /* The copy, paste, cpabort are ISA 3.0 instructions. However, the memory - to memory copy is only supported on ISA 3.1 era machines. */ + to memory copy is only supported on ISA 3.1 era machines. + + The following test does a memory to memory copy test, an out of order + paste test, and a copy paste abort test. This test is only supported + ISA 3.1 systems. */ #include <stdio.h> #include <stdint.h> @@ -7,7 +11,7 @@ #include <string.h> #include <malloc.h> -#ifdef HAS_ISA_3_00 +#ifdef HAS_ISA_3_1 #include <altivec.h> /* return CR0 in least significant bits */ @@ -17,17 +21,20 @@ void test_copy (uint8_t *reg) { - __asm__ __volatile__ ("copy 0,%0" : : "r" (reg)); + __asm__ __volatile__ (".machine push; .machine power9; " \ + "copy 0,%0; hwsync; .machine pop;" : : "r" (reg)); } void test_paste (uint8_t *reg) { - __asm__ __volatile__ ("paste. 0,%0" : : "r" (reg)); + __asm__ __volatile__ (".machine push; .machine power9; " \ + "paste. 0,%0; hwsync; .machine pop;" : : "r" (reg)); } void test_cpabort (void) { - __asm__ __volatile__ ("cpabort"); + __asm__ __volatile__ (".machine push; .machine power9; " \ + "cpabort; hwsync; .machine pop;"); } #define NUM_ELEMENTS 128 @@ -39,7 +46,7 @@ void test_cpabort (void) int main() { -#ifdef HAS_ISA_3_00 +#ifdef HAS_ISA_3_1 int i; unsigned int cc_value; int result = SUCCESS; @@ -66,6 +73,10 @@ int main() test_paste (dst_buffer); GET_CR0(cc_value); +#if DEBUG + printf("CR0 = 0x%x\n", cc_value); +#endif + #if DEBUG printf("AFTER COPY/PASTE Contents of src/dst buffer\n"); for (i=0; i<NUM_ELEMENTS; i++) { @@ -111,7 +122,7 @@ int main() printf("FAILURE.\n"); #else - printf("HAS_ISA_3_00 not detected.\n"); + printf("HAS_ISA_3_1 not detected.\n"); #endif return 0; } |
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From: Carl L. <ca...@so...> - 2021-09-30 22:32:59
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a9b5f6cfeb0592cb52199cdbe3a36d173b3e32b6 commit a9b5f6cfeb0592cb52199cdbe3a36d173b3e32b6 Author: carl love <ce...@us...> Date: Mon Sep 13 13:02:11 2021 -0500 Configure,makefile and test case fixes for older powerpc targets. Assorted changes to fix up compile issues as seen during regression testing of VG on hardware back as far as Power 6 (ISA 2.05). Diff: --- VEX/priv/guest_ppc_helpers.c | 3 ++- configure.ac | 6 +++++- none/tests/ppc64/Makefile.am | 18 +++++++++++++++--- none/tests/ppc64/scv_test.c | 10 +++++++++- none/tests/ppc64/scv_test.vgtest | 2 +- none/tests/ppc64/subnormal_test.vgtest | 2 +- none/tests/ppc64/test_copy_paste.c | 7 +++++++ none/tests/ppc64/test_darn_inst.c | 7 +++++++ none/tests/ppc64/test_mod_instructions.c | 7 ++++++- 9 files changed, 53 insertions(+), 9 deletions(-) diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 6c8191a474..87f094c670 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -3164,7 +3164,8 @@ VexGuestLayout }; UInt copy_paste_abort_dirty_helper(UInt addr, UInt op) { -# if defined(__powerpc__) +# if defined(__powerpc__) && defined(HAS_ISA_3_00) +/* The enable copy, paste., and cpabort were introduced in ISA 3.0. */ ULong ret; UInt cr; diff --git a/configure.ac b/configure.ac index 462068a5ac..81f2e23497 100755 --- a/configure.ac +++ b/configure.ac @@ -1660,12 +1660,17 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ __asm__ __volatile__("cnttzw 1,2 "); ]])], [ +# guest_ppc_helpers.c needs the HAS_ISA_3_OO to enable copy, paste, +# cpabort support +safe_CFLAGS=$CFLAGS +CFLAGS="-DHAS_ISA_3_00" ac_asm_have_isa_3_00=yes AC_MSG_RESULT([yes]) ], [ ac_asm_have_isa_3_00=no AC_MSG_RESULT([no]) ]) +CFLAGS=$safe_CFLAGS # xscvhpdp checking AC_MSG_CHECKING([that assembler knows xscvhpdp ]) @@ -1697,7 +1702,6 @@ AC_MSG_RESULT([no]) # isa 3.01 checking AC_MSG_CHECKING([that assembler knows ISA 3.1 ]) - AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]], [[ __asm__ __volatile__("brh 1,2 "); diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 61b6ec9342..9527cdf1e8 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -88,11 +88,16 @@ AM_CCASFLAGS += @FLAG_M64@ allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ +scv_test_SOURCES = scv_test.c +test_copy_paste_SOURCES = test_copy_paste.c +test_mod_instructions_SOURCES = test_mod_instructions.c +test_isa_3_0_SOURCES = test_isa_3_0.c test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c +test_darn_inst_SOURCES = test_darn_inst.c if HAS_ALTIVEC BUILD_FLAG_ALTIVEC = -maltivec @@ -111,7 +116,8 @@ BUILD_FLAG_VSX = endif if HAS_DFP -BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6 +# The DFP test uses the Power7 dcffix instruction. +BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power7 DFP_FLAG = -DHAS_DFP else BUILD_FLAGS_DFP = @@ -192,6 +198,12 @@ test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) +scv_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ + @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) + +test_mod_instructions_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ + @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) + test_darn_inst_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) @@ -206,8 +218,8 @@ test_isa_3_1_AT_CFLAGS = $(test_isa_3_1_CFLAGS) subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) -test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_3_1_FLAG) \ - @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_3_1) +test_copy_paste_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \ + @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00) test_isa_2_06_part3_LDADD = -lm test_dfp1_LDADD = -lm diff --git a/none/tests/ppc64/scv_test.c b/none/tests/ppc64/scv_test.c index d292c4be8f..39bf82aa20 100644 --- a/none/tests/ppc64/scv_test.c +++ b/none/tests/ppc64/scv_test.c @@ -1,10 +1,11 @@ #include <stdio.h> #include <stdint.h> #include <stdlib.h> + +#ifdef HAS_ISA_3_00 #include <asm/unistd.h> #include <sys/auxv.h> - #define ASM_INPUT_0 "0" (r0) #define INTERNAL_SYSCALL_SCV(name, nr) \ @@ -55,9 +56,13 @@ #define PPC_FEATURE2_SCV 0x00100000 /* scv syscall enabled */ +#endif + int main(void) { + +#ifdef HAS_ISA_3_00 int result; unsigned long hwcaps2_val; @@ -81,5 +86,8 @@ main(void) } printf("Success\n"); +#else + printf("HAS_ISA_3_00 not detected.\n"); +#endif return 0; } diff --git a/none/tests/ppc64/scv_test.vgtest b/none/tests/ppc64/scv_test.vgtest index 163d874a0b..93cc28c1a5 100644 --- a/none/tests/ppc64/scv_test.vgtest +++ b/none/tests/ppc64/scv_test.vgtest @@ -1,2 +1,2 @@ -prereq: +prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00 prog: scv_test diff --git a/none/tests/ppc64/subnormal_test.vgtest b/none/tests/ppc64/subnormal_test.vgtest index 91c5cd6acf..098809e470 100644 --- a/none/tests/ppc64/subnormal_test.vgtest +++ b/none/tests/ppc64/subnormal_test.vgtest @@ -1,2 +1,2 @@ -prereq: ../../../tests/check_ppc64_auxv_cap altivec +prereq: ../../../tests/check_ppc64_auxv_cap altivec && ../../../tests/check_ppc64_auxv_cap arch_2_06 prog: subnormal_test diff --git a/none/tests/ppc64/test_copy_paste.c b/none/tests/ppc64/test_copy_paste.c index 0f4659ed88..dc5f42c1a0 100644 --- a/none/tests/ppc64/test_copy_paste.c +++ b/none/tests/ppc64/test_copy_paste.c @@ -6,6 +6,8 @@ #include <stdlib.h> #include <string.h> #include <malloc.h> + +#ifdef HAS_ISA_3_00 #include <altivec.h> /* return CR0 in least significant bits */ @@ -33,9 +35,11 @@ void test_cpabort (void) #define FAILURE 2 #define DEBUG 0 #define PASTE_ERROR 0 +#endif int main() { +#ifdef HAS_ISA_3_00 int i; unsigned int cc_value; int result = SUCCESS; @@ -106,5 +110,8 @@ int main() else printf("FAILURE.\n"); +#else + printf("HAS_ISA_3_00 not detected.\n"); +#endif return 0; } diff --git a/none/tests/ppc64/test_darn_inst.c b/none/tests/ppc64/test_darn_inst.c index ba828a3a90..cd72fac14a 100644 --- a/none/tests/ppc64/test_darn_inst.c +++ b/none/tests/ppc64/test_darn_inst.c @@ -1,7 +1,10 @@ #include <stdio.h> #include <stdint.h> #include <stdlib.h> + +#ifdef HAS_ISA_3_00 #include <altivec.h> +#endif #define TRUE 1 #define FALSE 0 @@ -9,6 +12,7 @@ int main() { +#ifdef HAS_ISA_3_00 unsigned long long rand; int success = TRUE; @@ -38,5 +42,8 @@ int main() else printf("Failure.\n"); +#else + printf("HAS_ISA_3_00 not detected.\n"); +#endif return 0; } diff --git a/none/tests/ppc64/test_mod_instructions.c b/none/tests/ppc64/test_mod_instructions.c index 07e1cd2881..ff5d55285f 100644 --- a/none/tests/ppc64/test_mod_instructions.c +++ b/none/tests/ppc64/test_mod_instructions.c @@ -1,5 +1,6 @@ #include <stdio.h> +#ifdef HAS_ISA_3_00 long test_modsd( long srcA, long srcB) { long dst; @@ -31,9 +32,11 @@ unsigned test_moduw( unsigned srcA, unsigned srcB) return dst; } +#endif int main() { +#ifdef HAS_ISA_3_00 int srcA_si, srcB_si, dst_si; unsigned int srcA_ui, srcB_ui, dst_ui; long srcA_sl, srcB_sl, dst_sl; @@ -245,7 +248,9 @@ int main() printf ("modud result = %lu\n", dst_ul); #endif } - +#else + printf("HAS_ISA_3_00 not detected.\n"); +#endif // HAS_ISA_3_0 return 0; } |
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From: Mark W. <ma...@so...> - 2021-09-30 16:23:01
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d281a09e8e115d7cc4054a8e43fb4dd9b4d7778d commit d281a09e8e115d7cc4054a8e43fb4dd9b4d7778d Author: Mark Wielaard <ma...@kl...> Date: Thu Sep 30 18:22:30 2021 +0200 Add generated man pages to .gitignore Diff: --- .gitignore | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.gitignore b/.gitignore index 3838b5b083..ed78bb8e3f 100644 --- a/.gitignore +++ b/.gitignore @@ -289,6 +289,16 @@ /docs/Makefile.in /docs/valid-manpages /docs/valid-manual +/docs/valgrind.1 +/docs/cg_annotate.1 +/docs/cg_diff.1 +/docs/cg_merge.1 +/docs/callgrind_annotate.1 +/docs/callgrind_control.1 +/docs/ms_print.1 +/docs/valgrind-listener.1 +/docs/valgrind-di-server.1 +/docs/vgdb.1 # /docs/images/ /docs/images/Makefile |
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From: Mark W. <ma...@so...> - 2021-09-30 15:57:57
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8f395c0032e9fd1c6e1c5962511ca4b0a30b6a10 commit 8f395c0032e9fd1c6e1c5962511ca4b0a30b6a10 Author: Mark Wielaard <ma...@kl...> Date: Thu Sep 30 17:57:25 2021 +0200 Remove VEX/nanoarm.orig file Diff: --- VEX/nanoarm.orig | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/VEX/nanoarm.orig b/VEX/nanoarm.orig deleted file mode 100644 index 90742dff36..0000000000 --- a/VEX/nanoarm.orig +++ /dev/null @@ -1,19 +0,0 @@ - 0: e1a0c00d mov ip, sp -. 0 00008000 4 -. 0d c0 a0 e1 - - 4: e92dd810 stmdb sp!, {r4, fp, ip, lr, pc} -. 1 00008004 4 -. 10 d8 2d e9 - - 8: e24cb004 sub fp, ip, #4 ; 0x4 -. 2 00008008 4 -. 04 b0 4c e2 - - c: e3a00014 mov r0, #20 ; 0x14 -. 3 0000800C 4 -. 14 00 a0 e3 - - 10: ebfffffe bl 0 <newHHW> -. 4 00008010 4 -. fe ff ff eb |
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From: Andreas A. <ar...@so...> - 2021-09-30 14:31:07
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=724460764d3613cb9092ede2a238d7dcb88f8055 commit 724460764d3613cb9092ede2a238d7dcb88f8055 Author: Andreas Arnez <ar...@li...> Date: Thu Sep 30 14:10:29 2021 +0200 configure.ac: Avoid the use of "which" The "which" command is not always installed, but configure.ac uses it in the function AC_HWCAP_CONTAINS_FLAG to force invocation of the executable "true" rather than the shell builtin with the same name. (The point here is to get LD_SHOW_AUXV=1 evaluated by the dynamic loader.) Another option might be to hard-wire the location /bin/true, because the filesystem hierarchy standard requires it to be there. However, the FHS doesn't apply to BSDs and at least some FreeBSD versions do not stick to that specific rule. On the other hand, the "env" command seems to be available on all relevant platforms, so use that instead. Diff: --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index beb5bba792..462068a5ac 100755 --- a/configure.ac +++ b/configure.ac @@ -1464,7 +1464,7 @@ AC_CHECK_MEMBER([pthread_mutex_t.__data.__kind], AC_DEFUN([AC_HWCAP_CONTAINS_FLAG],[ AUXV_CHECK_FOR=$1 AC_MSG_CHECKING([if AT_HWCAP contains the $AUXV_CHECK_FOR indicator]) - if LD_SHOW_AUXV=1 `which true` | grep ^AT_HWCAP | grep -q -w ${AUXV_CHECK_FOR} + if env LD_SHOW_AUXV=1 true | grep ^AT_HWCAP | grep -q -w ${AUXV_CHECK_FOR} then AC_MSG_RESULT([yes]) AC_SUBST([$2],[yes]) |