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From: Ed M. <em...@fr...> - 2021-09-24 18:46:05
|
On Thu, 23 Sept 2021 at 15:06, Paul Floyd <pj...@wa...> wrote: > > Hi Mark > > I have FreeBSD support that I'd like to add. > > I'll refresh the patches in bugzilla. Not much has changed, but there > has been at least one merge conflict since I last generated the patches. Thank you Paul for pushing this along. Let me know if I can do anything to help. We also have FreeBSD quarterly status updates[1] coming up and it would be great to include this work in a report. I can help put one together. [1] https://github.com/freebsd/freebsd-quarterly |
|
From: Paul F. <pj...@wa...> - 2021-09-23 19:05:42
|
On 9/22/21 1:02 PM, Mark Wielaard wrote: > Hi, > > I would like to propose we do a valgrind 3.18.0 release next month. > There have been various useful changes since 3.17.0 for power10, s390x > z15 updates, arm64 v8.2, glibc 2.34 updates (which are really needed, > without them things simply break). > > I have backported most of the above improvements to the Fedora valgrind > package (mainly because Fedora 35 has already switched to glibc 2.34), > but that contains 25 patches now (where the power10 and z15 backports > count as just one, so it is more like 35 patches), which is not ideal. > > There is also the DWARF reader speedup patch: > https://bugs.kde.org/show_bug.cgi?id=442061 > which I would really like to see go in because it really helps startup > time (especially with distros that use debuginfod, which valgrind now > also supports). > > I propose to do the release on October 15. So we have some time to go > over the open bugs and see which really should get resolved before > then. Please do respond if you have bugs/patches that really deserve to > be resolved before the 3.18.0 release. Hi Mark I have FreeBSD support that I'd like to add. I'll refresh the patches in bugzilla. Not much has changed, but there has been at least one merge conflict since I last generated the patches. A+ Paul |
|
From: Julian S. <se...@so...> - 2021-09-23 13:47:34
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e3f6c6610401ce4dfd87efe54ac87cdaa0b0f9bd commit e3f6c6610401ce4dfd87efe54ac87cdaa0b0f9bd Author: Julian Seward <js...@ac...> Date: Thu Sep 23 15:46:21 2021 +0200 amd64: add spec rules for: S/NS after ADDL, S after ADDQ. Diff: --- VEX/priv/guest_amd64_helpers.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c index af2ddc29c5..9d61e7a0fd 100644 --- a/VEX/priv/guest_amd64_helpers.c +++ b/VEX/priv/guest_amd64_helpers.c @@ -1092,6 +1092,7 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, /*---------------- ADDQ ----------------*/ + /* 4, */ if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondZ)) { /* long long add, then Z --> test (dst+src == 0) */ return unop(Iop_1Uto64, @@ -1100,8 +1101,22 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, mkU64(0))); } + /* 8, */ + if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondS)) { + /* long long add, then S (negative) + --> (dst+src)[63] + --> ((dst + src) >>u 63) & 1 + */ + return binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(63)), + mkU64(1)); + } + /*---------------- ADDL ----------------*/ + /* 0, */ if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondO)) { /* This is very commonly generated by Javascript JITs, for the idiom "do a 32-bit add and jump to out-of-line code if @@ -1127,6 +1142,32 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, } + /* 8, 9 */ + if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondS)) { + /* long add, then S (negative) + --> (dst+src)[31] + --> ((dst +64 src) >>u 31) & 1 + Pointless to narrow the args to 32 bit before the add. */ + return binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(31)), + mkU64(1)); + } + if (isU64(cc_op, AMD64G_CC_OP_ADDL) && isU64(cond, AMD64CondNS)) { + /* long add, then NS (not negative) + --> (dst+src)[31] ^ 1 + --> (((dst +64 src) >>u 31) & 1) ^ 1 + Pointless to narrow the args to 32 bit before the add. */ + return binop(Iop_Xor64, + binop(Iop_And64, + binop(Iop_Shr64, + binop(Iop_Add64, cc_dep1, cc_dep2), + mkU8(31)), + mkU64(1)), + mkU64(1)); + } + /*---------------- SUBQ ----------------*/ /* 0, */ |
|
From: Carl L. <ce...@us...> - 2021-09-22 16:03:44
|
Mark:
Will and I have been working on some PPC patches. These patches
include some fixes for the latest GCC compiler, adding support for a
missing instruction and some basic cleanup. Specifically on PPC the
option -many has changed which requires adding .machine directives and
fixes to the makefile to ensure the correct processor is specified when
compiling the test cases.
We will see if we can get these finished up and committed in the next
week or so. Other than these cleanups/fixes we have no new
functionality.
Carl Love
On Wed, 2021-09-22 at 15:02 +0200, Mark Wielaard wrote:
> Hi,
>
> I would like to propose we do a valgrind 3.18.0 release next month.
> There have been various useful changes since 3.17.0 for power10,
> s390x
> z15 updates, arm64 v8.2, glibc 2.34 updates (which are really needed,
> without them things simply break).
>
> I have backported most of the above improvements to the Fedora
> valgrind
> package (mainly because Fedora 35 has already switched to glibc
> 2.34),
> but that contains 25 patches now (where the power10 and z15 backports
> count as just one, so it is more like 35 patches), which is not
> ideal.
>
> There is also the DWARF reader speedup patch:
> https://bugs.kde.org/show_bug.cgi?id=442061
> which I would really like to see go in because it really helps
> startup
> time (especially with distros that use debuginfod, which valgrind now
> also supports).
>
> I propose to do the release on October 15. So we have some time to go
> over the open bugs and see which really should get resolved before
> then. Please do respond if you have bugs/patches that really deserve
> to
> be resolved before the 3.18.0 release.
>
> Cheers,
>
> Mark
>
>
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers
|
|
From: Mark W. <ma...@kl...> - 2021-09-22 13:02:59
|
Hi, I would like to propose we do a valgrind 3.18.0 release next month. There have been various useful changes since 3.17.0 for power10, s390x z15 updates, arm64 v8.2, glibc 2.34 updates (which are really needed, without them things simply break). I have backported most of the above improvements to the Fedora valgrind package (mainly because Fedora 35 has already switched to glibc 2.34), but that contains 25 patches now (where the power10 and z15 backports count as just one, so it is more like 35 patches), which is not ideal. There is also the DWARF reader speedup patch: https://bugs.kde.org/show_bug.cgi?id=442061 which I would really like to see go in because it really helps startup time (especially with distros that use debuginfod, which valgrind now also supports). I propose to do the release on October 15. So we have some time to go over the open bugs and see which really should get resolved before then. Please do respond if you have bugs/patches that really deserve to be resolved before the 3.18.0 release. Cheers, Mark |
|
From: Mark W. <ma...@kl...> - 2021-09-19 10:09:57
|
Hi Chuep, On Sat, Sep 18, 2021 at 02:10:47AM +0200, yann puech via Valgrind-developers wrote: > Thanks Mark for your reply, > Here is the location: https://www.valgrind.org/downloads/old.html Aha, yes. It would probably be best if we simply linked to https://sourceware.org/pub/valgrind/ for older releases on that page. But I don't remember how to update the website. Cheers, Mark |
|
From: Mark W. <ma...@so...> - 2021-09-18 20:29:53
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=10922b70b825a0a9b4df9694ceb9f20e93e2c11d commit 10922b70b825a0a9b4df9694ceb9f20e93e2c11d Author: Mark Wielaard <ma...@kl...> Date: Sat Sep 18 02:19:13 2021 +0200 m_debuginfo: Handle DW_TAG_atomic_type DW_TAG_atomic_type is a DWARF5 qualifier tag like DW_TAG_volatile_type, DW_TAG_const_type and DW_TAG_restrict_type. Diff: --- coregrind/m_debuginfo/readdwarf3.c | 5 +++-- coregrind/m_debuginfo/tytypes.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/coregrind/m_debuginfo/readdwarf3.c b/coregrind/m_debuginfo/readdwarf3.c index 52c27d4bb4..968c37bd63 100644 --- a/coregrind/m_debuginfo/readdwarf3.c +++ b/coregrind/m_debuginfo/readdwarf3.c @@ -4191,14 +4191,15 @@ static void parse_type_DIE ( /*MOD*/XArray* /* of TyEnt */ tyents, } if (dtag == DW_TAG_volatile_type || dtag == DW_TAG_const_type - || dtag == DW_TAG_restrict_type) { + || dtag == DW_TAG_restrict_type || dtag == DW_TAG_atomic_type) { Int have_ty = 0; VG_(memset)(&typeE, 0, sizeof(typeE)); typeE.cuOff = D3_INVALID_CUOFF; typeE.tag = Te_TyQual; typeE.Te.TyQual.qual = (dtag == DW_TAG_volatile_type ? 'V' - : (dtag == DW_TAG_const_type ? 'C' : 'R')); + : (dtag == DW_TAG_const_type ? 'C' + : (dtag == DW_TAG_restrict_type ? 'R' : 'A'))); /* target type defaults to 'void' */ typeE.Te.TyQual.typeR = D3_FAKEVOID_CUOFF; nf_i = 0; diff --git a/coregrind/m_debuginfo/tytypes.c b/coregrind/m_debuginfo/tytypes.c index 75e4cf500b..e356b92c9a 100644 --- a/coregrind/m_debuginfo/tytypes.c +++ b/coregrind/m_debuginfo/tytypes.c @@ -295,6 +295,7 @@ void ML_(pp_TyEnt_C_ishly)( const XArray* /* of TyEnt */ tyents, case 'C': VG_(printf)("const "); break; case 'V': VG_(printf)("volatile "); break; case 'R': VG_(printf)("restrict "); break; + case 'A': VG_(printf)("atomic "); break; default: goto unhandled; } ML_(pp_TyEnt_C_ishly)(tyents, ent->Te.TyQual.typeR); |
|
From: yann p. <ch...@ya...> - 2021-09-18 00:10:59
|
Thanks Mark for your reply, Here is the location: https://www.valgrind.org/downloads/old.html Chuep On 9/18/21 2:06 AM, Mark Wielaard wrote: > Hi Chuep, > > On Sat, Sep 18, 2021 at 01:39:06AM +0200, yann puech via Valgrind-developers wrote: >> I am looking for an old version of the software (3.3), but it looks like >> some archived releases do not have hyperlinks anymore while their md5 >> checksums are shown. >> >> Can you please fix the issue? > Where do you see the issue? > Older releases can be found here: > https://sourceware.org/pub/valgrind/ > > Cheers, > > Mark |
|
From: Mark W. <ma...@kl...> - 2021-09-18 00:06:45
|
Hi Chuep, On Sat, Sep 18, 2021 at 01:39:06AM +0200, yann puech via Valgrind-developers wrote: > I am looking for an old version of the software (3.3), but it looks like > some archived releases do not have hyperlinks anymore while their md5 > checksums are shown. > > Can you please fix the issue? Where do you see the issue? Older releases can be found here: https://sourceware.org/pub/valgrind/ Cheers, Mark |
|
From: yann p. <ch...@ya...> - 2021-09-17 23:39:20
|
Hi dear Developers, I am looking for an old version of the software (3.3), but it looks like some archived releases do not have hyperlinks anymore while their md5 checksums are shown. Can you please fix the issue? Cheers, Chuep |
|
From: Andreas A. <ar...@so...> - 2021-09-17 17:17:07
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=687aad3498226d35459b147f751e90bcaeef80e4 commit 687aad3498226d35459b147f751e90bcaeef80e4 Author: Andreas Arnez <ar...@li...> Date: Fri Sep 17 18:48:12 2021 +0200 s390x: Fix 64-bit shift in s390_irgen_VSTRS The function s390_irgen_VSTRS in guest_s390_toIR.c contains a shift operation that is intended to yield a 64-bit number but uses 1UL instead of 1ULL. This doesn't work on systems where 'unsigned long' is only 32 bits wide. Fix by replacing 1UL by 1ULL. Diff: --- VEX/priv/guest_s390_toIR.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 1bd18f7602..72222ab045 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -17679,7 +17679,7 @@ s390_irgen_VSTRS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) assign(result, unop(Iop_ClzNat64, binop(Iop_Or64, unop(Iop_V128HIto64, match), - mkU64((1UL << 48) - 1)))); + mkU64((1ULL << 48) - 1)))); put_vr_qw(v1, binop(Iop_64HLtoV128, mkexpr(result), mkU64(0))); /* Set condition code. |
|
From: Carl L. <ca...@so...> - 2021-09-13 16:40:28
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=093bef43d69236287ccc748591c9560a71181b0a commit 093bef43d69236287ccc748591c9560a71181b0a Author: Carl Love <ce...@us...> Date: Fri Sep 10 17:15:57 2021 -0500 Remove deprecated regression tests for mftgpr and mffgpr. The mftgpr and mffgpr instructions are deprecated. Added comments in VEX/priv/guest_ppc_toIR.c for the instructions stating the instructions are deprecated. Valgrind support can be removed if the opcodes get reused in the future. For now, leaving the functional support in Valgrind for the instructions. Removed the regression test power6_mf_gpr.c, expect files and vgtest file from none/tests/ppc64. Diff: --- VEX/priv/guest_ppc_toIR.c | 6 ++++ none/tests/ppc64/Makefile.am | 3 +- none/tests/ppc64/power6_mf_gpr.c | 47 ------------------------------- none/tests/ppc64/power6_mf_gpr.stderr.exp | 2 -- none/tests/ppc64/power6_mf_gpr.stdout.exp | 3 -- none/tests/ppc64/power6_mf_gpr.vgtest | 1 - 6 files changed, 7 insertions(+), 55 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 57ac7bcf48..e30e431581 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -8401,6 +8401,9 @@ static Bool dis_int_logic ( UInt prefix, UInt theInstr ) break; case 0x2DF: { // mftgpr (move floating-point to general purpose register) + /* The mftgpr instruction was deprecated in Power 7, 2009 timeframe. + Leaving support in Valgrind for now (9/10/2021). Can remove the + mftgpr support in Valgrind if the opcode ever gets reused. */ IRTemp frB = newTemp(Ity_F64); DIP("mftgpr r%u,fr%u\n", rS_addr, rB_addr); @@ -8415,6 +8418,9 @@ static Bool dis_int_logic ( UInt prefix, UInt theInstr ) } case 0x25F: { // mffgpr (move floating-point from general purpose register) + /* The mffgpr instruction was deprecated in Power 7, 2009 timeframe. + Leaving support in Valgrind for now (9/10/2021). Can remove the + mftgpr support in Valgrind if the opcode ever gets reused. */ IRTemp frA = newTemp(Ity_F64); DIP("mffgpr fr%u,r%u\n", rS_addr, rB_addr); diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index df03dbec31..61b6ec9342 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -21,7 +21,6 @@ EXTRA_DIST = \ tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \ opcodes.h \ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \ - power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \ test_isa_2_06_part1.stdout.exp-LE \ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \ @@ -75,7 +74,7 @@ check_PROGRAMS = \ test_isa_3_1_Misc test_isa_3_1_AT \ subnormal_test test_darn_inst test_copy_paste \ test_tm test_touch_tm data-cache-instructions \ - power6_mf_gpr std_reg_imm \ + std_reg_imm \ twi_tdi tw_td power6_bcmp scv_test # lmw, stmw, lswi, lswx, stswi, stswx compile (and run) only on big endian. diff --git a/none/tests/ppc64/power6_mf_gpr.c b/none/tests/ppc64/power6_mf_gpr.c deleted file mode 100644 index 6151a34784..0000000000 --- a/none/tests/ppc64/power6_mf_gpr.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright (C) 2007 IBM - - Author: Pete Eberlein ebe...@us... - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, see <http://www.gnu.org/licenses/>. - - The GNU General Public License is contained in the file COPYING. -*/ - -#include <stdio.h> -#include <string.h> - - - -int main(int argc, char *argv[]) -{ - - long i; - double f; - - i = 0; - f = 100.0; - - printf("%lx %f\n", i, f); - - asm("mftgpr %0, %1\n": "=r"(i):"f"(f)); - - f = 0.0; - printf("%lx %f\n", i, f); - - asm("mffgpr %0, %1\n": "=f"(f):"r"(i)); - - printf("%lx %f\n", i, f); - - return 0; -} diff --git a/none/tests/ppc64/power6_mf_gpr.stderr.exp b/none/tests/ppc64/power6_mf_gpr.stderr.exp deleted file mode 100644 index 139597f9cb..0000000000 --- a/none/tests/ppc64/power6_mf_gpr.stderr.exp +++ /dev/null @@ -1,2 +0,0 @@ - - diff --git a/none/tests/ppc64/power6_mf_gpr.stdout.exp b/none/tests/ppc64/power6_mf_gpr.stdout.exp deleted file mode 100644 index 7bc827dd22..0000000000 --- a/none/tests/ppc64/power6_mf_gpr.stdout.exp +++ /dev/null @@ -1,3 +0,0 @@ -0 100.000000 -4059000000000000 0.000000 -4059000000000000 100.000000 diff --git a/none/tests/ppc64/power6_mf_gpr.vgtest b/none/tests/ppc64/power6_mf_gpr.vgtest deleted file mode 100644 index 5868fe66ee..0000000000 --- a/none/tests/ppc64/power6_mf_gpr.vgtest +++ /dev/null @@ -1 +0,0 @@ -prog: power6_mf_gpr |
|
From: Eli D. <el...@aa...> - 2021-09-13 15:42:02
|
Hello!
I have inherited a valgrind-based instrumentation tool, and I have
discovered a very strange error. I have an instrumentation function that
adds a call to a logging function. If said logging function contains an
if statement that evaluates to false, valgrind segfaults. If it contains
no if, or the if evaluates to true, the tool works fine. See this MVP:
static void BK_(log_call)(UInt dest) {
if (0x400000 < dest) {
VG_(printf)("Call of %u\n", dest);
}
}
static
IRSB* bk_instrument ( VgCallbackClosure* closure,
IRSB* bb,
const VexGuestLayout* layout,
const VexGuestExtents* vge,
const VexArchInfo* archinfo_host,
IRType gWordTy, IRType hWordTy )
{
IRSB *ibb = deepCopyIRSBExceptStmts(bb);
IRDirty *dirty = unsafeIRDirty_0_N(0, "log_call",
VG_(fnptr_to_fnentry)(&BK_(log_call)),
mkIRExprVec_1(IRConstExprArg(1000))
);
addStmtToIRSB(ibb, IRStmt_Dirty(dirty));
for (int i = 0; i < bb->stmts_used; i++) {
addStmtToIRSB(ibb, bb->stmts[i]);
}
VG_(printf)("\n\nOriginal BB: \n");
ppIRSB(bb);
VG_(printf)("New BB: \n");
ppIRSB(ibb);
VG_(printf)("------------------------------\n");
return ibb;
}
As-is, this will segfault. If I remove the `if (0x400000 < dest)`, swap
the sign of the if, or add another print statement above the if, it will
work as intended. This doesn't happen on all programs, and I'm running
this on mipsel, if that's relevant. I believe I have removed everything
else from the pass -- I'm pretty sure the error lies here, although I
have no idea how that could be the case
The exact segfault I get is
```
==8333==
==8333== Process terminating with default action of signal 11 (SIGSEGV)
==8333== Access not within mapped region at address 0x0
==8333== at 0x48ED8B0: ioctl (in /lib/libuClibc-0.9.33.2.so)
==8333== by 0x4913D0C: tcgetattr (in /lib/libuClibc-0.9.33.2.so)
==8333== If you believe this happened as a result of a stack
==8333== overflow in your program's main thread (unlikely but
==8333== possible), you can try to
increase the size of the
==8333== main thread stack using the --main-stacksize= flag.
==8333== The main thread stack size used in this run was 8388608.
==8333==
[ 97.868000] beck-mips32-lin/8333: potentially unexpected fatal signal 11.
[ 97.868000]
[ 97.868000] Cpu 0
[ 97.868000] $ 0 : 00000000 3000a400 00000000 0000000b
[ 97.868000] $ 4 : 0000208d 0000000b 00000000 00000000
[ 97.868000] $ 8 : 41d1a010 00000000 420b5ac0 420b9ad8
[ 97.868000] $12 : 420b9adc 00060528 0000006f fffffffe
[ 97.868000] $16 : 428b8e50 428b8eec 428b8edc 428b8e88
[ 97.868000] $20 : 582aeac0 58a8c03c 00000000 00000000
[ 97.868000] $24 : 00064541 58015080
[ 97.868000] $28 : 582b5880 428b8dd8 58bdc328 58015198
[ 97.868000] Hi : 00000000
[ 97.868000] Lo : 00000000
[ 97.868000] epc : 58015088 0x58015088
[ 97.868000] Not tainted
[ 97.872000] ra : 58015198 0x58015198
[ 97.872000] Status: 0000a413 USER EXL IE
[ 97.872000] Cause : 10800020
[ 97.872000] PrId : 00019300 (MIPS 24Kc)
```
and the basic block it's crashing on is
New BB:
IRSB {
t0:I32 t1:I32 t2:I32 t3:I32 t4:I64 t5:I32 t6:I32 t7:I32
t8:I32 t9:I32 t10:I32 t11:I32 t12:I32 t13:I32 t14:I32 t15:I32
t16:I32
DIRTY 1:I1 ::: log_call{0x58000208}(0x3E8:I32)
------ IMark(0x4000B4C, 4, 0) ------
t6 = GET:I32(132)
t7 = GET:I32(40)
t5 = Sub32(t6,t7)
PUT(40) = t5
PUT(136) = 0x4000B50:I32
------ IMark(0x4000B50, 4, 0) ------
t9 = GET:I32(120)
t8 = Add32(t9,0xFFFF801C:I32)
t10 = LDle:I32(t8)
------ IMark(0x4000B54, 4, 0) ------
t11 = Add32(t10,0x4B44:I32)
------ IMark(0x4000B58, 4, 0) ------
t13 = Add32(t11,t5)
PUT(108) = t13
------ IMark(0x4000B5C, 4, 0) ------
PUT(132) = 0x4000B64:I32
------ IMark(0x4000B60, 4, 0) ------
PUT(136) = t13; exit-Call
}
If anyone has any advice on what's wrong with this code or suggestions
on how to debug it further, it would be very much appreciated!
|
|
From: Carl L. <ca...@so...> - 2021-09-10 21:37:13
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=81032a82f77fc7038d80621fefd75b5726760a60 commit 81032a82f77fc7038d80621fefd75b5726760a60 Author: Carl Love <ce...@us...> Date: Fri Sep 10 16:20:10 2021 -0500 Cleanup of none/tests/ppc64/Makefile.am Fixing indentation and move the jm_insns_CFLAGS next to the other CFLAGS definitions. No functional changes. Diff: --- none/tests/ppc64/Makefile.am | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 5c2ee87d58..df03dbec31 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -7,7 +7,7 @@ noinst_HEADERS = ppc64_helpers.h isa_3_1_helpers.h isa_3_1_register_defines.h EXTRA_DIST = \ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \ - jm-int.stdout.exp-LE-ISA3_0 \ + jm-int.stdout.exp-LE-ISA3_0 \ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \ jm-int_other.stdout.exp-LE \ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \ @@ -141,9 +141,6 @@ else HTM_FLAG = endif -jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \ - @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC) - if HAS_ISA_3_00 BUILD_FLAGS_ISA_3_00 = -mcpu=power8 ISA_3_00_FLAG = -DHAS_ISA_3_00 @@ -160,6 +157,9 @@ BUILD_FLAGS_ISA_3_1 = ISA_3_1_FLAG = endif +jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \ + @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC) + test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) |
|
From: Mark W. <ma...@so...> - 2021-09-08 10:52:56
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=cadf0432290b0bc147c7b5dd54c63bc94986743c commit cadf0432290b0bc147c7b5dd54c63bc94986743c Author: Mark Wielaard <ma...@kl...> Date: Wed Sep 8 12:51:18 2021 +0200 Add getoff-arm64-linux to .gitignore Diff: --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index cf45901132..3838b5b083 100644 --- a/.gitignore +++ b/.gitignore @@ -40,6 +40,7 @@ # /auxprogs/ /auxprogs/.deps /auxprogs/getoff-amd64-darwin +/auxprogs/getoff-arm64-linux /auxprogs/getoff-x86-darwin /auxprogs/getoff-amd64-linux /auxprogs/getoff-x86-linux |
|
From: Carl L. <ca...@so...> - 2021-09-07 18:39:35
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=9aaeafa70c5126b22857485449f8d5eeb1d9c527 commit 9aaeafa70c5126b22857485449f8d5eeb1d9c527 Author: Carl Love <ce...@us...> Date: Tue Sep 7 17:15:38 2021 +0000 Update the expected output for test_isa_3_1_VRT. The inputs into the vinsdlx,vinsdrx instructions changed as a result of the impossible constraint issue fix. This patch updates the expected results. https://bugs.kde.org/show_bug.cgi?id=441534 Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 72 ++++++++++++++-------------- 2 files changed, 37 insertions(+), 36 deletions(-) diff --git a/NEWS b/NEWS index f869343326..ce182030f0 100644 --- a/NEWS +++ b/NEWS @@ -54,6 +54,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 432387 s390x: z15 instructions support 440906 Fix impossible constraint issue in P10 testcase. 441512 Remove a unneeded / unnecessary prefix check. +441534 Update the expected output for test_isa_3_1_VRT. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 39c4d86197..8f04ee2cbb 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -6798,24 +6798,24 @@ vinsdlx 0 4 => 4,1111111111111111 vinsdlx 0 6 => 6,1111111111111111 vinsdlx 0 8 => 8,1111111111111111 vinsdlx 0 a => a,1111111111111111 -vinsdlx 4 0 => 1111111100000000,0000000011111111 -vinsdlx 4 2 => 1111111100000000,0000000211111111 -vinsdlx 4 4 => 1111111100000000,0000000411111111 -vinsdlx 4 6 => 1111111100000000,0000000611111111 -vinsdlx 4 8 => 1111111100000000,0000000811111111 -vinsdlx 4 a => 1111111100000000,0000000a11111111 -vinsdlx 8 0 => 1111111111111111,0000000000000000 -vinsdlx 8 2 => 1111111111111111,0000000000000002 -vinsdlx 8 4 => 1111111111111111,0000000000000004 -vinsdlx 8 6 => 1111111111111111,0000000000000006 -vinsdlx 8 8 => 1111111111111111,0000000000000008 -vinsdlx 8 a => 1111111111111111,000000000000000a -vinsdlx 3 0 => 1111110000000000,0000001111111111 -vinsdlx 3 2 => 1111110000000000,0000021111111111 -vinsdlx 3 4 => 1111110000000000,0000041111111111 -vinsdlx 3 6 => 1111110000000000,0000061111111111 -vinsdlx 3 8 => 1111110000000000,0000081111111111 -vinsdlx 3 a => 1111110000000000,00000a1111111111 +vinsdlx 6 0 => 1111111111110000,0000000000001111 +vinsdlx 6 2 => 1111111111110000,0000000000021111 +vinsdlx 6 4 => 1111111111110000,0000000000041111 +vinsdlx 6 6 => 1111111111110000,0000000000061111 +vinsdlx 6 8 => 1111111111110000,0000000000081111 +vinsdlx 6 a => 1111111111110000,00000000000a1111 +vinsdlx 6 0 => 1111111111110000,0000000000001111 +vinsdlx 6 2 => 1111111111110000,0000000000021111 +vinsdlx 6 4 => 1111111111110000,0000000000041111 +vinsdlx 6 6 => 1111111111110000,0000000000061111 +vinsdlx 6 8 => 1111111111110000,0000000000081111 +vinsdlx 6 a => 1111111111110000,00000000000a1111 +vinsdlx 2 0 => 1111000000000000,0000111111111111 +vinsdlx 2 2 => 1111000000000000,0002111111111111 +vinsdlx 2 4 => 1111000000000000,0004111111111111 +vinsdlx 2 6 => 1111000000000000,0006111111111111 +vinsdlx 2 8 => 1111000000000000,0008111111111111 +vinsdlx 2 a => 1111000000000000,000a111111111111 vinsdrx 0 0 => 1111111111111111,0000000000000000 vinsdrx 0 2 => 1111111111111111,0000000000000002 @@ -6823,24 +6823,24 @@ vinsdrx 0 4 => 1111111111111111,0000000000000004 vinsdrx 0 6 => 1111111111111111,0000000000000006 vinsdrx 0 8 => 1111111111111111,0000000000000008 vinsdrx 0 a => 1111111111111111,000000000000000a -vinsdrx 4 0 => 1111111100000000,0000000011111111 -vinsdrx 4 2 => 1111111100000000,0000000211111111 -vinsdrx 4 4 => 1111111100000000,0000000411111111 -vinsdrx 4 6 => 1111111100000000,0000000611111111 -vinsdrx 4 8 => 1111111100000000,0000000811111111 -vinsdrx 4 a => 1111111100000000,0000000a11111111 -vinsdrx 8 0 => 0,1111111111111111 -vinsdrx 8 2 => 2,1111111111111111 -vinsdrx 8 4 => 4,1111111111111111 -vinsdrx 8 6 => 6,1111111111111111 -vinsdrx 8 8 => 8,1111111111111111 -vinsdrx 8 a => a,1111111111111111 -vinsdrx 3 0 => 1111111111000000,0000000000111111 -vinsdrx 3 2 => 1111111111000000,0000000002111111 -vinsdrx 3 4 => 1111111111000000,0000000004111111 -vinsdrx 3 6 => 1111111111000000,0000000006111111 -vinsdrx 3 8 => 1111111111000000,0000000008111111 -vinsdrx 3 a => 1111111111000000,000000000a111111 +vinsdrx 6 0 => 1111000000000000,0000111111111111 +vinsdrx 6 2 => 1111000000000000,0002111111111111 +vinsdrx 6 4 => 1111000000000000,0004111111111111 +vinsdrx 6 6 => 1111000000000000,0006111111111111 +vinsdrx 6 8 => 1111000000000000,0008111111111111 +vinsdrx 6 a => 1111000000000000,000a111111111111 +vinsdrx 6 0 => 1111000000000000,0000111111111111 +vinsdrx 6 2 => 1111000000000000,0002111111111111 +vinsdrx 6 4 => 1111000000000000,0004111111111111 +vinsdrx 6 6 => 1111000000000000,0006111111111111 +vinsdrx 6 8 => 1111000000000000,0008111111111111 +vinsdrx 6 a => 1111000000000000,000a111111111111 +vinsdrx 2 0 => 1111111111110000,0000000000001111 +vinsdrx 2 2 => 1111111111110000,0000000000021111 +vinsdrx 2 4 => 1111111111110000,0000000000041111 +vinsdrx 2 6 => 1111111111110000,0000000000061111 +vinsdrx 2 8 => 1111111111110000,0000000000081111 +vinsdrx 2 a => 1111111111110000,00000000000a1111 vinsd 3 0 => 1111110000000000,0000001111111111 vinsd 3 2 => 1111110000000000,0000021111111111 |
|
From: Carl L. <ca...@so...> - 2021-09-07 18:36:01
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=733aba84822efe101a098446079b4798f1b51faf commit 733aba84822efe101a098446079b4798f1b51faf Author: Carl Love <ce...@us...> Date: Fri Sep 3 17:14:50 2021 +0000 Fix impossible constraint issue in P10 testcase. This reworks the modulo operation as seen in valgrind/none/tests/ppc64/test_isa_3_1_common.c: initialize_source_registers(). Due to a GCC issue (PR101882), we will try to avoid a modulo operation with both input and outputs set to a hard register. In this case, we can apply the modulo operation to the args[] array value used to initialize the ra value. https://bugs.kde.org/show_bug.cgi?id=440906 Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_1_common.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 5643be5e47..f869343326 100644 --- a/NEWS +++ b/NEWS @@ -52,6 +52,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 439590 glibc-2.34 breaks suppressions against obj:*/lib*/libc-2.*so* 440670 unhandled ppc64le-linux syscall: 252 (statfs64) and 253 (fstatfs64) 432387 s390x: z15 instructions support +440906 Fix impossible constraint issue in P10 testcase. 441512 Remove a unneeded / unnecessary prefix check. To see details of a given bug, visit diff --git a/none/tests/ppc64/test_isa_3_1_common.c b/none/tests/ppc64/test_isa_3_1_common.c index 8222a857fc..7c3dc6f009 100644 --- a/none/tests/ppc64/test_isa_3_1_common.c +++ b/none/tests/ppc64/test_isa_3_1_common.c @@ -2263,8 +2263,13 @@ void initialize_source_registers () { if (has_ra) ra = 4*vrai; if (is_insert_double) { /* For an insert_double, the results are undefined - for ra > 8, so modulo those into a valid range. */ - ra = ra % 9; + for ra > 8, so modulo those into a valid range. + Since ra is defined as a hard register, and due to gcc + issue (PR101882) where a modulo operation fails with + both input and output regs set to a hard register, this + assignment references the args[] array again, versus + ra = ra % 9;. */ + ra = args[vrai] % 9; } } |
|
From: Carl L. <ca...@so...> - 2021-09-07 18:32:13
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=041f6c19a0cd40fe684571c380399be518b8d6b2 commit 041f6c19a0cd40fe684571c380399be518b8d6b2 Author: Carl Love <ce...@us...> Date: Fri Sep 3 16:36:31 2021 +0000 Remove a unneeded / unnecessary prefix check. The pstxvp instruction is valid for R=1, i.e. use pc relative addressing. The test should have been remmoved before committing the ISA 3.1 support. https://bugs.kde.org/show_bug.cgi?id=441512 Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 6 ------ 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/NEWS b/NEWS index 66a4b8d8bc..5643be5e47 100644 --- a/NEWS +++ b/NEWS @@ -52,6 +52,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 439590 glibc-2.34 breaks suppressions against obj:*/lib*/libc-2.*so* 440670 unhandled ppc64le-linux syscall: 252 (statfs64) and 253 (fstatfs64) 432387 s390x: z15 instructions support +441512 Remove a unneeded / unnecessary prefix check. To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index f223fe9456..57ac7bcf48 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -14563,12 +14563,6 @@ static Bool dis_fp_pair_prefix ( UInt prefix, UInt theInstr ) pDIP( is_prefix, "stxvp %u,%llu(%u)\n", XTp, immediate_val, rA_addr ); DIPp( is_prefix, ",%u", R ); - if ( R == 1 ) { - vex_printf("Illegal instruction R = 1; pstxvp %u,%llu(%u)\n", - XTp, immediate_val, rA_addr ); - return False; - } - assign( EA_8, binop( Iop_Add64, mkU64( 8 ), mkexpr( EA ) ) ); assign( EA_16, binop( Iop_Add64, mkU64( 16 ), mkexpr( EA ) ) ); assign( EA_24, binop( Iop_Add64, mkU64( 24 ), mkexpr( EA ) ) ); |
|
From: Audrey D. <au...@rh...> - 2021-09-02 13:04:58
|
Hello, I'm writing to ask about the status of the development of AVX-512 support for valgrind. Last I heard, there was a partial patch available, last updated in 2018. I saw some discussion recently (in march) that implied that it was expected that patch could be merged sometime in the next few versions, but nothing to indicate that anyone was actually working on it. My personal stake in the patch is that I am using just the vex lifter for static analysis, and just having the ability to lift avx512 instructions would improve my analysis substantially. I am willing to put in some effort in getting this patch merged as long as I can have some mentorship! Please let me know what the patch's status is and whether I can help :) Thanks, - Audrey -- Audrey Dutcher she/her/hers http://rhelmot.io/ |
|
From: Andreas A. <ar...@so...> - 2021-09-01 17:01:26
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=62b7052ab529d02b5852b547bfac6c6547a944e9 commit 62b7052ab529d02b5852b547bfac6c6547a944e9 Author: Andreas Arnez <ar...@li...> Date: Mon May 17 15:34:15 2021 +0200 s390x: Vec-enh-2, test cases Add test cases for verifying the new/enhanced instructions in the vector-enhancements facility 2. For "vector string search" VSTRS add a memcheck test case. Diff: --- .gitignore | 2 + memcheck/tests/s390x/Makefile.am | 3 +- memcheck/tests/s390x/vstrs.c | 68 ++++++++ memcheck/tests/s390x/vstrs.stderr.exp | 16 ++ memcheck/tests/s390x/vstrs.stdout.exp | 0 memcheck/tests/s390x/vstrs.vgtest | 2 + none/tests/s390x/Makefile.am | 3 +- none/tests/s390x/vec2.c | 314 ++++++++++++++++++++++++++++++++++ none/tests/s390x/vec2.stderr.exp | 2 + none/tests/s390x/vec2.stdout.exp | 168 ++++++++++++++++++ none/tests/s390x/vec2.vgtest | 2 + tests/s390x_features.c | 4 + 12 files changed, 582 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index b418f52fdc..cf45901132 100644 --- a/.gitignore +++ b/.gitignore @@ -1121,6 +1121,7 @@ /memcheck/tests/s390x/vstrc /memcheck/tests/s390x/vfae /memcheck/tests/s390x/vistr +/memcheck/tests/s390x/vstrs # /memcheck/tests/solaris/ /memcheck/tests/solaris/*.stderr.diff @@ -1888,6 +1889,7 @@ /none/tests/s390x/high-word /none/tests/s390x/vector_float /none/tests/s390x/misc3 +/none/tests/s390x/vec2 # /none/tests/scripts/ /none/tests/scripts/*.dSYM diff --git a/memcheck/tests/s390x/Makefile.am b/memcheck/tests/s390x/Makefile.am index d183841ef0..668fd9933c 100644 --- a/memcheck/tests/s390x/Makefile.am +++ b/memcheck/tests/s390x/Makefile.am @@ -2,7 +2,7 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = filter_stderr -INSN_TESTS = cdsg cu21 cu42 ltgjhe vstrc vfae vistr +INSN_TESTS = cdsg cu21 cu42 ltgjhe vstrc vfae vistr vstrs check_PROGRAMS = $(INSN_TESTS) @@ -18,3 +18,4 @@ AM_CCASFLAGS += @FLAG_M64@ vstrc_CFLAGS = $(AM_CFLAGS) -march=z13 vfae_CFLAGS = $(AM_CFLAGS) -march=z13 vistr_CFLAGS = $(AM_CFLAGS) -march=z13 +vstrs_CFLAGS = $(AM_CFLAGS) -march=z13 diff --git a/memcheck/tests/s390x/vstrs.c b/memcheck/tests/s390x/vstrs.c new file mode 100644 index 0000000000..3354c2e538 --- /dev/null +++ b/memcheck/tests/s390x/vstrs.c @@ -0,0 +1,68 @@ +#include <stdio.h> +#include <string.h> + +#define VECTOR __attribute__ ((vector_size (16))) + +typedef char VECTOR char_v; + +volatile char tmp; +static const char *hex_digit = "0123456789abcdefGHIJKLMNOPQRSTUV"; + +static char_v to_char_vec(const char *str) +{ + char buf[17]; + char_v v; + + for (int i = 0; i < sizeof(buf); i++) { + char ch = str[i]; + if (ch == '\0') + break; + else if (ch == '$') + buf[i] = '\0'; + else if (ch != '~') + buf[i] = ch; + } + v = *(char_v *) buf; + return v; +} + +static void test_vstrs_char(const char *haystack, const char *needle, + int expect_res, int expect_cc) +{ + int cc; + char_v v2val = to_char_vec(haystack); + char_v v3val = to_char_vec(needle); + + register unsigned long VECTOR v4 __asm__("v4") = { strlen(needle), 0 }; + register char_v v1 __asm__("v1"); + register char_v v2 __asm__("v2") = v2val; + register char_v v3 __asm__("v3") = v3val; + + __asm__( + "cr 0,0\n\t" /* Clear CC */ + ".short 0xe712,0x3020,0x408b\n\t" /* vstrs %v1,%v2,%v3,%v4,0,2 */ + "ipm %[cc]\n\t" + "srl %[cc],28" + : "=v" (v1), [cc] "=d" (cc) + : "v" (v2), "v" (v3), "v" (v4) + : "cc"); + + tmp = hex_digit[v1[7] & 0x1f]; + if (expect_res >= 0 && v1[7] != expect_res) + printf("result %u != %d\n", v1[7], expect_res); + + tmp = hex_digit[cc & 0xf]; + if (expect_cc >= 0 && cc != expect_cc) + printf("CC %d != %d\n", cc, expect_cc); +} + +int main() +{ + test_vstrs_char("haystack$needle", "needle$haystack", 16, 1); + test_vstrs_char("haystack, needle", "needle, haystack", 10, 3); + test_vstrs_char("ABCDEFGH", "DEFGHI", -1, -1); + test_vstrs_char("match in UNDEF", "UN", 9, 2); + test_vstrs_char("after ~ UNDEF", "DEF", -1, -1); + test_vstrs_char("", "", 0, 2); + return 0; +} diff --git a/memcheck/tests/s390x/vstrs.stderr.exp b/memcheck/tests/s390x/vstrs.stderr.exp new file mode 100644 index 0000000000..c5c3ef705c --- /dev/null +++ b/memcheck/tests/s390x/vstrs.stderr.exp @@ -0,0 +1,16 @@ +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:50) + by 0x........: main (vstrs.c:63) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:54) + by 0x........: main (vstrs.c:63) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:50) + by 0x........: main (vstrs.c:65) + +Use of uninitialised value of size 8 + at 0x........: test_vstrs_char (vstrs.c:54) + by 0x........: main (vstrs.c:65) + diff --git a/memcheck/tests/s390x/vstrs.stdout.exp b/memcheck/tests/s390x/vstrs.stdout.exp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/memcheck/tests/s390x/vstrs.vgtest b/memcheck/tests/s390x/vstrs.vgtest new file mode 100644 index 0000000000..fd2a298739 --- /dev/null +++ b/memcheck/tests/s390x/vstrs.vgtest @@ -0,0 +1,2 @@ +prog: vstrs +vgopts: -q diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index 2fd45ec1e8..ca38db935c 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -20,7 +20,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \ spechelper-icm-1 spechelper-icm-2 spechelper-tmll \ spechelper-tm laa vector lsc2 ppno vector_string vector_integer \ vector_float add-z14 sub-z14 mul-z14 bic \ - misc3 + misc3 vec2 if BUILD_DFP_TESTS INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo @@ -74,3 +74,4 @@ lsc2_CFLAGS = -march=z13 -DS390_TESTS_NOCOLOR vector_string_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=5 vector_integer_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 vector_float_CFLAGS = $(AM_CFLAGS) -march=z13 -DS390_TEST_COUNT=4 +vec2_CFLAGS = $(AM_CFLAGS) -march=z13 diff --git a/none/tests/s390x/vec2.c b/none/tests/s390x/vec2.c new file mode 100644 index 0000000000..73b04dee49 --- /dev/null +++ b/none/tests/s390x/vec2.c @@ -0,0 +1,314 @@ +#include <stdio.h> + +#define VECTOR __attribute__ ((vector_size (16))) + +typedef unsigned long VECTOR ulong_v; +typedef float VECTOR float_v; + +static const ulong_v vec_a = { 0x0123456789abcdef, 0xfedcba9876543210 }; +static const ulong_v vec_b = { 0xfedcba9876543210, 0x0123456789abcdef }; +static const ulong_v vec_c = { 0x8040201008040201, 0x7fbfdfeff7fbfdfe }; +static const ulong_v vec_one = { -1, -1 }; +static const ulong_v vec_ini = { 0x0112233445566778, 0x899aabbccddeeff0 }; + +static const float_v vec_fa = { 16777215., -16777215., 42.5, 10000. }; +static const float_v vec_fb = { 4., 3., 2., 1. }; + +/* -- Vector shift -- */ + +#define TEST_GENERATE(insn) \ + static void test_##insn(ulong_v a, ulong_v b) \ + { \ + ulong_v out; \ + __asm__( \ + #insn " %[out],%[a],%[b]" \ + : [out] "=v" (out) \ + : [a] "v" (a), \ + [b] "v" (b) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define TEST_EXEC(insn) \ + do { \ + puts(#insn); \ + test_##insn(vec_a, vec_b); \ + test_##insn(vec_b, vec_a); \ + test_##insn(vec_c, vec_a); \ + test_##insn(vec_one, vec_b); \ + } while (0) + +#define INSNS \ + XTEST(vsl); \ + XTEST(vsrl); \ + XTEST(vsra); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_single_bitshifts() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector load element-/byte-swapped -- */ + +#define TEST_EXEC(opc1,opc2,insn,m3) \ + do { \ + puts(#insn " " #m3); \ + test_##insn##_##m3(vec_a); \ + test_##insn##_##m3(vec_b); \ + } while (0) + +#define TEST_GENERATE(opc1,opc2,insn,m3) \ + static void test_##insn##_##m3(ulong_v a) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrx,0x" #opc1 "00000000" #opc2 ",%[out],%[a]," #m3 \ + : [out] "+v" (out) \ + : [a] "R" (a) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define INSNS \ + XTEST(e6,01, vlebrh, 0); \ + XTEST(e6,01, vlebrh, 7); \ + XTEST(e6,01, vlebrh, 2); \ + XTEST(e6,03, vlebrf, 0); \ + XTEST(e6,03, vlebrf, 3); \ + XTEST(e6,03, vlebrf, 1); \ + XTEST(e6,02, vlebrg, 0); \ + XTEST(e6,02, vlebrg, 1); \ + XTEST(e6,04, vllebrz, 1); \ + XTEST(e6,04, vllebrz, 2); \ + XTEST(e6,04, vllebrz, 3); \ + XTEST(e6,04, vllebrz, 6); \ + XTEST(e6,05, vlbrrep, 1); \ + XTEST(e6,05, vlbrrep, 2); \ + XTEST(e6,05, vlbrrep, 3); \ + XTEST(e6,06, vlbr, 1); \ + XTEST(e6,06, vlbr, 2); \ + XTEST(e6,06, vlbr, 3); \ + XTEST(e6,06, vlbr, 4); \ + XTEST(e6,07, vler, 1); \ + XTEST(e6,07, vler, 2); \ + XTEST(e6,07, vler, 3); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_swapped_loads() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_GENERATE + +/* -- Vector store element-/byte-swapped -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m3) \ + static void test_##insn##_##m3(ulong_v a) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrx,0x" #opc1 "00000000" #opc2 ",%[a],%[out]," #m3 \ + : [out] "+R" (out) \ + : [a] "v" (a) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define INSNS \ + XTEST(e6,09, vstebrh, 0); \ + XTEST(e6,09, vstebrh, 7); \ + XTEST(e6,09, vstebrh, 2); \ + XTEST(e6,0b, vstebrf, 0); \ + XTEST(e6,0b, vstebrf, 3); \ + XTEST(e6,0b, vstebrf, 1); \ + XTEST(e6,0a, vstebrg, 0); \ + XTEST(e6,0a, vstebrg, 1); \ + XTEST(e6,0e, vstbr, 1); \ + XTEST(e6,0e, vstbr, 2); \ + XTEST(e6,0e, vstbr, 3); \ + XTEST(e6,0e, vstbr, 4); \ + XTEST(e6,0f, vster, 1); \ + XTEST(e6,0f, vster, 2); \ + XTEST(e6,0f, vster, 3); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_swapped_stores() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector shift double by bit -- */ + +#define TEST_GENERATE(opc1,opc2,insn,i4) \ + static void test_##insn##_##i4(ulong_v a, ulong_v b) \ + { \ + ulong_v out = vec_ini; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],%[b],0," #i4 ",0" \ + : [out] "+v" (out) \ + : [a] "v" (a), \ + [b] "v" (b) \ + : ); \ + printf("\t%016lx %016lx\n", out[0], out[1]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,i4) \ + do { \ + puts(#insn " " #i4); \ + test_##insn##_##i4(vec_a, vec_one); \ + test_##insn##_##i4(vec_b, vec_a); \ + } while (0) + +#define INSNS \ + XTEST(e7,86,vsld,0); \ + XTEST(e7,86,vsld,7); \ + XTEST(e7,86,vsld,4); \ + XTEST(e7,87,vsrd,0); \ + XTEST(e7,87,vsrd,7); \ + XTEST(e7,87,vsrd,4); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_double_bitshifts() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector integer -> FP conversions -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m4) \ + static void test_##insn##_##m4(ulong_v a) \ + { \ + float_v out; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],0,2," #m4 ",0" \ + : [out] "=v" (out) \ + : [a] "v" (a) \ + : ); \ + if (m4 & 8) \ + printf("\t%a - - -\n", out[0]); \ + else \ + printf("\t%a %a %a %a\n", out[0], out[1], out[2], out[3]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,m4) \ + do { \ + puts(#insn " " #m4); \ + test_##insn##_##m4(vec_a); \ + test_##insn##_##m4(vec_c); \ + } while (0) + +#define INSNS \ + XTEST(e7,c1,vcfpl,0); \ + XTEST(e7,c1,vcfpl,8); \ + XTEST(e7,c3,vcfps,0); \ + XTEST(e7,c3,vcfps,8); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_int_fp_conversions() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + +/* -- Vector FP -> integer conversions -- */ + +#define TEST_GENERATE(opc1,opc2,insn,m4) \ + static void test_##insn##_##m4(float_v a) \ + { \ + unsigned int VECTOR out; \ + __asm__( \ + ".insn vrr,0x" #opc1 "00000000" #opc2 \ + ",%[out],%[a],0,2," #m4 ",0" \ + : [out] "=v" (out) \ + : [a] "v" (a) \ + : ); \ + if (m4 & 8) \ + printf("\t%08x - - -\n", out[0]); \ + else \ + printf("\t%08x %08x %08x %08x\n", \ + out[0], out[1], out[2], out[3]); \ + } + +#define TEST_EXEC(opc1,opc2,insn,m4) \ + do { \ + puts(#insn " " #m4); \ + test_##insn##_##m4(vec_fa); \ + test_##insn##_##m4(vec_fb); \ + } while (0) + +#define INSNS \ + XTEST(e7,c0,vclfp,0); \ + XTEST(e7,c0,vclfp,8); \ + XTEST(e7,c2,vcsfp,0); \ + XTEST(e7,c2,vcsfp,8); + +#define XTEST TEST_GENERATE +INSNS +#undef XTEST + +static void test_all_fp_int_conversions() +{ +#define XTEST TEST_EXEC + INSNS +#undef XTEST +} + +#undef INSNS +#undef TEST_EXEC +#undef TEST_GENERATE + + +int main() +{ + test_all_single_bitshifts(); + test_all_swapped_loads(); + test_all_swapped_stores(); + test_all_double_bitshifts(); + test_all_int_fp_conversions(); + test_all_fp_int_conversions(); + return 0; +} diff --git a/none/tests/s390x/vec2.stderr.exp b/none/tests/s390x/vec2.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/s390x/vec2.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/vec2.stdout.exp b/none/tests/s390x/vec2.stdout.exp new file mode 100644 index 0000000000..b32cbe1bc0 --- /dev/null +++ b/none/tests/s390x/vec2.stdout.exp @@ -0,0 +1,168 @@ +vsl + 483415676abc37ef fde5533beca14200 + fde5533beca14200 483415676abc37ef + 00010204102040bf effd7feffebff7fe + ffffffffffffffff ffffffffffffff80 +vsrl + 0012d1679e9af3ef ffdbe5753bcaa164 + 7fdbe5753bcaa164 4012d1679e9af3ef + 4008014004002004 05fbf7efbf7ffffe + 03ffffffffffffff ffffffffffffffff +vsra + 0012d1679e9af3ef ffdbe5753bcaa164 + ffdbe5753bcaa164 4012d1679e9af3ef + c008014004002004 05fbf7efbf7ffffe + ffffffffffffffff ffffffffffffffff +vlebrh 0 + 2301233445566778 899aabbccddeeff0 + dcfe233445566778 899aabbccddeeff0 +vlebrh 7 + 0112233445566778 899aabbccdde2301 + 0112233445566778 899aabbccddedcfe +vlebrh 2 + 0112233423016778 899aabbccddeeff0 + 01122334dcfe6778 899aabbccddeeff0 +vlebrf 0 + 6745230145566778 899aabbccddeeff0 + 98badcfe45566778 899aabbccddeeff0 +vlebrf 3 + 0112233445566778 899aabbc67452301 + 0112233445566778 899aabbc98badcfe +vlebrf 1 + 0112233467452301 899aabbccddeeff0 + 0112233498badcfe 899aabbccddeeff0 +vlebrg 0 + efcdab8967452301 899aabbccddeeff0 + 1032547698badcfe 899aabbccddeeff0 +vlebrg 1 + 0112233445566778 efcdab8967452301 + 0112233445566778 1032547698badcfe +vllebrz 1 + 0000000000002301 0000000000000000 + 000000000000dcfe 0000000000000000 +vllebrz 2 + 0000000067452301 0000000000000000 + 0000000098badcfe 0000000000000000 +vllebrz 3 + efcdab8967452301 0000000000000000 + 1032547698badcfe 0000000000000000 +vllebrz 6 + 6745230100000000 0000000000000000 + 98badcfe00000000 0000000000000000 +vlbrrep 1 + 2301230123012301 2301230123012301 + dcfedcfedcfedcfe dcfedcfedcfedcfe +vlbrrep 2 + 6745230167452301 6745230167452301 + 98badcfe98badcfe 98badcfe98badcfe +vlbrrep 3 + efcdab8967452301 efcdab8967452301 + 1032547698badcfe 1032547698badcfe +vlbr 1 + 23016745ab89efcd dcfe98ba54761032 + dcfe98ba54761032 23016745ab89efcd +vlbr 2 + 67452301efcdab89 98badcfe10325476 + 98badcfe10325476 67452301efcdab89 +vlbr 3 + efcdab8967452301 1032547698badcfe + 1032547698badcfe efcdab8967452301 +vlbr 4 + 1032547698badcfe efcdab8967452301 + efcdab8967452301 1032547698badcfe +vler 1 + 32107654ba98fedc cdef89ab45670123 + cdef89ab45670123 32107654ba98fedc +vler 2 + 76543210fedcba98 89abcdef01234567 + 89abcdef01234567 76543210fedcba98 +vler 3 + fedcba9876543210 0123456789abcdef + 0123456789abcdef fedcba9876543210 +vstebrh 0 + 2301233445566778 899aabbccddeeff0 + dcfe233445566778 899aabbccddeeff0 +vstebrh 7 + 1032233445566778 899aabbccddeeff0 + efcd233445566778 899aabbccddeeff0 +vstebrh 2 + ab89233445566778 899aabbccddeeff0 + 5476233445566778 899aabbccddeeff0 +vstebrf 0 + 6745230145566778 899aabbccddeeff0 + 98badcfe45566778 899aabbccddeeff0 +vstebrf 3 + 1032547645566778 899aabbccddeeff0 + efcdab8945566778 899aabbccddeeff0 +vstebrf 1 + efcdab8945566778 899aabbccddeeff0 + 1032547645566778 899aabbccddeeff0 +vstebrg 0 + efcdab8967452301 899aabbccddeeff0 + 1032547698badcfe 899aabbccddeeff0 +vstebrg 1 + 1032547698badcfe 899aabbccddeeff0 + efcdab8967452301 899aabbccddeeff0 +vstbr 1 + 23016745ab89efcd dcfe98ba54761032 + dcfe98ba54761032 23016745ab89efcd +vstbr 2 + 67452301efcdab89 98badcfe10325476 + 98badcfe10325476 67452301efcdab89 +vstbr 3 + efcdab8967452301 1032547698badcfe + 1032547698badcfe efcdab8967452301 +vstbr 4 + 1032547698badcfe efcdab8967452301 + efcdab8967452301 1032547698badcfe +vster 1 + 32107654ba98fedc cdef89ab45670123 + cdef89ab45670123 32107654ba98fedc +vster 2 + 76543210fedcba98 89abcdef01234567 + 89abcdef01234567 76543210fedcba98 +vster 3 + fedcba9876543210 0123456789abcdef + 0123456789abcdef fedcba9876543210 +vsld 0 + 0123456789abcdef fedcba9876543210 + fedcba9876543210 0123456789abcdef +vsld 7 + 91a2b3c4d5e6f7ff 6e5d4c3b2a19087f + 6e5d4c3b2a190800 91a2b3c4d5e6f780 +vsld 4 + 123456789abcdeff edcba9876543210f + edcba98765432100 123456789abcdef0 +vsrd 0 + ffffffffffffffff ffffffffffffffff + 0123456789abcdef fedcba9876543210 +vsrd 7 + 21ffffffffffffff ffffffffffffffff + de02468acf13579b dffdb97530eca864 +vsrd 4 + 0fffffffffffffff ffffffffffffffff + f0123456789abcde ffedcba987654321 +vcfpl 0 + 0x1.234568p+24 0x1.13579cp+31 0x1.fdb976p+31 0x1.d950c8p+30 + 0x1.00804p+31 0x1.00804p+27 0x1.feff8p+30 0x1.eff7fcp+31 +vcfpl 8 + 0x1.234568p+24 - - - + 0x1.00804p+31 - - - +vcfps 0 + 0x1.234568p+24 -0x1.d950c8p+30 -0x1.234568p+24 0x1.d950c8p+30 + -0x1.feff8p+30 0x1.00804p+27 0x1.feff8p+30 -0x1.00804p+27 +vcfps 8 + 0x1.234568p+24 - - - + -0x1.feff8p+30 - - - +vclfp 0 + 00ffffff 00000000 0000002a 00002710 + 00000004 00000003 00000002 00000001 +vclfp 8 + 00ffffff - - - + 00000004 - - - +vcsfp 0 + 00ffffff ff000001 0000002a 00002710 + 00000004 00000003 00000002 00000001 +vcsfp 8 + 00ffffff - - - + 00000004 - - - diff --git a/none/tests/s390x/vec2.vgtest b/none/tests/s390x/vec2.vgtest new file mode 100644 index 0000000000..45e942e640 --- /dev/null +++ b/none/tests/s390x/vec2.vgtest @@ -0,0 +1,2 @@ +prog: vec2 +prereq: test -e vec2 && ../../../tests/s390x_features s390x-vx diff --git a/tests/s390x_features.c b/tests/s390x_features.c index 25b98f3a3a..e7939c4635 100644 --- a/tests/s390x_features.c +++ b/tests/s390x_features.c @@ -270,6 +270,10 @@ static int go(char *feature, char *cpu) match = facilities[0] & FAC_BIT(57); /* message security assist 5 facility */ } else if (strcmp(feature, "s390x-mi2") == 0 ) { match = facilities[0] & FAC_BIT(58); + } else if (strcmp(feature, "s390x-mi3") == 0 ) { + match = facilities[0] & FAC_BIT(61); + } else if (strcmp(feature, "s390x-vx2") == 0 ) { + match = facilities[2] & FAC_BIT(20); } else { return 2; // Unrecognised feature. } |
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From: Andreas A. <ar...@so...> - 2021-09-01 17:01:26
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1bee3ab757661f4bc161218272b33b1541613773 commit 1bee3ab757661f4bc161218272b33b1541613773 Author: Andreas Arnez <ar...@li...> Date: Tue May 18 19:59:32 2021 +0200 s390x: Wrap up misc-insn-3 and vec-enh-2 support Wrap up support for the miscellaneous-instruction-extensions facility 3 and the vector-enhancements facility 2: Add 'case' statements for the remaining unhandled arch13 instructions to 'guest_s390_toIR.c', document the new support in 's390-opcodes.csv', adjust 's390-check-opcodes.pl', and announce the new feature in 'NEWS'. Diff: --- NEWS | 5 +++ VEX/priv/guest_s390_toIR.c | 5 ++- auxprogs/s390-check-opcodes.pl | 22 ++++++++++- docs/internals/s390-opcodes.csv | 81 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 108 insertions(+), 5 deletions(-) diff --git a/NEWS b/NEWS index 2fe96269fb..66a4b8d8bc 100644 --- a/NEWS +++ b/NEWS @@ -15,6 +15,10 @@ support for X86/macOS 10.13, AMD64/macOS 10.13 and nanoMIPS/Linux. * s390: + - Support the miscellaneous-instruction-extensions facility 3 and the + vector-enhancements facility 2. This enables programs compiled with + "-march=arch13" or "-march=z15" to be executed under Valgrind. + * ppc64: - ISA 3.1 support is now complete @@ -47,6 +51,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. have debug information 439590 glibc-2.34 breaks suppressions against obj:*/lib*/libc-2.*so* 440670 unhandled ppc64le-linux syscall: 252 (statfs64) and 253 (fstatfs64) +432387 s390x: z15 instructions support To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 46a867475c..1bd18f7602 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -8,7 +8,7 @@ This file is part of Valgrind, a dynamic binary instrumentation framework. - Copyright IBM Corp. 2010-2020 + Copyright IBM Corp. 2010-2021 This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as @@ -20503,6 +20503,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes) RRE_r2(ovl)); goto ok; case 0xb931: s390_format_RRE_RR(s390_irgen_CLGFR, RRE_r1(ovl), RRE_r2(ovl)); goto ok; + case 0xb938: /* SORTL */ goto unimplemented; + case 0xb939: /* DFLTCC */ goto unimplemented; + case 0xb93a: /* KDSA */ goto unimplemented; case 0xb93c: s390_format_RRE_RR(s390_irgen_PPNO, RRE_r1(ovl), RRE_r2(ovl)); goto ok; case 0xb93e: /* KIMD */ goto unimplemented; diff --git a/auxprogs/s390-check-opcodes.pl b/auxprogs/s390-check-opcodes.pl index b3c1c9bdb3..515ff9a71a 100755 --- a/auxprogs/s390-check-opcodes.pl +++ b/auxprogs/s390-check-opcodes.pl @@ -28,19 +28,32 @@ my %csv_implemented = (); my %toir_implemented = (); my %toir_decoded = (); my %known_arch = map {($_ => 1)} - qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12); + qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12 arch13); # Patterns for identifying certain extended mnemonics that shall be # skipped in "s390-opc.txt" and "s390-opcodes.csv". my @extended_mnemonics = ( "bi", # extended mnemonic for bic + 'brul?', + 'jasl?', + 'jctg?', + 'jg?nop', + 'jxleg?', + 'jxhg?', + 'l[de]rv', + 'risbgn?z', + 'st[de]rv', "va[bhfgq]", "vacc[bhfgq]", "vacccq", "vacq", "vavgl*[bhfg]", "vcdl*gb", + 'vcfp[sl]', + '[vw]cel?fb', + 'vc[sl]fp', + '[vw]cl?feb', "vceq[bhfg]s*", "vchl*[bhfg]s*", "vcl*gdb", @@ -77,10 +90,14 @@ my @extended_mnemonics = ( "vgfma*[bhfg]", "vgm[bhfg]", "vistr[bhfg]s*", + 'vlbr[hfgq]', + 'vlbrrep[hfg]', "vlc[bhfg]", "[vw]ldeb", "[vw]ledb", + 'vler[hfg]', "vlgv[bhfg]", + 'vllebrz[hfge]', "vllez[bhfg]", "vllezlf", "vlp[bhfg]", @@ -105,7 +122,10 @@ my @extended_mnemonics = ( "vsbiq", "vscbi[bhfgq]", "vseg[bfh]", + 'vstbr[hfgq]', + 'vster[hfg]', "vstrcz*[bhf]s*", + 'vstrsz?[bhf]', "vsum(b|gh|gf|h|qf|qg)", "vuplh[bhf]", "vuph[bhf]", diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv index fc7ff86bf8..cd0b4b375e 100644 --- a/docs/internals/s390-opcodes.csv +++ b/docs/internals/s390-opcodes.csv @@ -903,7 +903,7 @@ srk,"subtract 3 operands 32 bit",implemented, sgrk,"subtract 3 operands 64 bit",implemented, slrk,"subtract logical 3 operands 32 bit",implemented, slgrk,"subtract logical 3 operands 64 bit",implemented, -popcnt,"population count","implemented", +popcnt,"population count",implemented,"z196/arch13" rrbm,"reset reference bits multiple",N/A,"privileged instruction" cefbra,"convert from 32 bit fixed to short bfp with rounding mode",implemented, cdfbra,"convert from 32 bit fixed to long bfp with rounding mode",implemented, @@ -1650,8 +1650,8 @@ vstrlr,"vector store rightmost with length",implemented,arch12 vstrl,"vector store rightmost with immediate length",implemented,arch12 vap,"vector add decimal","not implemented","arch12" vcp,"vector compare decimal","not implemented","arch12" -vcvb,"vector convert to binary 32 bit","not implemented","arch12" -vcvbg,"vector convert to binary 64 bit","not implemented","arch12" +vcvb,"vector convert to binary 32 bit","not implemented","arch12/arch13" +vcvbg,"vector convert to binary 64 bit","not implemented","arch12/arch13" vcvd,"vector convert to decimal 32 bit","not implemented","arch12" vcvdg,"vector convert to decimal 64 bit","not implemented","arch12" vdp,"vector divide decimal","not implemented","arch12" @@ -1671,3 +1671,78 @@ llgfsg,"load logical and shift guarded 64 bit","not implemented","arch12" lgsc,"load guarded storage controls","not implemented","arch12" stgsc,"store guarded storage controls","not implemented","arch12" kma,"cipher message with galois counter mode","not implemented","arch12" +ncrk,"and with complement 32 bit",implemented,arch13 +ncgrk,"and with complement 64 bit",implemented,arch13 +mvcrl,"move right to left",implemented,arch13 +nnrk,"nand 32 bit",implemented,arch13 +nngrk,"nand 64 bit",implemented,arch13 +nork,"nor 32 bit",implemented,arch13 +nogrk,"nor 64 bit",implemented,arch13 +nxrk,"not exclusive or 32 bit",implemented,arch13 +nxgrk,"not exclusive or 64 bit",implemented,arch13 +ocrk,"or with complement 32 bit",implemented,arch13 +ocgrk,"or with complement 64 bit",implemented,arch13 +selr,"select 32 bit",implemented,arch13 +selgr,"select 64 bit",implemented,arch13 +selfhr,"select high",implemented,arch13 +vlbr,"vector load byte reversed elements",implemented,arch13 +vlbrh,"vector load byte reversed halfword elements",implemented,arch13 +vlbrf,"vector load byte reversed word elements",implemented,arch13 +vlbrg,"vector load byte reversed doubleword elements",implemented,arch13 +vlbrq,"vector load byte reversed quadword elements",implemented,arch13 +vler,"vector load elements reversed",implemented,arch13 +vlerh,"vector load halfword elements reversed",implemented,arch13 +vlerf,"vector load word elements reversed",implemented,arch13 +vlerg,"vector load doubleword elements reversed",implemented,arch13 +vllebrz,"vector load byte reversed element and zero",implemented,arch13 +vllebrzh,"vector load byte reversed halfword element and zero",implemented,arch13 +vllebrzf,"vector load byte reversed word element and zero",implemented,arch13 +ldrv,"load byte reversed doubleword",implemented,arch13 +vllebrzg,"vector load byte reversed doubleword element and zero",implemented,arch13 +lerv,"load byte reversed word",implemented,arch13 +vllebrze,"vector load byte reversed word element left-aligned and zero",implemented,arch13 +vlebrh,"vector load byte reversed halfword element",implemented,arch13 +vlebrf,"vector load byte reversed word element",implemented,arch13 +vlebrg,"vector load byte reversed doubleword element",implemented,arch13 +vlbrrep,"vector load byte reversed element and replicate",implemented,arch13 +vlbrreph,"vector load byte reversed halfword element and replicate",implemented,arch13 +vlbrrepf,"vector load byte reversed word element and replicate",implemented,arch13 +vlbrrepg,"vector load byte reversed doubleword element and replicate",implemented,arch13 +vstbr,"vector store byte reversed elements",implemented,arch13 +vstbrh,"vector store byte reversed halfword elements",implemented,arch13 +vstbrf,"vector store byte reversed word elements",implemented,arch13 +vstbrg,"vector store byte reversed doubleword elements",implemented,arch13 +vstbrq,"vector store byte reversed quadword elements",implemented,arch13 +vster,"vector store elements reversed",implemented,arch13 +vsterh,"vector store halfword elements reversed",implemented,arch13 +vsterf,"vector store word elements reversed",implemented,arch13 +vsterg,"vector store doubleword elements reversed",implemented,arch13 +vstebrh,"vector store byte reversed halfword element",implemented,arch13 +vstebrf,"vector store byte reversed word element",implemented,arch13 +sterv,"store byte reversed word",implemented,arch13 +vstebrg,"vector store byte reversed doubleword element",implemented,arch13 +stdrv,"store byte reversed doubleword",implemented,arch13 +vsld,"vector shift left double by bit",implemented,arch13 +vsrd,"vector shift right double by bit",implemented,arch13 +vstrs,"vector string search",implemented,arch13 +vstrsb,"vector string search byte",implemented,arch13 +vstrsh,"vector string search halfword",implemented,arch13 +vstrsf,"vector string search word",implemented,arch13 +vstrszb,"vector string search byte zero",implemented,arch13 +vstrszh,"vector string search halfword zero",implemented,arch13 +vstrszf,"vector string search word zero",implemented,arch13 +vcfps,"vector fp convert from fixed",implemented,arch13 +vcefb,"vector fp convert from fixed 32 bit",implemented,arch13 +wcefb,"vector fp convert from fixed 32 bit",implemented,arch13 +vcfpl,"vector fp convert from logical",implemented,arch13 +vcelfb,"vector fp convert from logical 32 bit",implemented,arch13 +wcelfb,"vector fp convert from logical 32 bit",implemented,arch13 +vcsfp,"vector fp convert to fixed",implemented,arch13 +vcfeb,"vector fp convert to fixed 32 bit",implemented,arch13 +wcfeb,"vector fp convert to fixed 32 bit",implemented,arch13 +vclfp,"vector fp convert to logical",implemented,arch13 +vclfeb,"vector fp convert to logical 32 bit",implemented,arch13 +wclfeb,"vector fp convert to logical 32 bit",implemented,arch13 +dfltcc,"deflate conversion call","not implemented",arch13 +sortl,"sort lists","not implemented",arch13 +kdsa,"compute digital signature authentication","not implemented",arch13 |
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From: Andreas A. <ar...@so...> - 2021-09-01 17:01:11
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=565bae9c7036e11af7d45ef3b0b18e9c616ebfe6 commit 565bae9c7036e11af7d45ef3b0b18e9c616ebfe6 Author: Andreas Arnez <ar...@li...> Date: Tue Feb 16 17:52:09 2021 +0100 s390x: Mark arch13 features as supported Make the STFLE instruction report the miscellaneous-instruction-extensions facility 3 and the vector-enhancements facility 2 as supported. Indicate support for the latter in the HWCAP vector as well. Diff: --- VEX/priv/guest_s390_helpers.c | 9 +++------ coregrind/m_initimg/initimg-linux.c | 3 ++- include/vki/vki-s390x-linux.h | 1 + 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c index 1e04f601a8..804b92a296 100644 --- a/VEX/priv/guest_s390_helpers.c +++ b/VEX/priv/guest_s390_helpers.c @@ -356,9 +356,7 @@ s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, ULong *addr) | s390_stfle_range(51, 55) /* 56: unassigned */ /* 57: MSA5, not supported */ - | s390_stfle_range(58, 60) - /* 61: miscellaneous-instruction 3, not supported */ - | s390_stfle_range(62, 63)), + | s390_stfle_range(58, 63)), /* === 64 .. 127 === */ (s390_stfle_range(64, 72) @@ -384,11 +382,10 @@ s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, ULong *addr) /* 143: unassigned */ | s390_stfle_range(144, 145) /* 146: MSA8, not supported */ - | s390_stfle_range(147, 147) - /* 148: vector-enhancements 2, not supported */ - | s390_stfle_range(149, 149) + | s390_stfle_range(147, 149) /* 150: unassigned */ /* 151: DEFLATE-conversion, not supported */ + /* 152: vector packed decimal enhancement, not supported */ /* 153: unassigned */ /* 154: unassigned */ /* 155: MSA9, not supported */ diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c index 73c580333e..7d02d55678 100644 --- a/coregrind/m_initimg/initimg-linux.c +++ b/coregrind/m_initimg/initimg-linux.c @@ -703,7 +703,8 @@ Addr setup_client_stack( void* init_sp, itself, is not supported by Valgrind. */ auxv->u.a_val &= ((VKI_HWCAP_S390_TE - 1) | VKI_HWCAP_S390_VXRS - | VKI_HWCAP_S390_VXRS_EXT); + | VKI_HWCAP_S390_VXRS_EXT + | VKI_HWCAP_S390_VXRS_EXT2); } # elif defined(VGP_arm64_linux) { diff --git a/include/vki/vki-s390x-linux.h b/include/vki/vki-s390x-linux.h index 4ab2d3334e..71b363029c 100644 --- a/include/vki/vki-s390x-linux.h +++ b/include/vki/vki-s390x-linux.h @@ -807,6 +807,7 @@ typedef vki_s390_regs vki_elf_gregset_t; #define VKI_HWCAP_S390_TE 1024 #define VKI_HWCAP_S390_VXRS 2048 #define VKI_HWCAP_S390_VXRS_EXT 8192 +#define VKI_HWCAP_S390_VXRS_EXT2 32768 //---------------------------------------------------------------------- |
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From: Andreas A. <ar...@so...> - 2021-09-01 17:01:07
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c0751ea89c758ef674f5c520155d23ba8e79ddba commit c0751ea89c758ef674f5c520155d23ba8e79ddba Author: Andreas Arnez <ar...@li...> Date: Wed Mar 10 19:22:51 2021 +0100 s390x: Vec-enh-2, VSTRS Support the new "vector string search" instruction VSTRS. The implementation is a full emulation and follows a similar approach as for the other vector string instructions. Diff: --- VEX/priv/guest_s390_toIR.c | 104 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index aa429d0853..46a867475c 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -17601,6 +17601,105 @@ s390_irgen_VSTRC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) return "vstrc"; } +static const HChar * +s390_irgen_VSTRS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) +{ + s390_insn_assert("vstrs", m5 <= 2 && m6 == (m6 & 2)); + + IRTemp op2 = newTemp(Ity_V128); + IRTemp op3 = newTemp(Ity_V128); + IRTemp op4 = newTemp(Ity_I8); + IRTemp op2clean = newTemp(Ity_V128); + IRTemp op3mask = newTemp(Ity_V128); + IRTemp result = newTemp(Ity_V128); + IRTemp ccnomatch = newTemp(Ity_I64); + IRExpr* tmp; + IRExpr* match = NULL; + UChar elem_bits = 8 << m5; + IROp cmpeq_op = S390_VEC_OP3(m5, Iop_CmpEQ8x16, + Iop_CmpEQ16x8, Iop_CmpEQ32x4); + + assign(op2, get_vr_qw(v2)); + assign(op3, get_vr_qw(v3)); + assign(op4, get_vr_b7(v4)); + + tmp = unop(Iop_Dup32x4, + unop(Iop_1Sto32, binop(Iop_CmpNE8, mkexpr(op4), mkU8(16)))); + tmp = binop(Iop_ShrV128, tmp, binop(Iop_Shl8, mkexpr(op4), mkU8(3))); + + if (s390_vr_is_zs_set(m6)) { + IRTemp op2eos = newTemp(Ity_V128); + IRExpr* t; + t = binop(cmpeq_op, mkexpr(op2), mkV128(0)); + for (UChar i = m5; i < 4; i++) { + IRTemp s = newTemp(Ity_V128); + assign(s, t); + t = binop(Iop_OrV128, mkexpr(s), binop(Iop_ShrV128, mkexpr(s), + mkU8(8 << i))); + } + assign(op2eos, t); + assign(op2clean, binop(Iop_AndV128, mkexpr(op2), + unop(Iop_NotV128, mkexpr(op2eos)))); + assign(ccnomatch, binop(Iop_And64, mkU64(1), + unop(Iop_V128to64, mkexpr(op2eos)))); + + t = binop(cmpeq_op, mkexpr(op3), mkV128(0)); + for (UChar i = m5; i < 4; i++) { + IRTemp s = newTemp(Ity_V128); + assign(s, t); + t = binop(Iop_OrV128, mkexpr(s), binop(Iop_ShrV128, mkexpr(s), + mkU8(8 << i))); + } + tmp = binop(Iop_OrV128, tmp, t); + } else { + assign(op2clean, mkexpr(op2)); + } + assign(op3mask, unop(Iop_NotV128, tmp)); + + for (UChar shift = 0; shift < 128; shift += elem_bits) { + IRTemp s = newTemp(Ity_V128); + tmp = unop(Iop_NotV128, + binop(cmpeq_op, mkexpr(op2clean), + binop(Iop_ShrV128, mkexpr(op3), mkU8(shift)))); + assign(s, binop(Iop_CmpEQ64x2, mkV128(0), + binop(Iop_AndV128, mkexpr(op3mask), + binop(Iop_ShlV128, tmp, mkU8(shift))))); + tmp = mkexpr(s); + if (shift < 64) { + tmp = binop(Iop_AndV128, tmp, + unop(Iop_Dup16x8, binop(Iop_GetElem16x8, tmp, mkU8(4)))); + } + tmp = binop(Iop_AndV128, tmp, + unop(Iop_Dup16x8, mkU16(1 << (15 - shift / 8)))); + if (shift) + match = binop(Iop_OrV128, mkexpr(mktemp(Ity_V128, match)), tmp); + else + match = tmp; + } + assign(result, unop(Iop_ClzNat64, + binop(Iop_Or64, + unop(Iop_V128HIto64, match), + mkU64((1UL << 48) - 1)))); + put_vr_qw(v1, binop(Iop_64HLtoV128, mkexpr(result), mkU64(0))); + + /* Set condition code. + 0: no match, no string terminator in op2 + 1: no match, string terminator found + 2: full match + 3: partial match */ + IRTemp cc = newTemp(Ity_I64); + tmp = binop(Iop_CmpLE64U, + binop(Iop_Add64, mkexpr(result), unop(Iop_8Uto64, mkexpr(op4))), + mkU64(16)); + assign(cc, mkite(binop(Iop_CmpEQ64, mkexpr(result), mkU64(16)), + s390_vr_is_zs_set(m6) ? mkexpr(ccnomatch) : mkU64(0), + mkite(tmp, mkU64(2), mkU64(3)))); + s390_cc_set(cc); + + dis_res->hint = Dis_HintVerbose; + return "vstrs"; +} + static const HChar * s390_irgen_VNC(UChar v1, UChar v2, UChar v3) { @@ -21596,6 +21695,11 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRRd_v4(ovl), VRRd_m5(ovl), VRRd_m6(ovl), VRRd_rxb(ovl)); goto ok; + case 0xe7000000008bULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRS, VRRd_v1(ovl), + VRRd_v2(ovl), VRRd_v3(ovl), + VRRd_v4(ovl), VRRd_m5(ovl), + VRRd_m6(ovl), + VRRd_rxb(ovl)); goto ok; case 0xe7000000008cULL: s390_format_VRR_VVVV(s390_irgen_VPERM, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), VRR_m4(ovl), VRR_rxb(ovl)); goto ok; |
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From: Andreas A. <ar...@so...> - 2021-09-01 17:01:01
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=45009a53f75ccb716d0188522791188960c1e2fb commit 45009a53f75ccb716d0188522791188960c1e2fb Author: Andreas Arnez <ar...@li...> Date: Tue Feb 23 19:10:37 2021 +0100 s390x: Vec-enh-2, VSLD and VSRD Support the new "vector shift left/right double by bit" instructions VSLD and VSRD. Diff: --- VEX/priv/guest_s390_toIR.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index f65b42705b..aa429d0853 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -18228,6 +18228,48 @@ s390_irgen_VSLDB(UChar v1, UChar v2, UChar v3, UChar i4) return "vsldb"; } +static const HChar * +s390_irgen_VSLD(UChar v1, UChar v2, UChar v3, UChar i4) +{ + s390_insn_assert("vsld", i4 <= 7); + + if (i4 == 0) { + /* Just copy v2. */ + put_vr_qw(v1, get_vr_qw(v2)); + } else { + /* Concatenate v2's tail with v3's head. */ + put_vr_qw(v1, + binop(Iop_OrV128, + binop(Iop_ShlV128, get_vr_qw(v2), mkU8(i4)), + binop(Iop_ShrV128, get_vr_qw(v3), mkU8(128 - i4)) + ) + ); + } + + return "vsld"; +} + +static const HChar * +s390_irgen_VSRD(UChar v1, UChar v2, UChar v3, UChar i4) +{ + s390_insn_assert("vsrd", i4 <= 7); + + if (i4 == 0) { + /* Just copy v3. */ + put_vr_qw(v1, get_vr_qw(v3)); + } else { + /* Concatenate v2's tail with v3's head. */ + put_vr_qw(v1, + binop(Iop_OrV128, + binop(Iop_ShlV128, get_vr_qw(v2), mkU8(128 - i4)), + binop(Iop_ShrV128, get_vr_qw(v3), mkU8(i4)) + ) + ); + } + + return "vsrd"; +} + static const HChar * s390_irgen_VMO(UChar v1, UChar v2, UChar v3, UChar m4) { @@ -21541,6 +21583,14 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe70000000085ULL: s390_format_VRR_VVV(s390_irgen_VBPERM, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), VRR_rxb(ovl)); goto ok; + case 0xe70000000086ULL: s390_format_VRId_VVVI(s390_irgen_VSLD, VRId_v1(ovl), + VRId_v2(ovl), VRId_v3(ovl), + VRId_i4(ovl), + VRId_rxb(ovl)); goto ok; + case 0xe70000000087ULL: s390_format_VRId_VVVI(s390_irgen_VSRD, VRId_v1(ovl), + VRId_v2(ovl), VRId_v3(ovl), + VRId_i4(ovl), + VRId_rxb(ovl)); goto ok; case 0xe7000000008aULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRC, VRRd_v1(ovl), VRRd_v2(ovl), VRRd_v3(ovl), VRRd_v4(ovl), VRRd_m5(ovl), |
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From: Andreas A. <ar...@so...> - 2021-09-01 17:00:57
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8584d8f078ceee07c858a5451c39a0cc45a4abf0 commit 8584d8f078ceee07c858a5451c39a0cc45a4abf0 Author: Andreas Arnez <ar...@li...> Date: Tue Feb 16 16:19:31 2021 +0100 s390x: Vec-enh-2, VLBR and friends Add support for the new byte- and element-swapping vector load/store instructions VLEBRH, VLEBRG, VLEBRF, VLLEBRZ, VLBRREP, VLBR, VLER, VSTEBRH, VSTEBRG, VSTEBRF, VSTBR, and VSTER. Diff: --- VEX/priv/guest_s390_toIR.c | 256 +++++++++++++++++++++++++++++++++++++++++++++ VEX/priv/host_s390_isel.c | 9 ++ 2 files changed, 265 insertions(+) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 11271a1c94..f65b42705b 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -19388,6 +19388,209 @@ s390_irgen_SELFHR(UChar r3, UChar m4, UChar r1, UChar r2) return "selfhr"; } +/* Helper function that byte-swaps each element of its V128 input operand */ +static IRExpr * +s390_byteswap_elements(IRExpr* v, UChar m) +{ + static const ULong perm[4][2] = { + { 0x0100030205040706, 0x09080b0a0d0c0f0e }, /* 2-byte elements */ + { 0x0302010007060504, 0x0b0a09080f0e0d0c }, /* 4-byte elements */ + { 0x0706050403020100, 0x0f0e0d0c0b0a0908 }, /* 8-byte elements */ + { 0x0f0e0d0c0b0a0908, 0x0706050403020100 }, /* whole vector */ + }; + return binop(Iop_Perm8x16, v, binop(Iop_64HLtoV128, + mkU64(perm[m - 1][0]), + mkU64(perm[m - 1][1]))); +} + +/* Helper function that reverses the elements of its V128 input operand */ +static IRExpr * +s390_reverse_elements(IRExpr* v, UChar m) +{ + static const ULong perm[3][2] = { + { 0x0e0f0c0d0a0b0809, 0x0607040502030001 }, /* 2-byte elements */ + { 0x0c0d0e0f08090a0b, 0x0405060700010203 }, /* 4-byte elements */ + { 0x08090a0b0c0d0e0f, 0x0001020304050607 }, /* 8-byte elements */ + }; + return binop(Iop_Perm8x16, v, binop(Iop_64HLtoV128, + mkU64(perm[m - 1][0]), + mkU64(perm[m - 1][1]))); +} + +static const HChar * +s390_irgen_VLBR(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vlbr", m3 >= 1 && m3 <= 4); + put_vr_qw(v1, s390_byteswap_elements(load(Ity_V128, mkexpr(op2addr)), m3)); + return "vlbr"; +} + +static const HChar * +s390_irgen_VSTBR(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vstbr", m3 >= 1 && m3 <= 4); + store(mkexpr(op2addr), s390_byteswap_elements(get_vr_qw(v1), m3)); + return "vstbr"; +} + +static const HChar * +s390_irgen_VLER(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vler", m3 >= 1 && m3 <= 3); + put_vr_qw(v1, s390_reverse_elements(load(Ity_V128, mkexpr(op2addr)), m3)); + return "vler"; +} + +static const HChar * +s390_irgen_VSTER(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vstbr", m3 >= 1 && m3 <= 4); + store(mkexpr(op2addr), s390_reverse_elements(get_vr_qw(v1), m3)); + return "vstbr"; +} + +/* Helper function that combines its two V128 operands by replacing element 'to' + in 'a' by byte-swapped element 'from' in 'b' */ +static IRExpr * +s390_insert_byteswapped(IRExpr* a, IRExpr* b, UChar m, UChar to, UChar from) +{ + UInt elem_size = 1U << m; + UInt start = elem_size * to; + UInt end = start + elem_size - 1; + UInt offs = end + elem_size * from + 16; + UInt i; + + ULong permH = 0; + for (i = 0; i < 8; i++) { + permH = (permH << 8) | (i >= start && i <= end ? offs - i : i); + } + ULong permL = 0; + for (i = 8; i < 16; i++) { + permL = (permL << 8) | (i >= start && i <= end ? offs - i : i); + } + return triop(Iop_Perm8x16x2, a, b, binop(Iop_64HLtoV128, + mkU64(permH), mkU64(permL))); +} + +static const HChar * +s390_irgen_VLEBRH(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vlebrh", m3 <= 7); + IRTemp op2 = newTemp(Ity_I16); + assign(op2, load(Ity_I16, mkexpr(op2addr))); + put_vr(v1, Ity_I16, m3, binop(Iop_Or16, + binop(Iop_Shl16, mkexpr(op2), mkU8(8)), + binop(Iop_Shr16, mkexpr(op2), mkU8(8)))); + return "vlebrh"; +} + +static const HChar * +s390_irgen_VLEBRF(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vlebrf", m3 <= 3); + IRTemp op1 = newTemp(Ity_V128); + assign(op1, get_vr_qw(v1)); + IRTemp op2 = newTemp(Ity_I64); + assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr)))); + IRExpr* b = binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)); + put_vr_qw(v1, s390_insert_byteswapped(mkexpr(op1), b, 2, m3, 3)); + return "vlebrf"; +} + +static const HChar * +s390_irgen_VLEBRG(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vlebrg", m3 <= 1); + IRTemp op1 = newTemp(Ity_V128); + assign(op1, get_vr_qw(v1)); + IRTemp op2 = newTemp(Ity_I64); + assign(op2, load(Ity_I64, mkexpr(op2addr))); + IRExpr* b = binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)); + put_vr_qw(v1, s390_insert_byteswapped(mkexpr(op1), b, 3, m3, 1)); + return "vlebrg"; +} + +static const HChar * +s390_irgen_VLBRREP(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vlbrrep", m3 >= 1 && m3 <= 3); + static const ULong perm[3] = { + 0x0f0e0f0e0f0e0f0e, /* 2-byte element */ + 0x0f0e0d0c0f0e0d0c, /* 4-byte element */ + 0x0f0e0d0c0b0a0908 /* 8-byte element */ + }; + IRExpr* permHL = mkU64(perm[m3 - 1]); + IRTemp op2 = newTemp(Ity_I64); + if (m3 == 3) + assign(op2, load(Ity_I64, mkexpr(op2addr))); + else + assign(op2, unop(m3 == 2 ? Iop_32Uto64 : Iop_16Uto64, + load(s390_vr_get_type(m3), mkexpr(op2addr)))); + put_vr_qw(v1, binop(Iop_Perm8x16, + binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)), + binop(Iop_64HLtoV128, permHL, permHL))); + return "vlbrrep"; +} + +static const HChar * +s390_irgen_VLLEBRZ(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vllebrz", (m3 >= 1 && m3 <= 3) || m3 == 6); + static const ULong perm[6] = { + 0x0000000000000f0e, /* 2-byte element */ + 0x000000000f0e0d0c, /* 4-byte element */ + 0x0f0e0d0c0b0a0908, /* 8-byte element */ + 0, /* invalid (4) */ + 0, /* invalid (5) */ + 0x0f0e0d0c00000000, /* 4-byte element, left-aligned */ + }; + IRExpr* permH = mkU64(perm[m3 - 1]); + IRTemp op2 = newTemp(Ity_I64); + if (m3 == 3) + assign(op2, load(Ity_I64, mkexpr(op2addr))); + else + assign(op2, unop((m3 & 3) == 2 ? Iop_32Uto64 : Iop_16Uto64, + load(s390_vr_get_type(m3 & 3), mkexpr(op2addr)))); + put_vr_qw(v1, binop(Iop_Perm8x16, + binop(Iop_64HLtoV128, mkU64(0), mkexpr(op2)), + binop(Iop_64HLtoV128, permH, mkU64(0)))); + return "vllebrz"; +} + +static const HChar * +s390_irgen_VSTEBRH(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vstebrh", m3 <= 7); + IRTemp op1 = newTemp(Ity_I16); + assign(op1, get_vr(v1, Ity_I16, m3)); + store(mkexpr(op2addr), binop(Iop_Or16, + binop(Iop_Shl16, mkexpr(op1), mkU8(8)), + binop(Iop_Shr16, mkexpr(op1), mkU8(8)))); + return "vstebrh"; +} + +static const HChar * +s390_irgen_VSTEBRF(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vstebrf", m3 <= 3); + IRTemp op1 = newTemp(Ity_V128); + assign(op1, get_vr_qw(v1)); + IRExpr* b = s390_insert_byteswapped(mkexpr(op1), mkexpr(op1), 2, 3, m3); + store(mkexpr(op2addr), unop(Iop_V128to32, b)); + return "vstebrf"; +} + +static const HChar * +s390_irgen_VSTEBRG(UChar v1, IRTemp op2addr, UChar m3) +{ + s390_insn_assert("vstebrg", m3 <= 1); + IRTemp op1 = newTemp(Ity_V128); + assign(op1, get_vr_qw(v1)); + IRExpr* b = s390_insert_byteswapped(mkexpr(op1), mkexpr(op1), 3, 1, m3); + store(mkexpr(op2addr), unop(Iop_V128to64, b)); + return "vstebrg"; +} + /* New insns are added here. If an insn is contingent on a facility being installed also check whether the list of supported facilities in function @@ -21003,6 +21206,59 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; + case 0xe60000000001ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRH, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000002ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRG, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000003ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRF, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000004ULL: s390_format_VRX_VRRDM(s390_irgen_VLLEBRZ, + VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000005ULL: s390_format_VRX_VRRDM(s390_irgen_VLBRREP, + VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000006ULL: s390_format_VRX_VRRDM(s390_irgen_VLBR, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000007ULL: s390_format_VRX_VRRDM(s390_irgen_VLER, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe60000000009ULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRH, + VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe6000000000aULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRG, + VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe6000000000bULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRF, + VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe6000000000eULL: s390_format_VRX_VRRDM(s390_irgen_VSTBR, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; + case 0xe6000000000fULL: s390_format_VRX_VRRDM(s390_irgen_VSTER, VRX_v1(ovl), + VRX_x2(ovl), VRX_b2(ovl), + VRX_d2(ovl), VRX_m3(ovl), + VRX_rxb(ovl)); goto ok; case 0xe60000000034ULL: /* VPKZ */ goto unimplemented; case 0xe60000000035ULL: s390_format_VSI_URDV(s390_irgen_VLRL, VSI_v1(ovl), VSI_b2(ovl), VSI_d2(ovl), diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 15ca92a6b3..f037255cb8 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -4192,6 +4192,15 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr) return dst; } + case Iop_Perm8x16: + size = 16; + reg1 = s390_isel_vec_expr(env, arg1); + reg2 = s390_isel_vec_expr(env, arg2); + + addInstr(env, s390_insn_vec_triop(size, S390_VEC_PERM, + dst, reg1, reg1, reg2)); + return dst; + case Iop_CmpEQ8x16: size = 1; vec_binop = S390_VEC_COMPARE_EQUAL; |