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From: Carl L. <ca...@so...> - 2021-02-25 17:59:17
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6daaeb0ff45af6b39f14003e392992a5ac7d51c8 commit 6daaeb0ff45af6b39f14003e392992a5ac7d51c8 Author: Carl Love <ce...@us...> Date: Wed Nov 4 12:23:53 2020 -0600 PPC64: 128-bit Binary Integer Operations, part tests. Diff: --- NEWS | 2 +- none/tests/ppc64/test_isa_3_1_VRT.c | 65 ++++ none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 525 ++++++++++++++++++++++++++- 3 files changed, 590 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 55bf58ae8a..a20f96f0c6 100644 --- a/NEWS +++ b/NEWS @@ -126,7 +126,7 @@ where XXXXXX is the bug number as listed below. 432809 VEX should support REX.W + POPF 432861 PPC modsw and modsd give incorrect results for 1 mod 12 n-i-bz helgrind: If hg_cli__realloc fails, return NULL. - +429352 PPC ISA 3.1 support is missing, part 7 Release 3.16.1 (22 June 2020) diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index 5f2e7ebd35..f5f5536d8e 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -187,6 +187,58 @@ static void test_vsraq (void) { static void test_vsrq (void) { __asm__ __volatile__ ("vsrq %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); } +static void test_dcffixqq (void) { +SET_FPSCR_ZERO; + __asm__ __volatile__ ("dcffixqq 28, %0" :: "v" (vrb) ); +GET_FPSCR(current_fpscr); +} +static void test_dctfixqq (void) { + __asm__ __volatile__ ("dctfixqq %0, 26" : "=v" (vrt) ); +} +static void test_vdivesq (void) { + __asm__ __volatile__ ("vdivesq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdiveuq (void) { + __asm__ __volatile__ ("vdiveuq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivsq (void) { + __asm__ __volatile__ ("vdivsq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivuq (void) { + __asm__ __volatile__ ("vdivuq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmodsq (void) { + __asm__ __volatile__ ("vmodsq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmoduq (void) { + __asm__ __volatile__ ("vmoduq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmsumcud (void) { + __asm__ __volatile__ ("vmsumcud %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "v" (vrc) ); +} +static void test_xscvqpsqz (void) { + __asm__ __volatile__ ("xscvqpsqz %0, %1 " : "=v" (vrt) : "v" (vrb) ); +} +static void test_xscvqpuqz (void) { + __asm__ __volatile__ ("xscvqpuqz %0, %1 " : "=v" (vrt) : "v" (vrb) ); +} +static void test_xscvsqqp (void) { +SET_FPSCR_ZERO; + __asm__ __volatile__ ("xscvsqqp %0, %1 " : "=v" (vrt) : "v" (vrb) ); +GET_FPSCR(current_fpscr); +} +static void test_xscvuqqp (void) { +SET_FPSCR_ZERO; + __asm__ __volatile__ ("xscvuqqp %0, %1 " : "=v" (vrt) : "v" (vrb) ); +GET_FPSCR(current_fpscr); +} static void test_vextdubvlx (void) { __asm__ __volatile__ ("vextdubvlx %0, %1, %2, %3" : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); @@ -385,6 +437,8 @@ static void test_xsmincqp (void) { } static test_list_t testgroup_generic[] = { + { &test_dcffixqq, "dcffixqq", "FRTp,VRB"}, /* bcs */ + { &test_dctfixqq, "dctfixqq", "VRT,FRBp"}, /* bcs */ { &test_dotted_vcmpequq, "vcmpequq.", "VRT,VRA,VRB"}, /* bcs */ { &test_dotted_vcmpgtsq, "vcmpgtsq.", "VRT,VRA,VRB"}, /* bcs */ { &test_dotted_vcmpgtuq, "vcmpgtuq.", "VRT,VRA,VRB"}, /* bcs */ @@ -401,12 +455,16 @@ static test_list_t testgroup_generic[] = { { &test_vcmpgtuq, "vcmpgtuq", "VRT,VRA,VRB"}, /* bcs */ { &test_vctzdm, "vctzdm", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivesq, "vdivesq", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesw, "vdivesw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdiveud, "vdiveud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdiveuq, "vdiveuq", "VRT,VRA,VRB"}, /* bcs */ { &test_vdiveuw, "vdiveuw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivsd, "vdivsd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivsq, "vdivsq", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivsw, "vdivsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivud, "vdivud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivuq, "vdivuq", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivuw, "vdivuw", "VRT,VRA,VRB"}, /* bcs */ { &test_vextddvlx, "vextddvlx", "VRT,VRA,VRB,RC"}, /* bcs */ { &test_vextddvrx, "vextddvrx", "VRT,VRA,VRB,RC"}, /* bcs */ @@ -436,9 +494,12 @@ static test_list_t testgroup_generic[] = { { &test_vinsw_3, "vinsw 3", "VRT,RB,UIM"}, /* bcwp */ { &test_vinsw_7, "vinsw 7", "VRT,RB,UIM"}, /* bcwp */ { &test_vmodsd, "vmodsd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmodsq, "vmodsq", "VRT,VRA,VRB"}, /* bcs */ { &test_vmodsw, "vmodsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmodud, "vmodud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmoduq, "vmoduq", "VRT,VRA,VRB"}, /* bcs */ { &test_vmoduw, "vmoduw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmsumcud, "vmsumcud", "VRT,VRA,VRB,VRC"}, /* bcs */ { &test_vmulesd, "vmulesd", "VRT,VRA,VRB"}, /* bcs */ { &test_vmuleud, "vmuleud", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhsd, "vmulhsd", "VRT,VRA,VRB"}, /* bcs */ @@ -467,6 +528,10 @@ static test_list_t testgroup_generic[] = { { &test_xscmpeqqp, "xscmpeqqp", "VRT,VRA,VRB"}, /* bcs */ { &test_xscmpgeqp, "xscmpgeqp", "VRT,VRA,VRB"}, /* bcs */ { &test_xscmpgtqp, "xscmpgtqp", "VRT,VRA,VRB"}, /* bcs */ + { &test_xscvqpsqz, "xscvqpsqz", "VRT,VRB"}, /* bcs */ + { &test_xscvqpuqz, "xscvqpuqz", "VRT,VRB"}, /* bcs */ + { &test_xscvsqqp, "xscvsqqp", "VRT,VRB"}, /* bcs */ + { &test_xscvuqqp, "xscvuqqp", "VRT,VRB"}, /* bcs */ { &test_xsmaxcqp, "xsmaxcqp", "VRT,VRA,VRB"}, /* bcs */ { &test_xsmincqp, "xsmincqp", "VRT,VRA,VRB"}, /* bcs */ { NULL, NULL }, diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 430604dab9..70e8feeb1f 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -1,3 +1,25 @@ +dcffixqq 7f800000ff800000,ff8000007f800000 => FPCC-FL -664613958433119175043064023681971 * 10^2 +dcffixqq ff8000007f800000,ff7ffffe7f7ffffe => FPCC-FL -66461411688944423124185532347989 * 10^2 +dcffixqq ff7ffffe7f7ffffe,0080000e8080000e => FPCC-FG 664615146855557174860634730633134 * 10^2 +dcffixqq 0080000e8080000e,0180055e0180077e => FPCC-FG 1993950853636931304178743957119828 * 10^3 +dcffixqq 0180055e0180077e,0000111e8000222e => FPCC-FG 347217422380172578240957306111870 * 10^0 +dcffixqq 0000111e8000222e,7ff0000000000000 => FPCC-FG 170058167107326744896308345973108 * 10^5 +dcffixqq 7ff0000000000000,fff0000000000000 => FPCC-FL -830767497365572328376195040411622 * 10^1 +dcffixqq fff0000000000000,2208400000000000 => FPCC-FG 45236588305775202510705711832996 * 10^4 +dcffixqq 2208400000000000,0000000000000009 => FPCC-FG 16847297729233377280 * 10^0 +dcffixqq 0000000000000009,ffff000180000001 => FPCC-FL -5192178162913778528032303742967 * 10^0 +dcffixqq ffff000180000001,0000000000000000 => FPCC-FG 18446462605175291905 * 10^0 +dcffixqq 0000000000000000,8000000000000000 => FPCC-FL -170141183460469231731687337158841 * 10^5 +dcffixqq 8000000000000000,7f800000ff800000 => FPCC-FG 1694765695416501938138124372817803 * 10^5 + +dctfixqq 1 * 10^0 => 0,0000000000000001 +dctfixqq - 1 * 10^2 => ffffffffffffffff,ffffffffffffff9c +dctfixqq 0 * 10^0 => 0,0000000000000000 +dctfixqq 1 * 10^-6176 => 0,0000000000000000 +dctfixqq 900000000001 * 10^6111 => 7fffffffffffffff,ffffffffffffffff +dctfixqq 9999999999999999999999999999999999 * 10^6111 => 7fffffffffffffff,ffffffffffffffff +dctfixqq 1 * 10^-6176 => 0,0000000000000000 + vcmpequq. 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff vcmpequq. 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 vcmpequq. 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 @@ -1705,6 +1727,77 @@ vdivesd 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vdivesd 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aaabdc510fae6c71,0000000000000000 vdivesd 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aaabdc510fae6cc5,8720a3d96689b826 +vdivesq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => aaabdafbbf1e5c09,04e6ad0ea8fb9661 +vdivesq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 55542daecc8a1394,ea1beda9ef588602 +vdivesq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivesq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ffddc2ffdda0e0da,a11a7aa0f83960da +vdivesq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => ffddc3006694dfc9,1f5d450816557214 +vdivesq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 223cfc1f398f79,588d1ed5724637ab +vdivesq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => b6981d5317b71,1ccbbd80048a0464 +vdivesq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivesq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 2000001fe0001ee0,201ee13ffee15f9f +vdivesq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 1fffff9fe0011f80,1ca120e9fdbba1a3 +vdivesq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => e00003a01f96dd8b,88e3937f01127062 +vdivesq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => f5557b7f821bd1e5,f43956f134cf70ed +vdivesq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq 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0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aaabdc510fae6cc5,8720a3d96689b826 +vdivesq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 + vdivesw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 vdivesw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,00000000fefefeff vdivesw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000fefefeff @@ -1847,6 +1940,77 @@ vdiveud 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vdiveud 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 vdiveud 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => fffffffdfeff7fbf,5f2f578c75d29512 +vdiveuq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdiveuq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq 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0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 1,007f3fa0d0a8f44a +vdiveuq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 1,007f3fa2d2a8734f +vdiveuq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 1ff,fdc6014093d9b242 +vdiveuq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => aa,a79d60963774bee5 +vdiveuq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => ef42b,cf7cbc92dc8c1c33 +vdiveuq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 8040200fc8041210,ec78452acb81d377 +vdiveuq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 80402010c904d292,ffebf4608b30e1ff +vdiveuq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => 7fbfdff0b83c0dfe,dc0c0d0530be75c5 +vdiveuq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => 7fbfdff1b83bcdc2,6e6cc8d06082807d +vdiveuq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 + vdiveuw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 vdiveuw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,7fbfdfef00000000 vdiveuw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => fe01fde6,7fbfdff000000000 @@ -1989,6 +2153,77 @@ vdivsd 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vdivsd 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,00000000000000fe vdivsd 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => fffffffffffff886,0000000000000054 +vdivsq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivsq 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0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => ffffffffffffffff,fffffffffff885e3 +vdivsq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ffffffffffffffff,ffffffffffffff01 +vdivsq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => ffffffffffffffff,ffffffffffffff02 +vdivsq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000000fe +vdivsq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 0,0000000000000054 +vdivsq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 0,00000000000772a3 +vdivsq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivsq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivsq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivsq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivsq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ffffffffffffffff,fffffffffffff886 + vdivsw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 100000001,0000000100000001 vdivsw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 1,ffffff0100000000 vdivsw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ffffffff,ffffff0200000000 @@ -2131,6 +2366,77 @@ vdivud 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vdivud 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aa,00000000000000fe vdivud 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => eecc0,0000000000000054 +vdivuq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivuq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000001 +vdivuq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000001fe +vdivuq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,00000000000000aa +vdivuq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,00000000000eecc0 +vdivuq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000001 +vdivuq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000001fe +vdivuq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => 0,00000000000000aa +vdivuq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => 0,00000000000eecc0 +vdivuq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000001 +vdivuq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivuq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 0,000000000000077a +vdivuq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000003 +vdivuq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 0,0000000000000001 +vdivuq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 0,000000000000166e +vdivuq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivuq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivuq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 0,0000000000000001 +vdivuq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000000ff +vdivuq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000055 +vdivuq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 0,000000000007792e +vdivuq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivuq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000001 +vdivuq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000001ff +vdivuq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => 0,00000000000000aa +vdivuq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => 0,00000000000ef34b +vdivuq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000044 +vdivuq fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000016 +vdivuq fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 0,000000000001fceb +vdivuq 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivuq 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivuq 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivuq 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivuq 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000001 +vdivuq 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000001ff +vdivuq 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => 0,00000000000000aa +vdivuq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => 0,00000000000ef42b +vdivuq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivuq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivuq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivuq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000000ff +vdivuq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000055 +vdivuq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000077a1d +vdivuq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivuq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivuq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000000fe +vdivuq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 0,0000000000000054 +vdivuq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 0,00000000000772a3 +vdivuq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000001 +vdivuq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000001 +vdivuq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,00000000000001fe +vdivuq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,00000000000000aa +vdivuq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,00000000000eecc0 + vdivuw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 100000001,0000000100000001 vdivuw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 100000001,0000000000000002 vdivuw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 1fe00000000,0000000000000002 @@ -6801,6 +7107,77 @@ vmodsd 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff vmodsd 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => ff8000007f800000,007ff19d807ff21c vmodsd 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => fffffe09807f8bec,017e3d28817d8aa8 +vmodsq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vmodsq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => fffffe09807f8bf7,b6a820d836b8040c +vmodsq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => fffffffdfffffffe,7fffffff80000000 +vmodsq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vmodsq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => ff7ffffe7f7ffffe,ff8000007f800000 +vmodsq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => ff7ffffe7f7ffffe,ff8000007f800000 +vmodsq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => fffffe07807f8bf6,36a820d7b6b8040c +vmodsq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => f0000000f,7effffff7efffffe +vmodsq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => d0000000d,fefffffefefffffe +vmodsq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vmodsq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 80000e8080000e,ff7ffffe7f7ffffe +vmodsq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 2057f807417,c857df274847fbf2 +vmodsq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 55f8000077f,7f0000117f00000e +vmodsq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 5598000077a,ff00000fff00000e +vmodsq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 53280000751,0200001302000014 +vmodsq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vmodsq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => b42fe816398,5b079d88dad7f3ea +vmodsq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 111e8000222e,0180055e0180077e +vmodsq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 111e8000222e,0180055e0180077e +vmodsq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 111e8000222e,0180055e0180077e +vmodsq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 111e8000222e,0180055e0180077e +vmodsq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vmodsq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => 70007f0080007f,0080121d0080222e +vmodsq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 6ffe81007fff00,8080119d8080222e +vmodsq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 6ff18e007ff10f,7f80129d7f80242c +vmodsq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 6e37c9807d8329,d5800c4dd5801d88 +vmodsq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 20400901286,12e3a10483023b8a +vmodsq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => fff0000000000000,7ff0000000000000 +vmodsq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => fff0000000000000,7ff0000000000000 +vmodsq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => fff0000000000000,7ff0000000000000 +vmodsq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => fff0000000000000,7ff0000000000000 +vmodsq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => fffffb79801fe8f3,e67502c36686fea2 +vmodsq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 84021de000022,ddf00043de000000 +vmodsq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => 83f99ddffffbc,ddf00021de000000 +vmodsq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 83c25ddfffc05,21f0006622000088 +vmodsq fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => 107c9ebdeff5b2c,f4effec0f4fffecc +vmodsq fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 3003c0d54cb,94c487ba909b1756 +vmodsq 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 9,2208400000000000 +vmodsq 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 9,2208400000000000 +vmodsq 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 9,2208400000000000 +vmodsq 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 9,2208400000000000 +vmodsq 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => 9,2208400000000000 +vmodsq 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => ffff000180000001,0000000000000009 +vmodsq 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => ffff000180000001,0000000000000009 +vmodsq 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => ffff000180000001,0000000000000009 +vmodsq 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ffff000180000001,0000000000000009 +vmodsq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => ffffefac8001de85,15004b24150068ed +vmodsq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 0,ffff000180000001 +vmodsq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffff000180000001 +vmodsq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffff000180000001 +vmodsq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 0,ffff000180000001 +vmodsq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => 0,ffff000180000001 +vmodsq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => ffffff807fffff80,7fffff0080000000 +vmodsq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => ff80017eff8000ff,7f7fff80ff800000 +vmodsq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => ff800e71ff800ef0,807ffe81007ffe02 +vmodsq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => ff81c8367f827cd6,2a8004d0aa8004a6 +vmodsq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => fffff9757f8fd66d,53a172dd6384e546 +vmodsq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => 800000007f,808000fe80800000 +vmodsq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => 7ffe83807fff02,0100007e81000000 +vmodsq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 7ff19d807ff11e,ff00017d7f0001fc +vmodsq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 17e3d28817d8aa8,55fffb3dd5fffb68 +vmodsq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 49480efb58a,6386adf9d3b31ec6 +vmodsq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vmodsq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => ff8000007f800000,7f800000ff800000 +vmodsq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => fffffe09807f8bf7,b6a820d836b8040c + vmodsw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 vmodsw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => ff80000000000002,00000000ff800000 vmodsw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff8000000000000e,007ffe04ff800000 @@ -6943,6 +7320,77 @@ vmodud 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vmodud 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7c6f93807b0654,007ff19d807ff21c vmodud 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => b1e815ff580,017e3d28817d8aa8 +vmoduq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vmoduq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 200000001,8000000080000000 +vmoduq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 7fe31c807fe21f,7e8002fefe8003fc +vmoduq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7c6f93807b0654,2a7ff65faa7ff6b4 +vmoduq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => b1e815fdf1d,0f653b1d6fae3980 +vmoduq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => ff7ffffe7f7ffffe,ff8000007f800000 +vmoduq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vmoduq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 7fe31a807fe21d,fe8002fe7e8003fc +vmoduq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => 7c6f91807b0652,aa7ff65f2a7ff6b4 +vmoduq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => b1c815fdf1b,8f653b1cefae3980 +vmoduq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 80000e8080000e,ff7ffffe7f7ffffe +vmoduq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 80000e8080000e,ff7ffffe7f7ffffe +vmoduq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vmoduq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 80000e8080000e,ff7ffffe7f7ffffe +vmoduq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 2057f807417,c857df274847fbf2 +vmoduq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 180055e0180077e,0080000e8080000e +vmoduq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 180055e0180077e,0080000e8080000e +vmoduq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 53280000751,0200001302000014 +vmoduq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vmoduq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => b42fe816398,5b079d88dad7f3ea +vmoduq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 111e8000222e,0180055e0180077e +vmoduq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 111e8000222e,0180055e0180077e +vmoduq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 111e8000222e,0180055e0180077e +vmoduq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 111e8000222e,0180055e0180077e +vmoduq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vmoduq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => 7ff0000000000000,0000111e8000222e +vmoduq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 7ff0000000000000,0000111e8000222e +vmoduq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 6ff18e007ff10f,7f80129d7f80242c +vmoduq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 6e37c9807d8329,d5800c4dd5801d88 +vmoduq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 20400901286,12e3a10483023b8a +vmoduq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 6fffff80800000,006fffff00800000 +vmoduq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 70000180800001,806fffff80800000 +vmoduq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 6fe30d807fe210,7f7002ff7f8003fe +vmoduq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => ec6f9300fb0654,2aeff65eaafff6b4 +vmoduq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => 88e81003c19,3f321d089f7d3416 +vmoduq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 2208400000000000,fff0000000000000 +vmoduq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => 2208400000000000,fff0000000000000 +vmoduq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 83c25ddfffc05,21f0006622000088 +vmoduq fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => 107c9ebdeff5b2c,f4effec0f4fffecc +vmoduq fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 3003c0d54cb,94c487ba909b1756 +vmoduq 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 9,2208400000000000 +vmoduq 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 9,2208400000000000 +vmoduq 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 9,2208400000000000 +vmoduq 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 9,2208400000000000 +vmoduq 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => 9,2208400000000000 +vmoduq 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => 7f000100800000,807fffff00800009 +vmoduq 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => 7f000300800002,007fffff80800009 +vmoduq 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => 7ee30f007fe210,ff8002ff7f800407 +vmoduq 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => fb6f9480fb0654,aafff65eaafff6bd +vmoduq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => de000e253d8,6f3d6ac74f76a5df +vmoduq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 0,ffff000180000001 +vmoduq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffff000180000001 +vmoduq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffff000180000001 +vmoduq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 0,ffff000180000001 +vmoduq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => 0,ffff000180000001 +vmoduq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 8000000000000000,0000000000000000 +vmoduq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 8000000000000000,0000000000000000 +vmoduq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 7ff18e007ff10f,7f80017eff8001fe +vmoduq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 7e37c9807d8329,d57ffb2f557ffb5a +vmoduq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => 68a80702992,ac5e8d229c7b1aba +vmoduq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => 7f800000ff800000,8000000000000000 +vmoduq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => 7f800000ff800000,8000000000000000 +vmoduq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 7ff19d807ff11e,ff00017d7f0001fc +vmoduq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 17e3d28817d8aa8,55fffb3dd5fffb68 +vmoduq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 49480efb58a,6386adf9d3b31ec6 +vmoduq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vmoduq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 200000001,8000000080000000 +vmoduq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 7fe31c807fe21f,7e8002fefe8003fc +vmoduq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7c6f93807b0654,2a7ff65faa7ff6b4 +vmoduq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => b1e815fdf1d,0f653b1d6fae3980 + vmoduw 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 vmoduw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 200000002,7f80000000800000 vmoduw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 7fe41c7f800000,7f80000000800004 @@ -7014,6 +7462,25 @@ vmoduw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vmoduw 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7c6f94017d8aa8,007ff21c7efffff2 vmoduw 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 4607f800000,017e3d28007b0654 +vmsumcud 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000002 +vmsumcud 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => 0,0000000000000001 +vmsumcud 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 0,00000000000... [truncated message content] |
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From: Carl L. <ca...@so...> - 2021-02-25 17:59:07
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=affeb57ccd48a77cd7b18e56191e1eb72152c13e commit affeb57ccd48a77cd7b18e56191e1eb72152c13e Author: Carl Love <ce...@us...> Date: Fri Jan 22 14:13:04 2021 -0600 PPC64: ISA 3.1 (new Iops) 128-bit Binary Integer Operations Add support for: dcffixqq DFP Convert From Fixed Quadword Quad dctfixqq DFP Convert To Fixed Quadword Quad vdivesq Vector Divide Extended Signed Quadword vdiveuq Vector Divide Extended Unsigned Quadword vdivsq Vector Divide Signed Quadword vdivuq Vector Divide Unsigned Quadword vmodsq Vector Modulo Signed Quadword vmoduq Vector Modulo Unsigned Quadword vmulesd Vector Multiply Even Signed Doubleword vmuleud Vector Multiply Even Unsigned Doubleword vmulosd Vector Multiply Odd Signed Doubleword vmuloud Vector Multiply Odd Unsigned Doubleword vmsumcud Vector Multiply-Sum & write Carry-out Unsigned Doubleword xscvqpsqz VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword xscvqpuqz VSX Scalar Convert with round to zero Quad-Precision toUnsigned Quadword xscvsqqp VSX Scalar Convert Signed Quadword to Quad-Precision xscvuqqp VSX Scalar Convert Unsigned Quadword to Quad-Precision Diff: --- VEX/priv/guest_ppc_defs.h | 4 + VEX/priv/guest_ppc_helpers.c | 49 +++++++ VEX/priv/guest_ppc_toIR.c | 287 ++++++++++++++++++++++++++++++++++--- VEX/priv/host_ppc_defs.c | 296 +++++++++++++++++++++++++++++++++++++-- VEX/priv/host_ppc_defs.h | 67 +++++++++ VEX/priv/host_ppc_isel.c | 211 ++++++++++++++++++++++++++++ VEX/priv/ir_defs.c | 49 ++++++- VEX/pub/libvex_ir.h | 34 ++++- memcheck/mc_translate.c | 30 +++- memcheck/tests/vbit-test/irops.c | 49 ++++++- tests/min_power_isa.c | 15 +- 11 files changed, 1045 insertions(+), 46 deletions(-) diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index da228b9f04..deda4dfcee 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -154,6 +154,10 @@ extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); extern ULong extract_bits_under_mask_helper( ULong src, ULong mask, UInt flag ); +extern UInt generate_DFP_FPRF_value_helper( UInt gfield, ULong exponent, + UInt exponent_bias, + Int min_norm_exp, + UInt sign, UInt T_value_is_zero ); extern UInt count_bits_under_mask_helper( ULong src, ULong mask, UInt flag ); extern ULong deposit_bits_under_mask_helper( ULong src, ULong mask ); diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index d2410d9537..c24191ef3c 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -318,6 +318,55 @@ ULong generate_C_FPCC_helper( ULong irType, ULong src_hi, ULong src ) } +UInt generate_DFP_FPRF_value_helper( UInt gfield, + ULong exponent, + UInt exponent_bias, + Int min_norm_exp, + UInt sign, + UInt T_value_is_zero ) +{ + UInt gfield_5_bit_mask = 0xF8000000; + UInt gfield_upper_5_bits = (gfield & gfield_5_bit_mask) >> (32 - 5); + UInt gfield_6_bit_mask = 0xF8000000; + UInt gfield_upper_6_bits = (gfield & gfield_6_bit_mask) >> (32 - 6); + UInt fprf_value = 0; + Int unbiased_exponent = exponent - exponent_bias; + + /* The assumption is the gfield bits are left justified. Mask off + the most significant 5-bits in the 32-bit wide field. */ + if ( T_value_is_zero == 1) { + if (sign == 0) + fprf_value = 0b00010; // positive zero + else + fprf_value = 0b10010; // negative zero + } else if ( unbiased_exponent < min_norm_exp ) { + if (sign == 0) + fprf_value = 0b10100; // posative subnormal + else + fprf_value = 0b11000; // negative subnormal + + } else if ( gfield_upper_5_bits == 0b11110 ) { // infinity + if (sign == 0) + fprf_value = 0b00101; // positive infinity + else + fprf_value = 0b01001; // negative infinity + + } else if ( gfield_upper_6_bits == 0b111110 ) { + fprf_value = 0b10001; // Quiet NaN + + } else if ( gfield_upper_6_bits == 0b111111 ) { + fprf_value = 0b10001; // Signaling NaN + + } else { + if (sign == 0) + fprf_value = 0b00100; // positive normal + else + fprf_value = 0b01000; // negative normal + } + + return fprf_value; +} + /*---------------------------------------------------------------*/ /*--- Misc BCD clean helpers. ---*/ /*---------------------------------------------------------------*/ diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 308c2fe762..3b58f883e4 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -611,6 +611,8 @@ typedef enum { /*--- Misc Helpers ---*/ /*------------------------------------------------------------*/ +static void Get_lmd( IRTemp * lmd, IRExpr * gfield_0_4 ); + /* Generate mask with 1's from 'begin' through 'end', wrapping if begin > end. begin->end works from right to left, 0=lsb @@ -15094,6 +15096,107 @@ static Bool dis_fp_scr ( UInt prefix, UInt theInstr, Bool GX_level ) (((_b4) << 4) | ((_b3) << 3) | ((_b2) << 2) | \ ((_b1) << 1) | ((_b0) << 0)) +static void generate_store_DFP_FPRF_value( ULong irType, IRExpr *src, + const VexAbiInfo* vbi ) +{ + /* This function takes a DFP value and computes the value of the FPRF + field in the FPCC register and store it. It is done as a clean helper. + The FPRF[0:4]: + bits[0:4] = + 0b00001 Signaling NaN (DFP only) + 0b10001 Quite NaN + 0b01001 negative infinity + 0b01000 negative normal number + 0b11000 negative subnormal number + 0b10010 negative zero + 0b00010 positive zero + 0b10100 positive subnormal number + 0b00100 positive normal number + 0b00101 positive infinity + */ + + IRTemp sign = newTemp( Ity_I32 ); + IRTemp gfield = newTemp( Ity_I32 ); + IRTemp gfield_mask = newTemp( Ity_I32 ); + IRTemp exponent = newTemp( Ity_I64 ); + UInt exponent_bias = 0; + IRTemp T_value_is_zero = newTemp( Ity_I32 ); + IRTemp fprf_value = newTemp( Ity_I32 ); + IRTemp lmd = newTemp( Ity_I32 ); + IRTemp lmd_zero_true = newTemp( Ity_I1 ); + Int min_norm_exp = 0; + + vassert( irType == Ity_D128); + + if (irType == Ity_D128) { + assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) ); + /* The gfield bits are left justified. */ + assign( gfield, binop( Iop_And32, + mkexpr( gfield_mask ), + unop( Iop_64HIto32, + unop( Iop_ReinterpD64asI64, + unop( Iop_D128HItoD64, src ) ) ) ) ); + assign( exponent, unop( Iop_ExtractExpD128, src ) ); + exponent_bias = 6176; + min_norm_exp = -6143; + + /* The significand is zero if the T field and LMD are all zeros */ + /* Check if LMD is zero */ + Get_lmd( &lmd, binop( Iop_Shr32, + mkexpr( gfield ), mkU8( 31 - 5 ) ) ); + + assign( lmd_zero_true, binop( Iop_CmpEQ32, + mkexpr( lmd ), + mkU32( 0 ) ) ); + /* The T value and the LMD are the BCD value of the significand. + If the upper and lower T value fields and the LMD are all zero + then the significand is zero. */ + assign( T_value_is_zero, + unop( Iop_1Uto32, + mkAND1 ( + mkexpr( lmd_zero_true ), + mkAND1 ( binop( Iop_CmpEQ64, + binop( Iop_And64, + mkU64( DFP_T_FIELD_EXTND_MASK ), + unop( Iop_ReinterpD64asI64, + unop( Iop_D128HItoD64, + src ) ) ), + mkU64( 0 ) ), + binop( Iop_CmpEQ64, + unop( Iop_ReinterpD64asI64, + unop( Iop_D128LOtoD64, + src ) ), + mkU64( 0 ) ) ) ) ) ); + + assign( sign, + unop( Iop_64to32, + binop( Iop_Shr64, + unop( Iop_ReinterpD64asI64, + unop( Iop_D128HItoD64, src ) ), + mkU8( 63 ) ) ) ); + } else { + /* generate_store_DFP_FPRF_value, unknown value for irType */ + vassert(0); + } + + /* Determine what the type of the number is. */ + assign( fprf_value, + mkIRExprCCall( Ity_I32, 0 /*regparms*/, + "generate_DFP_FPRF_value_helper", + fnptr_to_fnentry( vbi, + &generate_DFP_FPRF_value_helper ), + mkIRExprVec_6( mkexpr( gfield ), + mkexpr( exponent ), + mkU32( exponent_bias ), + mkU32( min_norm_exp ), + mkexpr( sign ), + mkexpr( T_value_is_zero ) ) ) ); + /* fprf[0:4] = (C | FPCC[0:3]) */ + putC( binop( Iop_Shr32, mkexpr( fprf_value ), mkU8( 4 ) ) ); + putFPCC( binop( Iop_And32, mkexpr( fprf_value ), mkU32 (0xF ) ) ); + return; +} + static IRExpr * Gfield_encoding( IRExpr * lmexp, IRExpr * lmd32 ) { IRTemp lmd_07_mask = newTemp( Ity_I32 ); @@ -15971,7 +16074,8 @@ static Bool dis_dfp_fmt_conv( UInt prefix, UInt theInstr ) { } /* Quad DFP format conversion instructions */ -static Bool dis_dfp_fmt_convq( UInt prefix, UInt theInstr ) { +static Bool dis_dfp_fmt_convq( UInt prefix, UInt theInstr, + const VexAbiInfo* vbi ) { UInt opc2 = ifieldOPClo10( theInstr ); UChar frS_addr = ifieldRegDS( theInstr ); UChar frB_addr = ifieldRegB( theInstr ); @@ -16028,6 +16132,45 @@ static Bool dis_dfp_fmt_convq( UInt prefix, UInt theInstr ) { putDReg_pair( frS_addr, mkexpr( frS128 ) ); break; } + + case 0x3E2: + { + Int opc3 = IFIELD( theInstr, 16, 5 ); + + flag_rC = 0; // These instructions do not set condition codes. + + if (opc3 == 0) { // dcffixqq + IRTemp tmpD128 = newTemp( Ity_D128 ); + IRTemp vB_src = newTemp( Ity_V128 ); + + DIP( "dcffixqq fr%u,v%u\n", frS_addr, frB_addr ); + + assign( vB_src, getVReg( frB_addr )); + assign( tmpD128, binop( Iop_I128StoD128, round, + unop( Iop_ReinterpV128asI128, + mkexpr( vB_src ) ) ) ); + /* tmp128 is a Dfp 128 value which is held in a hi/lo 64-bit values. + */ + generate_store_DFP_FPRF_value( Ity_D128, mkexpr( tmpD128 ), vbi); + putDReg_pair( frS_addr, mkexpr( tmpD128 ) ); + + } else if (opc3 == 1) { // dctfixqq + IRTemp tmp128 = newTemp(Ity_I128); + + DIP( "dctfixqq v%u,fr%u\n", frS_addr, frB_addr ); + assign( tmp128, binop( Iop_D128toI128S, round, + getDReg_pair( frB_addr ) ) ); + + putVReg( frS_addr, + unop( Iop_ReinterpI128asV128, mkexpr( tmp128 ) ) ); + + } else { + vex_printf("ERROR: dis_dfp_fmt_convq unknown opc3 = %d value.\n", + opc3); + return False; + } + } + break; } if (flag_rC && clear_CR1) { @@ -20408,10 +20551,10 @@ dis_vxv_sp_arith ( UInt prefix, UInt theInstr, UInt opc2 ) mkexpr( flags2 ), mkexpr( flags3 ) ) ) ), crfD ); - break; } - case 0x174: // xvtdivsp (VSX Vector Test for software Divide Single-Precision) + + case 0x174: // xvtdivsp (VSX Vector Test for software Divide Single-Precision) { IRTemp flags0 = newTemp(Ity_I32); IRTemp flags1 = newTemp(Ity_I32); @@ -26426,6 +26569,13 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt prefix, UInt theInstr, UInt inst_select = IFIELD( theInstr, 16, 5); switch (inst_select) { + case 0: // xscvqpuqz, VSX Scalar Convert with round to zero + // Quad-Precision to Unsigned Quadword X-form + { + DIP("xscvqpuqz, v%d,v%d\n", vT_addr, vB_addr); + assign( vT, unop( Iop_TruncF128toI128U, mkexpr( vB ) ) ); + break; + } case 1: // xscvqpuwz VSX Scalar Truncate & Convert Quad-Precision // format to Unsigned Word format { @@ -26445,6 +26595,24 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt prefix, UInt theInstr, generate_store_FPRF( Ity_F128, vT, vbi ); break; } + case 3: // xscvuqqp, VSX Scalar Convert Unsigned Quadword + // to Quad-Precision X-form + { + DIP("xscvqpuqz, v%d,v%d\n", vT_addr, vB_addr); + assign( vT, + binop( Iop_I128UtoF128, rm, + unop ( Iop_ReinterpF128asI128, + getF128Reg( vB_addr ) ) ) ); + generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } + case 8: // xscvqpsqz, VSX Scalar Convert with round to zero + // Quad-Precision to Signed Quadword X-form + { + DIP("xscvqpsqz, v%d,v%d\n", vT_addr, vB_addr); + assign( vT, unop( Iop_TruncF128toI128S, mkexpr( vB ) ) ); + break; + } case 9: // xsvqpswz VSX Scalar Truncate & Convert Quad-Precision // format to Signed Word format { @@ -26465,6 +26633,17 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt prefix, UInt theInstr, generate_store_FPRF( Ity_F128, vT, vbi ); break; } + case 11: // xscvsqqp, VSX Scalar Convert Unsigned Quadword + // to Quad-Precision X-form + { + DIP("xscvsqqp, v%d,v%d\n", vT_addr, vB_addr); + assign( vT, + binop( Iop_I128StoF128, rm, + unop ( Iop_ReinterpF128asI128, + mkexpr( vB ) ) ) ); + generate_store_FPRF( Ity_F128, vT, vbi ); + break; + } case 17: // xsvqpudz VSX Scalar Truncate & Convert Quad-Precision // format to Unigned Doubleword format { @@ -27670,28 +27849,28 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) IRTemp tmp128 = newTemp(Ity_I128); if ( opc2 == 0x0C8) { - DIP("vwuloud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + DIP("vmuloud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); /* multiply lower D-words together, upper D-words not used. */ assign( tmp128, binop( Iop_MullU64, unop( Iop_V128to64, mkexpr( vA ) ), unop( Iop_V128to64, mkexpr( vB ) ) ) ); } else if ( opc2 == 0x1C8) { - DIP("vwulosd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + DIP("vmulosd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); /* multiply lower D-words together, upper D-words not used. */ assign( tmp128, binop( Iop_MullS64, unop( Iop_V128to64, mkexpr( vA ) ), unop( Iop_V128to64, mkexpr( vB ) ) ) ); } else if ( opc2 == 0x2C8) { - DIP("vwuleud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + DIP("vmuleud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); /* multiply upper D-words together, lower D-words not used. */ assign( tmp128, binop( Iop_MullU64, unop( Iop_V128HIto64, mkexpr( vA ) ), unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); } else { - DIP("vwulesd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + DIP("vmulesd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); /* multiply upper D-words together, lower D-words not used. */ assign( tmp128, binop( Iop_MullS64, unop( Iop_V128HIto64, mkexpr( vA ) ), @@ -27892,7 +28071,7 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) mkexpr( res_tmp[ 1 ] ), mkexpr( res_tmp[ 0 ] ) ) ) ) ); } else { - /* Doing a modulo instruction, + /* Doing a modulo instruction, vmodsw/vmoduw res_tmp[] contains the quotients of VRA/VRB. Calculate modulo as VRA - VRB * res_tmp. */ IRTemp res_Tmp = newTemp( Ity_V128 ); @@ -28477,7 +28656,7 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) UChar vA_addr = ifieldRegA(theInstr); UChar vB_addr = ifieldRegB(theInstr); UChar opc1 = ifieldOPC(theInstr); - UInt opc2 = ifieldOPClo11( theInstr ); + UInt opc2; IRTemp vA = newTemp(Ity_V128); IRTemp vB = newTemp(Ity_V128); @@ -28489,6 +28668,27 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) assign( vA, getVReg( vA_addr ) ); assign( vB, getVReg( vB_addr ) ); + opc2 = IFIELD(theInstr, 0, 6); + switch (opc2) { + case 0x017: // vmsumcud Vector Multiply-Sum & write Carry-out Unsigned + // Doubleword VA-form + { + UChar vC_addr = ifieldRegC(theInstr); + IRTemp vC = newTemp(Ity_V128); + + assign( vC, getVReg( vC_addr ) ); + + DIP("vmsumcud %d,%d,%d,%d\n", vT_addr, vA_addr, vB_addr, vC_addr); + putVReg( vT_addr, triop( Iop_2xMultU64Add128CarryOut, + mkexpr( vA ), mkexpr( vB ), mkexpr( vC ) ) ); + return True; + } + + default: + break; /* fall thru to next case statement */ + } /* switch (opc2) */ + + opc2 = ifieldOPClo11( theInstr ); switch (opc2) { case 0x005: //vrlq Vector Rotate Left Quadword { @@ -28517,7 +28717,8 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) break; case 0x00B: //vdivuq Vector Divide Unsigned Quadword - vex_printf("WARNING: instruction vdivuq not currently supported. dis_vx_quadword_arith(ppc)\n"); + DIP("vdivuq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_DivU128, mkexpr( vA ), mkexpr( vB ) ) ); break; case 0x101: //vcmpuq Vector Compare Unsigned Quadword @@ -28574,7 +28775,8 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) break; case 0x10B: //vdivsq Vector Divide Signed Quadword - vex_printf("WARNING: instruction vdivsq not currently supported. dis_vx_quadword_arith(ppc)\n"); + DIP("vdivsq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_DivS128, mkexpr( vA ), mkexpr( vB ) ) ); break; case 0x141: //vcmpsq Vector Compare Signed Quadword @@ -28767,8 +28969,9 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) } break; - case 0x20B: //vdiveuq Vector Divide Extended Unsigned Quadword - vex_printf("WARNING: instruction vdiveuq not currently supported. dis_vx_quadword_arith(ppc)\n"); + case 0x20B: //vdiveuq Vector Divide Extended Unsigned Quadword VX form + DIP("vdiveuq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_DivU128E, mkexpr( vA ), mkexpr( vB ) ) ); break; case 0x305: //vsraq Vector Shift Right Algebraic Quadword @@ -28819,20 +29022,23 @@ static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) } break; - case 0x30B: //vdivesq Vector Divide Extended Signed Quadword - vex_printf("WARNING: instruction vdivesq not currently supported. dis_vx_quadword_arith(ppc)\n"); + case 0x30B: //vdivesq Vector Divide Extended Signed Quadword VX form + DIP("vdivesq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_DivS128E, mkexpr( vA ), mkexpr( vB ) ) ); break; case 0x60B: //vmoduq Vector Modulo Unsigned Quadword - vex_printf("WARNING: instruction vmoduq not currently supported. dis_vx_quadword_arith(ppc)\n"); + DIP("vmoduq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_ModU128, mkexpr( vA ), mkexpr( vB ) ) ); break; case 0x70B: //vmodsq Vector Modulo Signed Quadword - vex_printf("WARNING: instruction vmodsq not currently supported. dis_vx_quadword_arith(ppc)\n"); + DIP("vmodsq %d,%d,%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_ModS128, mkexpr( vA ), mkexpr( vB ) ) ); break; default: - vex_printf("dis_av_arith(ppc)(opc2=0x%x)\n", opc2); + vex_printf("dis_av_arith(ppc)(opc2 bits[21:31]=0x%x)\n", opc2); return False; } /* switch (opc2) */ @@ -35626,12 +35832,20 @@ DisResult disInstr_PPC_WRK ( goto decode_success; goto decode_failure; + case 0x3E2: // dcffixqq - DFP Convert From Fixed Quadword + // dctfixqq - DFP Convert To Fixed Quadword + if (!allow_DFP) goto decode_noDFP; + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_dfp_fmt_convq( prefix, theInstr, abiinfo )) + goto decode_success; + goto decode_failure; + case 0x102: // dctqpq - DFP convert to DFP extended case 0x302: // drdpq - DFP round to dfp Long case 0x122: // dctfixq - DFP convert to fixed quad case 0x322: // dcffixq - DFP convert from fixed quad if (!allow_DFP) goto decode_noDFP; - if (dis_dfp_fmt_convq( prefix, theInstr )) + if (dis_dfp_fmt_convq( prefix, theInstr, abiinfo )) goto decode_success; goto decode_failure; @@ -35760,10 +35974,33 @@ DisResult disInstr_PPC_WRK ( case 0x204: // xssubqp (VSX Scalar Subrtact Quad-Precision [using RN mode] // xsdivqpo (VSX Scalar Divde Quad-Precision [using round to ODD] case 0x224: // xsdivqp (VSX Scalar Divde Quad-Precision [using RN mode] + if ( dis_vx_Floating_Point_Arithmetic_quad_precision( prefix, + theInstr, + abiinfo ) ) + goto decode_success; + goto decode_failure; + case 0x344: // xscvudqp, xscvsdqp, xscvqpdp, xscvqpdpo, xsvqpdp // xscvqpswz, xscvqpuwz, xscvqpudz, xscvqpsdz + /* ISA 3.1 instructions: xscvqpuqz, xscvuqqp, xscvqpsqz, + xscvsqqp. */ + if (( IFIELD( theInstr, 16, 5) == 0 // xscvqpuqz + || IFIELD( theInstr, 16, 5) == 3 // xscvuqqp + || IFIELD( theInstr, 16, 5) == 8 // xscvqpsqz + || IFIELD( theInstr, 16, 5) == 11 )) { // xscvsqqp + if (!allow_isa_3_1) + goto decode_noIsa3_1; + + if ( dis_vx_Floating_Point_Arithmetic_quad_precision( prefix, + theInstr, + abiinfo ) ) + goto decode_success; + goto decode_failure; + } + if ( !mode64 || !allow_isa_3_0 ) goto decode_failure; - if ( dis_vx_Floating_Point_Arithmetic_quad_precision( prefix, theInstr, + if ( dis_vx_Floating_Point_Arithmetic_quad_precision( prefix, + theInstr, abiinfo ) ) goto decode_success; goto decode_failure; @@ -36309,10 +36546,16 @@ DisResult disInstr_PPC_WRK ( /* AV Mult-Add, Mult-Sum */ case 0x16: // vsldbi/vsrdbi if (!allow_V) goto decode_noV; - if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; if (dis_av_shift( prefix, theInstr )) goto decode_success; goto decode_failure; + case 0x17: // vmsumcud + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_vx_quadword_arith( prefix, theInstr )) { + goto decode_success; + } + goto decode_failure; + case 0x18: case 0x19: // vextdubvlx, vextdubvrx case 0x1A: case 0x1B: // vextduhvlx, vextduhvrx case 0x1C: case 0x1D: // vextduwvlx, vextduwvrx @@ -36681,7 +36924,7 @@ DisResult disInstr_PPC_WRK ( case 0x783: case 0x7c3: // vpopcntw, vpopcntd if (!allow_isa_2_07) goto decode_noP8; if (dis_av_count_bitTranspose( prefix, theInstr, opc2 )) - goto decode_success; + goto decode_success; goto decode_failure; case 0x50c: // vgbbd diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index 843009422e..3ae0f6e082 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -574,6 +574,8 @@ const HChar* showPPCFpOp ( PPCFpOp op ) { case Pfp_FPDTOQ: return "xscvdpqp"; case Pfp_IDSTOQ: return "xscvsdqp"; case Pfp_IDUTOQ: return "xscvudqp"; + case Pfp_IQSTOQ: return "xscvsqqp"; + case Pfp_IQUTOQ: return "xscvuqqp"; case Pfp_TRUNCFPQTOISD: return "xscvqpsdz"; case Pfp_TRUNCFPQTOISW: return "xscvqpswz"; case Pfp_TRUNCFPQTOIUD: return "xscvqpudz"; @@ -586,6 +588,8 @@ const HChar* showPPCFpOp ( PPCFpOp op ) { case Pfp_DFPMULQ: return "dmulq"; case Pfp_DFPDIV: return "ddivd"; case Pfp_DFPDIVQ: return "ddivq"; + case Pfp_DFPTOIQ: return "dctfixqq"; + case Pfp_IQUTODFP: return "dcffixqq"; case Pfp_DCTDP: return "dctdp"; case Pfp_DRSP: return "drsp"; case Pfp_DCTFIX: return "dctfix"; @@ -727,7 +731,7 @@ const HChar* showPPCAvOp ( PPCAvOp op ) { case Pav_F16toF64x2: return"xvcvhpdp"; - /* Vector Half-precision format to Double precision conversion */ + /* Vector Half-precision format to Double precision conversion */ case Pav_F64toF16x2: return"xvcvdphp"; @@ -735,6 +739,45 @@ const HChar* showPPCAvOp ( PPCAvOp op ) { } } +const HChar* showPPCAvOpBin128 ( PPCAvOpBin128 op ) { + + switch (op) { + /* Binary ops */ + + /* Vector Divide Signed Quadword VX-form */ + case Pav_DivU128: + return "vdivuq"; + + case Pav_DivS128: + return "vdivsq"; + + case Pav_DivU128E: + return "vdivuq"; + + case Pav_DivS128E: + return "vdivsq"; + + case Pav_ModU128: + return "vmoduq"; + + case Pav_ModS128: + return "vmodsq"; + + default: vpanic("showPPCAvOpBin128"); + } +} + +const HChar* showPPCAvOpTri128 ( PPCAvOpTri128 op ) { + + /* Vector Quadword VX-form */ + switch (op) { + case Pav_2xMultU64Add128CarryOut: + return "vmsumcud"; + + default: vpanic("showPPCAvOpTri128"); + } +} + const HChar* showPPCAvFpOp ( PPCAvFpOp op ) { switch (op) { /* Floating Point Binary */ @@ -765,6 +808,19 @@ const HChar* showPPCAvFpOp ( PPCAvFpOp op ) { } } +const HChar* showXFormUnary994 ( PPCXFormUnary994 op ) { + + /* Vector Quadword VX-form */ + switch (op) { + case Px_IQSTODFP: + return "dcffixqq"; + case Px_DFPTOIQS: + return "dctfixqq"; + + default: vpanic("showXFormUnary994"); + } +} + PPCInstr* PPCInstr_LI ( HReg dst, ULong imm64, Bool mode64 ) { PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr)); @@ -1007,13 +1063,13 @@ PPCInstr* PPCInstr_Fp128Binary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { i->Pin.Fp128Binary.srcR = srcR; return i; } -PPCInstr* PPCInstr_Fp128Ternnary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { +PPCInstr* PPCInstr_Fp128Ternary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { PPCInstr* i = LibVEX_Alloc_inline( sizeof(PPCInstr) ); - i->tag = Pin_Fp128Ternnary; - i->Pin.Fp128Ternnary.op = op; - i->Pin.Fp128Ternnary.dst = dst; - i->Pin.Fp128Ternnary.srcL = srcL; - i->Pin.Fp128Ternnary.srcR = srcR; + i->tag = Pin_Fp128Ternary; + i->Pin.Fp128Ternary.op = op; + i->Pin.Fp128Ternary.dst = dst; + i->Pin.Fp128Ternary.srcL = srcL; + i->Pin.Fp128Ternary.srcR = srcR; return i; } PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, @@ -1369,6 +1425,27 @@ PPCInstr* PPCInstr_AvBinaryInt ( PPCAvOp op, HReg dst, i->Pin.AvBinaryInt.val = val; return i; } +PPCInstr* PPCInstr_AvBinaryInt128 ( PPCAvOpBin128 op, HReg dst, + HReg src1, HReg src2 ) { + PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr)); + i->tag = Pin_AvBinaryInt128; + i->Pin.AvBinaryInt128.op = op; + i->Pin.AvBinaryInt128.dst = dst; + i->Pin.AvBinaryInt128.src1 = src1; + i->Pin.AvBinaryInt128.src2 = src2; + return i; +} +PPCInstr* PPCInstr_AvTernaryInt128 ( PPCAvOpTri128 op, HReg dst, + HReg src1, HReg src2, HReg src3 ) { + PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr)); + i->tag = Pin_AvTernaryInt128; + i->Pin.AvTernaryInt128.op = op; + i->Pin.AvTernaryInt128.dst = dst; + i->Pin.AvTernaryInt128.src1 = src1; + i->Pin.AvTernaryInt128.src2 = src2; + i->Pin.AvTernaryInt128.src3 = src3; + return i; +} PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ) { PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr)); @@ -1526,7 +1603,19 @@ PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst, i->Pin.AvBCDV128Binary.src2 = src2; return i; } - +PPCInstr* PPCInstr_XFormUnary994 ( PPCXFormUnary994 op, HReg reg0, HReg reg1, + HReg reg2 ) { + /* This is used to issue istructions with opc1=63, opc2=994. The specific + instruction is given in bits[11:15], the VRA field, of the instruction. + Currently only used for dcffixqq and dctfixqq instructions. */ + PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr)); + i->tag = Pin_XFormUnary994; + i->Pin.XFormUnary994.op = op; + i->Pin.XFormUnary994.reg0 = reg0; + i->Pin.XFormUnary994.reg1 = reg1; + i->Pin.XFormUnary994.reg2 = reg2; + return i; +} /* Pretty Print instructions */ static void ppLoadImm ( HReg dst, ULong imm, Bool mode64 ) { @@ -1831,9 +1920,9 @@ void ppPPCInstr ( const PPCInstr* i, Bool mode64 ) vex_printf(","); ppHRegPPC(i->Pin.Fp128Binary.srcR); return; - case Pin_Fp128Ternnary: - vex_printf("%s ", showPPCFpOp(i->Pin.Fp128Ternnary.op)); - ppHRegPPC(i->Pin.Fp128Ternnary.dst); + case Pin_Fp128Ternary: + vex_printf("%s ", showPPCFpOp(i->Pin.Fp128Ternary.op)); + ppHRegPPC(i->Pin.Fp128Ternary.dst); vex_printf(","); ppHRegPPC(i->Pin.Fp128Ternary.srcL); vex_printf(","); @@ -2004,6 +2093,24 @@ void ppPPCInstr ( const PPCInstr* i, Bool mode64 ) vex_printf(","); ppPPCRI(i->Pin.AvBinaryInt.val); return; + case Pin_AvBinaryInt128: + vex_printf("%s ", showPPCAvOpBin128(i->Pin.AvBinaryInt128.op)); + ppHRegPPC(i->Pin.AvBinaryInt128.dst); + vex_printf(","); + ppHRegPPC(i->Pin.AvBinaryInt128.src1); + vex_printf(","); + ppHRegPPC(i->Pin.AvBinaryInt128.src2); + return; + case Pin_AvTernaryInt128: + vex_printf("%s ", showPPCAvOpTri128(i->Pin.AvTernaryInt128.op)); + ppHRegPPC(i->Pin.AvTernaryInt128.dst); + vex_printf(","); + ppHRegPPC(i->Pin.AvTernaryInt128.src1); + vex_printf(","); + ppHRegPPC(i->Pin.AvTernaryInt128.src2); + vex_printf(","); + ppHRegPPC(i->Pin.AvTernaryInt128.src3); + return; case Pin_AvBin8x16: vex_printf("%s(b) ", showPPCAvOp(i->Pin.AvBin8x16.op)); ppHRegPPC(i->Pin.AvBin8x16.dst); @@ -2321,6 +2428,21 @@ void ppPPCInstr ( const PPCInstr* i, Bool mode64 ) ppHRegPPC(i->Pin.Dfp128Cmp.dst); vex_printf(",8,28,31"); return; + + case Pin_XFormUnary994: + if (i->Pin.XFormUnary994.op == Px_DFPTOIQS) { + vex_printf("%s(w) ", showXFormUnary994(i->Pin.XFormUnary994.op)); + ppHRegPPC(i->Pin.XFormUnary994.reg0); + vex_printf(","); + ppHRegPPC(i->Pin.XFormUnary994.reg1); + } else { + vex_printf("%s(w) ", showXFormUnary994(i->Pin.XFormUnary994.op)); + ppHRegPPC(i->Pin.XFormUnary994.reg0); + vex_printf(","); + ppHRegPPC(i->Pin.XFormUnary994.reg2); + } + return; + case Pin_EvCheck: /* Note that the counter dec is 32 bit even in 64-bit mode. */ vex_printf("(evCheck) "); @@ -2594,6 +2716,17 @@ void getRegUsage_PPCInstr ( HRegUsage* u, const PPCInstr* i, Bool mode64 ) addHRegUse(u, HRmWrite, i->Pin.AvBinaryInt.dst); addHRegUse(u, HRmRead, i->Pin.AvBinaryInt.src); return; + case Pin_AvBinaryInt128: + addHRegUse(u, HRmWrite, i->Pin.AvBinaryInt128.dst); + addHRegUse(u, HRmRead, i->Pin.AvBinaryInt128.src1); + addHRegUse(u, HRmRead, i->Pin.AvBinaryInt128.src2); + return; + case Pin_AvTernaryInt128: + addHRegUse(u, HRmWrite, i->Pin.AvTernaryInt128.dst); + addHRegUse(u, HRmRead, i->Pin.AvTernaryInt128.src1); + addHRegUse(u, HRmRead, i->Pin.AvTernaryInt128.src2); + addHRegUse(u, HRmRead, i->Pin.AvTernaryInt128.src3); + return; case Pin_AvBin8x16: addHRegUse(u, HRmWrite, i->Pin.AvBin8x16.dst); addHRegUse(u, HRmRead, i->Pin.AvBin8x16.srcL); @@ -2767,6 +2900,17 @@ void getRegUsage_PPCInstr ( HRegUsage* u, const PPCInstr* i, Bool mode64 ) addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_hi); addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_lo); return; + case Pin_XFormUnary994: + if (i->Pin.XFormUnary994.op == Px_DFPTOIQS) { + addHRegUse(u, HRmWrite, i->Pin.XFormUnary994.reg0); + addHRegUse(u, HRmRead, i->Pin.XFormUnary994.reg1); + addHRegUse(u, HRmRead, i->Pin.XFormUnary994.reg2); + } else { + addHRegUse(u, HRmWrite, i->Pin.XFormUnary994.reg0); + addHRegUse(u, HRmWrite, i->Pin.XFormUnary994.reg1); + addHRegUse(u, HRmRead, i->Pin.XFormUnary994.reg2); + } + return; case Pin_EvCheck: /* We expect both amodes only to mention the GSP (r31), so this is in fact pointless, since GSP isn't allocatable, but @@ -2948,6 +3092,17 @@ void mapRegs_PPCInstr ( HRegRemap* m, PPCInstr* i, Bool mode64 ) mapReg(m, &i->Pin.AvBinaryInt.dst); mapReg(m, &i->Pin.AvBinaryInt.src); return; + case Pin_AvBinaryInt128: + mapReg(m, &i->Pin.AvBinaryInt128.dst); + mapReg(m, &i->Pin.AvBinaryInt128.src1); + mapReg(m, &i->Pin.AvBinaryInt128.src2); + return; + case Pin_AvTernaryInt128: + mapReg(m, &i->Pin.AvTernaryInt128.dst); + mapReg(m, &i->Pin.AvTernaryInt128.src1); + mapReg(m, &i->Pin.AvTernaryInt128.src2); + mapReg(m, &i->Pin.AvTernaryInt128.src3); + return; case Pin_AvBin8x16: mapReg(m, &i->Pin.AvBin8x16.dst); mapReg(m, &i->Pin.AvBin8x16.srcL); @@ -3118,6 +3273,11 @@ void mapRegs_PPCInstr ( HRegRemap* m, PPCInstr* i, Bool mode64 ) mapReg(m, &i->Pin.Dfp128Cmp.srcR_hi); mapReg(m, &i->Pin.Dfp128Cmp.srcR_lo); return; + case Pin_XFormUnary994: + mapReg(m, &i->Pin.XFormUnary994.reg0); + mapReg(m, &i->Pin.XFormUnary994.reg1); + mapReg(m, &i->Pin.XFormUnary994.reg2); + return; case Pin_EvCheck: /* We expect both amodes only to mention the GSP (r31), so this is in fact pointless, since GSP isn't allocatable, but @@ -3345,6 +3505,19 @@ static UChar* mkFormXO ( UChar* p, UInt opc1, UInt r1, UInt r2, return emit32(p, theInstr, endness_host); } +static UChar* mkFormX994 ( UChar* p, UInt inst_sel, + UInt rdst, UInt rsrc, VexEndness endness_host ) +{ + /* This issues an X-Form instruction with opc1 = 63 and opc2 = 994. The + specific instruction is given in bits[11:15]. */ + UInt theInstr; + vassert(inst_sel < 0x2); + vassert(rdst < 0x20); + vassert(rsrc < 0x20); + theInstr = ((63<<26) | (rdst<<21) | (inst_sel<<16) | (rsrc<<11) | (994 << 1)); + return emit32(p, theInstr, endness_host); +} + static UChar* mkFormXL ( UChar* p, UInt opc1, UInt f1, UInt f2, UInt f3, UInt opc2, UInt b0, VexEndness endness_host ) { @@ -4902,13 +5075,25 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, case Pfp_IDUTOQ: // xscvudqp p = mkFormVXR0( p, 63, fr_dst, 2, fr_src, 836, 0, endness_host ); break; + case Pfp_IQSTOQ: // xscvsqqp + p = mkFormVXR0( p, 63, fr_dst, 11, fr_src, 836, 0, endness_host ); + break; + case Pfp_IQUTOQ: // xscvuqqp + p = mkFormVXR0( p, 63, fr_dst, 3, fr_src, 836, 0, endness_host ); + break; + case Pfp_TRUNCFPQTOISQ: // xscvqpsqz + p = mkFormVXR0( p, 63, fr_dst, 8, fr_src, 836, 0, endness_host ); + break; case Pfp_TRUNCFPQTOISD: // xscvqpsdz p = mkFormVXR0( p, 63, fr_dst, 25, fr_src, 836, 0, endness_host ); break; - case Pfp_TRUNCFPQTOISW: // xscvqpswz + case Pfp_TRUNCFPQTOISW: // xscvqpswz p = mkFormVXR0( p, 63, fr_dst, 9, fr_src, 836, 0, endness_host ); break; - case Pfp_TRUNCFPQTOIUD: // xscvqpudz + case Pfp_TRUNCFPQTOIUQ: // xscvqpuqz + p = mkFormVXR0( p, 63, fr_dst, 0, fr_src, 836, 0, endness_host ); + break; + case Pfp_TRUNCFPQTOIUD: // xscvqpudz p = mkFormVXR0( p, 63, fr_dst, 17, fr_src, 836, 0, endness_host ); break; case Pfp_TRUNCFPQTOIUW: // xscvqpuwz @@ -5420,6 +5605,44 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, goto done; } + case Pin_AvBinaryInt128: { + UInt dst = vregEnc(i->Pin.AvBinaryInt128.dst); + UInt src1 = vregEnc(i->Pin.AvBinaryInt128.src1); + UInt src2 = vregEnc(i->Pin.AvBinaryInt128.src2); + int opc2; + + switch (i->Pin.AvBinaryInt128.op) { + case Pav_DivS128: opc2 = 267; break; //vdivsq + case Pav_DivU128: opc2 = 11; break; //vdivuq + case Pav_DivU128E: opc2 = 523; break; //vdiveuq + case Pav_DivS128E: opc2 = 779; break; //vdivesq + case Pav_ModS128: opc2 = 1803; break; //vmodsq + case Pav_ModU128: opc2 = 1547; break; //vmoduq + + default: + goto bad; + } + p = mkFormVX( p, 4, dst, src1, src2, opc2, endness_host ); + goto done; + } + + case Pin_AvTernaryInt128: { + UInt dst = vregEnc(i->Pin.AvTernaryInt128.dst); + UInt src1 = vregEnc(i->Pin.AvTernaryInt128.src1); + UInt src2 = vregEnc(i->Pin.AvTernaryInt128.src2); + UInt src3 = vregEnc(i->Pin.AvTernaryInt128.src3); + int opc2; + + switch (i->Pin.AvTernaryInt128.op) { + case Pav_2xMultU64Add128CarryOut: opc2 = 23; break; //vsumcud + + default: + goto bad; + } + p = mkFormVA( p, 4, dst, src1, src2, src3, opc2, endness_host ); + goto done; + } + case Pin_AvBin8x16: { UInt v_dst = vregEnc(i->Pin.AvBin8x16.dst); UInt v_srcL = vregEnc(i->Pin.AvBin8x16.srcL); @@ -6302,6 +6525,53 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, goto done; } + case Pin_XFormUnary994: { + + switch (i->Pin.XFormUnary994.op) { + + case Px_IQSTODFP: // dcffixqq + { + UInt dstHi = fregEnc(i->Pin.XFormUnary994.reg0); + UInt dstLo = fregEnc(i->Pin.XFormUnary994.reg1); + UInt src = vregEnc(i->Pin.XFormUnary994.reg2); + Int inst_sel = 0; + + /* Do instruction, 128-bit integer source operand, result in two + floating point registers VSR(10,11) */ + /* dcffixqq put result in VSR[10], VSR[11] dword 0 */ + p = mkFormX994( p, inst_sel, 10, src, endness_host ); + + /* Move results to destination floating point register pair. + Floating point regs are VSR[0] to VSR[31] */ + p = mkFormX( p, 63, dstHi, 0, 10, 72, 0, endness_host ); + p = mkFormX( p, 63, dstLo, 0, 11, 72, 0, endness_host ); + break; + } + + case Px_DFPTOIQS: // dctfixqq + { + UInt dstVSR = vregEnc(i->Pin.XFormUnary994.reg0); + UInt srcHi = fregEnc(i->Pin.XFormUnary994.reg1); + UInt srcLo = fregEnc(i->Pin.XFormUnary994.reg2); + Int inst_sel = 1; + + /* Setup the upper and lower registers of the source operand + * register pair. + */ + p = mkFormX( p, 63, 10, 0, srcHi, 72, 0, endness_host ); + p = mkFormX( p, 63, 11, 0, srcLo, 72, 0, endness_host ); + + /* Do instruction, two 64-bit source operands in registers floating + point registers VSR(10,11) */ + p = mkFormX994( p, inst_sel, dstVSR, 10, endness_host ); + break; + } + default: + goto bad; + } + goto done; + } + case Pin_EvCheck: { /* This requires a 32-bit dec/test in both 32- and 64-bit modes. */ diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index de21826a21..39dca08a2e 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -348,8 +348,12 @@ typedef Pfp_FPDTOQ, Pfp_IDSTOQ, Pfp_IDUTOQ, + Pfp_IQSTOQ, + Pfp_IQUTOQ, + Pfp_TRUNCFPQTOISQ, Pfp_TRUNCFPQTOISD, Pfp_TRUNCFPQTOISW, + Pfp_TRUNCFPQTOIUQ, Pfp_TRUNCFPQTOIUD, Pfp_TRUNCFPQTOIUW, Pfp_DFPADD, Pfp_DFPADDQ, @@ -357,6 +361,7 @@ typedef Pfp_DFPMUL, Pfp_DFPMULQ, Pfp_DFPDIV, Pfp_DFPDIVQ, Pfp_DQUAQ, Pfp_DRRNDQ, + Pfp_DFPTOIQ, Pfp_IQUTODFP, /* Binary */ Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, @@ -477,6 +482,39 @@ typedef extern const HChar* showPPCAvOp ( PPCAvOp ); +typedef + enum { + Pav_INVALIDBinary128, + + /* 128-bit integer Binary Divide */ + Pav_DivU128, Pav_DivS128, Pav_DivU128E, Pav_DivS128E, + Pav_ModU128, Pav_ModS128, + } + PPCAvOpBin128; + +extern const HChar* showPPCAvOpBin128 ( PPCAvOpBin128 ); + +typedef + enum { + Pav_INVALIDTri128, + + /* 128-bit integer */ + Pav_2xMultU64Add128CarryOut, + } + PPCAvOpTri128; + +extern const HChar* showPPCAvOpTri128 ( PPCAvOpTri128 ); + +typedef + enum { + Px_INVALID_XFormUnary994, + + /* 128-bit integer */ + Px_DFPTOIQS, Px_IQSTODFP, + } + PPCXFormUnary994; + +extern const HChar* showXFormUnary994 ( PPCXFormUnary994 ); /* --------- */ typedef @@ -543,6 +581,8 @@ typedef Pin_AvBinary, /* AV binary general reg,reg=>reg */ Pin_AvBinaryInt,/* AV binary reg,int=>reg */ + Pin_AvBinaryInt128,/* AV binary 128-bit reg, 128-bitint => 128-bit reg */ + Pin_AvTernaryInt128,/* AV ternary 128-bit reg, 128-bitint => 128-bit reg */ Pin_AvBin8x16, /* AV binary, 8x4 */ Pin_AvBin16x8, /* AV binary, 16x4 */ Pin_AvBin32x4, /* AV binary, 32x4 */ @@ -584,6 +624,8 @@ typedef * round */ Pin_DfpQuantize128, /* D128 quantize using register value, significance * round */ + + Pin_XFormUnary994, /* X-form instructions with opc1=63, opc2=994 */ Pin_EvCheck, /* Event check */ Pin_ProfInc /* 64-bit profile counter increment */ } @@ -860,6 +902,19 @@ typedef HReg src; PPCRI* val; } AvBinaryInt; + struct { + PPCAvOpBin128 op; + HReg dst; + HReg src1; + HReg src2; + } AvBinaryInt128; + struct { + PPCAvOpTri128 op; + HReg dst; + HReg src1; + HReg src2; + HReg src3; + } AvTernaryInt128; struct { PPCAvOp op; HReg dst; @@ -1068,6 +1123,12 @@ typedef HReg srcR_hi; HReg srcR_lo; } Dfp128Cmp; + struct { + PPCXFormUnary994 op; + HReg reg0; + HReg reg1; + HReg reg2; + } XFormUnary994; struct { PPCAMode* amCounter; PPCAMode* amFailAddr; @@ -1134,6 +1195,10 @@ extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); extern PPCInstr* PPCInstr_AvBinaryInt( PPCAvOp op, HReg dst, HReg src, PPCRI* val ); +extern PPCInstr* PPCInstr_AvBinaryInt128( PPCAvOpBin128 op, HReg dst, + HReg src1, HReg src2 ); +extern PPCInstr* PPCInstr_AvTernaryInt128( PPCAvOpTri128 op, HReg dst, + HReg src1, HReg src2, HReg src3 ); extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); @@ -1188,6 +1253,8 @@ extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR ); extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo, HReg srcR_hi, HReg srcR_lo ); +extern PPCInstr* PPCInstr_XFormUnary994 ( PPCXFormUnary994 op, HReg dst, + HReg srcHi, HReg srcLo ); extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter, PPCAMode* amFailAddr ); extern PPCInstr* PPCInstr_ProfInc ( void ); diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 38801a19e6..5ee6d1b6da 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -3383,6 +3383,39 @@ static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); return; + + case Iop_D128toI128S: { + HReg srcHi = INVALID_HREG; + HReg srcLo = INVALID_HREG; + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + HReg tmp = newVRegV(env); + PPCAMode* am_addr; + PPCAMode* am_addr4; + + /* Get the DF128 value, store in two 64-bit halves */ + iselDfp128Expr( &srcHi, &srcLo, env, e->Iex.Binop.arg2, IEndianess ); + + sub_from_sp( env, 16 ); // Move SP down 16 bytes + am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) ); + am_addr4 = advance4(env, am_addr); + + addInstr(env, PPCInstr_XFormUnary994(Px_DFPTOIQS, tmp, srcHi, srcLo)); + + // store the result in the VSR + addInstr(env, PPCInstr_AvLdSt( False/*store*/, 16, tmp, am_addr )); + + // load the two Ity_64 values + addInstr(env, PPCInstr_Load( 8, dstHi, am_addr, mode64 )); + addInstr(env, PPCInstr_Load( 8, dstLo, am_addr4, mode64 )); + + *rHi = dstHi; + *rLo = dstLo; + + add_to_sp( env, 16 ); // Reset SP + return; + } + default: break; } @@ -3392,6 +3425,35 @@ static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, /* --------- UNARY ops --------- */ if (e->tag == Iex_Unop) { switch (e->Iex.Unop.op) { + case Iop_ReinterpV128asI128: + case Iop_ReinterpF128asI128: { + HReg src; + HReg dstLo = newVRegI(env); + HReg dstHi = newVRegI(env); + PPCAMode* am_addr; + PPCAMode* am_addr4; + + if (e->Iex.Unop.op == Iop_ReinterpF128asI128) + src = iselFp128Expr(env, e->Iex.Unop.arg, IEndianess); + else + src = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); + + sub_from_sp( env, 16 ); // Move SP down 16 bytes + am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) ); + am_addr4 = advance4(env, am_addr); + + // store the Ity_F128 value + addInstr(env, PPCInstr_AvLdSt( False/*store*/, 16, src, am_addr )); + + // load the two Ity_64 values + addInstr(env, PPCInstr_Load( 8, dstHi, am_addr, mode64 )); + addInstr(env, PPCInstr_Load( 8, dstLo, am_addr4, mode64 )); + + *rHi = dstHi; + *rLo = dstLo; + add_to_sp( env, 16 ); // Reset SP + return; + } default: break; } @@ -4744,6 +4806,10 @@ static HReg iselFp128Expr_wrk( ISelEnv* env, const IRExpr* e, fpop = Pfp_TRUNCFPQTOIUD; goto do_Un_F128; case Iop_TruncF128toI32U: fpop = Pfp_TRUNCFPQTOIUW; goto do_Un_F128; + case Iop_TruncF128toI128U: + fpop = Pfp_TRUNCFPQTOIUQ; goto do_Un_F128; + case Iop_TruncF128toI128S: + fpop = Pfp_TRUNCFPQTOISQ; goto do_Un_F128; do_Un_F128: { HReg r_dst = newVRegV(env); @@ -4804,6 +4870,31 @@ static HReg iselFp128Expr_wrk( ISelEnv* env, const IRExpr* e, return r_dst; } + case Iop_ReinterpI128asF128: + { + PPCAMode* am_addr; + PPCAMode* am_addr4; + HReg rHi = INVALID_HREG; + HReg rLo = INVALID_HREG; + HReg dst = newVRegV(env); + + iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); + + sub_from_sp( env, 16 ); // Move SP down 16 bytes + am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) ); + am_addr4 = advance4(env, am_addr); + + // store the two 64-bit pars + addInstr(env, PPCInstr_Store( 8, am_addr, rHi, mode64 )); + addInstr(env, PPCInstr_Store( 8, am_addr4, rLo, mode64 )); + + // load as Ity_F128 + addInstr(env, PPCInstr_AvLdSt( True/*fetch*/, 16, dst, am_addr )); + + add_to_sp( env, 16 ); // Reset SP + return dst; + } + default: break; } /* switch (e->Iex.Unop.op) */ @@ -4892,6 +4983,40 @@ static HReg iselFp128Expr_wrk( ISelEnv* env, const IRExpr* e, return r_dst; } + case Iop_I128StoF128: + fpop = Pfp_IQSTOQ; goto do_Un_I128_F128_DFP_conversions; + case Iop_I128UtoF128: + fpop = Pfp_IQUTOQ; goto do_Un_I128_F128_DFP_conversions; + do_Un_I128_F128_DFP_conversions: { + PPCAMode* am_addr; + PPCAMode* am_addr4; + HReg rHi, rLo; + HReg r_tmp = newVRegV(env); + HReg r_dst = newVRegV(env); + + iselInt128Expr(&rHi,&rLo, env, e->Iex.Binop.arg2, IEndianess); + + /* Set host rounding mode for the conversion instruction */ + set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); + + sub_from_sp( env, 16 ); + + am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) ); + am_addr4 = advance4(env, am_addr); + + // store the two 64-bit halfs of the I128 + addInstr(env, PPCInstr_Store( 8, am_addr, rHi, mode64 )); + addInstr(env, PPCInstr_Store( 8, am_addr4, rLo, mode64 )); + + /* Fetch the I128 into an V128 register */ + addInstr(env, PPCInstr_AvLdSt( True/*fetch*/, 16, r_tmp, am_addr )); + addInstr(env, PPCInstr_Fp128Unary(fpop, r_dst, r_tmp)); + + add_to_sp( env, 16 ); // Reset SP + + return r_dst; + } + default: break; } /* switch (e->Iex.Binop.op) */ @@ -5459,6 +5584,41 @@ static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, *rLo = r_dstLo; return; } + + case Iop_I128StoD128: { + HReg tmpF128 = newVRegV(env); + HReg FdstHi = newVRegF(env); + HReg FdstLo = newVRegF(env); + HReg srcLo = newVRegI(env); + HReg srcHi = newVRegI(env); + PPCAMode* am_addr; + PPCAMode* am_addr4; + + set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); + + // Get the I128 value, store into a VSR register + iselInt128Expr(&srcHi, &srcLo, env, e->Iex.Binop.arg2, IEndianess); + + sub_from_sp( env, 16 ); // Move SP down 16 bytes + am_addr = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); + am_addr4 = advance4(env, am_addr); + + addInstr(env, PPCInstr_Store( 8, am_addr, srcHi, env->mode64 )); + addInstr(env, PPCInstr_Store( 8, am_addr4, srcLo, env->mode64 )); + + // load as Ity_F128 + addInstr(env, PPCInstr_AvLdSt( True/*fetch*/, 16, tmpF128, am_addr )); + + // do conversion + addInstr( env, PPCInstr_XFormUnary994( Px_IQSTODFP, FdstHi, FdstLo, + tmpF128 ) ); + + *rHi = FdstHi; + *rLo = FdstLo; + add_to_sp( env, 16 ); // Reset SP + return; + } + default: vex_printf( "ERROR: iselDfp128Expr_wrk, UNKNOWN binop case %d\n", (Int)e->Iex.Binop.op ); @@ -5594,6 +5754,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e, Bool mode64 = env->mode64; PPCAvOp op = Pav_INVALID; PPCAvFpOp fpop = Pavfp_INVALID; + PPCAvOpBin128 opav128 = Pav_INVALIDBinary128; + PPCAvOpTri128 optri128 = Pav_INVALIDTri128; IRType ty = typeOfIRExpr(env->type_env,e); vassert(e); vassert(ty == Ity_V128); @@ -5933,6 +6095,29 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e, return dst; } + case Iop_ReinterpI128asV128: { + PPCAMode* am_addr; + PPCAMode* am_addr4; + HReg rHi, rLo; + HReg dst = newVRegV(env); + + iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); + + sub_from_sp( env, 16 ); // Move SP down 16 bytes + am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) ); + am_addr4 = advance4(env, am_addr); + + // store the two 64-bit pars + addInstr(env, PPCInstr_Store( 8, am_addr, rHi, mode64 )); + addInstr(env, PPCInstr_Store( 8, am_addr4, rLo, mode64 )); + + // load as Ity_V128 + addInstr(env, PPCInstr_AvLdSt( True/*fetch*/, 16, dst, am_addr )); + + add_to_sp( env, 16 ); // Reset SP + return dst; + } + default: break; } /* switch (e->Iex.Unop.op) */ @@ -6295,6 +6480,20 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e, return dst; } + case Iop_DivU128: opav128 = Pav_DivU128; goto do_IntArithBinaryI128; + case Iop_DivS128: opav128 = Pav_DivS128; goto do_IntArithBinaryI128; + case Iop_DivU128E: opav128 = Pav_DivU128E; goto do_IntArithBinaryI128; + case Iop_DivS128E: opav128 = Pav_DivS128E; goto do_IntArithBinaryI128; + case Iop_ModU128: opav128 = Pav_ModU128; goto do_IntArithBinaryI128; + case Iop_ModS128: opav128 = Pav_ModS128; goto do_IntArithBinaryI128; + do_IntArithBinaryI128: { + HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); + HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); + HReg dst = newVRegV(env); + addInstr(env, PPCInstr_AvBinaryInt128(opav128, dst, arg1, arg2)); + return dst; + } + default: break; } /* switch (e->Iex.Binop.op) */ @@ -6322,6 +6521,18 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e, return dst; } + case Iop_2xMultU64Add128CarryOut: + optri128 = Pav_2xMultU64Add128CarryOut; goto do_IntArithTrinaryI128; + do_IntArithTrinaryI128: { + HReg arg1 = iselVecExpr(env, triop->arg1, IEndianess); + HReg arg2 = iselVecExpr(env, triop->arg2, IEndianess); + HReg arg3 = iselVecExpr(env, triop->arg3, IEndianess); + HReg dst = newVRegV(env); + addInstr(env, PPCInstr_AvTernaryInt128(optri128, dst, arg1, arg2, + arg3)); + return dst; + } + default: break; } /* switch (e->Iex.Triop.op) */ diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 1b8cffb771..96236a9f51 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -294,8 +294,10 @@ void ppIROp ( IROp op ) case Iop_MulF128: vex_printf("MulF128"); return; case Iop_DivF128: vex_printf("DivF128"); return; + case Iop_TruncF128toI128S: vex_printf("TruncF128toI128S"); return; case Iop_TruncF128toI64S: vex_printf("TruncF128toI64S"); return; case Iop_TruncF128toI32S: vex_printf("TruncF128toI32S"); return; + case Iop_TruncF128toI128U: vex_printf("TruncF128toI128U"); return; case Iop_TruncF128toI64U: vex_printf("TruncF128toI64U"); return; case Iop_TruncF128toI32U: vex_printf("TruncF128toI32U"); return; @@ -314,8 +316,10 @@ void ppIROp ( IROp op ) case Iop_F128LOtoF64: vex_printf("F128LOtoF64"); return; case Iop_I32StoF128: vex_printf("I32StoF128"); return; case Iop_I64StoF128: vex_printf("I64StoF128"); return; + case Iop_I128StoF128: vex_printf("I128StoF128"); return; case Iop_I32UtoF128: vex_printf("I32UtoF128"); return; case Iop_I64UtoF128: vex_printf("I64UtoF128"); return; + case Iop_I128UtoF128: vex_printf("I128UtoF128"); return; case Iop_F128toI32S: vex_printf("F128toI32S"); return; case Iop_F128toI64S: vex_printf("F128toI64S"); return; case Iop_F128toI32U: vex_printf("F128toI32U"); return; @@ -326,6 +330,8 @@ void ppIROp ( IROp op ) case Iop_F128toF32: vex_printf("F128toF32"); return; case Iop_F128toI128S: vex_printf("F128toI128"); return; case Iop_RndF128: vex_printf("RndF128"); return; + case Iop_I128StoD128: vex_printf("I128StoD128"); return; + case Iop_D128toI128S: vex_printf("D128toI128S"); return; case Iop_MAddF32: vex_printf("MAddF32"); return; case Iop_MSubF32: vex_printf("MSubF32"); return; @@ -434,6 +440,10 @@ void ppIROp ( IROp op ) case Iop_RoundF32toInt: vex_printf("RoundF32toInt"); return; case Iop_RoundF64toF32: vex_printf("RoundF64toF32"); return; + case Iop_ReinterpV128asI128: vex_printf("ReinterpV128asI128"); return; + case Iop_ReinterpI128asV128: vex_printf("ReinterpI128asV128"); return; + case Iop_ReinterpF128asI128: vex_printf("ReinterpF128asI128"); return; + case Iop_ReinterpI128asF128: vex_printf("ReinterpI128asF128"); return; case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return; case Iop_ReinterpI64asF64: vex_printf("ReinterpI64asF64"); return; case Iop_ReinterpF32asI32: vex_printf("ReinterpF32asI32"); return; @@ -1338,6 +1348,15 @@ void ppIROp ( IROp op ) case Iop_PwBitMtxXpose64x2: vex_printf("BitMatrixTranspose64x2"); return; + case Iop_DivU128: vex_printf("DivU128"); return; + ... [truncated message content] |
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From: Carl L. <ca...@so...> - 2021-02-25 17:58:47
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5defeb017f94686aa4c746729ff5eca35aa79fb1 commit 5defeb017f94686aa4c746729ff5eca35aa79fb1 Author: Carl Love <ce...@us...> Date: Mon Feb 22 12:11:05 2021 -0600 PPC64: Fix naming trinary to ternary Diff: --- VEX/priv/host_ppc_defs.c | 40 ++++++++++++++++++++-------------------- VEX/priv/host_ppc_defs.h | 6 +++--- VEX/priv/host_ppc_isel.c | 2 +- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index 6c298fa18b..843009422e 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -1007,13 +1007,13 @@ PPCInstr* PPCInstr_Fp128Binary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { i->Pin.Fp128Binary.srcR = srcR; return i; } -PPCInstr* PPCInstr_Fp128Trinary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { +PPCInstr* PPCInstr_Fp128Ternnary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) { PPCInstr* i = LibVEX_Alloc_inline( sizeof(PPCInstr) ); - i->tag = Pin_Fp128Trinary; - i->Pin.Fp128Trinary.op = op; - i->Pin.Fp128Trinary.dst = dst; - i->Pin.Fp128Trinary.srcL = srcL; - i->Pin.Fp128Trinary.srcR = srcR; + i->tag = Pin_Fp128Ternnary; + i->Pin.Fp128Ternnary.op = op; + i->Pin.Fp128Ternnary.dst = dst; + i->Pin.Fp128Ternnary.srcL = srcL; + i->Pin.Fp128Ternnary.srcR = srcR; return i; } PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, @@ -1831,13 +1831,13 @@ void ppPPCInstr ( const PPCInstr* i, Bool mode64 ) vex_printf(","); ppHRegPPC(i->Pin.Fp128Binary.srcR); return; - case Pin_Fp128Trinary: - vex_printf("%s ", showPPCFpOp(i->Pin.Fp128Trinary.op)); - ppHRegPPC(i->Pin.Fp128Trinary.dst); + case Pin_Fp128Ternnary: + vex_printf("%s ", showPPCFpOp(i->Pin.Fp128Ternnary.op)); + ppHRegPPC(i->Pin.Fp128Ternnary.dst); vex_printf(","); - ppHRegPPC(i->Pin.Fp128Trinary.srcL); + ppHRegPPC(i->Pin.Fp128Ternary.srcL); vex_printf(","); - ppHRegPPC(i->Pin.Fp128Trinary.srcR); + ppHRegPPC(i->Pin.Fp128Ternary.srcR); return; case Pin_FpMulAcc: vex_printf("%s ", showPPCFpOp(i->Pin.FpMulAcc.op)); @@ -2520,10 +2520,10 @@ void getRegUsage_PPCInstr ( HRegUsage* u, const PPCInstr* i, Bool mode64 ) addHRegUse(u, HRmRead, i->Pin.Fp128Binary.srcL); addHRegUse(u, HRmRead, i->Pin.Fp128Binary.srcR); return; - case Pin_Fp128Trinary: - addHRegUse(u, HRmModify, i->Pin.Fp128Trinary.dst); - addHRegUse(u, HRmRead, i->Pin.Fp128Trinary.srcL); - addHRegUse(u, HRmRead, i->Pin.Fp128Trinary.srcR); + case Pin_Fp128Ternary: + addHRegUse(u, HRmModify, i->Pin.Fp128Ternary.dst); + addHRegUse(u, HRmRead, i->Pin.Fp128Ternary.srcL); + addHRegUse(u, HRmRead, i->Pin.Fp128Ternary.srcR); return; case Pin_FpMulAcc: addHRegUse(u, HRmWrite, i->Pin.FpMulAcc.dst); @@ -2889,10 +2889,10 @@ void mapRegs_PPCInstr ( HRegRemap* m, PPCInstr* i, Bool mode64 ) mapReg(m, &i->Pin.Fp128Binary.srcL); mapReg(m, &i->Pin.Fp128Binary.srcR); return; - case Pin_Fp128Trinary: - mapReg(m, &i->Pin.Fp128Trinary.dst); - mapReg(m, &i->Pin.Fp128Trinary.srcL); - mapReg(m, &i->Pin.Fp128Trinary.srcR); + case Pin_Fp128Ternary: + mapReg(m, &i->Pin.Fp128Ternary.dst); + mapReg(m, &i->Pin.Fp128Ternary.srcL); + mapReg(m, &i->Pin.Fp128Ternary.srcR); return; case Pin_FpMulAcc: mapReg(m, &i->Pin.FpMulAcc.dst); @@ -4992,7 +4992,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, goto done; } - case Pin_Fp128Trinary: { + case Pin_Fp128Ternary: { /* Note Fp128 instructions use the vector registers */ UInt fr_dst = vregEnc(i->Pin.Fp128Binary.dst); UInt fr_srcL = vregEnc(i->Pin.Fp128Binary.srcL); diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index 70c3b6cb96..de21826a21 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -526,7 +526,7 @@ typedef Pin_FpBinary, /* FP binary op */ Pin_Fp128Unary, /* FP unary op for 128-bit floating point */ Pin_Fp128Binary, /* FP binary op for 128-bit floating point */ - Pin_Fp128Trinary, /* FP trinary op for 128-bit floating point */ + Pin_Fp128Ternary, /* FP ternary op for 128-bit floating point */ Pin_FpMulAcc, /* FP multipy-accumulate style op */ Pin_FpLdSt, /* FP load/store */ Pin_FpSTFIW, /* stfiwx */ @@ -776,7 +776,7 @@ typedef HReg dst; HReg srcL; HReg srcR; - } Fp128Trinary; + } Fp128Ternary; struct { PPCFpOp op; HReg dst; @@ -1112,7 +1112,7 @@ extern PPCInstr* PPCInstr_MFence ( void ); extern PPCInstr* PPCInstr_Fp128Unary ( PPCFpOp op, HReg dst, HReg src ); extern PPCInstr* PPCInstr_Fp128Binary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); -extern PPCInstr* PPCInstr_Fp128Trinary ( PPCFpOp op, HReg dst, HReg srcL, +extern PPCInstr* PPCInstr_Fp128Ternary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR); extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 3c76feb2d5..38801a19e6 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -5002,7 +5002,7 @@ static HReg iselFp128Expr_wrk( ISelEnv* env, const IRExpr* e, HReg r_srcR = iselFp128Expr(env, qop->arg4, IEndianess); - addInstr(env, PPCInstr_Fp128Trinary(fpop, r_dst, r_srcL, r_srcR)); + addInstr(env, PPCInstr_Fp128Ternary(fpop, r_dst, r_srcL, r_srcR)); return r_dst; } |
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From: Carl L. <ca...@so...> - 2021-02-25 17:58:37
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=953f54085dfb06e53b47d1d08e4014bac2202282 commit 953f54085dfb06e53b47d1d08e4014bac2202282 Author: Carl Love <ce...@us...> Date: Mon Jan 25 11:44:12 2021 -0600 PPC64: Add ACC register file registers to get_otrack_shadow_offset_wrkget_otrack_shadow_offset_wrk() Diff: --- memcheck/mc_machine.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c index 7a87143b53..a95bfd9959 100644 --- a/memcheck/mc_machine.c +++ b/memcheck/mc_machine.c @@ -330,6 +330,72 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62); if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63); + /* ACC register file. Each register is 128 bits. */ + if (o >= GOF(ACC_0_r0) && o+sz <= GOF(ACC_0_r0)+SZB(ACC_0_r0)) + return 0+ GOF(ACC_0_r0); + if (o >= GOF(ACC_0_r1) && o+sz <= GOF(ACC_0_r1)+SZB(ACC_0_r1)) + return 0+ GOF(ACC_0_r1); + if (o >= GOF(ACC_0_r2) && o+sz <= GOF(ACC_0_r2)+SZB(ACC_0_r2)) + return 0+ GOF(ACC_0_r2); + if (o >= GOF(ACC_0_r3) && o+sz <= GOF(ACC_0_r3)+SZB(ACC_0_r3)) + return 0+ GOF(ACC_0_r3); + if (o >= GOF(ACC_1_r0) && o+sz <= GOF(ACC_1_r0)+SZB(ACC_1_r0)) + return 0+ GOF(ACC_1_r0); + if (o >= GOF(ACC_1_r1) && o+sz <= GOF(ACC_1_r1)+SZB(ACC_1_r1)) + return 0+ GOF(ACC_1_r1); + if (o >= GOF(ACC_1_r2) && o+sz <= GOF(ACC_1_r2)+SZB(ACC_1_r2)) + return 0+ GOF(ACC_1_r2); + if (o >= GOF(ACC_1_r3) && o+sz <= GOF(ACC_1_r3)+SZB(ACC_1_r3)) + return 0+ GOF(ACC_1_r3); + if (o >= GOF(ACC_2_r0) && o+sz <= GOF(ACC_2_r0)+SZB(ACC_2_r0)) + return 0+ GOF(ACC_2_r0); + if (o >= GOF(ACC_2_r1) && o+sz <= GOF(ACC_2_r1)+SZB(ACC_2_r1)) + return 0+ GOF(ACC_2_r1); + if (o >= GOF(ACC_2_r2) && o+sz <= GOF(ACC_2_r2)+SZB(ACC_2_r2)) + return 0+ GOF(ACC_2_r2); + if (o >= GOF(ACC_2_r3) && o+sz <= GOF(ACC_2_r3)+SZB(ACC_2_r3)) + return 0+ GOF(ACC_2_r3); + if (o >= GOF(ACC_3_r0) && o+sz <= GOF(ACC_3_r0)+SZB(ACC_3_r0)) + return 0+ GOF(ACC_3_r0); + if (o >= GOF(ACC_3_r1) && o+sz <= GOF(ACC_3_r1)+SZB(ACC_3_r1)) + return 0+ GOF(ACC_3_r1); + if (o >= GOF(ACC_3_r2) && o+sz <= GOF(ACC_3_r2)+SZB(ACC_3_r2)) + return 0+ GOF(ACC_3_r2); + if (o >= GOF(ACC_3_r3) && o+sz <= GOF(ACC_3_r3)+SZB(ACC_3_r3)) + return 0+ GOF(ACC_3_r3); + if (o >= GOF(ACC_4_r0) && o+sz <= GOF(ACC_4_r0)+SZB(ACC_4_r0)) + return 0+ GOF(ACC_4_r0); + if (o >= GOF(ACC_4_r1) && o+sz <= GOF(ACC_4_r1)+SZB(ACC_4_r1)) + return 0+ GOF(ACC_4_r1); + if (o >= GOF(ACC_4_r2) && o+sz <= GOF(ACC_4_r2)+SZB(ACC_4_r2)) + return 0+ GOF(ACC_4_r2); + if (o >= GOF(ACC_4_r3) && o+sz <= GOF(ACC_4_r3)+SZB(ACC_4_r3)) + return 0+ GOF(ACC_4_r3); + if (o >= GOF(ACC_5_r0) && o+sz <= GOF(ACC_5_r0)+SZB(ACC_5_r0)) + return 0+ GOF(ACC_5_r0); + if (o >= GOF(ACC_5_r1) && o+sz <= GOF(ACC_5_r1)+SZB(ACC_5_r1)) + return 0+ GOF(ACC_5_r1); + if (o >= GOF(ACC_5_r2) && o+sz <= GOF(ACC_5_r2)+SZB(ACC_5_r2)) + return 0+ GOF(ACC_5_r2); + if (o >= GOF(ACC_5_r3) && o+sz <= GOF(ACC_5_r3)+SZB(ACC_5_r3)) + return 0+ GOF(ACC_5_r3); + if (o >= GOF(ACC_6_r0) && o+sz <= GOF(ACC_6_r0)+SZB(ACC_6_r0)) + return 0+ GOF(ACC_6_r0); + if (o >= GOF(ACC_6_r1) && o+sz <= GOF(ACC_6_r1)+SZB(ACC_6_r1)) + return 0+ GOF(ACC_6_r1); + if (o >= GOF(ACC_6_r2) && o+sz <= GOF(ACC_6_r2)+SZB(ACC_6_r2)) + return 0+ GOF(ACC_6_r2); + if (o >= GOF(ACC_6_r3) && o+sz <= GOF(ACC_6_r3)+SZB(ACC_6_r3)) + return 0+ GOF(ACC_6_r3); + if (o >= GOF(ACC_7_r0) && o+sz <= GOF(ACC_7_r0)+SZB(ACC_7_r0)) + return 0+ GOF(ACC_7_r0); + if (o >= GOF(ACC_7_r1) && o+sz <= GOF(ACC_7_r1)+SZB(ACC_7_r1)) + return 0+ GOF(ACC_7_r1); + if (o >= GOF(ACC_7_r2) && o+sz <= GOF(ACC_7_r2)+SZB(ACC_7_r2)) + return 0+ GOF(ACC_7_r2); + if (o >= GOF(ACC_7_r3) && o+sz <= GOF(ACC_7_r3)+SZB(ACC_7_r3)) + return 0+ GOF(ACC_7_r3); + VG_(printf)("MC_(get_otrack_shadow_offset)(ppc64)(off=%d,sz=%d)\n", offset,szB); tl_assert(0); @@ -533,6 +599,8 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62); if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63); + /* ACC registers are not supported on ppc32. */ + VG_(printf)("MC_(get_otrack_shadow_offset)(ppc32)(off=%d,sz=%d)\n", offset,szB); tl_assert(0); |
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From: Carl L. <ca...@so...> - 2021-02-25 17:58:27
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4ebdf8653859ac31f4f9e6c0f4ec4e0114498d7c commit 4ebdf8653859ac31f4f9e6c0f4ec4e0114498d7c Author: Carl Love <ce...@us...> Date: Fri Jan 22 13:15:20 2021 -0600 PPC64: Fix V-bit casting for existing Iops. Iop_TruncF128toI64S, Iop_TruncF128toI32S, Iop_TruncF128toI64U, Iop_TruncF128toI32U, Iop_ReinterpI32asF32, Iop_ReinterpF32asI32, Iop_ReinterpF64asI64, Iop_ReinterpI64asF64, Iop_ReinterpI64asD64, Iop_ReinterpD64asI64 Diff: --- memcheck/mc_translate.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 288895dea2..8c515494f3 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -5080,10 +5080,6 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_NegF128: case Iop_AbsF128: case Iop_RndF128: - case Iop_TruncF128toI64S: /* F128 -> I64S */ - case Iop_TruncF128toI32S: /* F128 -> I32S (result stored in 64-bits) */ - case Iop_TruncF128toI64U: /* F128 -> I64U */ - case Iop_TruncF128toI32U: /* F128 -> I32U (result stored in 64-bits) */ return mkPCastTo(mce, Ity_I128, vatom); case Iop_BCD128toI128S: @@ -5094,6 +5090,16 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) // FIXME JRS 2018-Nov-15. This is surely not correct! return vatom; + case Iop_ReinterpI32asF32: + case Iop_ReinterpF32asI32: + return assignNew('V', mce, Ity_I32, vatom); + + case Iop_ReinterpF64asI64: + case Iop_ReinterpI64asF64: + case Iop_ReinterpI64asD64: + case Iop_ReinterpD64asI64: + return assignNew('V', mce, Ity_I64, vatom); + case Iop_I32StoF128: /* signed I32 -> F128 */ case Iop_I64StoF128: /* signed I64 -> F128 */ case Iop_I32UtoF128: /* unsigned I32 -> F128 */ @@ -5224,12 +5230,6 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_64to1: return assignNew('V', mce, Ity_I1, unop(Iop_64to1, vatom)); - case Iop_ReinterpF64asI64: - case Iop_ReinterpI64asF64: - case Iop_ReinterpI32asF32: - case Iop_ReinterpF32asI32: - case Iop_ReinterpI64asD64: - case Iop_ReinterpD64asI64: case Iop_NotV256: case Iop_NotV128: case Iop_Not64: @@ -5286,9 +5286,13 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Ctz32x4: return mkPCast32x4(mce, vatom); + case Iop_TruncF128toI32S: /* F128 -> I32S (result stored in 64-bits) */ + case Iop_TruncF128toI32U: /* F128 -> I32U (result stored in 64-bits) */ case Iop_CmpwNEZ32: return mkPCastTo(mce, Ity_I32, vatom); + case Iop_TruncF128toI64S: /* F128 -> I64S */ + case Iop_TruncF128toI64U: /* F128 -> I64U */ case Iop_CmpwNEZ64: return mkPCastTo(mce, Ity_I64, vatom); |