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From: Andreas A. <ar...@so...> - 2020-03-13 19:37:04
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=95df121886a398f2bf5205eb63d5a9bceca5a764 commit 95df121886a398f2bf5205eb63d5a9bceca5a764 Author: Andreas Arnez <ar...@li...> Date: Fri Mar 13 17:20:20 2020 +0100 s390x: Actually use "load on condition" for conditional moves Although the implementation of the cond_move insn is prepared to emit "load on condition" instructions, it doesn't, because of a reversed check. The check is supposed to prevent emitting LOCx instructions when the condition code mask is set to "always", but it's accidentally negated. Fix the reversal of the check, so LOCx instructions are actually emitted when applicable. Diff: --- VEX/priv/host_s390_defs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 98c160d712..80e56f603a 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -10105,7 +10105,7 @@ s390_insn_cond_move_emit(UChar *buf, const s390_insn *insn) if (s390_host_has_lsc) { /* LOCx is not the preferred way to implement an unconditional load. */ - if (cond != S390_CC_ALWAYS) goto use_branch_insn; + if (cond == S390_CC_ALWAYS) goto use_branch_insn; switch (src.tag) { case S390_OPND_REG: |
|
From: Andreas A. <ar...@so...> - 2020-03-13 19:36:56
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b0eb7193a52c562bb25fd605781f4d8d05c21d52 commit b0eb7193a52c562bb25fd605781f4d8d05c21d52 Author: Andreas Arnez <ar...@li...> Date: Mon Mar 9 17:26:26 2020 +0100 s390x: Mark register usage with HRmModify when applicable Instead of marking register usage for the same register with HRmRead and HRmWrite separately, use HRmModify instead. This makes the code a bit easier to read. Diff: --- VEX/priv/host_s390_defs.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 04da842ee2..98c160d712 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -681,31 +681,26 @@ s390_insn_get_reg_usage(HRegUsage *u, const s390_insn *insn) break; case S390_INSN_ALU: - addHRegUse(u, HRmWrite, insn->variant.alu.dst); - addHRegUse(u, HRmRead, insn->variant.alu.dst); /* op1 */ + addHRegUse(u, HRmModify, insn->variant.alu.dst); /* op1 */ s390_opnd_RMI_get_reg_usage(u, insn->variant.alu.op2); break; case S390_INSN_SMUL: case S390_INSN_UMUL: - addHRegUse(u, HRmRead, insn->variant.mul.dst_lo); /* op1 */ - addHRegUse(u, HRmWrite, insn->variant.mul.dst_lo); + addHRegUse(u, HRmModify, insn->variant.mul.dst_lo); /* op1 */ addHRegUse(u, HRmWrite, insn->variant.mul.dst_hi); s390_opnd_RMI_get_reg_usage(u, insn->variant.mul.op2); break; case S390_INSN_SDIV: case S390_INSN_UDIV: - addHRegUse(u, HRmRead, insn->variant.div.op1_lo); - addHRegUse(u, HRmRead, insn->variant.div.op1_hi); - addHRegUse(u, HRmWrite, insn->variant.div.op1_lo); - addHRegUse(u, HRmWrite, insn->variant.div.op1_hi); + addHRegUse(u, HRmModify, insn->variant.div.op1_lo); + addHRegUse(u, HRmModify, insn->variant.div.op1_hi); s390_opnd_RMI_get_reg_usage(u, insn->variant.div.op2); break; case S390_INSN_DIVS: - addHRegUse(u, HRmRead, insn->variant.divs.op1); - addHRegUse(u, HRmWrite, insn->variant.divs.op1); /* quotient */ + addHRegUse(u, HRmModify, insn->variant.divs.op1); /* quotient */ addHRegUse(u, HRmWrite, insn->variant.divs.rem); /* remainder */ s390_opnd_RMI_get_reg_usage(u, insn->variant.divs.op2); break; @@ -788,19 +783,16 @@ s390_insn_get_reg_usage(HRegUsage *u, const s390_insn *insn) } case S390_INSN_BFP_TRIOP: - addHRegUse(u, HRmWrite, insn->variant.bfp_triop.dst); - addHRegUse(u, HRmRead, insn->variant.bfp_triop.dst); /* first */ + addHRegUse(u, HRmModify, insn->variant.bfp_triop.dst); /* first */ addHRegUse(u, HRmRead, insn->variant.bfp_triop.op2); /* second */ addHRegUse(u, HRmRead, insn->variant.bfp_triop.op3); /* third */ break; case S390_INSN_BFP_BINOP: - addHRegUse(u, HRmWrite, insn->variant.bfp_binop.dst_hi); - addHRegUse(u, HRmRead, insn->variant.bfp_binop.dst_hi); /* left */ + addHRegUse(u, HRmModify, insn->variant.bfp_binop.dst_hi); /* left */ addHRegUse(u, HRmRead, insn->variant.bfp_binop.op2_hi); /* right */ if (insn->size == 16) { - addHRegUse(u, HRmWrite, insn->variant.bfp_binop.dst_lo); - addHRegUse(u, HRmRead, insn->variant.bfp_binop.dst_lo); /* left */ + addHRegUse(u, HRmModify, insn->variant.bfp_binop.dst_lo); /* left */ addHRegUse(u, HRmRead, insn->variant.bfp_binop.op2_lo); /* right */ } break; @@ -957,8 +949,7 @@ s390_insn_get_reg_usage(HRegUsage *u, const s390_insn *insn) break; case S390_INSN_VEC_AMODEINTOP: - addHRegUse(u, HRmRead, insn->variant.vec_amodeintop.dst); - addHRegUse(u, HRmWrite, insn->variant.vec_amodeintop.dst); + addHRegUse(u, HRmModify, insn->variant.vec_amodeintop.dst); s390_amode_get_reg_usage(u, insn->variant.vec_amodeintop.op2); addHRegUse(u, HRmRead, insn->variant.vec_amodeintop.op3); break; |
|
From: Andreas A. <ar...@so...> - 2020-03-13 19:36:49
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ea91ebf5dec2a8e469b5cabdb9ff11bc2f3b27b6 commit ea91ebf5dec2a8e469b5cabdb9ff11bc2f3b27b6 Author: Andreas Arnez <ar...@li...> Date: Mon Mar 9 15:14:16 2020 +0100 s390x: Enable 1- and 2-byte operands for v-test The v-test operation tests its operand against zero and sets the condition code accordingly. So far the operation was only supported for 4- and 8-byte operands. Lift this restriction and enable 1- and 2-byte operands for v-test, using the z/Architecture "test under mask" instructions TM, TMY, and TMLL. Exploit this in the instruction selector, getting rid of the conversion to a 4-byte operand. This slightly reduces the generated code on s390x. Diff: --- VEX/priv/host_s390_defs.c | 81 ++++++++++++++++++++++++++++++++++++----------- VEX/priv/host_s390_isel.c | 15 +-------- 2 files changed, 64 insertions(+), 32 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 1cd469637e..04da842ee2 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -2081,6 +2081,36 @@ s390_emit_NILL(UChar *p, UChar r1, UShort i2) } +static UChar * +s390_emit_TM(UChar *p, UChar i2, UChar b1, UShort d1) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC3(MNM, UDXB, INT), "tm", d1, 0, b1, i2); + + return emit_SI(p, 0x91000000, i2, b1, d1); +} + + +static UChar * +s390_emit_TMY(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC3(MNM, SDXB, INT), "tmy", dh1, dl1, 0, b1, (Int)(Char)i2); + + return emit_SIY(p, 0xeb0000000051ULL, i2, b1, dl1, dh1); +} + + +static UChar * +s390_emit_TMLL(UChar *p, UChar r1, UShort i2) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC3(MNM, GPR, UINT), "tmll", r1, i2); + + return emit_RI(p, 0xa7010000, r1, i2); +} + + static UChar * s390_emit_BASR(UChar *p, UChar r1, UChar r2) { @@ -6490,7 +6520,7 @@ s390_insn_test(UChar size, s390_opnd_RMI src) { s390_insn *insn = LibVEX_Alloc_inline(sizeof(s390_insn)); - vassert(size == 4 || size == 8); + vassert(size == 1 || size == 2 || size == 4 || size == 8); insn->tag = S390_INSN_TEST; insn->size = size; @@ -9300,9 +9330,7 @@ s390_insn_unop_emit(UChar *buf, const s390_insn *insn) } -/* Only 4-byte and 8-byte operands are handled. 1-byte and 2-byte - comparisons will have been converted to 4-byte comparisons in - s390_isel_cc and should not occur here. */ +/* Test operand for zero. */ static UChar * s390_insn_test_emit(UChar *buf, const s390_insn *insn) { @@ -9315,6 +9343,12 @@ s390_insn_test_emit(UChar *buf, const s390_insn *insn) UInt reg = hregNumber(opnd.variant.reg); switch (insn->size) { + case 1: + return s390_emit_TMLL(buf, reg, 0xff); + + case 2: + return s390_emit_TMLL(buf, reg, 0xffff); + case 4: return s390_emit_LTR(buf, reg, reg); @@ -9333,6 +9367,27 @@ s390_insn_test_emit(UChar *buf, const s390_insn *insn) Int d = am->d; switch (insn->size) { + case 1: + switch (am->tag) { + case S390_AMODE_B12: + return s390_emit_TM(buf, 0xff, b, d); + case S390_AMODE_B20: + return s390_emit_TMY(buf, 0xff, b, DISP20(d)); + default: + buf = s390_emit_LB(buf, R0, x, b, DISP20(d)); + return s390_emit_TMLL(buf, R0, 0xff); + } + + case 2: + switch (am->tag) { + case S390_AMODE_B12: + buf = s390_emit_LH(buf, R0, x, b, d); + return s390_emit_TMLL(buf, R0, 0xffff); + default: + buf = s390_emit_LHY(buf, R0, x, b, DISP20(d)); + return s390_emit_TMLL(buf, R0, 0xffff); + } + case 4: return s390_emit_LTw(buf, R0, x, b, DISP20(d)); @@ -9345,20 +9400,10 @@ s390_insn_test_emit(UChar *buf, const s390_insn *insn) } case S390_OPND_IMMEDIATE: { - ULong value = opnd.variant.imm; - - switch (insn->size) { - case 4: - buf = s390_emit_load_32imm(buf, R0, value); - return s390_emit_LTR(buf, R0, R0); - - case 8: - buf = s390_emit_load_64imm(buf, R0, value); - return s390_emit_LTGR(buf, R0, R0); - - default: - goto fail; - } + if (opnd.variant.imm == 0) + return s390_emit_CR(buf, R0, R0); + else + return s390_emit_OILL(buf, R0, 1); } default: diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 4d0cf1721b..b374024c8c 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -3514,20 +3514,7 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) } case Iop_CmpNEZ8: - case Iop_CmpNEZ16: { - s390_opnd_RMI src; - s390_unop_t op; - HReg dst; - - op = (cond->Iex.Unop.op == Iop_CmpNEZ8) ? S390_ZERO_EXTEND_8 - : S390_ZERO_EXTEND_16; - dst = newVRegI(env); - src = s390_isel_int_expr_RMI(env, arg); - addInstr(env, s390_insn_unop(4, op, dst, src)); - addInstr(env, s390_insn_test(4, s390_opnd_reg(dst))); - return S390_CC_NE; - } - + case Iop_CmpNEZ16: case Iop_CmpNEZ32: case Iop_CmpNEZ64: { s390_opnd_RMI src; |
|
From: Andreas A. <ar...@so...> - 2020-03-13 19:36:41
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5a35fe81017b63daea47f062894604979f25535e commit 5a35fe81017b63daea47f062894604979f25535e Author: Andreas Arnez <ar...@li...> Date: Wed Feb 5 18:18:49 2020 +0100 s390x: Support And1/Or1, improve handling of Int1 expressions This provides an instruction selector for Int1-expressions that supports And1 and Or1. This implementation tries to keep values in registers as much as possible, to avoid too many conversions from a Boolean value to a condition code or vice versa. To this end, the new function s390_isel_int1_expr() is added, which handles bit-typed expressions that are supposed to end up in a register. Also change the representation of Int1 values in registers and always sign-extend them to 64 bits. Diff: --- VEX/priv/host_s390_defs.c | 13 +++-- VEX/priv/host_s390_isel.c | 118 ++++++++++++++++++++++++---------------------- 2 files changed, 67 insertions(+), 64 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index de267078e1..1cd469637e 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -9376,25 +9376,24 @@ s390_insn_cc2bool_emit(UChar *buf, const s390_insn *insn) UChar r1 = hregNumber(insn->variant.cc2bool.dst); s390_cc_t cond = insn->variant.cc2bool.cond; - /* Make the destination register be 1 or 0, depending on whether + /* Make the destination register be -1 or 0, depending on whether the relevant condition holds. A 64-bit value is computed. */ if (cond == S390_CC_ALWAYS) - return s390_emit_LGHI(buf, r1, 1); /* r1 = 1 */ + return s390_emit_LGHI(buf, r1, -1); /* r1 = -1 */ /* If LOCGHI is available, use it. */ if (s390_host_has_lsc2) { - /* Clear r1, then load immediate 1 on condition. */ + /* Clear r1, then load immediate -1 on condition. */ buf = s390_emit_LGHI(buf, r1, 0); if (cond != S390_CC_NEVER) - buf = s390_emit_LOCGHI(buf, r1, 1, cond); + buf = s390_emit_LOCGHI(buf, r1, -1, cond); return buf; } buf = s390_emit_load_cc(buf, r1); /* r1 = cc */ buf = s390_emit_LGHI(buf, R0, cond); /* r0 = mask */ - buf = s390_emit_SLLG(buf, r1, R0, r1, DISP20(0)); /* r1 = mask << cc */ - buf = s390_emit_SRLG(buf, r1, r1, 0, DISP20(3)); /* r1 = r1 >> 3 */ - buf = s390_emit_NILL(buf, r1, 1); /* r1 = r1 & 0x1 */ + buf = s390_emit_SLLG(buf, r1, R0, r1, DISP20(60)); /* r1 = mask << (cc+60) */ + buf = s390_emit_SRAG(buf, r1, r1, 0, DISP20(63)); /* r1 = r1 >> 63 */ return buf; } diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 00b4aee818..4d0cf1721b 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -127,6 +127,7 @@ static HReg s390_isel_int_expr(ISelEnv *, IRExpr *); static s390_amode *s390_isel_amode(ISelEnv *, IRExpr *); static s390_amode *s390_isel_amode_b12_b20(ISelEnv *, IRExpr *); static s390_cc_t s390_isel_cc(ISelEnv *, IRExpr *); +static HReg s390_isel_int1_expr(ISelEnv *env, IRExpr *expr, HReg dst); static s390_opnd_RMI s390_isel_int_expr_RMI(ISelEnv *, IRExpr *); static void s390_isel_int128_expr(HReg *, HReg *, ISelEnv *, IRExpr *); static HReg s390_isel_float_expr(ISelEnv *, IRExpr *); @@ -1763,9 +1764,7 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) /* Expressions whose argument is 1-bit wide */ if (typeOfIRExpr(env->type_env, arg) == Ity_I1) { - s390_cc_t cond = s390_isel_cc(env, arg); - dst = newVRegI(env); /* Result goes into a new register */ - addInstr(env, s390_insn_cc2bool(dst, cond)); + dst = s390_isel_int1_expr(env, arg, INVALID_HREG); switch (unop) { case Iop_1Uto8: @@ -1784,16 +1783,9 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) case Iop_1Sto8: case Iop_1Sto16: case Iop_1Sto32: - shift.variant.imm = 31; - addInstr(env, s390_insn_alu(4, S390_ALU_LSH, dst, shift)); - addInstr(env, s390_insn_alu(4, S390_ALU_RSHA, dst, shift)); - break; - case Iop_1Sto64: - shift.variant.imm = 63; - addInstr(env, s390_insn_alu(8, S390_ALU_LSH, dst, shift)); - addInstr(env, s390_insn_alu(8, S390_ALU_RSHA, dst, shift)); - break; + /* Int1 values are already sign-extended to 64 bits. */ + return dst; default: goto irreducible; @@ -3466,7 +3458,8 @@ s390_isel_dfp_expr(ISelEnv *env, IRExpr *expr) /*--- ISEL: Condition Code ---*/ /*---------------------------------------------------------*/ -/* This function handles all operators that produce a 1-bit result */ +/* Handle all operators that produce a 1-bit result. This function is mutually + recursive with s390_isel_int1_expr. */ static s390_cc_t s390_isel_cc(ISelEnv *env, IRExpr *cond) { @@ -3554,45 +3547,14 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) if (cond->tag == Iex_Binop) { IRExpr *arg1 = cond->Iex.Binop.arg1; IRExpr *arg2 = cond->Iex.Binop.arg2; - HReg reg1, reg2; - - /* sewardj 2019Nov30: This will be needed when chasing through conditional - branches in guest_generic_bb_to_IR.c is enabled on s390x. - Unfortunately that is currently disabled on s390x as it causes - mysterious segfaults and also exposes some unhandled Iex_ITE cases in - this instruction selector. The following Iop_And1/Iop_Or1 cases are - also needed when enabled. The code below is *believed* to be correct, - and has been lightly tested, but it is #if 0'd until such time as we - need it. */ -# if 0 - /* FIXME: We could (and probably should) do a lot better here, by using - the iselCondCode_C/_R scheme used in the amd64 insn selector. */ + + /* And1 / Or1 */ if (cond->Iex.Binop.op == Iop_And1 || cond->Iex.Binop.op == Iop_Or1) { - /* In short: force both operands into registers, AND or OR them, mask - off all but the lowest bit, then convert the result back into a - condition code. */ - const s390_opnd_RMI one = s390_opnd_imm(1); - - HReg x_as_64 = newVRegI(env); - s390_cc_t cc_x = s390_isel_cc(env, arg1); - addInstr(env, s390_insn_cc2bool(x_as_64, cc_x)); - addInstr(env, s390_insn_alu(8, S390_ALU_AND, x_as_64, one)); - - HReg y_as_64 = newVRegI(env); - s390_cc_t cc_y = s390_isel_cc(env, arg2); - addInstr(env, s390_insn_cc2bool(y_as_64, cc_y)); - addInstr(env, s390_insn_alu(8, S390_ALU_AND, y_as_64, one)); - - s390_alu_t opkind - = cond->Iex.Binop.op == Iop_And1 ? S390_ALU_AND : S390_ALU_OR; - addInstr(env, s390_insn_alu(/*size=*/8, - opkind, x_as_64, s390_opnd_reg(y_as_64))); - - addInstr(env, s390_insn_alu(/*size=*/8, S390_ALU_AND, x_as_64, one)); - addInstr(env, s390_insn_test(/*size=*/8, s390_opnd_reg(x_as_64))); + /* Perform the calculation in registers, but ignore the resulting + value. Instead, assume that the condition code is set. */ + (void) s390_isel_int1_expr(env, cond, INVALID_HREG); return S390_CC_NE; } -# endif /* 0 */ // |sizeofIRType| asserts on Ity_I1, so we can't do it until after we're // sure that Iop_And1 and Iop_Or1 can't make it this far. @@ -3627,14 +3589,12 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) goto do_compare_ze; do_compare_ze: { - s390_opnd_RMI op1, op2; - - op1 = s390_isel_int_expr_RMI(env, arg1); - reg1 = newVRegI(env); + s390_opnd_RMI op1 = s390_isel_int_expr_RMI(env, arg1); + HReg reg1 = newVRegI(env); addInstr(env, s390_insn_unop(4, op, reg1, op1)); - op2 = s390_isel_int_expr_RMI(env, arg2); - reg2 = newVRegI(env); + s390_opnd_RMI op2 = s390_isel_int_expr_RMI(env, arg2); + HReg reg2 = newVRegI(env); addInstr(env, s390_insn_unop(4, op, reg2, op2)); /* zero extend */ op2 = s390_opnd_reg(reg2); @@ -3713,6 +3673,51 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) vpanic("s390_isel_cc: unexpected operator"); } +/*---------------------------------------------------------*/ +/*--- ISEL: Bit-typed expression ---*/ +/*---------------------------------------------------------*/ + +/* Handle Int1-typed expressions that are supposed to end up in a register. + Place the result into the given target register 'dst', or, if INVALID_HREG is + specified, create a new virtual integer register if necessary. Keep Int1 + values in registers always sign-extended to 64 bits. This function is + mutually recursive with s390_isel_cc. */ +static HReg +s390_isel_int1_expr(ISelEnv *env, IRExpr *expr, HReg dst) +{ + vassert(expr); + vassert(typeOfIRExpr(env->type_env, expr) == Ity_I1); + + /* Variable. */ + if (expr->tag == Iex_RdTmp) { + HReg res = lookupIRTemp(env, expr->Iex.RdTmp.tmp); + if (hregIsInvalid(dst)) { + return res; + } + addInstr(env, s390_insn_move(8, dst, res)); + return dst; + } + + HReg res = hregIsInvalid(dst) ? newVRegI(env) : dst; + + /* And1 / Or1 */ + if (expr->tag == Iex_Binop + && (expr->Iex.Binop.op == Iop_And1 || expr->Iex.Binop.op == Iop_Or1)) { + HReg reg1 = s390_isel_int1_expr(env, expr->Iex.Binop.arg1, res); + HReg reg2 = s390_isel_int1_expr(env, expr->Iex.Binop.arg2, INVALID_HREG); + s390_alu_t opkind + = expr->Iex.Binop.op == Iop_And1 ? S390_ALU_AND : S390_ALU_OR; + + /* Ensure that the condition code is set; s390_isel_cc relies on it. */ + addInstr(env, s390_insn_alu(8, opkind, reg1, s390_opnd_reg(reg2))); + return reg1; + } + + /* Else, call s390_isel_cc and force the value into a register. */ + addInstr(env, s390_insn_cc2bool(res, s390_isel_cc(env, expr))); + return res; +} + /*---------------------------------------------------------*/ /*--- ISEL: Vector expressions (128 bit) ---*/ @@ -4988,9 +4993,8 @@ no_memcpy_put: break; case Ity_I1: { - s390_cc_t cond = s390_isel_cc(env, stmt->Ist.WrTmp.data); dst = lookupIRTemp(env, tmp); - addInstr(env, s390_insn_cc2bool(dst, cond)); + dst = s390_isel_int1_expr(env, stmt->Ist.WrTmp.data, dst); return; } |
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From: Andreas A. <ar...@so...> - 2020-03-13 19:36:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=73ab20e67818ccca943f033b8afa0d7869bc75e3 commit 73ab20e67818ccca943f033b8afa0d7869bc75e3 Author: Andreas Arnez <ar...@li...> Date: Mon Mar 2 19:45:29 2020 +0100 Update vbit-test after move from Clz to ClzNat on s390x After removing support of Iop_Clz64 and defining Iop_ClzNat64 instead (see commit #bb594e098b75ae6309), this needs to be reflected in vbit-test. Diff: --- memcheck/tests/vbit-test/irops.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 79745f5939..1f1ba909ac 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -108,11 +108,11 @@ static irop_t irops[] = { { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts + { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, - { DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts + { DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, { DEFOP(Iop_CtzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, { DEFOP(Iop_CtzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, |
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From: Andreas A. <ar...@so...> - 2020-03-13 19:36:26
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b9a4f7d7ca98487e7b66c2c56bc0c9ea7fe6776b commit b9a4f7d7ca98487e7b66c2c56bc0c9ea7fe6776b Author: Andreas Arnez <ar...@li...> Date: Tue Mar 10 17:18:48 2020 +0100 s390x: Fix down-cast from memory operand with size < 8 A down-cast always copies 8 bytes from the source operand, even if the operand is actually smaller. This doesn't matter for register operands, but it does for memory operands. Fix this and copy the correct number of bytes instead. Diff: --- VEX/priv/host_s390_isel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 5d26825daf..00b4aee818 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -1893,7 +1893,8 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) /* Down-casts are no-ops. Upstream operations will only look at the bytes that make up the result of the down-cast. So there is no point setting the other bytes to 0. */ - insn = s390_opnd_copy(8, dst, opnd); + size = sizeofIRType(typeOfIRExpr(env->type_env, arg)); + insn = s390_opnd_copy(size, dst, opnd); break; case Iop_64HIto32: |
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From: Andreas A. <ar...@so...> - 2020-03-13 19:36:18
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b4ce6da03a8c886e1fab14eaa1f9b4f091308c3d commit b4ce6da03a8c886e1fab14eaa1f9b4f091308c3d Author: Andreas Arnez <ar...@li...> Date: Fri Mar 13 17:18:55 2020 +0100 s390x: Mark VRs as clobbered by helper calls According to the s390x ABI, all vector registers are call-clobbered (except for their portions that overlap with the call-saved FPRs). But the s390x backend doesn't mark them as such when determining the register usage of helper call insns. Fix this in s390_insn_get_reg_usage when handling S390_INSN_HELPER_CALL. Diff: --- VEX/priv/host_s390_defs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 43b89c9253..de267078e1 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -770,6 +770,11 @@ s390_insn_get_reg_usage(HRegUsage *u, const s390_insn *insn) addHRegUse(u, HRmWrite, s390_hreg_fpr(i)); } + /* Ditto for all allocatable vector registers. */ + for (i = 16; i <= 31; ++i) { + addHRegUse(u, HRmWrite, s390_hreg_vr(i)); + } + /* The registers that are used for passing arguments will be read. Not all of them may, but in general we need to assume that. */ for (i = 0; i < insn->variant.helper_call.details->num_args; ++i) { |
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From: Julian S. <se...@so...> - 2020-03-13 13:36:19
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=95bde348622823a7c8d6167199f7c54313848e56 commit 95bde348622823a7c8d6167199f7c54313848e56 Author: Julian Seward <js...@ac...> Date: Fri Mar 13 14:35:59 2020 +0100 Update bug status. Diff: --- NEWS | 1 + docs/internals/3_15_BUGSTATUS.txt | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/NEWS b/NEWS index a60062b95d..d7852320e5 100644 --- a/NEWS +++ b/NEWS @@ -111,6 +111,7 @@ where XXXXXX is the bug number as listed below. 413330 avx-1 test fails on AMD EPYC 7401P 24-Core Processor 413603 callgrind_annotate/cg_annotate truncate function names at '#' 414565 Specific use case bug found in SysRes VG_(do_sys_sigprocmask) +415136 ARMv8.1 Compare-and-Swap instructions are not supported 415757 vex x86->IR: 0x66 0xF 0xCE 0x4F (bswapw) 416239 valgrind crashes when handling clock_adjtime 416286 DRD reports "conflicting load" error on std::mutex::lock() diff --git a/docs/internals/3_15_BUGSTATUS.txt b/docs/internals/3_15_BUGSTATUS.txt index 0ac7deda85..ac4b5f48f5 100644 --- a/docs/internals/3_15_BUGSTATUS.txt +++ b/docs/internals/3_15_BUGSTATUS.txt @@ -130,8 +130,6 @@ of 3.15.0. It doesn't carry over bugs from earlier versions. 414270 Collection of bugs for new ARMv8.1 work and features 414268 Enable AArch64 feature detection and decoding for v8.x instructions (where x>0) -415136 ARMv8.1 Compare-and-Swap instructions are not supported - All of this 8.x stuff is WIP === VEX/mips =========================================================== === VEX/other ========================================================== |