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From: Andreas A. <ar...@so...> - 2020-02-25 15:50:15
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=75878add525a00d14be360c3bb1bc9e27596d43a commit 75878add525a00d14be360c3bb1bc9e27596d43a Author: Andreas Arnez <ar...@li...> Date: Wed Feb 5 19:28:53 2020 +0100 s390x: Exploit LOCGHI for converting from CC to Int1 Whenever converting a condition code to a Boolean value, the current implementation in s390_insn_cc2bool_emit() generates six instructions including "insert program mask" (IPM). On systems with the load/store-on-condition facility 2, this can be done in two instructions instead, using "load halfword immediate on condition" (LOCGHI). Add the new hardware capability VEX_HWCAPS_S390X_LSC2 and the respective macro s390_host_has_lsc2. In s390_insn_cc2bool_emit(), check for the facility and exploit it if available. A conditional move from an immediate value can be slightly improved with LOCGHI as well, so do that in s390_insn_cond_move_emit() if possible. Diff: --- VEX/priv/host_s390_defs.c | 36 ++++++++++++++++++++++++++++++++++++ VEX/priv/host_s390_defs.h | 2 ++ VEX/priv/main_main.c | 1 + VEX/pub/libvex.h | 4 +++- coregrind/m_machine.c | 1 + 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 47928cb..43b89c9 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -1414,6 +1414,19 @@ emit_RIL(UChar *p, ULong op, UChar r1, UInt i2) static UChar * +emit_RIE(UChar *p, ULong op, UChar r1, UShort i2, UChar m3) +{ + ULong the_insn = op; + + the_insn |= ((ULong)r1) << 36; + the_insn |= ((ULong)m3) << 32; + the_insn |= ((ULong)i2) << 16; + + return emit_6bytes(p, the_insn); +} + + +static UChar * emit_RR(UChar *p, UInt op, UChar r1, UChar r2) { ULong the_insn = op; @@ -5131,6 +5144,15 @@ s390_emit_LOCG(UChar *p, UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) return emit_RSY(p, 0xeb00000000e2ULL, r1, m3, b2, dl2, dh2); } +static UChar * +s390_emit_LOCGHI(UChar *p, UChar r1, UShort i2, UChar m3) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC4(MNM, GPR, INT, UINT), "locghi", r1, (Int)(Short)i2, m3); + + return emit_RIE(p, 0xec0000000046ULL, r1, i2, m3); +} + /* Provide a symbolic name for register "R0" */ #define R0 0 @@ -9354,6 +9376,15 @@ s390_insn_cc2bool_emit(UChar *buf, const s390_insn *insn) if (cond == S390_CC_ALWAYS) return s390_emit_LGHI(buf, r1, 1); /* r1 = 1 */ + /* If LOCGHI is available, use it. */ + if (s390_host_has_lsc2) { + /* Clear r1, then load immediate 1 on condition. */ + buf = s390_emit_LGHI(buf, r1, 0); + if (cond != S390_CC_NEVER) + buf = s390_emit_LOCGHI(buf, r1, 1, cond); + return buf; + } + buf = s390_emit_load_cc(buf, r1); /* r1 = cc */ buf = s390_emit_LGHI(buf, R0, cond); /* r0 = mask */ buf = s390_emit_SLLG(buf, r1, R0, r1, DISP20(0)); /* r1 = mask << cc */ @@ -10069,6 +10100,11 @@ s390_insn_cond_move_emit(UChar *buf, const s390_insn *insn) case S390_OPND_IMMEDIATE: { ULong value = src.variant.imm; + /* If LOCGHI is available, use it. */ + if (s390_host_has_lsc2 && ulong_fits_signed_16bit(value)) { + return s390_emit_LOCGHI(p, hregNumber(dst), value, cond); + } + /* Load value into R0, then use LOCGR */ if (insn->size <= 4) { p = s390_emit_load_32imm(p, R0, value); diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h index e79b990..bbafa4f 100644 --- a/VEX/priv/host_s390_defs.h +++ b/VEX/priv/host_s390_defs.h @@ -926,6 +926,8 @@ extern UInt s390_host_hwcaps; (s390_host_hwcaps & (VEX_HWCAPS_S390X_VX)) #define s390_host_has_msa5 \ (s390_host_hwcaps & (VEX_HWCAPS_S390X_MSA5)) +#define s390_host_has_lsc2 \ + (s390_host_hwcaps & (VEX_HWCAPS_S390X_LSC2)) #endif /* ndef __VEX_HOST_S390_DEFS_H */ /*---------------------------------------------------------------*/ diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 5acab9e..8215530 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1791,6 +1791,7 @@ static const HChar* show_hwcaps_s390x ( UInt hwcaps ) { VEX_HWCAPS_S390X_VX, "vx" }, { VEX_HWCAPS_S390X_MSA5, "msa5" }, { VEX_HWCAPS_S390X_MI2, "mi2" }, + { VEX_HWCAPS_S390X_LSC2, "lsc2" }, }; /* Allocate a large enough buffer */ static HChar buf[sizeof prefix + diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 5d3733d..359d108 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -165,6 +165,7 @@ typedef #define VEX_HWCAPS_S390X_VX (1<<18) /* Vector facility */ #define VEX_HWCAPS_S390X_MSA5 (1<<19) /* message security assistance facility */ #define VEX_HWCAPS_S390X_MI2 (1<<20) /* miscellaneous-instruction-extensions facility 2 */ +#define VEX_HWCAPS_S390X_LSC2 (1<<21) /* Conditional load/store facility2 */ /* Special value representing all available s390x hwcaps */ @@ -182,7 +183,8 @@ typedef VEX_HWCAPS_S390X_PFPO | \ VEX_HWCAPS_S390X_VX | \ VEX_HWCAPS_S390X_MSA5 | \ - VEX_HWCAPS_S390X_MI2) + VEX_HWCAPS_S390X_MI2 | \ + VEX_HWCAPS_S390X_LSC2) #define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK) #define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK) diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 32c242a..672a021 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1537,6 +1537,7 @@ Bool VG_(machine_get_hwcaps)( void ) { False, S390_FAC_VX, VEX_HWCAPS_S390X_VX, "VX" }, { False, S390_FAC_MSA5, VEX_HWCAPS_S390X_MSA5, "MSA5" }, { False, S390_FAC_MI2, VEX_HWCAPS_S390X_MI2, "MI2" }, + { False, S390_FAC_LSC2, VEX_HWCAPS_S390X_LSC2, "LSC2" }, }; /* Set hwcaps according to the detected facilities */ |
|
From: Andreas A. <ar...@so...> - 2020-02-25 15:50:09
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bb594e098b75ae6309c8f2ee2a7ddc5c6dc2361f commit bb594e098b75ae6309c8f2ee2a7ddc5c6dc2361f Author: Andreas Arnez <ar...@li...> Date: Tue Feb 25 15:54:46 2020 +0100 s390x: Replace use of deprecated Iop_Clz64 operator The operator Iop_Clz64 has been deprecated. Drop it in the s390x backend and replace it by Iop_ClzNat64. Previously s390_irgen_FLOGR() handled the value zero specially and replaced it by 1 before applying Iop_Clz64. With Iop_ClzNat64 this is no longer needed, so remove this special-case handling. Diff: --- VEX/priv/guest_s390_toIR.c | 20 ++++---------------- VEX/priv/host_s390_isel.c | 2 +- 2 files changed, 5 insertions(+), 17 deletions(-) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index ed95fc0..eb3a25b 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -14883,27 +14883,15 @@ static const HChar * s390_irgen_FLOGR(UChar r1, UChar r2) { IRTemp input = newTemp(Ity_I64); - IRTemp not_zero = newTemp(Ity_I64); - IRTemp tmpnum = newTemp(Ity_I64); IRTemp num = newTemp(Ity_I64); IRTemp shift_amount = newTemp(Ity_I8); - /* We use the "count leading zeroes" operator because the number of - leading zeroes is identical with the bit position of the first '1' bit. - However, that operator does not work when the input value is zero. - Therefore, we set the LSB of the input value to 1 and use Clz64 on - the modified value. If input == 0, then the result is 64. Otherwise, - the result of Clz64 is what we want. */ + /* Use the "count leading zeroes" operator with "natural" semantics. The + results of FLOGR and Iop_ClzNat64 are the same for all inputs, including + input == 0, in which case both operators yield 64. */ assign(input, get_gpr_dw0(r2)); - assign(not_zero, binop(Iop_Or64, mkexpr(input), mkU64(1))); - assign(tmpnum, unop(Iop_Clz64, mkexpr(not_zero))); - - /* num = (input == 0) ? 64 : tmpnum */ - assign(num, mkite(binop(Iop_CmpEQ64, mkexpr(input), mkU64(0)), - /* == 0 */ mkU64(64), - /* != 0 */ mkexpr(tmpnum))); - + assign(num, unop(Iop_ClzNat64, mkexpr(input))); put_gpr_dw0(r1, mkexpr(num)); /* Set the leftmost '1' bit of the input value to zero. The general scheme diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index fff81fe..5d26825 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -1943,7 +1943,7 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) return dst; } - case Iop_Clz64: { + case Iop_ClzNat64: { HReg r10, r11; /* This will be implemented using FLOGR, if possible. So we need to |