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From: Paul F. <pj...@wa...> - 2020-01-14 19:16:25
|
Hi I’m having quick look at building Valgrind on macOS Catalina I’m using this repo https://github.com/LouisBrunner/valgrind-macos.git <https://github.com/LouisBrunner/valgrind-macos.git> Plus I’ve merged in the changes up to head from sourceware. After a few mods to configure.ac and a few of the Darwin files it builds and I get ==39161== Lackey, an example Valgrind tool ==39161== Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote. ==39161== Using Valgrind-3.16.0.GIT and LibVEX; rerun with -h for copyright info ==39161== Command: pwd ==39161== ==39161== valgrind: Unrecognised instruction at address 0x1006037bd. In the past when I’ve seen this sort of thing there was also a vex printf of the opcodes, but not in this case. Any suggestions what to try next? A+ Paul |
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From: Petar J. <pe...@so...> - 2020-01-14 17:47:49
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8b809cdbba8dbb8ae3093bf68653e47dbff7e215 commit 8b809cdbba8dbb8ae3093bf68653e47dbff7e215 Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 17:45:00 2020 +0000 mips: Implement Iex_CCall for nanoMIPS Implement Iex_CCall for nanoMIPS. This fixes none/tests/nestedfns. Patch by Stefan Maksimovic. Diff: --- VEX/priv/host_nanomips_isel.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/VEX/priv/host_nanomips_isel.c b/VEX/priv/host_nanomips_isel.c index 59adf58..d348f21 100644 --- a/VEX/priv/host_nanomips_isel.c +++ b/VEX/priv/host_nanomips_isel.c @@ -877,8 +877,23 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) } case Iex_CCall: { - /* unimplemented yet */ - vassert(0); + HReg r_dst = newVRegI(env); + UInt addToSp = 0; + RetLoc rloc = mk_RetLoc_INVALID(); + + /* Be very restrictive for now. Only 32-bit ints allowed for + args, and 32 bits for return type. Don't forget to change + the RetLoc if more return types are allowed in future. */ + vassert(Ity_I32 == e->Iex.CCall.retty); + + /* Marshal args, do the call, clear stack. */ + doHelperCall(&rloc, env, NULL /*guard*/, e->Iex.CCall.cee, + e->Iex.CCall.retty, e->Iex.CCall.args); + vassert(is_sane_RetLoc(rloc)); + vassert(rloc.pri == RLPri_Int); + vassert(addToSp == 0); + addInstr(env, mk_iMOVds_RR(r_dst, hregNANOMIPS_GPR4())); + return r_dst; } default: |
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From: Petar J. <pe...@so...> - 2020-01-14 17:38:34
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3501c118dfb9b4fbd3bd005f30e2cafc65f6fed8 commit 3501c118dfb9b4fbd3bd005f30e2cafc65f6fed8 Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 17:37:21 2020 +0000 mips: Fix BEQC[16] and BNEC[16] instructions for nanoMIPS Instruction decoding was not correct. In some cases, BEQC has been decoded as BNEC and vice versa. It caused problems with musl malloc() function. Patch by Stefan Maksimovic. Diff: --- VEX/priv/guest_nanomips_toIR.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c index f06370f..0cc80b0 100755 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -2201,10 +2201,12 @@ static void nano_p16br(DisResult *dres, UShort cins) putPC(getIReg(rt)); dres->whatNext = Dis_StopHere; } else { - UChar rt = GPR3_list[(cins >> 7) & 0x07]; - UChar rs = GPR3_list[(cins >> 4) & 0x07]; + UChar rt3 = (cins >> 7) & 0x07; + UChar rs3 = (cins >> 4) & 0x07; + UChar rt = GPR3_list[rt3]; + UChar rs = GPR3_list[rs3]; - if (rs < rt) { /* beqc[16] */ + if (rs3 < rt3) { /* beqc[16] */ DIP("beqc r%u, r%u, %X", rt, rs, guest_PC_curr_instr + 2 + u); ir_for_branch(dres, binop(Iop_CmpEQ32, getIReg(rt), getIReg(rs)), 2, (Int)u); |
|
From: Petar J. <pe...@so...> - 2020-01-14 17:38:30
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d7b2a29718daa9dad66b609d2bc6166a62db38ef commit d7b2a29718daa9dad66b609d2bc6166a62db38ef Author: Aleksandar Rikalo <ale...@rt...> Date: Tue Jan 14 17:24:29 2020 +0000 mips: Fix return from syscall mechanism for nanoMIPS - Restore guest sigmask in VG_(sigframe_destroy) - Use "syscall[32]" asm idiom instead of "syscall" with immediate parameter in VG_(nanomips_linux_SUBST_FOR_rt_sigreturn) - Call ML_(fixup_guest_state_to_restart_syscall) from PRE(sys_rt_sigreturn) - Tiny code refactor of sigframe-nanomips-linux.c This fixes none/tests/thread-exits. Diff: --- coregrind/m_sigframe/sigframe-nanomips-linux.c | 6 ++++-- coregrind/m_syswrap/syswrap-nanomips-linux.c | 6 ++++++ coregrind/m_trampoline.S | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/coregrind/m_sigframe/sigframe-nanomips-linux.c b/coregrind/m_sigframe/sigframe-nanomips-linux.c index 222ca24..cdf329c 100644 --- a/coregrind/m_sigframe/sigframe-nanomips-linux.c +++ b/coregrind/m_sigframe/sigframe-nanomips-linux.c @@ -150,7 +150,7 @@ void VG_(sigframe_create)( ThreadId tid, * Arguments to signal handler: * * a0 = signal number - * a1 = 0 (should be cause) + * a1 = pointer to siginfo_t * a2 = pointer to ucontext * * $25 and c0_epc point to the signal handler, $29 points to @@ -196,9 +196,11 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) { tst = VG_(get_ThreadState)(tid); frame = (struct rt_sigframe *)(Addr)tst->arch.vex.guest_r29; priv1 = &frame->priv; + vg_assert(priv1->magicPI == 0x31415927); ucp = &frame->rs_uc; + tst->sig_mask = ucp->uc_sigmask; + tst->tmp_sig_mask = ucp->uc_sigmask; mc = &ucp->uc_mcontext; - vg_assert(priv1->magicPI == 0x31415927); tst->arch.vex.guest_r1 = mc->sc_regs[1]; tst->arch.vex.guest_r2 = mc->sc_regs[2]; tst->arch.vex.guest_r3 = mc->sc_regs[3]; diff --git a/coregrind/m_syswrap/syswrap-nanomips-linux.c b/coregrind/m_syswrap/syswrap-nanomips-linux.c index db13bd7..4ab9bcc 100644 --- a/coregrind/m_syswrap/syswrap-nanomips-linux.c +++ b/coregrind/m_syswrap/syswrap-nanomips-linux.c @@ -471,10 +471,16 @@ POST(sys_ptrace) PRE(sys_rt_sigreturn) { + ThreadState* tst; PRINT ("rt_sigreturn ( )"); vg_assert (VG_ (is_valid_tid) (tid)); vg_assert (tid >= 1 && tid < VG_N_THREADS); vg_assert (VG_ (is_running_thread) (tid)); + + tst = VG_(get_ThreadState)(tid); + + ML_(fixup_guest_state_to_restart_syscall)(&tst->arch); + /* Restore register state from frame and remove it */ VG_ (sigframe_destroy) (tid, True); /* Tell the driver not to update the guest state with the "result", diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S index eb89f02..c2d6429 100644 --- a/coregrind/m_trampoline.S +++ b/coregrind/m_trampoline.S @@ -1326,8 +1326,8 @@ VG_(trampoline_stuff_start): .global VG_(nanomips_linux_SUBST_FOR_rt_sigreturn) VG_(nanomips_linux_SUBST_FOR_rt_sigreturn): - li $t4,__NR_rt_sigreturn - syscall 1 + li $t4, __NR_rt_sigreturn + syscall[32] .long 0 .global VG_(nanomips_linux_REDIR_FOR_index) |
|
From: Petar J. <pe...@so...> - 2020-01-14 12:44:26
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8557d219283e321a9976755895cf34cbe02f3ccd commit 8557d219283e321a9976755895cf34cbe02f3ccd Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 12:43:13 2020 +0000 mips: Add membarrier syscall for nanoMIPS This fixes none/tests/linux/membarrier. Diff: --- coregrind/m_syswrap/syswrap-nanomips-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/coregrind/m_syswrap/syswrap-nanomips-linux.c b/coregrind/m_syswrap/syswrap-nanomips-linux.c index 0badf56..db13bd7 100644 --- a/coregrind/m_syswrap/syswrap-nanomips-linux.c +++ b/coregrind/m_syswrap/syswrap-nanomips-linux.c @@ -805,7 +805,7 @@ static SyscallTableEntry syscall_main_table[] = { // (__NR_bpf, sys_ni_syscall), // (__NR_execveat, sys_ni_syscall), // (__NR_userfaultfd, sys_ni_syscall), - // (__NR_membarrier, sys_ni_syscall), + LINX_ (__NR_membarrier, sys_membarrier), // (__NR_mlock2, sys_ni_syscall), // (__NR_copy_file_range, sys_ni_syscall), // (__NR_preadv2, sys_ni_syscall), |
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From: Petar J. <pe...@so...> - 2020-01-14 12:44:24
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ab8807ee5398408fe09a9ea5a2ea8804e4cbade2 commit ab8807ee5398408fe09a9ea5a2ea8804e4cbade2 Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 12:40:09 2020 +0000 mips: Add Iop_ROTX for nanoMIPS Implement Iop_ROTX and use it for ROTX instruction. Fixes libvexmultiarch_test and libvex_test. Patch by: Aleksandra Karadzic and Nikola Milutinovic. Diff: --- VEX/priv/guest_nanomips_toIR.c | 145 +++++++---------------------------------- VEX/priv/host_nanomips_defs.c | 14 +++- VEX/priv/host_nanomips_defs.h | 1 + VEX/priv/host_nanomips_isel.c | 17 +++++ 4 files changed, 54 insertions(+), 123 deletions(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c index 7233a73..f06370f 100755 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -216,11 +216,6 @@ static IRExpr *mkU32(UInt i) return IRExpr_Const(IRConst_U32(i)); } -static IRExpr *mkU64(ULong i) -{ - return IRExpr_Const(IRConst_U64(i)); -} - static void putPC(IRExpr * e) { stmt(IRStmt_Put(OFFB_PC, e)); @@ -285,6 +280,11 @@ static IRExpr *binop(IROp op, IRExpr * a1, IRExpr * a2) return IRExpr_Binop(op, a1, a2); } +static IRExpr *qop(IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3, IRExpr * a4) +{ + return IRExpr_Qop(op, a1, a2, a3, a4); +} + /* Generate a new temporary of the given type. */ static IRTemp newTemp(IRType ty) { @@ -466,11 +466,23 @@ static void nano_pl32a0(DisResult *dres, UInt cins) IRConst_U32(guest_PC_curr_instr + 4), OFFB_PC)); } else { /* teq */ - DIP("teq r%u, r%u", rs, rt); - stmt(IRStmt_Exit(binop(Iop_CmpEQ32, getIReg(rs), - getIReg(rt)), Ijk_SigTRAP, - IRConst_U32(guest_PC_curr_instr + 4), - OFFB_PC)); + UChar trap_code = (cins >> 11) & 0x1F; + DIP("teq r%u, r%u %u", rs, rt, trap_code); + if (trap_code == 7) + stmt(IRStmt_Exit(binop(Iop_CmpEQ32, getIReg(rs), + getIReg(rt)), Ijk_SigFPE_IntDiv, + IRConst_U32(guest_PC_curr_instr + 4), + OFFB_PC)); + else if (trap_code == 6) + stmt(IRStmt_Exit(binop(Iop_CmpEQ32, getIReg(rs), + getIReg(rt)), Ijk_SigFPE_IntOvf, + IRConst_U32(guest_PC_curr_instr + 4), + OFFB_PC)); + else + stmt(IRStmt_Exit(binop(Iop_CmpEQ32, getIReg(rs), + getIReg(rt)), Ijk_SigTRAP, + IRConst_U32(guest_PC_curr_instr + 4), + OFFB_PC)); } break; @@ -1232,118 +1244,9 @@ static void nano_protx(UInt cins) switch ((cins >> 5) & 0x41) { case 0x00: { /* rotx */ - int i; - IRTemp t0 = newTemp(Ity_I64); - IRTemp t1 = newTemp(Ity_I64); - IRTemp t2 = newTemp(Ity_I64); - IRTemp t3 = newTemp(Ity_I64); - IRTemp t4 = newTemp(Ity_I64); - IRTemp t5 = newTemp(Ity_I64); - IRTemp tmp = newTemp(Ity_I64); - IRTemp s = newTemp(Ity_I32); DIP("rotx r%u, r%u, %u, %u, %u", rt, rs, shift, shiftx, stripe); - assign(t0, binop(Iop_Or64, getIReg(rs), binop(Iop_Shl64, - getIReg(rs), mkU8(32)))); - assign(t1, mkexpr(t0)); - - for (i = 0; i < 46; i++) { - assign(s, IRExpr_ITE(binop(Iop_And32, mkU32(i), mkU32(0x08)), - mkU32(shift), mkU32(shiftx))); - assign(s, IRExpr_ITE(binop(Iop_And32, mkU32(stripe), - binop(Iop_CmpNE32, mkU32(0x0), - binop(Iop_And32, - mkU32(i), mkU32(0x04)))), - unop(Iop_Not32, mkU32(s)), mkexpr(s))); - assign(tmp, binop(Iop_Or64, binop(Iop_And64, - binop(Iop_Shr64, mkexpr(t0), - mkU8(0x10)), - binop(Iop_Shl64, mkU64(0x01), - mkU8(i))), - binop(Iop_And64, mkexpr(t1), - unop(Iop_Not64, - binop(Iop_Shl64, mkU64(0x01), - mkU8(i)))))); - assign(t1, IRExpr_ITE(binop(Iop_And32, mkexpr(s), mkU32(0x10)), - mkexpr(tmp), - mkexpr(t1))); - - } - - assign(t2, mkexpr(t1)); - - for (i = 0; i < 38; i++) { - assign(s, IRExpr_ITE(binop(Iop_And32, mkU32(i), mkU32(0x04)), - mkU32(shift), mkU32(shiftx))); - assign(tmp, binop(Iop_Or64, - binop(Iop_And64, - binop(Iop_Shr64, mkexpr(t1), mkU8(0x08)), - binop(Iop_Shl64, mkU64(0x01), mkU8(i))), - binop(Iop_And64, mkexpr(t2), - unop(Iop_Not64, binop(Iop_Shl64, - mkU64(0x01), - mkU8(i)))))); - assign(t2, IRExpr_ITE(binop(Iop_And32, mkexpr(s), mkU32(0x08)), - mkexpr(tmp), - mkexpr(t2))); - - } - - assign(t3, mkexpr(t2)); - - for (i = 0; i < 34; i++) { - assign(s, IRExpr_ITE(binop(Iop_And32, mkU32(i), mkU32(0x02)), - mkU32(shift), mkU32(shiftx))); - assign(tmp, binop(Iop_Or64, - binop(Iop_And64, - binop(Iop_Shr64, mkexpr(t2), mkU8(0x04)), - binop(Iop_Shl64, mkU64(0x01), mkU8(i))), - binop(Iop_And64, mkexpr(t3), - unop(Iop_Not64, binop(Iop_Shl64, - mkU64(0x01), - mkU8(i)))))); - assign(t3, IRExpr_ITE(binop(Iop_And32, mkexpr(s), mkU32(0x04)), - mkexpr(tmp), - mkexpr(t3))); - - } - - assign(t4, mkexpr(t3)); - - for (i = 0; i < 32; i++) { - assign(s, IRExpr_ITE(binop(Iop_And32, mkU32(i), mkU32(0x01)), - mkU32(shift), mkU32(shiftx))); - assign(tmp, binop(Iop_Or64, - binop(Iop_And64, - binop(Iop_Shr64, mkexpr(t3), mkU8(0x02)), - binop(Iop_Shl64, mkU64(0x01), mkU8(i))), - binop(Iop_And64, mkexpr(t4), - unop(Iop_Not64, binop(Iop_Shl64, - mkU64(0x01), - mkU8(i)))))); - assign(t4, IRExpr_ITE(binop(Iop_And32, mkexpr(s), mkU32(0x02)), - mkexpr(tmp), - mkexpr(t4))); - - } - - assign(t5, mkexpr(t4)); - - for (i = 0; i < 32; i++) { - assign(tmp, binop(Iop_Or64, - binop(Iop_And64, - binop(Iop_Shr64, mkexpr(t4), mkU8(0x01)), - binop(Iop_Shl64, mkU64(0x01), mkU8(i))), - binop(Iop_And64, mkexpr(t5), - unop(Iop_Not64, binop(Iop_Shl64, - mkU64(0x01), - mkU8(i)))))); - assign(t4, IRExpr_ITE(binop(Iop_And32, mkexpr(shift), mkU32(0x02)), - mkexpr(tmp), - mkexpr(t5))); - - } - - putIReg(rt, mkexpr(t5)); + putIReg(rt, qop(Iop_Rotx32, getIReg(rs), mkU8(shift), + mkU8(shiftx), mkU8(stripe))); break; } diff --git a/VEX/priv/host_nanomips_defs.c b/VEX/priv/host_nanomips_defs.c old mode 100644 new mode 100755 index 9f0b975..1b66947 --- a/VEX/priv/host_nanomips_defs.c +++ b/VEX/priv/host_nanomips_defs.c @@ -304,6 +304,9 @@ void ppNANOMIPSInstr(const NANOMIPSInstr* i) case NMimm_ANDI: vex_printf("andi "); break; + case NMimm_ROTX: + vex_printf("rotx "); + break; default: vassert(0); @@ -317,8 +320,11 @@ void ppNANOMIPSInstr(const NANOMIPSInstr* i) vex_printf(", "); } - vex_printf("0x%X (%d)", i->NMin.Imm.imm, (Int)i->NMin.Imm.imm); - + if (i->NMin.Imm.op == NMimm_ROTX) + vex_printf("%u, %u, %u", (i->NMin.Imm.imm >> 7) & 0xF, + (i->NMin.Imm.imm >> 6) & 1, i->NMin.Imm.imm & 0x1F); + else + vex_printf("0x%X (%d)", i->NMin.Imm.imm, (Int)i->NMin.Imm.imm); break; case NMin_Alu: @@ -1202,6 +1208,7 @@ static UChar *mkFormNanoPU12(UChar * p, UInt rt, UInt rs, UInt opc2, UInt imm) case PU12_ORI: /* ORI */ case PU12_SLTIU: /* SLTIU */ case PU12_XORI: /* XORI */ + case PU12_PROTX: /* ROTX */ theInstr = ((PU12 << 26) | (rt << 21) | (rs << 16) | (opc2 << 12) | (imm)); return emit32(p, theInstr); @@ -1380,6 +1387,9 @@ Int emit_NANOMIPSInstr ( /*MB_MOD*/Bool* is_profInc, p = mkFormNanoPU12(p, r_dst, r_src, i->NMin.Imm.op - 0x6, i->NMin.Imm.imm); break; + case NMimm_ROTX: + p = mkFormNanoPU12(p, r_dst, r_src, PU12_PROTX, i->NMin.Imm.imm); + break; default: goto bad; diff --git a/VEX/priv/host_nanomips_defs.h b/VEX/priv/host_nanomips_defs.h index d1b4939..6690ad0 100644 --- a/VEX/priv/host_nanomips_defs.h +++ b/VEX/priv/host_nanomips_defs.h @@ -179,6 +179,7 @@ typedef enum { NMimm_ORI = 0x06, /* Logical or */ NMimm_XORI = 0x07, /* Logical xor */ NMimm_ANDI = 0x08, /* Logical and */ + NMimm_ROTX = 0x09, /* Rotx */ } NANOMIPSImmOp; typedef enum { diff --git a/VEX/priv/host_nanomips_isel.c b/VEX/priv/host_nanomips_isel.c index fe60a49..59adf58 100644 --- a/VEX/priv/host_nanomips_isel.c +++ b/VEX/priv/host_nanomips_isel.c @@ -840,6 +840,23 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) vpanic("\n"); } + case Iex_Qop: { + HReg dst = newVRegI(env); + HReg src1 = iselWordExpr_R(env, e->Iex.Qop.details->arg1); + UChar src2 = e->Iex.Qop.details->arg2->Iex.Const.con->Ico.U8; + UChar src3 = e->Iex.Qop.details->arg3->Iex.Const.con->Ico.U8; + UChar src4 = e->Iex.Qop.details->arg4->Iex.Const.con->Ico.U8; + UInt imm = (src3 << 6) | (src4 << 6) | src2; + switch (e->Iex.Qop.details->op) { + case Iop_Rotx32: + addInstr(env, NANOMIPSInstr_Imm(NMimm_ROTX, dst, src1, imm)); + return dst; + default: + break; + } + break; + } + case Iex_ITE: { vassert(typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1); HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse); |
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From: Petar J. <pe...@so...> - 2020-01-14 12:14:32
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8b7a3a2107c4e4465b256c61ae69bcf0421816bd commit 8b7a3a2107c4e4465b256c61ae69bcf0421816bd Author: Aleksandar Rikalo <ale...@rt...> Date: Tue Jan 14 12:09:18 2020 +0000 mips: Fix UASWM and UALWM instructions for nanoMIPS UASWM and UALWM have not been implemented correctly. Code used to implement SWM and LWM has been reused without making all of the required adjustments. This fixes memcpy() and memset() libc functions. Diff: --- VEX/priv/guest_nanomips_toIR.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c index 373ba5f..7233a73 100755 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -2086,19 +2086,27 @@ static void nano_plsuawm(DisResult *dres, UInt cins) UChar count3 = (cins >> 12) & 0x07; UChar count = count3 ? count3 : 8; UChar counter = 0; - UInt offset = extend_sign(s, 9); + UInt offset = s; UChar rt_tmp, offset_tmp; - if ((cins >> 11) & 0x01) { /* swm */ - while (counter++ != count) { + if ((cins >> 11) & 0x01) { /* uaswm */ + + DIP("uaswm r%u, %d(r%u), %u", rt, (int)offset, rs, count); + + while (counter != count) { rt_tmp = rt ? (rt & 0x10) | ((rt + counter) & 0x1F) : 0; offset_tmp = offset + (counter << 2); store(binop(Iop_Add32, getIReg(rs), mkU32(offset_tmp)), getIReg(rt_tmp)); + counter+=1; } - } else { /* lwm */ - while (counter++ != count) { - rt_tmp = (rt & 0x10) | (rt + counter); + + } else { /* ualwm */ + + DIP("ualwm r%u, %d(r%u), %u", rt, (int)offset, rs, count); + + while (counter != count) { + rt_tmp = (rt & 0x10) | ((rt + counter) & 0x1F); offset_tmp = offset + (counter << 2); putIReg(rt_tmp, load(Ity_I32, binop(Iop_Add32, getIReg(rs), mkU32(offset_tmp)))); @@ -2107,6 +2115,7 @@ static void nano_plsuawm(DisResult *dres, UInt cins) vassert(0); // raise UNPREDICTABLE() } + counter+=1; } } |
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From: Petar J. <pe...@so...> - 2020-01-14 12:14:24
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0fb2f59f57df506b39bd6959d69b87aa4d4143aa commit 0fb2f59f57df506b39bd6959d69b87aa4d4143aa Author: Aleksandar Rikalo <ale...@rt...> Date: Tue Jan 14 12:07:11 2020 +0000 mips: Change client request convention for nanoMIPS Use a7/t0 register pair for for client requests. The same convention is used throughout the rest of the code, as well as for mips32/64. Diff: --- VEX/priv/guest_nanomips_toIR.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c index 67f2313..373ba5f 100755 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -2987,15 +2987,15 @@ static Bool check_for_special_requests_nanoMIPS(DisResult *dres, getUInt(code + 8) == word3 && getUInt(code + 12) == word4) { /* Got a "Special" instruction preamble. Which one is it? */ if (getUInt(code + 16) == 0x218C6290 /* or t0, t0, t0 */ ) { - /* $a0 = client_request ( $a1 ) */ - DIP("a0 = client_request(a1)"); + /* $a7 = client_request ( $t0 ) */ + DIP("a7 = client_request(t0)"); dres->jk_StopHere = Ijk_ClientReq; dres->whatNext = Dis_StopHere; dres->len = 20; return True; } else if (getUInt(code + 16) == 0x21AD6A90 /* or t1, t1, t1 */ ) { - /* $a0 = guest_NRADDR */ - DIP("a0 = guest_NRADDR"); + /* $a7 = guest_NRADDR */ + DIP("a7 = guest_NRADDR"); putIReg(11, IRExpr_Get(offsetof(VexGuestMIPS32State, guest_NRADDR), Ity_I32)); dres->len = 20; |
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From: Petar J. <pe...@so...> - 2020-01-14 12:14:17
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d4d92fe5db8942e55b27398ccdafe927454271b6 commit d4d92fe5db8942e55b27398ccdafe927454271b6 Author: Aleksandar Rikalo <ale...@rt...> Date: Tue Jan 14 12:04:31 2020 +0000 mips: Fix Ist_CAS for nanoMIPS This code portion introduced a SEGFAULT: - if (&i->NMin.Cas.sz){ + if (i->NMin.Cas.sz == 8) { The implementation of Ist_Cas has been fixed and missing logging has been added as well. Diff: --- VEX/priv/host_nanomips_defs.c | 92 ++++++++++++++++++++++++++++++++----------- 1 file changed, 70 insertions(+), 22 deletions(-) diff --git a/VEX/priv/host_nanomips_defs.c b/VEX/priv/host_nanomips_defs.c index eadac53..9f0b975 100644 --- a/VEX/priv/host_nanomips_defs.c +++ b/VEX/priv/host_nanomips_defs.c @@ -605,9 +605,8 @@ void ppNANOMIPSInstr(const NANOMIPSInstr* i) break; case NMin_Cas: - if (i->NMin.Cas.sz == 4){ - vex_printf("cas: \n"); - + vex_printf("cas: \n"); + if (i->NMin.Cas.sz == 4) { vex_printf("ll "); ppHRegNANOMIPS(i->NMin.Cas.oldLo); vex_printf(", 0("); @@ -639,9 +638,61 @@ void ppNANOMIPSInstr(const NANOMIPSInstr* i) vex_printf(", "); ppHRegNANOMIPS(i->NMin.Cas.dataLo); vex_printf("; end:"); - } - else{ - vassert(0); + } else { + vex_printf("llwp "); + ppHRegNANOMIPS(i->NMin.Cas.oldLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.oldHi); + vex_printf(", 0("); + ppHRegNANOMIPS(i->NMin.Cas.addr); + vex_printf("); "); + + vex_printf("bnec "); + ppHRegNANOMIPS(i->NMin.Cas.oldLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.expdLo); + vex_printf(", end; "); + + vex_printf("bnec "); + ppHRegNANOMIPS(i->NMin.Cas.oldHi); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.expdHi); + vex_printf(", end; "); + + vex_printf("addiu "); + ppHRegNANOMIPS(i->NMin.Cas.oldLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.oldLo); + vex_printf(", 1; "); + + vex_printf("addiu "); + ppHRegNANOMIPS(i->NMin.Cas.oldHi); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.oldHi); + vex_printf(", 1; "); + + vex_printf("scwp "); + ppHRegNANOMIPS(i->NMin.Cas.dataLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.dataHi); + vex_printf(", 0("); + ppHRegNANOMIPS(i->NMin.Cas.addr); + vex_printf("); "); + + vex_printf("movn "); + ppHRegNANOMIPS(i->NMin.Cas.oldLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.expdLo); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.dataLo); + + vex_printf("movn "); + ppHRegNANOMIPS(i->NMin.Cas.oldHi); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.expdHi); + vex_printf(", "); + ppHRegNANOMIPS(i->NMin.Cas.dataHi); + vex_printf("; end:"); } break; @@ -807,18 +858,13 @@ void getRegUsage_NANOMIPSInstr(HRegUsage* u, const NANOMIPSInstr* i) return; case NMin_Cas: - if (i->NMin.Cas.sz == 4){ - addHRegUse(u, HRmWrite, i->NMin.Cas.oldLo); - addHRegUse(u, HRmRead, i->NMin.Cas.addr); - addHRegUse(u, HRmRead, i->NMin.Cas.expdLo); - addHRegUse(u, HRmModify, i->NMin.Cas.dataLo); - } else { - addHRegUse(u, HRmWrite, i->NMin.Cas.oldLo); + addHRegUse(u, HRmWrite, i->NMin.Cas.oldLo); + addHRegUse(u, HRmRead, i->NMin.Cas.addr); + addHRegUse(u, HRmRead, i->NMin.Cas.expdLo); + addHRegUse(u, HRmModify, i->NMin.Cas.dataLo); + if (i->NMin.Cas.sz == 8) { addHRegUse(u, HRmWrite, i->NMin.Cas.oldHi); - addHRegUse(u, HRmRead, i->NMin.Cas.addr); - addHRegUse(u, HRmRead, i->NMin.Cas.expdLo); addHRegUse(u, HRmRead, i->NMin.Cas.expdHi); - addHRegUse(u, HRmModify, i->NMin.Cas.dataLo); addHRegUse(u, HRmModify, i->NMin.Cas.dataHi); } return; @@ -938,7 +984,7 @@ void mapRegs_NANOMIPSInstr(HRegRemap * m, NANOMIPSInstr * i) mapReg(m, &i->NMin.Cas.addr); mapReg(m, &i->NMin.Cas.expdLo); mapReg(m, &i->NMin.Cas.dataLo); - if (&i->NMin.Cas.sz){ + if (i->NMin.Cas.sz == 8) { mapReg(m, &i->NMin.Cas.oldHi); mapReg(m, &i->NMin.Cas.expdHi); mapReg(m, &i->NMin.Cas.dataHi); @@ -1785,15 +1831,17 @@ Int emit_NANOMIPSInstr ( /*MB_MOD*/Bool* is_profInc, } case NMin_Cas: { + vassert((i->NMin.Cas.sz == 4) || (i->NMin.Cas.sz == 8)); UInt oldLo = iregNo(i->NMin.Cas.oldLo); - UInt oldHi = iregNo(i->NMin.Cas.oldHi); UInt addr = iregNo(i->NMin.Cas.addr); UInt expdLo = iregNo(i->NMin.Cas.expdLo); - UInt expdHi = iregNo(i->NMin.Cas.expdHi); UInt dataLo = iregNo(i->NMin.Cas.dataLo); - UInt dataHi = iregNo(i->NMin.Cas.dataHi); - - vassert((i->NMin.Cas.sz == 4) || (i->NMin.Cas.sz == 8)); + UInt oldHi = 0, expdHi = 0, dataHi = 0; + if (i->NMin.Cas.sz == 8) { + oldHi = iregNo(i->NMin.Cas.oldHi); + expdHi = iregNo(i->NMin.Cas.expdHi); + dataHi = iregNo(i->NMin.Cas.dataHi); + } if (i->NMin.Cas.sz == 4) { /* |
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From: Petar J. <pe...@so...> - 2020-01-14 11:55:31
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=43c90db16fdc3cfa9a3f11f409e2e3689d161978 commit 43c90db16fdc3cfa9a3f11f409e2e3689d161978 Author: Aleksandar Rikalo <ale...@rt...> Date: Tue Jan 14 11:54:15 2020 +0000 mips: Fix SAVE instruction for nanoMIPS During a save (push) instruction adjusting the SP is required before doing a store, otherwise Memcheck reports warning because of a write operation outside of the stack area. Diff: --- VEX/priv/guest_nanomips_toIR.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c index 2000896..67f2313 100755 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -980,17 +980,21 @@ static void nano_ppsr(DisResult *dres, UInt cins) DIP("save %u, r%u-r%u", u, (rt & 0x1fu) | (rt & 0x10u), ((rt + count - 1) & 0x1fu) | (rt & 0x10u)); + IRTemp t1 = newTemp(Ity_I32); + assign(t1, getIReg(29)); + + putIReg(29, binop(Iop_Sub32, mkexpr(t1), mkU32(u))); + while (counter != count) { Bool use_gp = (cins & 0x04) && (counter + 1 == count); UChar this_rt = use_gp ? 28 : (UChar)((rt + counter) & 0x1f) | (rt & 0x10); Int offset = -((counter + 1) << 2); - store(binop(Iop_Add32, getIReg(29), mkU32(offset)), + store(binop(Iop_Add32, mkexpr(t1), mkU32(offset)), getIReg(this_rt)); counter++; } - putIReg(29, binop(Iop_Sub32, getIReg(29), mkU32(u))); break; } @@ -2328,14 +2332,17 @@ static void nano_p16sr(DisResult *dres, UShort cins) DIP("save %u, r%u-r%u", u, (rt & 0x1fu) | (rt & 0x10u), ((rt + count - 1) & 0x1fu) | (rt & 0x10u)); + IRTemp t1 = newTemp(Ity_I32); + assign(t1, getIReg(29)); + + putIReg(29, binop(Iop_Sub32, mkexpr(t1), mkU32(u))); + while (counter != count) { UChar this_rt = ((rt + counter) & 0x1f) | (rt & 0x10); Int offset = -((counter + 1) << 2); - store(binop(Iop_Add32, getIReg(29), mkU32(offset)), getIReg(this_rt)); + store(binop(Iop_Add32, mkexpr(t1), mkU32(offset)), getIReg(this_rt)); counter++; } - - putIReg(29, binop(Iop_Sub32, getIReg(29), mkU32(u))); } } |
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From: Petar J. <pe...@so...> - 2020-01-14 11:55:27
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6eb5b451d31c3fb117bf61e0a62cf743dde83945 commit 6eb5b451d31c3fb117bf61e0a62cf743dde83945 Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 09:48:56 2020 +0000 mips: Fix BRSC and BALRSC instructions for nanoMIPS Basic blocks should be terminated after detecting branch instruction. Diff: --- VEX/priv/guest_nanomips_toIR.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/VEX/priv/guest_nanomips_toIR.c b/VEX/priv/guest_nanomips_toIR.c old mode 100644 new mode 100755 index ad099ed..2000896 --- a/VEX/priv/guest_nanomips_toIR.c +++ b/VEX/priv/guest_nanomips_toIR.c @@ -2547,8 +2547,10 @@ static void nano_pj(DisResult *dres, UInt cins) putIReg(rt, mkU32(guest_PC_curr_instr + 4)); putPC(mkexpr(t1)); } + dres->jk_StopHere = Ijk_Boring; + dres->whatNext = Dis_StopHere; + break; } - break; } } |
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From: Petar J. <pe...@so...> - 2020-01-14 11:55:21
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1d3a772034d0c8243882c2f43afcb7245d707bf4 commit 1d3a772034d0c8243882c2f43afcb7245d707bf4 Author: Petar Jovanovic <mip...@gm...> Date: Tue Jan 14 09:31:48 2020 +0000 mips: Fix clone syscall for nanoMIPS - Reset syscall return register (a0) in clone_new_thread() - Use "syscall[32]" asm idiom instead of "syscall" with immediate parameter in ML_ (call_on_new_stack_0_1)() - Optimize stack usage in ML_ (call_on_new_stack_0_1)() - Code refactor of ML_ (call_on_new_stack_0_1)() It partially fixes all tests which use clone system call, e.g. none/tests/pth_atfork1. Patch by Aleksandar Rikalo. Diff: --- coregrind/m_syswrap/syswrap-linux.c | 2 +- coregrind/m_syswrap/syswrap-nanomips-linux.c | 99 ++++++++++++++-------------- 2 files changed, 49 insertions(+), 52 deletions(-) diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index 96c309e..25d9a95 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -528,7 +528,7 @@ static SysRes clone_new_thread ( Word (*fn)(void *), res = VG_ (mk_SysRes_mips32_linux) (/*val */ ret, 0, /*errflag */ 0); #elif defined(VGP_nanomips_linux) UInt ret = 0; - ctst->arch.vex.guest_r2 = 0; + ctst->arch.vex.guest_r4 = 0; ret = do_syscall_clone_nanomips_linux (ML_(start_thread_NORETURN), stack, flags, ctst, child_tidptr, parent_tidptr, NULL); diff --git a/coregrind/m_syswrap/syswrap-nanomips-linux.c b/coregrind/m_syswrap/syswrap-nanomips-linux.c index aac595a..0badf56 100644 --- a/coregrind/m_syswrap/syswrap-nanomips-linux.c +++ b/coregrind/m_syswrap/syswrap-nanomips-linux.c @@ -88,24 +88,24 @@ asm ( " move $ra, $a1 \n\t" // retaddr to $ra " move $t9, $a2 \n\t" // f to t9 " move $a0, $a3 \n\t" // arg1 to $a0 - " li $t4, 0\n\t" // zero all GP regs - " li $t5, 0\n\t" - " li $a1, 0\n\t" - " li $a2, 0\n\t" - " li $a3, 0\n\t" - " li $t0, 0\n\t" - " li $t1, 0\n\t" - " li $t2, 0\n\t" - " li $t3, 0\n\t" - " li $s0, 0\n\t" - " li $s1, 0\n\t" - " li $s2, 0\n\t" - " li $s3, 0\n\t" - " li $s4, 0\n\t" - " li $s5, 0\n\t" - " li $s6, 0\n\t" - " li $s7, 0\n\t" - " li $t8, 0\n\t" + " li $t4, 0 \n\t" // zero all GP regs + " li $t5, 0 \n\t" + " li $a1, 0 \n\t" + " li $a2, 0 \n\t" + " li $a3, 0 \n\t" + " li $t0, 0 \n\t" + " li $t1, 0 \n\t" + " li $t2, 0 \n\t" + " li $t3, 0 \n\t" + " li $s0, 0 \n\t" + " li $s1, 0 \n\t" + " li $s2, 0 \n\t" + " li $s3, 0 \n\t" + " li $s4, 0 \n\t" + " li $s5, 0 \n\t" + " li $s6, 0 \n\t" + " li $s7, 0 \n\t" + " li $t8, 0 \n\t" " jrc $t9 \n\t" // jump to dst " break 0x7 \n" // should never get here ".previous\n" @@ -142,48 +142,45 @@ asm ( // See priv_syswrap-linux.h for arg profile. asm ( -" .text\n" -" .set noreorder\n" -" .set nomacro\n" -" .globl do_syscall_clone_nanomips_linux\n" -" do_syscall_clone_nanomips_linux:\n" -" addiu $sp, $sp, -32\n" -" sw $ra, 0($sp) \n\t" -" sw $fp, 4($sp) \n\t" -" sw $gp, 8($sp) \n\t" -" sw $t4, 12($sp) \n\t" - -" addiu $a1, $a1, -32\n" -" sw $a0, 0($a1)\n" /* fn */ -" sw $a3, 4($a1)\n" /* arg */ -" sw $a2, 8($a1)\n" /* flags */ - +" .text \n" +" .set noreorder \n" +" .set nomacro \n" +" .globl do_syscall_clone_nanomips_linux \n" +" do_syscall_clone_nanomips_linux: \n\t" +" addiu $sp, $sp, -16 \n\t" +" sw $ra, 0($sp) \n\t" +" sw $fp, 4($sp) \n\t" +" sw $gp, 8($sp) \n\t" + +" addiu $a1, $a1, -16 \n\t" +" sw $a0, 0($a1) \n\t" /* fn */ +" sw $a3, 4($a1) \n\t" /* arg */ /* 1. arg for syscalls */ -" move $a0, $a2\n" /* flags */ -" move $a2, $a5\n" /* parent */ -" move $a3, $a6\n" /* tls */ +" move $a0, $a2 \n\t" /* flags */ +" move $a2, $a5 \n\t" /* parent */ +" move $a3, $a6 \n\t" /* tls */ /* 2. do a syscall to clone */ -" li $t4, " __NR_CLONE "\n\t" /* __NR_clone */ -" syscall 1\n" +" li $t4, " __NR_CLONE "\n\t" /* __NR_clone */ +" syscall[32] \n\t" /* 3. See if we are a child, call fn and after that exit */ -" bnezc $a0, p_or_error\n" +" bnezc $a0, p_or_error \n\t" + +" lw $t9, 0($sp) \n\t" +" lw $a0, 4($sp) \n\t" +" jalrc $t9 \n\t" -" lw $t9,0($sp)\n" -" lw $a0,4($sp)\n" -" jalrc $t9\n" +" li $t4, " __NR_EXIT "\n\t" /* NR_exit */ +" syscall[32] \n" -" li $t4, " __NR_EXIT "\n\t" /* NR_exit */ -" syscall 1\n\t" /* 4. If we are parent or error, just return to caller */ -" p_or_error:\n" -" lw $ra, 0($sp)\n" -" lw $fp, 4($sp)\n" -" lw $gp, 8($sp)\n" -" lw $t4, 12($sp)\n" -" addiu $sp,$sp, 32\n" +" p_or_error: \n\t" +" lw $ra, 0($sp) \n\t" +" lw $fp, 4($sp) \n\t" +" lw $gp, 8($sp) \n\t" +" addiu $sp, $sp, 16 \n\t" " jrc $ra\n" " .previous\n" |