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From: Petar J. <pe...@so...> - 2019-11-27 13:33:36
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b150644902b99669664dc83e6ca9887ae76747cc commit b150644902b99669664dc83e6ca9887ae76747cc Author: Petar Jovanovic <mip...@gm...> Date: Wed Nov 27 13:32:57 2019 +0000 mips64: use generic Linux wrapper for sys_unshare No need for mips64-specific Linux wrappers for sys_unshare. Diff: --- coregrind/m_syswrap/syswrap-mips64-linux.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/coregrind/m_syswrap/syswrap-mips64-linux.c b/coregrind/m_syswrap/syswrap-mips64-linux.c index d0bb3cd..b1f548a 100644 --- a/coregrind/m_syswrap/syswrap-mips64-linux.c +++ b/coregrind/m_syswrap/syswrap-mips64-linux.c @@ -226,7 +226,6 @@ DECL_TEMPLATE (mips_linux, sys_sethostname); DECL_TEMPLATE (mips_linux, sys_reboot); DECL_TEMPLATE (mips_linux, sys_cacheflush); DECL_TEMPLATE (mips_linux, sys_sched_rr_get_interval); -DECL_TEMPLATE (mips_linux, sys_unshare); DECL_TEMPLATE (mips_linux, sys_prctl); DECL_TEMPLATE (mips_linux, sys_ptrace); DECL_TEMPLATE (mips_linux, sys_mmap); @@ -242,12 +241,6 @@ PRE(sys_vmsplice) vki_size_t, len, int, flags); } -PRE(sys_unshare) -{ - PRINT("sys_unshare ( %" FMT_REGWORD "u )", ARG1); - PRE_REG_READ1(long, "sys_unshare", unsigned long, flags); -} - PRE(sys_sched_rr_get_interval) { PRINT("sys_sched_rr_get_interval ( %ld, %#" FMT_REGWORD "x)", SARG1, ARG2); @@ -784,7 +777,7 @@ static SyscallTableEntry syscall_main_table[] = { LINX_ (__NR_faccessat, sys_faccessat), LINXY (__NR_pselect6, sys_pselect6), LINXY (__NR_ppoll, sys_ppoll), - PLAX_ (__NR_unshare, sys_unshare), + LINX_ (__NR_unshare, sys_unshare), LINX_ (__NR_splice, sys_splice), LINX_ (__NR_sync_file_range, sys_sync_file_range), LINX_ (__NR_tee, sys_tee), |
|
From: Petar J. <pe...@so...> - 2019-11-27 12:25:19
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7c2e222b118f6168211f20c028b8debcb3023c45 commit 7c2e222b118f6168211f20c028b8debcb3023c45 Author: Petar Jovanovic <mip...@gm...> Date: Wed Nov 27 12:22:46 2019 +0000 mips: enable sloppyXcheck for mips32 and mips64 Newer mips kernels (post 4.7.0) assign execute permissions to loadable program segments which originally did not have them as per the information provided in the elf file itself. Include mips32/mips64 in the list of architectures for which the address space manager should allow the kernel to report execute permissions in sync_check_mapping_callback. Patch by Stefan Maksimovic. Diff: --- coregrind/m_aspacemgr/aspacemgr-linux.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/coregrind/m_aspacemgr/aspacemgr-linux.c b/coregrind/m_aspacemgr/aspacemgr-linux.c index 7ddef30..7c4c4eb 100644 --- a/coregrind/m_aspacemgr/aspacemgr-linux.c +++ b/coregrind/m_aspacemgr/aspacemgr-linux.c @@ -818,7 +818,8 @@ static void sync_check_mapping_callback ( Addr addr, SizeT len, UInt prot, have a sloppyXcheck mode which we enable on x86 and s390 - in this mode we allow the kernel to report execute permission when we weren't expecting it but not vice versa. */ -# if defined(VGA_x86) || defined (VGA_s390x) +# if defined(VGA_x86) || defined (VGA_s390x) || \ + defined(VGA_mips32) || defined(VGA_mips64) sloppyXcheck = True; # else sloppyXcheck = False; |
|
From: Petar J. <pe...@so...> - 2019-11-27 12:15:04
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=da6f04b9249054ab815ac815ef5efbb470f731b8 commit da6f04b9249054ab815ac815ef5efbb470f731b8 Author: Petar Jovanovic <mip...@gm...> Date: Wed Nov 27 12:00:43 2019 +0000 mips: add ld-linux-mipsn8.so.1 as a valid soname NaN2008 dynamic linker is named ld-linux-mipsn8.so.1. Update include/pub_tool_redir.h by adding ld-linux-mipsn8.so.1 to the list of sonames with an accompanying check in coregrind/m_redir.c. Patch by Stefan Maksimovic. Diff: --- coregrind/m_redir.c | 1 + include/pub_tool_redir.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c index d1211c5..1a1117e 100644 --- a/coregrind/m_redir.c +++ b/coregrind/m_redir.c @@ -1211,6 +1211,7 @@ Bool VG_(is_soname_ld_so) (const HChar *soname) if (VG_STREQ(soname, VG_U_LD_SO_1)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_AARCH64_SO_1)) return True; if (VG_STREQ(soname, VG_U_LD_LINUX_ARMHF_SO_3)) return True; + if (VG_STREQ(soname, VG_U_LD_LINUX_MIPSN8_S0_1)) return True; # elif defined(VGO_darwin) if (VG_STREQ(soname, VG_U_DYLD)) return True; # elif defined(VGO_solaris) diff --git a/include/pub_tool_redir.h b/include/pub_tool_redir.h index e194ddb..bd65a44 100644 --- a/include/pub_tool_redir.h +++ b/include/pub_tool_redir.h @@ -316,6 +316,8 @@ #define VG_U_LD_LINUX_ARMHF_SO_3 "ld-linux-armhf.so.3" +#define VG_U_LD_LINUX_MIPSN8_S0_1 "ld-linux-mipsn8.so.1" + #endif /* --- Executable name for Darwin Mach-O linker. --- */ |
|
From: Petar J. <pe...@so...> - 2019-11-27 12:14:59
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fbb8ce693d789af0a45f1a8ab7eb89cc80085925 commit fbb8ce693d789af0a45f1a8ab7eb89cc80085925 Author: Petar Jovanovic <mip...@gm...> Date: Tue Nov 26 13:33:15 2019 +0000 update .gitignore with /none/tests/amd64/avx_estimate_insn Add /none/tests/amd64/avx_estimate_insn to .gitignore. Diff: --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 7c3d304..bacb265 100644 --- a/.gitignore +++ b/.gitignore @@ -1473,6 +1473,7 @@ /none/tests/amd64/asorep /none/tests/amd64/avx-1 /none/tests/amd64/avx2-1 +/none/tests/amd64/avx_estimate_insn /none/tests/amd64/bmi /none/tests/amd64/bt_flags /none/tests/amd64/bug127521-64 |
|
From: Julian S. <se...@so...> - 2019-11-27 07:53:54
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d072997a1dc701bb8c436a7181302d351cacd3c1 commit d072997a1dc701bb8c436a7181302d351cacd3c1 Author: Julian Seward <js...@ac...> Date: Wed Nov 27 08:52:45 2019 +0100 'grail' fixes for ppc32 and ppc64: * do_minimal_initial_iropt_BB: for ppc64, flatten rather than assert flatness. (Kludge. Sigh.) * priv/host_ppc_isel.c iselCondCode_wrk(): handle And1 and Or1, the not-particularly-optimal way * priv/host_ppc_isel.c iselCondCode_wrk(): handle Ico_U1(0). Diff: --- VEX/priv/host_ppc_isel.c | 31 ++++++++++++++++++++++++++++--- VEX/priv/ir_opt.c | 11 ++++++++++- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 5e2a3b8..9c954da 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -3095,13 +3095,15 @@ static PPCCondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e, vassert(typeOfIRExpr(env->type_env,e) == Ity_I1); /* Constant 1:Bit */ - if (e->tag == Iex_Const && e->Iex.Const.con->Ico.U1 == True) { - // Make a compare that will always be true: + if (e->tag == Iex_Const) { + // Make a compare that will always be true (or always false): + vassert(e->Iex.Const.con->Ico.U1 == True || e->Iex.Const.con->Ico.U1 == False); HReg r_zero = newVRegI(env); addInstr(env, PPCInstr_LI(r_zero, 0, env->mode64)); addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/, 7/*cr*/, r_zero, PPCRH_Reg(r_zero))); - return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ ); + return mk_PPCCondCode( e->Iex.Const.con->Ico.U1 ? Pct_TRUE : Pct_FALSE, + Pcf_7EQ ); } /* Not1(...) */ @@ -3260,6 +3262,29 @@ static PPCCondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e, return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ ); } + /* --- And1(x,y), Or1(x,y) --- */ + /* FIXME: We could (and probably should) do a lot better here, by using the + iselCondCode_C/_R scheme used in the amd64 insn selector. */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_And1 || e->Iex.Binop.op == Iop_Or1)) { + HReg x_as_int = newVRegI(env); + PPCCondCode cc_x = iselCondCode(env, e->Iex.Binop.arg1, IEndianess); + addInstr(env, PPCInstr_Set(cc_x, x_as_int)); + + HReg y_as_int = newVRegI(env); + PPCCondCode cc_y = iselCondCode(env, e->Iex.Binop.arg2, IEndianess); + addInstr(env, PPCInstr_Set(cc_y, y_as_int)); + + HReg tmp = newVRegI(env); + PPCAluOp op = e->Iex.Binop.op == Iop_And1 ? Palu_AND : Palu_OR; + addInstr(env, PPCInstr_Alu(op, tmp, x_as_int, PPCRH_Reg(y_as_int))); + + addInstr(env, PPCInstr_Alu(Palu_AND, tmp, tmp, PPCRH_Imm(False,1))); + addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/, + 7/*cr*/, tmp, PPCRH_Imm(False,1))); + return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ ); + } + vex_printf("iselCondCode(ppc): No such tag(%u)\n", e->tag); ppIRExpr(e); vpanic("iselCondCode(ppc)"); diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c index 7f39924..c5b7a2f 100644 --- a/VEX/priv/ir_opt.c +++ b/VEX/priv/ir_opt.c @@ -6682,7 +6682,16 @@ IRSB* do_iropt_BB( processed by do_minimal_initial_iropt_BB. And that will have flattened them out. */ // FIXME Remove this assertion once the 'grail' machinery seems stable - vassert(isFlatIRSB(bb0)); + // FIXME2 The TOC-redirect-hacks generators in m_translate.c -- gen_PUSH() + // and gen_PO() -- don't generate flat IR, and so cause this assertion + // to fail. For the time being, hack around this by flattening, + // rather than asserting for flatness, on the afflicted platforms. + // This is a kludge, yes. + if (guest_arch == VexArchPPC64) { + bb0 = flatten_BB(bb0); // Kludge! + } else { + vassert(isFlatIRSB(bb0)); // How it Really Should Be (tm). + } /* If at level 0, stop now. */ if (vex_control.iropt_level <= 0) return bb0; |
|
From: Julian S. <se...@so...> - 2019-11-27 05:38:31
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=effd32dd0e79a3100e767c6b76a1635af0bf1002 commit effd32dd0e79a3100e767c6b76a1635af0bf1002 Author: Julian Seward <js...@ac...> Date: Wed Nov 27 06:37:42 2019 +0100 'grail' fixes for arm32: * priv/guest_generic_bb_to_IR.c expr_is_guardable(), stmt_is_guardable(): add some missing cases * do_minimal_initial_iropt_BB: add comment (no functional change) * priv/host_arm_isel.c iselCondCode_wrk(): handle And1 and Or1, the not-particularly-optimal way Diff: --- VEX/priv/guest_generic_bb_to_IR.c | 4 ++++ VEX/priv/host_arm_isel.c | 24 ++++++++++++++++++++++++ VEX/priv/ir_opt.c | 2 ++ 3 files changed, 30 insertions(+) diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c index 677cfca..6a1d4dc 100644 --- a/VEX/priv/guest_generic_bb_to_IR.c +++ b/VEX/priv/guest_generic_bb_to_IR.c @@ -426,6 +426,7 @@ static Bool expr_is_guardable ( const IRExpr* e ) case Iex_CCall: case Iex_Get: case Iex_Const: + case Iex_RdTmp: return True; default: vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); @@ -446,6 +447,7 @@ static Bool stmt_is_guardable ( const IRStmt* st ) { switch (st->tag) { // These are easily guarded. + case Ist_NoOp: case Ist_IMark: case Ist_Put: return True; @@ -458,6 +460,7 @@ static Bool stmt_is_guardable ( const IRStmt* st ) // These could be guarded, with some effort, if really needed, but // currently aren't guardable. case Ist_Store: + case Ist_StoreG: case Ist_Exit: return False; // This is probably guardable, but it depends on the RHS of the @@ -492,6 +495,7 @@ static void add_guarded_stmt_to_end_of ( /*MOD*/IRSB* bb, /*IN*/ IRStmt* st, IRTemp guard ) { switch (st->tag) { + case Ist_NoOp: case Ist_IMark: case Ist_WrTmp: addStmtToIRSB(bb, st); diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index 510336b..acbd39a 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -1293,6 +1293,30 @@ static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) return e->Iex.Const.con->Ico.U1 ? ARMcc_EQ : ARMcc_NE; } + /* --- And1(x,y), Or1(x,y) --- */ + /* FIXME: We could (and probably should) do a lot better here, by using the + iselCondCode_C/_R scheme used in the amd64 insn selector. */ + if (e->tag == Iex_Binop + && (e->Iex.Binop.op == Iop_And1 || e->Iex.Binop.op == Iop_Or1)) { + HReg x_as_32 = newVRegI(env); + ARMCondCode cc_x = iselCondCode(env, e->Iex.Binop.arg1); + addInstr(env, ARMInstr_Mov(x_as_32, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cc_x, x_as_32, ARMRI84_I84(1,0))); + + HReg y_as_32 = newVRegI(env); + ARMCondCode cc_y = iselCondCode(env, e->Iex.Binop.arg2); + addInstr(env, ARMInstr_Mov(y_as_32, ARMRI84_I84(0,0))); + addInstr(env, ARMInstr_CMov(cc_y, y_as_32, ARMRI84_I84(1,0))); + + HReg tmp = newVRegI(env); + ARMAluOp aop = e->Iex.Binop.op == Iop_And1 ? ARMalu_AND : ARMalu_OR; + addInstr(env, ARMInstr_Alu(aop, tmp, x_as_32, ARMRI84_R(y_as_32))); + + ARMRI84* one = ARMRI84_I84(1,0); + addInstr(env, ARMInstr_CmpOrTst(False/*test*/, tmp, one)); + return ARMcc_NE; + } + // JRS 2013-Jan-03: this seems completely nonsensical /* --- CasCmpEQ* --- */ /* Ist_Cas has a dummy argument to compare with, so comparison is diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c index d3bc989..7f39924 100644 --- a/VEX/priv/ir_opt.c +++ b/VEX/priv/ir_opt.c @@ -6783,6 +6783,8 @@ IRSB* do_minimal_initial_iropt_BB(IRSB* bb0) { redundant_get_removal_BB ( bb ); // Do minimal constant prop: copy prop and constant prop only. No folding. + // JRS FIXME 2019Nov25: this is too weak to be effective on arm32. For that, + // specifying doFolding=True makes a huge difference. bb = cprop_BB_WRK ( bb, /*mustRetainNoOps=*/True, /*doFolding=*/False ); |