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From: Julian S. <se...@so...> - 2018-12-22 05:12:10
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6cb6bdbd0a38e9b5f5c4f676afb72a23b6bfb1b5 commit 6cb6bdbd0a38e9b5f5c4f676afb72a23b6bfb1b5 Author: Julian Seward <js...@ac...> Date: Sat Dec 22 06:06:19 2018 +0100 amd64 hosts: detect SSSE3 (not SSE3) capabilities on the host. As-yet unused. n-i-bz. Diff: --- VEX/priv/guest_amd64_toIR.c | 6 +++--- VEX/priv/host_amd64_isel.c | 1 + VEX/priv/main_main.c | 22 ++++++++++++++-------- VEX/pub/libvex.h | 1 + coregrind/m_machine.c | 13 ++++++++++--- 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 2cabf80..e753ffa 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -22071,21 +22071,21 @@ Long dis_ESC_0F ( /* This isn't entirely correct, CPUID should depend on the VEX capabilities, not on the underlying CPU. See bug #324882. */ - if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) && + if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSSE3) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) { fName = "amd64g_dirtyhelper_CPUID_avx2"; fAddr = &amd64g_dirtyhelper_CPUID_avx2; /* This is a Core-i7-4910-like machine */ } - else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) && + else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSSE3) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { fName = "amd64g_dirtyhelper_CPUID_avx_and_cx16"; fAddr = &amd64g_dirtyhelper_CPUID_avx_and_cx16; /* This is a Core-i5-2300-like machine */ } - else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) && + else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSSE3) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16)) { fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16"; fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16; diff --git a/VEX/priv/host_amd64_isel.c b/VEX/priv/host_amd64_isel.c index 1787e87..05e2e72 100644 --- a/VEX/priv/host_amd64_isel.c +++ b/VEX/priv/host_amd64_isel.c @@ -4953,6 +4953,7 @@ HInstrArray* iselSB_AMD64 ( const IRSB* bb, vassert(arch_host == VexArchAMD64); vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3 + | VEX_HWCAPS_AMD64_SSSE3 | VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 41ad371..f387f16 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1575,6 +1575,7 @@ static const HChar* show_hwcaps_amd64 ( UInt hwcaps ) { VEX_HWCAPS_AMD64_LZCNT, "lzcnt" }, { VEX_HWCAPS_AMD64_RDTSCP, "rdtscp" }, { VEX_HWCAPS_AMD64_SSE3, "sse3" }, + { VEX_HWCAPS_AMD64_SSSE3, "ssse3" }, { VEX_HWCAPS_AMD64_AVX, "avx" }, { VEX_HWCAPS_AMD64_AVX2, "avx2" }, { VEX_HWCAPS_AMD64_BMI, "bmi" }, @@ -1881,15 +1882,20 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps ) orthogonal. */ /* Throw out obviously stupid cases: */ - Bool have_sse3 = (hwcaps & VEX_HWCAPS_AMD64_SSE3) != 0; - Bool have_avx = (hwcaps & VEX_HWCAPS_AMD64_AVX) != 0; - Bool have_bmi = (hwcaps & VEX_HWCAPS_AMD64_BMI) != 0; - Bool have_avx2 = (hwcaps & VEX_HWCAPS_AMD64_AVX2) != 0; - - /* AVX without SSE3 */ - if (have_avx && !have_sse3) + Bool have_sse3 = (hwcaps & VEX_HWCAPS_AMD64_SSE3) != 0; + Bool have_ssse3 = (hwcaps & VEX_HWCAPS_AMD64_SSSE3) != 0; + Bool have_avx = (hwcaps & VEX_HWCAPS_AMD64_AVX) != 0; + Bool have_bmi = (hwcaps & VEX_HWCAPS_AMD64_BMI) != 0; + Bool have_avx2 = (hwcaps & VEX_HWCAPS_AMD64_AVX2) != 0; + + /* SSSE3 without SSE3 */ + if (have_ssse3 && !have_sse3) + invalid_hwcaps(arch, hwcaps, + "Support for SSSE3 requires SSE3 capabilities\n"); + /* AVX without SSSE3 */ + if (have_avx && !have_ssse3) invalid_hwcaps(arch, hwcaps, - "Support for AVX requires SSE3 capabilities\n"); + "Support for AVX requires SSSE3 capabilities\n"); /* AVX2 or BMI without AVX */ if (have_avx2 && !have_avx) invalid_hwcaps(arch, hwcaps, diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index e6c1974..629a258 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -92,6 +92,7 @@ typedef /* amd64: baseline capability is SSE2, with cmpxchg8b but not cmpxchg16b. */ #define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */ +#define VEX_HWCAPS_AMD64_SSSE3 (1<<12) /* Supplemental SSE3 support */ #define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */ #define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */ #define VEX_HWCAPS_AMD64_AVX (1<<8) /* AVX instructions */ diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 31b0e1b..7aa051b 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -943,7 +943,7 @@ Bool VG_(machine_get_hwcaps)( void ) } #elif defined(VGA_amd64) - { Bool have_sse3, have_cx8, have_cx16; + { Bool have_sse3, have_ssse3, have_cx8, have_cx16; Bool have_lzcnt, have_avx, have_bmi, have_avx2; Bool have_rdtscp; UInt eax, ebx, ecx, edx, max_basic, max_extended; @@ -951,6 +951,12 @@ Bool VG_(machine_get_hwcaps)( void ) HChar vstr[13]; vstr[0] = 0; + have_sse3 = have_ssse3 = have_cx8 = have_cx16 + = have_lzcnt = have_avx = have_bmi = have_avx2 + = have_rdtscp = False; + + eax = ebx = ecx = edx = max_basic = max_extended = 0; + if (!VG_(has_cpuid)()) /* we can't do cpuid at all. Give up. */ return False; @@ -975,8 +981,8 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(cpuid)(1, 0, &eax, &ebx, &ecx, &edx); // we assume that SSE1 and SSE2 are available by default - have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */ - // ssse3 is ecx:9 + have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */ + have_ssse3 = (ecx & (1<<9)) != 0; /* True => have Sup SSE3 insns */ // sse41 is ecx:19 // sse42 is ecx:20 @@ -1054,6 +1060,7 @@ Bool VG_(machine_get_hwcaps)( void ) va = VexArchAMD64; vai.endness = VexEndnessLE; vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) + | (have_ssse3 ? VEX_HWCAPS_AMD64_SSSE3 : 0) | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0) | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0) |
|
From: Roger L. <ro...@at...> - 2018-12-20 22:27:12
|
Dear all, I have packaged valgrind as a snap. In case you aren't familiar with snaps, they are containerised packages that bundle dependencies, and run on a variety of Linux distributions, but are most well supported on Ubuntu. The advantage for me is that they can provide up to date versions of software even on older distributions - so with this package, 3.14.0 is available on all supported versions of Ubuntu back to 14.04, for example. To install on a snap supported distro, you would run snap install --beta --classic valgrind At the moment the package is still very new so I have only released it to the beta channel. As far as I have used the different tools everything seems fine, but I had been hoping for some other feedback. Once it is fully released you would run snap install --classic valgrind In both cases you would then use the valgrind command line programs as normal, but they would be running from /snap/... instead. The store page for the package is https://snapcraft.io/valgrind I'm writing to tell you out of interest, but also in case you would like to take over providing this package. I think that binaries managed by upstream are best, where possible. I am very well aware that packaging is a thankless task, but in my experience of building debs, a bit of rpm, and homebrew, the update procedure for this is very straightforward. Just update the version number in the snap packaging file (https://github.com/ralight/valgrind-snap/blob/master/snap/snapcraft.yaml ), commit and push, then wait for the package to be autobuilt for all architectures and release it to the stable channel on the store. Having said all that, I'd be quite happy to keep on maintaining the package myself. Regards, Roger |
|
From: Mark W. <ma...@so...> - 2018-12-20 21:51:29
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3af8e12b0d49dc87cd26258131ebd60c9b587c74 commit 3af8e12b0d49dc87cd26258131ebd60c9b587c74 Author: Julian Seward <js...@ac...> Date: Wed Dec 12 13:55:01 2018 +0100 Fix memcheck/tests/undef_malloc_args failure. Try harder to trigger a memcheck error if a value is (partially) undefined. Diff: --- coregrind/m_replacemalloc/vg_replace_malloc.c | 16 +++++++++++++--- memcheck/tests/undef_malloc_args.c | 16 ++++++++-------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/coregrind/m_replacemalloc/vg_replace_malloc.c b/coregrind/m_replacemalloc/vg_replace_malloc.c index 28bdb4a..564829a 100644 --- a/coregrind/m_replacemalloc/vg_replace_malloc.c +++ b/coregrind/m_replacemalloc/vg_replace_malloc.c @@ -216,9 +216,19 @@ static void init(void); Apart of allowing memcheck to detect an error, the macro TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED has no effect and has a minimal cost for other tools replacing malloc functions. + + Creating an "artificial" use of _x that works reliably is not entirely + straightforward. Simply comparing it against zero often produces no + warning if _x contains at least one nonzero bit is defined, because + Memcheck knows that the result of the comparison will be defined (cf + expensiveCmpEQorNE). + + Really we want to PCast _x, so as to create a value which is entirely + undefined if any bit of _x is undefined. But there's no portable way to do + that. */ -#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(x) \ - if ((ULong)x == 0) __asm__ __volatile__( "" ::: "memory" ) +#define TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED(_x) \ + if ((UWord)(_x) == 0) __asm__ __volatile__( "" ::: "memory" ) /*---------------------- malloc ----------------------*/ @@ -504,7 +514,7 @@ static void init(void); void VG_REPLACE_FUNCTION_EZU(10040,soname,fnname) (void *zone, void *p) \ { \ DO_INIT; \ - TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord) zone); \ + TRIGGER_MEMCHECK_ERROR_IF_UNDEFINED((UWord)zone ^ (UWord)p); \ MALLOC_TRACE(#fnname "(%p, %p)\n", zone, p ); \ if (p == NULL) \ return; \ diff --git a/memcheck/tests/undef_malloc_args.c b/memcheck/tests/undef_malloc_args.c index 99e2799..654d70d 100644 --- a/memcheck/tests/undef_malloc_args.c +++ b/memcheck/tests/undef_malloc_args.c @@ -11,29 +11,29 @@ int main (int argc, char*argv[]) { size_t size = def_size; - (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size)); p = malloc(size); } - (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&p, sizeof(p)); new_p = realloc(p, def_size); - (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p)); new_p = realloc(new_p, def_size); - (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&new_p, sizeof(new_p)); free (new_p); { size_t nmemb = 1; - (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&nmemb, sizeof(nmemb)); new_p = calloc(nmemb, def_size); free (new_p); } #if 0 { size_t alignment = 1; - (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&alignment, sizeof(alignment)); new_p = memalign(alignment, def_size); free(new_p); } @@ -41,14 +41,14 @@ int main (int argc, char*argv[]) { size_t nmemb = 16; size_t size = def_size; - (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size)); new_p = memalign(nmemb, size); free(new_p); } { size_t size = def_size; - (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, 1); + (void) VALGRIND_MAKE_MEM_UNDEFINED(&size, sizeof(size)); new_p = valloc(size); free (new_p); } |
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From: Mark W. <ma...@so...> - 2018-12-20 21:51:23
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=01f1936b1238a3bbeaf2821b61ecb36ba0ae15b1 commit 01f1936b1238a3bbeaf2821b61ecb36ba0ae15b1 Author: Julian Seward <js...@ac...> Date: Mon Dec 10 17:18:20 2018 +0100 Adjust ppc set_AV_CR6 computation to help Memcheck instrumentation. * changes set_AV_CR6 so that it does scalar comparisons against zero, rather than sometimes against an all-ones word. This is something that Memcheck can instrument exactly. * in Memcheck, requests expensive instrumentation of Iop_Cmp{EQ,NE}64 by default on ppc64le. https://bugs.kde.org/show_bug.cgi?id=386945#c62 Diff: --- VEX/priv/guest_ppc_toIR.c | 103 ++++++++++++++++++++++++++++++++-------------- memcheck/mc_translate.c | 3 ++ 2 files changed, 76 insertions(+), 30 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 6b02fb4..18df822 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -2062,45 +2062,88 @@ static void set_CR0 ( IRExpr* result ) static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones ) { /* CR6[0:3] = {all_ones, 0, all_zeros, 0} - all_ones = (v[0] && v[1] && v[2] && v[3]) - all_zeros = ~(v[0] || v[1] || v[2] || v[3]) + 32 bit: all_zeros = (v[0] || v[1] || v[2] || v[3]) == 0x0000'0000 + all_ones = ~(v[0] && v[1] && v[2] && v[3]) == 0x0000'0000 + where v[] denotes 32-bit lanes + or + 64 bit: all_zeros = (v[0] || v[1]) == 0x0000'0000'0000'0000 + all_ones = ~(v[0] && v[1]) == 0x0000'0000'0000'0000 + where v[] denotes 64-bit lanes + + The 32- and 64-bit versions compute the same thing, but the 64-bit one + tries to be a bit more efficient. */ - IRTemp v0 = newTemp(Ity_V128); - IRTemp v1 = newTemp(Ity_V128); - IRTemp v2 = newTemp(Ity_V128); - IRTemp v3 = newTemp(Ity_V128); - IRTemp rOnes = newTemp(Ity_I8); - IRTemp rZeros = newTemp(Ity_I8); - vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_V128); - assign( v0, result ); - assign( v1, binop(Iop_ShrV128, result, mkU8(32)) ); - assign( v2, binop(Iop_ShrV128, result, mkU8(64)) ); - assign( v3, binop(Iop_ShrV128, result, mkU8(96)) ); + IRTemp overlappedOred = newTemp(Ity_V128); + IRTemp overlappedAnded = newTemp(Ity_V128); + + if (mode64) { + IRTemp v0 = newTemp(Ity_V128); + IRTemp v1 = newTemp(Ity_V128); + assign( v0, result ); + assign( v1, binop(Iop_ShrV128, result, mkU8(64)) ); + assign(overlappedOred, + binop(Iop_OrV128, mkexpr(v0), mkexpr(v1))); + assign(overlappedAnded, + binop(Iop_AndV128, mkexpr(v0), mkexpr(v1))); + } else { + IRTemp v0 = newTemp(Ity_V128); + IRTemp v1 = newTemp(Ity_V128); + IRTemp v2 = newTemp(Ity_V128); + IRTemp v3 = newTemp(Ity_V128); + assign( v0, result ); + assign( v1, binop(Iop_ShrV128, result, mkU8(32)) ); + assign( v2, binop(Iop_ShrV128, result, mkU8(64)) ); + assign( v3, binop(Iop_ShrV128, result, mkU8(96)) ); + assign(overlappedOred, + binop(Iop_OrV128, + binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)), + binop(Iop_OrV128, mkexpr(v2), mkexpr(v3)))); + assign(overlappedAnded, + binop(Iop_AndV128, + binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)), + binop(Iop_AndV128, mkexpr(v2), mkexpr(v3)))); + } + + IRTemp rOnes = newTemp(Ity_I8); + IRTemp rZeroes = newTemp(Ity_I8); - assign( rZeros, unop(Iop_1Uto8, - binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), - unop(Iop_Not32, - unop(Iop_V128to32, - binop(Iop_OrV128, - binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)), - binop(Iop_OrV128, mkexpr(v2), mkexpr(v3)))) - ))) ); + if (mode64) { + assign(rZeroes, + unop(Iop_1Uto8, + binop(Iop_CmpEQ64, + mkU64(0), + unop(Iop_V128to64, mkexpr(overlappedOred))))); + assign(rOnes, + unop(Iop_1Uto8, + binop(Iop_CmpEQ64, + mkU64(0), + unop(Iop_Not64, + unop(Iop_V128to64, mkexpr(overlappedAnded)))))); + } else { + assign(rZeroes, + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, + mkU32(0), + unop(Iop_V128to32, mkexpr(overlappedOred))))); + assign(rOnes, + unop(Iop_1Uto8, + binop(Iop_CmpEQ32, + mkU32(0), + unop(Iop_Not32, + unop(Iop_V128to32, mkexpr(overlappedAnded)))))); + } + + // rOnes might not be used below. But iropt will remove it, so there's no + // inefficiency as a result. if (test_all_ones) { - assign( rOnes, unop(Iop_1Uto8, - binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), - unop(Iop_V128to32, - binop(Iop_AndV128, - binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)), - binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))) - ))) ); putCR321( 6, binop(Iop_Or8, binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)), - binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) ); + binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1))) ); } else { - putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) ); + putCR321( 6, binop(Iop_Shl8, mkexpr(rZeroes), mkU8(1)) ); } putCR0( 6, mkU8(0) ); } diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 1e770b3..04ed864 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -8323,6 +8323,9 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, # elif defined(VGA_amd64) mce.dlbo.dl_Add64 = DLauto; mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; +# elif defined(VGA_ppc64le) + // Needed by (at least) set_AV_CR6() in the front end. + mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive; # endif /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then |
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From: Mark W. <ma...@so...> - 2018-12-20 21:51:18
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3ef4b2c780ea76a80ae5beaa63c1cb1d6530988b commit 3ef4b2c780ea76a80ae5beaa63c1cb1d6530988b Author: Mark Wielaard <ma...@kl...> Date: Sun Dec 9 23:25:05 2018 +0100 Implement ppc64 lxvb16x as 128-bit vector load with reversed double words. This makes it possible for memcheck to know which part of the 128bit vector is defined, even if the load is partly beyond an addressable block. Partially resolves bug 386945. Diff: --- VEX/priv/guest_ppc_toIR.c | 61 ++++++++++++++--------------------------------- 1 file changed, 18 insertions(+), 43 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 72c9c13..6b02fb4 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -20702,54 +20702,29 @@ dis_vx_load ( UInt theInstr ) { DIP("lxvb16x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); - IRTemp byte[16]; - int i; - UInt ea_off = 0; - IRExpr* irx_addr; - IRTemp tmp_low[9]; - IRTemp tmp_hi[9]; + /* The result of lxvb16x should be the same on big and little + endian systems. We do a host load, then reverse the bytes in + the double words. If the host load was little endian we swap + them around again. */ - tmp_low[0] = newTemp( Ity_I64 ); - tmp_hi[0] = newTemp( Ity_I64 ); - assign( tmp_low[0], mkU64( 0 ) ); - assign( tmp_hi[0], mkU64( 0 ) ); - - for ( i = 0; i < 8; i++ ) { - byte[i] = newTemp( Ity_I64 ); - tmp_low[i+1] = newTemp( Ity_I64 ); - - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); - ea_off += 1; - - assign( byte[i], binop( Iop_Shl64, - unop( Iop_8Uto64, - load( Ity_I8, irx_addr ) ), - mkU8( 8 * ( 7 - i ) ) ) ); + IRTemp high = newTemp(Ity_I64); + IRTemp high_rev = newTemp(Ity_I64); + IRTemp low = newTemp(Ity_I64); + IRTemp low_rev = newTemp(Ity_I64); - assign( tmp_low[i+1], - binop( Iop_Or64, - mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) ); - } + IRExpr *t128 = load( Ity_V128, mkexpr( EA ) ); - for ( i = 0; i < 8; i++ ) { - byte[i + 8] = newTemp( Ity_I64 ); - tmp_hi[i+1] = newTemp( Ity_I64 ); + assign( high, unop(Iop_V128HIto64, t128) ); + assign( high_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(high)) ); + assign( low, unop(Iop_V128to64, t128) ); + assign( low_rev, unop(Iop_Reverse8sIn64_x1, mkexpr(low)) ); - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); - ea_off += 1; + if (host_endness == VexEndnessLE) + t128 = binop( Iop_64HLtoV128, mkexpr (low_rev), mkexpr (high_rev) ); + else + t128 = binop( Iop_64HLtoV128, mkexpr (high_rev), mkexpr (low_rev) ); - assign( byte[i+8], binop( Iop_Shl64, - unop( Iop_8Uto64, - load( Ity_I8, irx_addr ) ), - mkU8( 8 * ( 7 - i ) ) ) ); - assign( tmp_hi[i+1], binop( Iop_Or64, - mkexpr( byte[i+8] ), - mkexpr( tmp_hi[i] ) ) ); - } - putVSReg( XT, binop( Iop_64HLtoV128, - mkexpr( tmp_low[8] ), mkexpr( tmp_hi[8] ) ) ); + putVSReg( XT, t128 ); break; } |
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From: Mark W. <ma...@so...> - 2018-12-20 21:51:13
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8d12697b157bb50ad98467b565b3a7a39097bf31 commit 8d12697b157bb50ad98467b565b3a7a39097bf31 Author: Mark Wielaard <ma...@kl...> Date: Sun Dec 9 14:26:39 2018 +0100 memcheck: Allow unaligned loads of 128bit vectors on ppc64[le]. On powerpc partial unaligned loads of vectors from partially invalid addresses are OK and could be generated by our translation of lxvd2x. Adjust partial_load memcheck tests to allow partial loads of 16 byte vectors on powerpc64. Part of resolving bug #386945. Diff: --- memcheck/mc_main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 737f79d..101916b 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -1354,6 +1354,9 @@ void mc_LOADV_128_or_256_slow ( /*OUT*/ULong* res, tl_assert(szB == 16); // s390 doesn't have > 128 bit SIMD /* OK if all loaded bytes are from the same page. */ Bool alignedOK = ((a & 0xfff) <= 0x1000 - szB); +# elif defined(VGA_ppc64be) || defined(VGA_ppc64le) + /* lxvd2x might generate an unaligned 128 bit vector load. */ + Bool alignedOK = (szB == 16); # else /* OK if the address is aligned by the load size. */ Bool alignedOK = (0 == (a & (szB - 1))); |
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From: Mark W. <ma...@so...> - 2018-12-20 21:51:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=98a73de1c0c83918a63e736b62d428bc2f98c943 commit 98a73de1c0c83918a63e736b62d428bc2f98c943 Author: Mark Wielaard <ma...@kl...> Date: Sun Dec 9 00:55:42 2018 +0100 Implement ppc64 lxvd2x as 128-bit load with double word swap for ppc64le. This makes it possible for memcheck to know which part of the 128bit vector is defined, even if the load is partly beyond an addressable block. Partially resolves bug 386945. Diff: --- VEX/priv/guest_ppc_toIR.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 10f6daa..72c9c13 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -20590,16 +20590,22 @@ dis_vx_load ( UInt theInstr ) } case 0x34C: // lxvd2x { - IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32; - IRExpr * high, *low; - ULong ea_off = 8; - IRExpr* high_addr; + IRExpr *t128; DIP("lxvd2x %d,r%u,r%u\n", XT, rA_addr, rB_addr); - high = load( Ity_I64, mkexpr( EA ) ); - high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off ) - : mkU32( ea_off ) ); - low = load( Ity_I64, high_addr ); - putVSReg( XT, binop( Iop_64HLtoV128, high, low ) ); + t128 = load( Ity_V128, mkexpr( EA ) ); + + /* The data in the vec register should be in big endian order. + So if we just did a little endian load then swap around the + high and low double words. */ + if (host_endness == VexEndnessLE) { + IRTemp high = newTemp(Ity_I64); + IRTemp low = newTemp(Ity_I64); + assign( high, unop(Iop_V128HIto64, t128) ); + assign( low, unop(Iop_V128to64, t128) ); + t128 = binop( Iop_64HLtoV128, mkexpr (low), mkexpr (high) ); + } + + putVSReg( XT, t128 ); break; } case 0x14C: // lxvdsx |
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From: Mark W. <ma...@so...> - 2018-12-20 21:51:03
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5ecdecdcd3efecadf149dcd6276140e833b7f8e6 commit 5ecdecdcd3efecadf149dcd6276140e833b7f8e6 Author: Mark Wielaard <ma...@kl...> Date: Sat Dec 8 13:47:43 2018 -0500 memcheck: Allow unaligned loads of words on ppc64[le]. On powerpc partial unaligned loads of words from partially invalid addresses are OK and could be generated by our translation of ldbrx. Adjust partial_load memcheck tests to allow partial loads of words on powerpc64. Part of resolving bug #386945. Diff: --- memcheck/mc_main.c | 3 +++ memcheck/tests/Makefile.am | 2 ++ memcheck/tests/partial_load.c | 12 ++++++------ memcheck/tests/partial_load_dflt.stderr.exp-ppc64 | 23 +++++++++++++++++++++++ memcheck/tests/partial_load_ok.stderr.exp-ppc64 | 23 +++++++++++++++++++++++ 5 files changed, 57 insertions(+), 6 deletions(-) diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 3ef7cb9..737f79d 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -1508,6 +1508,9 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) # if defined(VGA_mips64) && defined(VGABI_N32) if (szB == VG_WORDSIZE * 2 && VG_IS_WORD_ALIGNED(a) && n_addrs_bad < VG_WORDSIZE * 2) +# elif defined(VGA_ppc64be) || defined(VGA_ppc64le) + /* On power unaligned loads of words are OK. */ + if (szB == VG_WORDSIZE && n_addrs_bad < VG_WORDSIZE) # else if (szB == VG_WORDSIZE && VG_IS_WORD_ALIGNED(a) && n_addrs_bad < VG_WORDSIZE) diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index 2af4dd1..70b8ada 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -235,8 +235,10 @@ EXTRA_DIST = \ partiallydefinedeq.stdout.exp \ partial_load_ok.vgtest partial_load_ok.stderr.exp \ partial_load_ok.stderr.exp64 \ + partial_load_ok.stderr.exp-ppc64 \ partial_load_dflt.vgtest partial_load_dflt.stderr.exp \ partial_load_dflt.stderr.exp64 \ + partial_load_dflt.stderr.exp-ppc64 \ partial_load_dflt.stderr.expr-s390x-mvc \ pdb-realloc.stderr.exp pdb-realloc.vgtest \ pdb-realloc2.stderr.exp pdb-realloc2.stdout.exp pdb-realloc2.vgtest \ diff --git a/memcheck/tests/partial_load.c b/memcheck/tests/partial_load.c index 0b2f10b..685ca8d 100644 --- a/memcheck/tests/partial_load.c +++ b/memcheck/tests/partial_load.c @@ -1,14 +1,14 @@ - +#include <stdio.h> #include <stdlib.h> #include <assert.h> int main ( void ) { - long w; - int i; - char* p; - + long w; int i; char* p; assert(sizeof(long) == sizeof(void*)); +#if defined(__powerpc64__) + fprintf (stderr, "powerpc64\n"); /* Used to select correct .exp file. */ +#endif /* partial load, which --partial-loads-ok=yes should suppress */ p = calloc( sizeof(long)-1, 1 ); @@ -16,7 +16,7 @@ int main ( void ) w = *(long*)p; free(p); - /* partial but misaligned, cannot be suppressed */ + /* partial but misaligned, ppc64[le] ok, but otherwise cannot be suppressed */ p = calloc( sizeof(long), 1 ); assert(p); p++; diff --git a/memcheck/tests/partial_load_dflt.stderr.exp-ppc64 b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64 new file mode 100644 index 0000000..cf32bcf --- /dev/null +++ b/memcheck/tests/partial_load_dflt.stderr.exp-ppc64 @@ -0,0 +1,23 @@ + +powerpc64 +Invalid read of size 2 + at 0x........: main (partial_load.c:30) + Address 0x........ is 0 bytes inside a block of size 1 alloc'd + at 0x........: calloc (vg_replace_malloc.c:...) + by 0x........: main (partial_load.c:28) + +Invalid read of size 8 + at 0x........: main (partial_load.c:37) + Address 0x........ is 0 bytes inside a block of size 8 free'd + at 0x........: free (vg_replace_malloc.c:...) + by 0x........: main (partial_load.c:36) + + +HEAP SUMMARY: + in use at exit: ... bytes in ... blocks + total heap usage: ... allocs, ... frees, ... bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/partial_load_ok.stderr.exp-ppc64 b/memcheck/tests/partial_load_ok.stderr.exp-ppc64 new file mode 100644 index 0000000..cf32bcf --- /dev/null +++ b/memcheck/tests/partial_load_ok.stderr.exp-ppc64 @@ -0,0 +1,23 @@ + +powerpc64 +Invalid read of size 2 + at 0x........: main (partial_load.c:30) + Address 0x........ is 0 bytes inside a block of size 1 alloc'd + at 0x........: calloc (vg_replace_malloc.c:...) + by 0x........: main (partial_load.c:28) + +Invalid read of size 8 + at 0x........: main (partial_load.c:37) + Address 0x........ is 0 bytes inside a block of size 8 free'd + at 0x........: free (vg_replace_malloc.c:...) + by 0x........: main (partial_load.c:36) + + +HEAP SUMMARY: + in use at exit: ... bytes in ... blocks + total heap usage: ... allocs, ... frees, ... bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) |
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From: Mark W. <ma...@so...> - 2018-12-20 21:50:58
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0ed17bc9f675c59cf1e93caa4290e0b21b84c0a0 commit 0ed17bc9f675c59cf1e93caa4290e0b21b84c0a0 Author: Mark Wielaard <ma...@kl...> Date: Fri Dec 7 10:42:22 2018 -0500 Implement ppc64 ldbrx as 64-bit load and Iop_Reverse8sIn64_x1. This makes it possible for memcheck to analyse the new gcc strcmp inlined code correctly even if the ldbrx load is partly beyond an addressable block. Partially resolves bug 386945. Diff: --- VEX/priv/guest_ppc_toIR.c | 38 +++++++++++++++++-------------- VEX/priv/host_ppc_isel.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 17 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 8977d4f..10f6daa 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -9178,24 +9178,28 @@ static Bool dis_int_ldst_rev ( UInt theInstr ) case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed) { - // JRS FIXME: - // * is the host_endness conditional below actually necessary? - // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1? - // That would be a lot more efficient. - IRExpr * nextAddr; - IRTemp w3 = newTemp( Ity_I32 ); - IRTemp w4 = newTemp( Ity_I32 ); + /* Caller makes sure we are only called in mode64. */ + + /* If we supported swapping LE/BE loads in the backend then we could + just load the value with the bytes reversed by doing a BE load + on an LE machine and a LE load on a BE machine. + + IRTemp dw1 = newTemp(Ity_I64); + if (host_endness == VexEndnessBE) + assign( dw1, IRExpr_Load(Iend_LE, Ity_I64, mkexpr(EA))); + else + assign( dw1, IRExpr_Load(Iend_BE, Ity_I64, mkexpr(EA))); + putIReg( rD_addr, mkexpr(dw1) ); + + But since we currently don't we load the value as is and then + switch it around with Iop_Reverse8sIn64_x1. */ + + IRTemp dw1 = newTemp(Ity_I64); + IRTemp dw2 = newTemp(Ity_I64); DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); - assign( w1, load( Ity_I32, mkexpr( EA ) ) ); - assign( w2, gen_byterev32( w1 ) ); - nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) ); - assign( w3, load( Ity_I32, nextAddr ) ); - assign( w4, gen_byterev32( w3 ) ); - if (host_endness == VexEndnessLE) - putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) ); - else - putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) ); + assign( dw1, load(Ity_I64, mkexpr(EA)) ); + assign( dw2, unop(Iop_Reverse8sIn64_x1, mkexpr(dw1)) ); + putIReg( rD_addr, mkexpr(dw2) ); break; } diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 750cf8d..4fc3eb5 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -2210,6 +2210,63 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e, return rr; } + case Iop_Reverse8sIn64_x1: { + /* See Iop_Reverse8sIn32_x1, but extended to 64bit. + Can only be used in 64bit mode. */ + vassert (mode64); + + HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); + HReg rr = newVRegI(env); + HReg rMask = newVRegI(env); + HReg rnMask = newVRegI(env); + HReg rtHi = newVRegI(env); + HReg rtLo = newVRegI(env); + + // Copy r_src since we need to modify it + addInstr(env, mk_iMOVds_RR(rr, r_src)); + + // r = (r & 0x00FF00FF00FF00FF) << 8 | (r & 0xFF00FF00FF00FF00) >> 8 + addInstr(env, PPCInstr_LI(rMask, 0x00FF00FF00FF00FFULL, + True/* 64bit imm*/)); + addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask)); + addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask))); + addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/, + rtHi, rtHi, + PPCRH_Imm(False/*!signed imm*/, 8))); + addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask))); + addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/, + rtLo, rtLo, + PPCRH_Imm(False/*!signed imm*/, 8))); + addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo))); + + // r = (r & 0x0000FFFF0000FFFF) << 16 | (r & 0xFFFF0000FFFF0000) >> 16 + addInstr(env, PPCInstr_LI(rMask, 0x0000FFFF0000FFFFULL, + True/* !64bit imm*/)); + addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask)); + addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask))); + addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/, + rtHi, rtHi, + PPCRH_Imm(False/*!signed imm*/, 16))); + addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask))); + addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/, + rtLo, rtLo, + PPCRH_Imm(False/*!signed imm*/, 16))); + addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo))); + + // r = (r & 0x00000000FFFFFFFF) << 32 | (r & 0xFFFFFFFF00000000) >> 32 + /* We don't need to mask anymore, just two more shifts and an or. */ + addInstr(env, mk_iMOVds_RR(rtLo, rr)); + addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/, + rtLo, rtLo, + PPCRH_Imm(False/*!signed imm*/, 32))); + addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/, + rr, rr, + PPCRH_Imm(False/*!signed imm*/, 32))); + addInstr(env, PPCInstr_Alu(Palu_OR, rr, rr, PPCRH_Reg(rtLo))); + + return rr; + } + case Iop_Left8: case Iop_Left16: case Iop_Left32: |
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From: Nicholas N. <n.n...@gm...> - 2018-12-20 09:20:03
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Hi, I have rewritten DHAT. The details, and a patch, are in https://bugs.kde.org/show_bug.cgi?id=402369. I'd be interested to hear feedback from anyone who wants to try it out. Nick |
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From: Bart V. A. <bva...@so...> - 2018-12-20 02:37:42
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5b4029b8cc8fc74a6e24e8bfaee1914e46081496 commit 5b4029b8cc8fc74a6e24e8bfaee1914e46081496 Author: Bart Van Assche <bva...@ac...> Date: Wed Dec 19 18:13:14 2018 -0800 drd/tests/tsan_thread_wrappers_pthread.h: Fix MyThread::ThreadBody() See also https://bugs.kde.org/show_bug.cgi?id=402341. Diff: --- drd/tests/tsan_thread_wrappers_pthread.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drd/tests/tsan_thread_wrappers_pthread.h b/drd/tests/tsan_thread_wrappers_pthread.h index bdca574..878d440 100644 --- a/drd/tests/tsan_thread_wrappers_pthread.h +++ b/drd/tests/tsan_thread_wrappers_pthread.h @@ -368,7 +368,7 @@ class MyThread { } if (my_thread->wpvpv_) return my_thread->wpvpv_(my_thread->arg_); - if (my_thread->wpvpv_) + if (my_thread->wvpv_) my_thread->wvpv_(my_thread->arg_); if (my_thread->wvv_) my_thread->wvv_(); |
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From: Mark W. <ma...@so...> - 2018-12-19 20:05:59
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a751b5be0114378c1b23c787798c8c3d61042cfb commit a751b5be0114378c1b23c787798c8c3d61042cfb Author: Mark Wielaard <ma...@kl...> Date: Wed Dec 19 20:52:29 2018 +0100 PR402134 assert fail in mc_translate.c (noteTmpUsesIn) Iex_VECRET on arm64 This happens when processing openssl aes_v8_set_encrypt_key (aesv8-armx.S:133). The noteTmpUsesIn () function is new since PR387664 Memcheck: make expensive-definedness-checks be the default. It didn't handle Iex_VECRET which is used in the arm64 crypto instruction dirty handlers. Diff: --- NEWS | 1 + memcheck/mc_translate.c | 1 + 2 files changed, 2 insertions(+) diff --git a/NEWS b/NEWS index c257f76..e1645ef 100644 --- a/NEWS +++ b/NEWS @@ -72,6 +72,7 @@ where XXXXXX is the bug number as listed below. 401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings 402006 mark helper regs defined in final_tidyup before freeres_wrapper call 402048 WARNING: unhandled ppc64[be|le]-linux syscall: 26 (ptrace) +402134 assertion fail in mc_translate.c (noteTmpUsesIn) Iex_VECRET on arm64 402327 Warning: DWARF2 CFI reader: unhandled DW_OP_ opcode 0x13 (DW_OP_drop) Release 3.14.0 (9 October 2018) diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index c24db91..1e770b3 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -8022,6 +8022,7 @@ static inline void noteTmpUsesIn ( /*MOD*/HowUsed* useEnv, use info. */ switch (at->tag) { case Iex_GSPTR: + case Iex_VECRET: case Iex_Const: return; case Iex_RdTmp: { |
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From: Mark W. <ma...@so...> - 2018-12-19 19:16:47
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e4dde1327e1ca1868aabf2b89bc818d37864e3cc commit e4dde1327e1ca1868aabf2b89bc818d37864e3cc Author: Mark Wielaard <ma...@kl...> Date: Wed Dec 19 20:14:03 2018 +0100 PR402327 Warning: DWARF2 CFI reader: unhandled DW_OP_ opcode 0x13 DW_OP_drop readdwarf.c (dwarfexpr_to_dag) didn't handle DW_OP_drop. Implement it by simply popping the last element on the stack. Diff: --- NEWS | 1 + coregrind/m_debuginfo/readdwarf.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/NEWS b/NEWS index dc41a2b..c257f76 100644 --- a/NEWS +++ b/NEWS @@ -72,6 +72,7 @@ where XXXXXX is the bug number as listed below. 401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings 402006 mark helper regs defined in final_tidyup before freeres_wrapper call 402048 WARNING: unhandled ppc64[be|le]-linux syscall: 26 (ptrace) +402327 Warning: DWARF2 CFI reader: unhandled DW_OP_ opcode 0x13 (DW_OP_drop) Release 3.14.0 (9 October 2018) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c index 70ab16d..3b7449a 100644 --- a/coregrind/m_debuginfo/readdwarf.c +++ b/coregrind/m_debuginfo/readdwarf.c @@ -2853,6 +2853,12 @@ static Int dwarfexpr_to_dag ( const UnwindContext* ctx, VG_(printf)("DW_OP_deref"); break; + case DW_OP_drop: + POP( ix ); + if (ddump_frames) + VG_(printf)("DW_OP_drop"); + break; + default: if (!VG_(clo_xml)) VG_(message)(Vg_DebugMsg, |
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From: Mark W. <ma...@so...> - 2018-12-14 13:42:38
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2e2ae5bda81c4a7967cdaff9fc5032cfd4c3b834 commit 2e2ae5bda81c4a7967cdaff9fc5032cfd4c3b834 Author: Mark Wielaard <ma...@kl...> Date: Wed Dec 12 14:11:29 2018 +0100 Implement minimal ptrace support for ppc64[le]-linux. Diff: --- NEWS | 1 + coregrind/m_syswrap/syswrap-ppc64-linux.c | 70 ++++++++++++++++++++++++++++++- memcheck/tests/linux/getregset.vgtest | 2 +- 3 files changed, 70 insertions(+), 3 deletions(-) diff --git a/NEWS b/NEWS index d2a4207..dc41a2b 100644 --- a/NEWS +++ b/NEWS @@ -71,6 +71,7 @@ where XXXXXX is the bug number as listed below. 401627 memcheck errors with glibc avx2 optimized wcsncmp 401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings 402006 mark helper regs defined in final_tidyup before freeres_wrapper call +402048 WARNING: unhandled ppc64[be|le]-linux syscall: 26 (ptrace) Release 3.14.0 (9 October 2018) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c index 6549dd1..0fdcc8e 100644 --- a/coregrind/m_syswrap/syswrap-ppc64-linux.c +++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c @@ -388,6 +388,7 @@ DECL_TEMPLATE(ppc64_linux, sys_mmap); //zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn); DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn); DECL_TEMPLATE(ppc64_linux, sys_fadvise64); +DECL_TEMPLATE(ppc64_linux, sys_ptrace); PRE(sys_mmap) { @@ -511,6 +512,72 @@ PRE(sys_rt_sigreturn) *flags |= SfPollAfter; } +// ARG3 is only used for pointers into the traced process's address +// space and for offsets into the traced process's struct +// user_regs_struct. It is never a pointer into this process's memory +// space, and we should therefore not check anything it points to. +// powerpc does have other ways to get/set registers, we only support +// GET/SETREGSET for now. +PRE(sys_ptrace) +{ + PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4); + PRE_REG_READ4(int, "ptrace", + long, request, long, pid, long, addr, long, data); + switch (ARG1) { + case VKI_PTRACE_PEEKTEXT: + case VKI_PTRACE_PEEKDATA: + case VKI_PTRACE_PEEKUSR: + PRE_MEM_WRITE( "ptrace(peek)", ARG4, + sizeof (long)); + break; + case VKI_PTRACE_GETEVENTMSG: + PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long)); + break; + case VKI_PTRACE_GETSIGINFO: + PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_SETSIGINFO: + PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_GETREGSET: + ML_(linux_PRE_getregset)(tid, ARG3, ARG4); + break; + case VKI_PTRACE_SETREGSET: + ML_(linux_PRE_setregset)(tid, ARG3, ARG4); + break; + default: + break; + } +} + +POST(sys_ptrace) +{ + switch (ARG1) { + case VKI_PTRACE_TRACEME: + ML_(linux_POST_traceme)(tid); + break; + case VKI_PTRACE_PEEKTEXT: + case VKI_PTRACE_PEEKDATA: + case VKI_PTRACE_PEEKUSR: + POST_MEM_WRITE( ARG4, sizeof (long)); + break; + case VKI_PTRACE_GETEVENTMSG: + POST_MEM_WRITE( ARG4, sizeof(unsigned long)); + break; + case VKI_PTRACE_GETSIGINFO: + /* XXX: This is a simplification. Different parts of the + * siginfo_t are valid depending on the type of signal. + */ + POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t)); + break; + case VKI_PTRACE_GETREGSET: + ML_(linux_POST_getregset)(tid, ARG3, ARG4); + break; + default: + break; + } +} + #undef PRE #undef POST @@ -562,8 +629,7 @@ static SyscallTableEntry syscall_table[] = { GENX_(__NR_getuid, sys_getuid), // 24 // _____(__NR_stime, sys_stime), // 25 -// When ptrace is supported, memcheck/tests/linux/getregset should be enabled -// _____(__NR_ptrace, sys_ptrace), // 26 + PLAXY(__NR_ptrace, sys_ptrace), // 26 GENX_(__NR_alarm, sys_alarm), // 27 // _____(__NR_oldfstat, sys_oldfstat), // 28 GENX_(__NR_pause, sys_pause), // 29 diff --git a/memcheck/tests/linux/getregset.vgtest b/memcheck/tests/linux/getregset.vgtest index 4c66108..c35be4c 100644 --- a/memcheck/tests/linux/getregset.vgtest +++ b/memcheck/tests/linux/getregset.vgtest @@ -1,4 +1,4 @@ prog: getregset vgopts: -q -prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 ) && ! ../../../tests/arch_test ppc64 +prereq: ((../../../tests/os_test linux 2.6.33 && ! ../../../tests/arch_test mips32) || ../../../tests/os_test linux 3.10.0 ) |
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From: Mark W. <ma...@so...> - 2018-12-14 13:42:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=43fe4bc236d667257eeebfb4f6bcbe2b92aea455 commit 43fe4bc236d667257eeebfb4f6bcbe2b92aea455 Author: Mark Wielaard <ma...@kl...> Date: Fri Dec 14 14:32:27 2018 +0100 arm64: Fix PTRACE_TRACEME memcheck/tests/linux/getregset.vgtest testcase. The sys_ptrace post didn't mark the thread as being in traceme mode. This occassionally would make the memcheck/tests/linux/getregset.vgtest testcase fail. With this patch it reliably passes. Diff: --- coregrind/m_syswrap/syswrap-arm64-linux.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c index 9ef54b4..650f5b9 100644 --- a/coregrind/m_syswrap/syswrap-arm64-linux.c +++ b/coregrind/m_syswrap/syswrap-arm64-linux.c @@ -499,6 +499,9 @@ PRE(sys_ptrace) POST(sys_ptrace) { switch (ARG1) { + case VKI_PTRACE_TRACEME: + ML_(linux_POST_traceme)(tid); + break; case VKI_PTRACE_PEEKTEXT: case VKI_PTRACE_PEEKDATA: case VKI_PTRACE_PEEKUSR: |
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From: Mark W. <ma...@kl...> - 2018-12-13 17:59:15
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On Thu, 2018-12-13 at 15:19 +0000, Petar Jovanovic wrote: > mips64: fix build break introduced by be7a730 > > Follow up to > commit be7a73004583aab5d4c97cf55276ca58d5b3090b > > that broke the build for mips64. Oops. Sorry about that. I clearly didn't have a mips setup, or it would have been obvious that I broke something. Thanks for the fix. My apologies, Mark |
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From: Petar J. <pe...@so...> - 2018-12-13 15:20:03
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c4ab123605d904024c21a2bcb37684d84c935194 commit c4ab123605d904024c21a2bcb37684d84c935194 Author: Petar Jovanovic <mip...@gm...> Date: Thu Dec 13 16:20:28 2018 +0100 mips64: fix build break introduced by be7a730 Follow up to commit be7a73004583aab5d4c97cf55276ca58d5b3090b that broke the build for mips64. Diff: --- coregrind/m_main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/coregrind/m_main.c b/coregrind/m_main.c index 22872a2..93998cf 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -2328,11 +2328,16 @@ static void final_tidyup(ThreadId tid) sizeof(VG_(threads)[tid].arch.vex.guest_GPR12)); # endif /* mips-linux note: we need to set t9 */ -# if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) +# if defined(VGP_mips32_linux) VG_(threads)[tid].arch.vex.guest_r25 = freeres_wrapper; VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, offsetof(VexGuestMIPS32State, guest_r25), sizeof(VG_(threads)[tid].arch.vex.guest_r25)); +# elif defined(VGP_mips64_linux) + VG_(threads)[tid].arch.vex.guest_r25 = freeres_wrapper; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestMIPS64State, guest_r25), + sizeof(VG_(threads)[tid].arch.vex.guest_r25)); # endif /* Pass a parameter to freeres_wrapper(). */ |
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From: Petar J. <pe...@so...> - 2018-12-12 18:15:57
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=71be91d2ddf065b86a5cd9d4f3bfc3eca3c87a4b commit 71be91d2ddf065b86a5cd9d4f3bfc3eca3c87a4b Author: Petar Jovanovic <mip...@gm...> Date: Wed Dec 12 17:45:34 2018 +0000 make outputs of drd/tests/fork* deterministic Wait for children to finish before terminating the main process. This fixes occasional failures of the following tests: drd/tests/fork-parallel (stderr) drd/tests/fork-serial (stderr) Diff: --- drd/tests/fork.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drd/tests/fork.c b/drd/tests/fork.c index 07aaf73..0f934ca 100644 --- a/drd/tests/fork.c +++ b/drd/tests/fork.c @@ -3,8 +3,12 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <sys/wait.h> -static pthread_t tid[2]; +#define NUM_THREADS 2 + +static pthread_t tid[NUM_THREADS]; +static pid_t pids[NUM_THREADS]; static void *startproc(void *arg) { @@ -16,6 +20,8 @@ static void *startproc(void *arg) } else if (pid == 0) { dup2(2, 1); // redirect stdout to stderr execv(argv[0], argv); // child + } else { + *((pid_t*)arg) = pid; } return NULL; @@ -29,17 +35,20 @@ int main(int argc, char **argv) int i = 0; int err; - for (i = 0; i < 2; i++) { - err = pthread_create(&tid[i], NULL, &startproc, NULL); + for (i = 0; i < NUM_THREADS; i++) { + err = pthread_create(&tid[i], NULL, &startproc, &pids[i]); if (err != 0) perror("pthread_create()"); if (serialize_fork) pthread_join(tid[i], NULL); } if (!serialize_fork) { - for (i = 0; i < 2; i++) + for (i = 0; i < NUM_THREADS; i++) if (tid[i]) pthread_join(tid[i], NULL); } + for (i = 0; i < NUM_THREADS; i++) + waitpid(pids[i], &err, 0); + return 0; } |
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From: Mark W. <ma...@so...> - 2018-12-12 13:20:37
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=be7a73004583aab5d4c97cf55276ca58d5b3090b commit be7a73004583aab5d4c97cf55276ca58d5b3090b Author: Mark Wielaard <ma...@kl...> Date: Wed Dec 12 14:15:28 2018 +0100 Mark helper regs defined in final_tidyup before freeres_wrapper call. In final_tidyup we setup the guest to call the freeres_wrapper, which will (possibly) call __gnu_cxx::__freeres() and/or __libc_freeres(). In a couple of cases (ppc64be, ppc64le and mips32) this involves setting up one or more helper registers. Since we setup these guest registers we should make sure to mark them as fully defined. Otherwise we might see spurious warnings about undefined value usage if the guest register happened to not be fully defined before. This fixes PR402006. Diff: --- NEWS | 1 + coregrind/m_main.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 562291f..d2a4207 100644 --- a/NEWS +++ b/NEWS @@ -70,6 +70,7 @@ where XXXXXX is the bug number as listed below. 401578 drd: crashes sometimes on fork() 401627 memcheck errors with glibc avx2 optimized wcsncmp 401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings +402006 mark helper regs defined in final_tidyup before freeres_wrapper call Release 3.14.0 (9 October 2018) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/coregrind/m_main.c b/coregrind/m_main.c index 00702fc..22872a2 100644 --- a/coregrind/m_main.c +++ b/coregrind/m_main.c @@ -2304,22 +2304,35 @@ static void final_tidyup(ThreadId tid) "Caught __NR_exit; running %s wrapper\n", msgs[to_run - 1]); } - /* set thread context to point to freeres_wrapper */ - /* ppc64be-linux note: freeres_wrapper gives us the real + /* Set thread context to point to freeres_wrapper. + ppc64be-linux note: freeres_wrapper gives us the real function entry point, not a fn descriptor, so can use it directly. However, we need to set R2 (the toc pointer) appropriately. */ VG_(set_IP)(tid, freeres_wrapper); + # if defined(VGP_ppc64be_linux) VG_(threads)[tid].arch.vex.guest_GPR2 = r2; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestPPC64State, guest_GPR2), + sizeof(VG_(threads)[tid].arch.vex.guest_GPR2)); # elif defined(VGP_ppc64le_linux) /* setting GPR2 but not really needed, GPR12 is needed */ VG_(threads)[tid].arch.vex.guest_GPR2 = freeres_wrapper; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestPPC64State, guest_GPR2), + sizeof(VG_(threads)[tid].arch.vex.guest_GPR2)); VG_(threads)[tid].arch.vex.guest_GPR12 = freeres_wrapper; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestPPC64State, guest_GPR12), + sizeof(VG_(threads)[tid].arch.vex.guest_GPR12)); # endif /* mips-linux note: we need to set t9 */ # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) VG_(threads)[tid].arch.vex.guest_r25 = freeres_wrapper; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestMIPS32State, guest_r25), + sizeof(VG_(threads)[tid].arch.vex.guest_r25)); # endif /* Pass a parameter to freeres_wrapper(). */ |
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From: Nicholas N. <nj...@so...> - 2018-12-12 09:56:43
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=46fb3eb81ceadf808a3bf1d6dd4ae079a4f44256 commit 46fb3eb81ceadf808a3bf1d6dd4ae079a4f44256 Author: Nicholas Nethercote <nne...@mo...> Date: Wed Dec 12 20:52:33 2018 +1100 Fix path handling in the new Cachegrind and Callgrind tests. Diff: --- cachegrind/tests/a.c | 7 +++++++ cachegrind/tests/ann1.post.exp | 4 ++-- cachegrind/tests/ann2.post.exp | 4 ++-- cachegrind/tests/cgout-test | 2 +- callgrind/tests/ann1.post.exp | 6 +++--- callgrind/tests/ann1.vgtest | 2 +- callgrind/tests/ann2.post.exp | 6 +++--- callgrind/tests/ann2.vgtest | 2 +- 8 files changed, 20 insertions(+), 13 deletions(-) diff --git a/cachegrind/tests/a.c b/cachegrind/tests/a.c new file mode 100644 index 0000000..cd1c66e --- /dev/null +++ b/cachegrind/tests/a.c @@ -0,0 +1,7 @@ +int main(void) { + int z = 0; + for (int i = 0; i < 1000000; i++) { + z += i; + } + return z % 256; +} diff --git a/cachegrind/tests/ann1.post.exp b/cachegrind/tests/ann1.post.exp index d82b6ab..1019637 100644 --- a/cachegrind/tests/ann1.post.exp +++ b/cachegrind/tests/ann1.post.exp @@ -20,7 +20,7 @@ Ir I1mr ILmr -------------------------------------------------------------------------------- Ir I1mr ILmr file:function -------------------------------------------------------------------------------- -5,000,015 1 1 /home/njn/grind/ws2/a.c:main +5,000,015 1 1 a.c:main 47,993 19 19 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x 28,534 11 11 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:_dl_lookup_symbol_x 28,136 7 7 /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c:__GI___tunables_init @@ -31,7 +31,7 @@ Ir I1mr ILmr file:function 6,898 2 2 /build/glibc-OTsEL5/glibc-2.27/elf/dl-misc.c:_dl_name_match_p -------------------------------------------------------------------------------- --- Auto-annotated source: /home/njn/grind/ws2/a.c +-- Auto-annotated source: a.c -------------------------------------------------------------------------------- Ir I1mr ILmr diff --git a/cachegrind/tests/ann2.post.exp b/cachegrind/tests/ann2.post.exp index 83d9378..d12fca0 100644 --- a/cachegrind/tests/ann2.post.exp +++ b/cachegrind/tests/ann2.post.exp @@ -20,7 +20,7 @@ Dw Dr Ir -------------------------------------------------------------------------------- Dw Dr Ir file:function -------------------------------------------------------------------------------- - 3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) /home/njn/grind/ws2/a.c:main + 3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) a.c:main 4,543 (25.23%) 17,566 ( 0.43%) 47,993 ( 0.92%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x 3,083 (17.12%) 5,750 ( 0.14%) 28,534 ( 0.55%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:_dl_lookup_symbol_x 8 ( 0.04%) 5,521 ( 0.14%) 28,136 ( 0.54%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c:__GI___tunables_init @@ -28,7 +28,7 @@ Dw Dr Ir file:function 0 5,158 ( 0.13%) 25,408 ( 0.49%) /build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcmp.S:strcmp -------------------------------------------------------------------------------- --- Auto-annotated source: /home/njn/grind/ws2/a.c +-- Auto-annotated source: a.c -------------------------------------------------------------------------------- Dw Dr Ir diff --git a/cachegrind/tests/cgout-test b/cachegrind/tests/cgout-test index d59359b..b625ec8 100644 --- a/cachegrind/tests/cgout-test +++ b/cachegrind/tests/cgout-test @@ -3525,7 +3525,7 @@ fn=wmemchr fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wmemset.c fn=wmemset 31 2 0 0 2 0 0 0 0 0 -fl=/home/njn/grind/ws2/a.c +fl=a.c fn=main 1 2 0 0 0 0 0 1 0 0 2 1 1 1 0 0 0 1 0 0 diff --git a/callgrind/tests/ann1.post.exp b/callgrind/tests/ann1.post.exp index 12ee255..201b967 100644 --- a/callgrind/tests/ann1.post.exp +++ b/callgrind/tests/ann1.post.exp @@ -9,7 +9,7 @@ Events recorded: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw Events shown: Ir I1mr ILmr Event sort order: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw Thresholds: 99 0 0 0 0 0 0 0 0 -Include dirs: +Include dirs: ../../cachegrind/tests/ User annotated: Auto-annotation: on @@ -21,7 +21,7 @@ Ir I1mr ILmr -------------------------------------------------------------------------------- Ir I1mr ILmr file:function -------------------------------------------------------------------------------- -5,000,015 1 1 /home/njn/grind/ws2/a.c:main +5,000,015 1 1 a.c:main 47,993 19 19 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x 28,534 11 11 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:_dl_lookup_symbol_x 28,136 7 7 /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c:__GI___tunables_init @@ -32,7 +32,7 @@ Ir I1mr ILmr file:function 6,898 2 2 /build/glibc-OTsEL5/glibc-2.27/elf/dl-misc.c:_dl_name_match_p -------------------------------------------------------------------------------- --- Auto-annotated source: /home/njn/grind/ws2/a.c +-- Auto-annotated source: ../../cachegrind/tests/ + a.c -------------------------------------------------------------------------------- Ir I1mr ILmr diff --git a/callgrind/tests/ann1.vgtest b/callgrind/tests/ann1.vgtest index 5791b97..6b80ee3 100644 --- a/callgrind/tests/ann1.vgtest +++ b/callgrind/tests/ann1.vgtest @@ -2,5 +2,5 @@ # the post-processing of the cgout-test file. prog: ../../tests/true vgopts: --callgrind-out-file=callgrind.out -post: perl ../../callgrind/callgrind_annotate --show=Ir,I1mr,ILmr --auto=yes ../../cachegrind/tests/cgout-test +post: perl ../../callgrind/callgrind_annotate --show=Ir,I1mr,ILmr --auto=yes --include=../../cachegrind/tests ../../cachegrind/tests/cgout-test cleanup: rm callgrind.out diff --git a/callgrind/tests/ann2.post.exp b/callgrind/tests/ann2.post.exp index 62dae60..47e5636 100644 --- a/callgrind/tests/ann2.post.exp +++ b/callgrind/tests/ann2.post.exp @@ -9,7 +9,7 @@ Events recorded: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw Events shown: Dw Dr Ir Event sort order: Dr Thresholds: 99 -Include dirs: +Include dirs: ../../cachegrind/tests/ User annotated: Auto-annotation: on @@ -21,11 +21,11 @@ Dw Dr Ir -------------------------------------------------------------------------------- Dw Dr Ir file:function -------------------------------------------------------------------------------- - 3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) /home/njn/grind/ws2/a.c:main + 3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) a.c:main 4,543 (25.23%) 17,566 ( 0.43%) 47,993 ( 0.92%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x -------------------------------------------------------------------------------- --- Auto-annotated source: /home/njn/grind/ws2/a.c +-- Auto-annotated source: ../../cachegrind/tests/ + a.c -------------------------------------------------------------------------------- Dw Dr Ir diff --git a/callgrind/tests/ann2.vgtest b/callgrind/tests/ann2.vgtest index 041fd85..e92f93a 100644 --- a/callgrind/tests/ann2.vgtest +++ b/callgrind/tests/ann2.vgtest @@ -2,5 +2,5 @@ # the post-processing of the cgout-test file. prog: ../../tests/true vgopts: --callgrind-out-file=callgrind.out -post: perl ../../callgrind/callgrind_annotate --sort=Dr --show=Dw,Dr,Ir --auto=yes --show-percs=yes ../../cachegrind/tests/cgout-test +post: perl ../../callgrind/callgrind_annotate --sort=Dr --show=Dw,Dr,Ir --auto=yes --include=../../cachegrind/tests --show-percs=yes ../../cachegrind/tests/cgout-test cleanup: rm callgrind.out |
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From: Nicholas N. <nj...@so...> - 2018-12-10 03:19:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e6e837752183dd2c0ef00bf687b9fe759bd6553c commit e6e837752183dd2c0ef00bf687b9fe759bd6553c Author: Nicholas Nethercote <nne...@mo...> Date: Fri Nov 23 15:16:02 2018 +1100 Add a --show-percs option to cg_annotate and callgrind_annotate. Because it's very useful. As part of this, the "percentage of events annotated" numbers at the bottom of the output is changed to "events annotated" so that --show-percs doesn't compute a percentage of a percentage. Example output lines: ``` 4,967,137,442 (100.0%) PROGRAM TOTALS 4,543 (25.23%) 17,566 ( 0.43%) 47,993 ( 0.92%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c 1 ( 0.01%) 2,000,001 (49.29%) 3,000,004 (57.36%) for (int i = 0; i < 1000000; i++) { ``` The commit also adds some much-needed tests for cg_annotate and callgrind_annotate. Diff: --- NEWS | 8 + cachegrind/cg_annotate.in | 74 +- cachegrind/docs/cg-manual.xml | 11 + cachegrind/tests/Makefile.am | 6 + cachegrind/tests/ann1.post.exp | 61 + cachegrind/tests/ann1.stderr.exp | 17 + cachegrind/tests/ann1.vgtest | 6 + cachegrind/tests/ann2.post.exp | 55 + cachegrind/tests/ann2.stderr.exp | 17 + cachegrind/tests/ann2.vgtest | 6 + cachegrind/tests/cgout-test | 3543 ++++++++++++++++++++++++++++++++++++++ cachegrind/tests/test.c | 7 + callgrind/callgrind_annotate.in | 84 +- callgrind/docs/cl-manual.xml | 11 + callgrind/tests/Makefile.am | 2 + callgrind/tests/ann1.post.exp | 62 + callgrind/tests/ann1.stderr.exp | 6 + callgrind/tests/ann1.vgtest | 6 + callgrind/tests/ann2.post.exp | 49 + callgrind/tests/ann2.stderr.exp | 6 + callgrind/tests/ann2.vgtest | 6 + 21 files changed, 4002 insertions(+), 41 deletions(-) diff --git a/NEWS b/NEWS index e6770cf..562291f 100644 --- a/NEWS +++ b/NEWS @@ -20,8 +20,16 @@ support for X86/macOS 10.13, AMD64/macOS 10.13. * ==================== TOOL CHANGES ==================== +* Cachegrind: + + - cg_annotate has a new option, --show-percs, which prints percentages next + to all event counts. + * Callgrind: + - callgrind_annotate has a new option, --show-percs, which prints percentages + next to all event counts. + - callgrind_annotate now inserts commas in call counts, and sort the caller/callee lists in the call tree. diff --git a/cachegrind/cg_annotate.in b/cachegrind/cg_annotate.in index fa0468e..b41c1c0 100644 --- a/cachegrind/cg_annotate.in +++ b/cachegrind/cg_annotate.in @@ -124,6 +124,9 @@ my $default_threshold = 0.1; my $single_threshold = $default_threshold; +# If on, show a percentage for each non-zero count. +my $show_percs = 0; + # If on, automatically annotates all files that are involved in getting over # all the threshold counts. my $auto_annotate = 0; @@ -151,6 +154,7 @@ usage: cg_annotate [options] cachegrind-out-file [source-files...] --sort=A,B,C sort columns by events A,B,C [event column order] --threshold=<0--20> a function is shown if it accounts for more than x% of the counts of the primary sort event [$default_threshold] + --show-percs=yes|no show a percentage for each non-zero count --auto=yes|no annotate all source files containing functions that helped reach the event count threshold [no] --context=N print N lines of context before and after @@ -219,6 +223,12 @@ sub process_cmd_line() $single_threshold = $1; ($1 >= 0 && $1 <= 20) or die($usage); + # --show-percs=yes|no + } elsif ($arg =~ /^--show-percs=yes$/) { + $show_percs = 1; + } elsif ($arg =~ /^--show-percs=no$/) { + $show_percs = 0; + # --auto=yes|no } elsif ($arg =~ /^--auto=yes$/) { $auto_annotate = 1; @@ -533,10 +543,14 @@ sub compute_CC_col_widths (@) foreach my $CC (@CCs) { foreach my $i (0 .. scalar(@$CC)-1) { if (defined $CC->[$i]) { - # Find length, accounting for commas that will be added + # Find length, accounting for commas that will be added, and + # possibly a percentage. my $length = length $CC->[$i]; - my $clength = $length + int(($length - 1) / 3); - $CC_col_widths->[$i] = max($CC_col_widths->[$i], $clength); + my $width = $length + int(($length - 1) / 3); + if ($show_percs) { + $width += 9; # e.g. " (12.34%)" is 9 chars + } + $CC_col_widths->[$i] = max($CC_col_widths->[$i], $width); } } } @@ -550,8 +564,33 @@ sub print_CC ($$) foreach my $i (@show_order) { my $count = (defined $CC->[$i] ? commify($CC->[$i]) : "."); - my $space = ' ' x ($CC_col_widths->[$i] - length($count)); - print("$space$count "); + + my $perc = ""; + if ($show_percs) { + if (defined $CC->[$i] && $CC->[$i] != 0) { + # Try our best to keep the number fitting into 5 chars. This + # requires dropping a digit after the decimal place if it's + # sufficiently negative (e.g. "-10.0") or positive (e.g. + # "100.0"). Thanks to diffs it's possible to have even more + # extreme values, like "-100.0" or "1000.0"; those rare case + # will end up with slightly wrong indenting, oh well. + $perc = safe_div($CC->[$i] * 100, $summary_CC->[$i]); + $perc = (-9.995 < $perc && $perc < 99.995) + ? sprintf(" (%5.2f%%)", $perc) + : sprintf(" (%5.1f%%)", $perc); + } else { + # Don't show percentages for "." and "0" entries. + $perc = " "; + } + } + + # $reps will be negative for the extreme values mentioned above. The + # use of max() avoids a possible warning about a negative repeat count. + my $text = $count . $perc; + my $len = length($text); + my $reps = $CC_col_widths->[$i] - length($text); + my $space = ' ' x max($reps, 0); + print("$space$text "); } } @@ -564,7 +603,7 @@ sub print_events ($) my $event_width = length($event); my $col_width = $CC_col_widths->[$i]; my $space = ' ' x ($col_width - $event_width); - print("$space$event "); + print("$event$space "); } } @@ -828,7 +867,7 @@ sub annotate_ann_files($) shift(@line_nums); } else { - print_CC( [], $CC_col_widths); + print_CC([], $CC_col_widths); } print(" $src_line"); @@ -869,29 +908,22 @@ sub annotate_ann_files($) print("$fancy"); print("The following files chosen for auto-annotation could not be found:\n"); print($fancy); - foreach my $f (@unfound_auto_annotate_files) { + foreach my $f (sort @unfound_auto_annotate_files) { print(" $f\n"); } print("\n"); } - # If we did any annotating, print what proportion of events were covered by - # annotated lines above. + # If we did any annotating, show how many events were covered by annotated + # lines above. if ($did_annotations) { - my $percent_printed_CC; - foreach (my $i = 0; $i < @$summary_CC; $i++) { - $percent_printed_CC->[$i] = - sprintf("%.0f", - 100 * safe_div(abs($printed_totals_CC->[$i]), - abs($summary_CC->[$i]))); - } - my $pp_CC_col_widths = compute_CC_col_widths($percent_printed_CC); + my $CC_col_widths = compute_CC_col_widths($printed_totals_CC); print($fancy); - print_events($pp_CC_col_widths); + print_events($CC_col_widths); print("\n"); print($fancy); - print_CC($percent_printed_CC, $pp_CC_col_widths); - print(" percentage of events annotated\n\n"); + print_CC($printed_totals_CC, $CC_col_widths); + print(" events annotated\n\n"); } } diff --git a/cachegrind/docs/cg-manual.xml b/cachegrind/docs/cg-manual.xml index 5f991b3..d90a3be 100644 --- a/cachegrind/docs/cg-manual.xml +++ b/cachegrind/docs/cg-manual.xml @@ -946,6 +946,17 @@ small differences like these; it works in the same way as <varlistentry> <term> + <option><![CDATA[--show-percs=<no|yes> [default: no] ]]></option> + </term> + <listitem> + <para>When enabled, a percentage is printed next to all event counts. + This helps gauge the relative importance of each function and line. + </para> + </listitem> + </varlistentry> + + <varlistentry> + <term> <option><![CDATA[--auto=<no|yes> [default: no] ]]></option> </term> <listitem> diff --git a/cachegrind/tests/Makefile.am b/cachegrind/tests/Makefile.am index e21d52d..f2f8902 100644 --- a/cachegrind/tests/Makefile.am +++ b/cachegrind/tests/Makefile.am @@ -10,11 +10,17 @@ DIST_SUBDIRS = x86 . dist_noinst_SCRIPTS = filter_stderr filter_cachesim_discards +# Note that test.c is not compiled. It just serves as input for cg_annotate in +# ann1 and ann2. EXTRA_DIST = \ + cgout-test \ + ann1.post.exp ann1.stderr.exp ann1.vgtest \ + ann2.post.exp ann2.stderr.exp ann2.vgtest \ chdir.vgtest chdir.stderr.exp \ clreq.vgtest clreq.stderr.exp \ dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \ notpower2.vgtest notpower2.stderr.exp \ + test.c \ wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp check_PROGRAMS = \ diff --git a/cachegrind/tests/ann1.post.exp b/cachegrind/tests/ann1.post.exp new file mode 100644 index 0000000..d82b6ab --- /dev/null +++ b/cachegrind/tests/ann1.post.exp @@ -0,0 +1,61 @@ +-------------------------------------------------------------------------------- +I1 cache: 32768 B, 64 B, 8-way associative +D1 cache: 32768 B, 64 B, 8-way associative +LL cache: 19922944 B, 64 B, 19-way associative +Command: ./a.out +Data file: cgout-test +Events recorded: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +Events shown: Ir I1mr ILmr +Event sort order: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +Thresholds: 0.1 100 100 100 100 100 100 100 100 +Include dirs: +User annotated: +Auto-annotation: on + +-------------------------------------------------------------------------------- +Ir I1mr ILmr +-------------------------------------------------------------------------------- +5,229,753 952 931 PROGRAM TOTALS + +-------------------------------------------------------------------------------- +Ir I1mr ILmr file:function +-------------------------------------------------------------------------------- +5,000,015 1 1 /home/njn/grind/ws2/a.c:main + 47,993 19 19 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x + 28,534 11 11 /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:_dl_lookup_symbol_x + 28,136 7 7 /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c:__GI___tunables_init + 25,408 47 47 /build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcmp.S:strcmp + 21,821 23 23 /build/glibc-OTsEL5/glibc-2.27/elf/../sysdeps/x86_64/dl-machine.h:_dl_relocate_object + 11,521 15 15 /build/glibc-OTsEL5/glibc-2.27/elf/do-rel.h:_dl_relocate_object + 8,055 0 0 /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.h:__GI___tunables_init + 6,898 2 2 /build/glibc-OTsEL5/glibc-2.27/elf/dl-misc.c:_dl_name_match_p + +-------------------------------------------------------------------------------- +-- Auto-annotated source: /home/njn/grind/ws2/a.c +-------------------------------------------------------------------------------- +Ir I1mr ILmr + + 2 0 0 int main(void) { + 1 1 1 int z = 0; +3,000,004 0 0 for (int i = 0; i < 1000000; i++) { +2,000,000 0 0 z += i; + . . . } + 6 0 0 return z % 256; + 2 0 0 } + +-------------------------------------------------------------------------------- +The following files chosen for auto-annotation could not be found: +-------------------------------------------------------------------------------- + /build/glibc-OTsEL5/glibc-2.27/elf/../sysdeps/x86_64/dl-machine.h + /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c + /build/glibc-OTsEL5/glibc-2.27/elf/dl-misc.c + /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c + /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.h + /build/glibc-OTsEL5/glibc-2.27/elf/do-rel.h + /build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcmp.S + +-------------------------------------------------------------------------------- +Ir I1mr ILmr +-------------------------------------------------------------------------------- +5,000,015 1 1 events annotated + diff --git a/cachegrind/tests/ann1.stderr.exp b/cachegrind/tests/ann1.stderr.exp new file mode 100644 index 0000000..e8084c1 --- /dev/null +++ b/cachegrind/tests/ann1.stderr.exp @@ -0,0 +1,17 @@ + + +I refs: +I1 misses: +LLi misses: +I1 miss rate: +LLi miss rate: + +D refs: +D1 misses: +LLd misses: +D1 miss rate: +LLd miss rate: + +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/ann1.vgtest b/cachegrind/tests/ann1.vgtest new file mode 100644 index 0000000..81243d3 --- /dev/null +++ b/cachegrind/tests/ann1.vgtest @@ -0,0 +1,6 @@ +# The 'prog' doesn't matter because we don't use its output. Instead we test +# the post-processing of the cgout-test file. +prog: ../../tests/true +vgopts: --cachegrind-out-file=cachegrind.out +post: perl ../../cachegrind/cg_annotate --show=Ir,I1mr,ILmr --auto=yes cgout-test +cleanup: rm cachegrind.out diff --git a/cachegrind/tests/ann2.post.exp b/cachegrind/tests/ann2.post.exp new file mode 100644 index 0000000..83d9378 --- /dev/null +++ b/cachegrind/tests/ann2.post.exp @@ -0,0 +1,55 @@ +-------------------------------------------------------------------------------- +I1 cache: 32768 B, 64 B, 8-way associative +D1 cache: 32768 B, 64 B, 8-way associative +LL cache: 19922944 B, 64 B, 19-way associative +Command: ./a.out +Data file: cgout-test +Events recorded: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +Events shown: Dw Dr Ir +Event sort order: Dr +Thresholds: 0.1 +Include dirs: +User annotated: +Auto-annotation: on + +-------------------------------------------------------------------------------- +Dw Dr Ir +-------------------------------------------------------------------------------- +18,005 (100.0%) 4,057,955 (100.0%) 5,229,753 (100.0%) PROGRAM TOTALS + +-------------------------------------------------------------------------------- +Dw Dr Ir file:function +-------------------------------------------------------------------------------- + 3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) /home/njn/grind/ws2/a.c:main +4,543 (25.23%) 17,566 ( 0.43%) 47,993 ( 0.92%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:do_lookup_x +3,083 (17.12%) 5,750 ( 0.14%) 28,534 ( 0.55%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c:_dl_lookup_symbol_x + 8 ( 0.04%) 5,521 ( 0.14%) 28,136 ( 0.54%) /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c:__GI___tunables_init +2,490 (13.83%) 5,219 ( 0.13%) 21,821 ( 0.42%) /build/glibc-OTsEL5/glibc-2.27/elf/../sysdeps/x86_64/dl-machine.h:_dl_relocate_object + 0 5,158 ( 0.13%) 25,408 ( 0.49%) /build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcmp.S:strcmp + +-------------------------------------------------------------------------------- +-- Auto-annotated source: /home/njn/grind/ws2/a.c +-------------------------------------------------------------------------------- +Dw Dr Ir + +1 ( 0.01%) 0 2 ( 0.00%) int main(void) { +1 ( 0.01%) 0 1 ( 0.00%) int z = 0; +1 ( 0.01%) 2,000,001 (49.29%) 3,000,004 (57.36%) for (int i = 0; i < 1000000; i++) { +0 2,000,000 (49.29%) 2,000,000 (38.24%) z += i; +. . . } +0 1 ( 0.00%) 6 ( 0.00%) return z % 256; +0 2 ( 0.00%) 2 ( 0.00%) } + +-------------------------------------------------------------------------------- +The following files chosen for auto-annotation could not be found: +-------------------------------------------------------------------------------- + /build/glibc-OTsEL5/glibc-2.27/elf/../sysdeps/x86_64/dl-machine.h + /build/glibc-OTsEL5/glibc-2.27/elf/dl-lookup.c + /build/glibc-OTsEL5/glibc-2.27/elf/dl-tunables.c + /build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcmp.S + +-------------------------------------------------------------------------------- +Dw Dr Ir +-------------------------------------------------------------------------------- +3 ( 0.02%) 4,000,004 (98.57%) 5,000,015 (95.61%) events annotated + diff --git a/cachegrind/tests/ann2.stderr.exp b/cachegrind/tests/ann2.stderr.exp new file mode 100644 index 0000000..e8084c1 --- /dev/null +++ b/cachegrind/tests/ann2.stderr.exp @@ -0,0 +1,17 @@ + + +I refs: +I1 misses: +LLi misses: +I1 miss rate: +LLi miss rate: + +D refs: +D1 misses: +LLd misses: +D1 miss rate: +LLd miss rate: + +LL refs: +LL misses: +LL miss rate: diff --git a/cachegrind/tests/ann2.vgtest b/cachegrind/tests/ann2.vgtest new file mode 100644 index 0000000..b46da02 --- /dev/null +++ b/cachegrind/tests/ann2.vgtest @@ -0,0 +1,6 @@ +# The 'prog' doesn't matter because we don't use its output. Instead we test +# the post-processing of the cgout-test file. +prog: ../../tests/true +vgopts: --cachegrind-out-file=cachegrind.out +post: perl ../../cachegrind/cg_annotate --sort=Dr --show=Dw,Dr,Ir --auto=yes --show-percs=yes cgout-test +cleanup: rm cachegrind.out diff --git a/cachegrind/tests/cgout-test b/cachegrind/tests/cgout-test new file mode 100644 index 0000000..d59359b --- /dev/null +++ b/cachegrind/tests/cgout-test @@ -0,0 +1,3543 @@ +desc: I1 cache: 32768 B, 64 B, 8-way associative +desc: D1 cache: 32768 B, 64 B, 8-way associative +desc: LL cache: 19922944 B, 64 B, 19-way associative +cmd: ./a.out +events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw +fl=/build/glibc-OTsEL5/glibc-2.27/csu/../csu/init-first.c +fn=_init +52 8 1 1 0 0 0 4 0 0 +55 4 1 1 1 1 0 1 0 0 +62 5 1 1 4 1 0 0 0 0 +67 1 0 0 0 0 0 1 1 1 +68 1 0 0 0 0 0 1 0 0 +69 2 0 0 1 1 0 1 1 1 +81 4 0 0 0 0 0 1 0 0 +84 1 0 0 0 0 0 1 0 0 +89 6 0 0 5 0 0 0 0 0 +fl=/build/glibc-OTsEL5/glibc-2.27/csu/../csu/libc-start.c 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From: Mark W. <ma...@so...> - 2018-12-07 13:06:02
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0c701ba2a4b10a5f6f3fae31cb0ec6ca034d51d9 commit 0c701ba2a4b10a5f6f3fae31cb0ec6ca034d51d9 Author: Mark Wielaard <ma...@kl...> Date: Fri Dec 7 14:01:20 2018 +0100 Fix sigkill.stderr.exp for glibc-2.28. glibc 2.28 filters out some bad signal numbers and returns Invalid argument instead of passing such bad signal numbers the kernel sigaction syscall. So we won't see such bad signal numbers and won't print "bad signal number" ourselves. Add a new memcheck/tests/sigkill.stderr.exp-glibc-2.28 to catch this case. Diff: --- memcheck/tests/Makefile.am | 3 +- memcheck/tests/sigkill.stderr.exp-glibc-2.28 | 197 +++++++++++++++++++++++++++ 2 files changed, 199 insertions(+), 1 deletion(-) diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index 76e0e90..2af4dd1 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -260,7 +260,8 @@ EXTRA_DIST = \ sh-mem-random.stdout.exp sh-mem-random.vgtest \ sigaltstack.stderr.exp sigaltstack.vgtest \ sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \ - sigkill.stderr.exp-solaris sigkill.vgtest \ + sigkill.stderr.exp-solaris \ + sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \ signal2.stderr.exp signal2.stdout.exp signal2.vgtest \ sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \ static_malloc.stderr.exp static_malloc.vgtest \ diff --git a/memcheck/tests/sigkill.stderr.exp-glibc-2.28 b/memcheck/tests/sigkill.stderr.exp-glibc-2.28 new file mode 100644 index 0000000..0e5f0cb --- /dev/null +++ b/memcheck/tests/sigkill.stderr.exp-glibc-2.28 @@ -0,0 +1,197 @@ + +setting signal 1: Success +getting signal 1: Success + +setting signal 2: Success +getting signal 2: Success + +setting signal 3: Success +getting signal 3: Success + +setting signal 4: Success +getting signal 4: Success + +setting signal 5: Success +getting signal 5: Success + +setting signal 6: Success +getting signal 6: Success + +setting signal 7: Success +getting signal 7: Success + +setting signal 8: Success +getting signal 8: Success + +setting signal 9: Warning: ignored attempt to set SIGKILL handler in sigaction(); + the SIGKILL signal is uncatchable +Invalid argument +getting signal 9: Success + +setting signal 10: Success +getting signal 10: Success + +setting signal 11: Success +getting signal 11: Success + +setting signal 12: Success +getting signal 12: Success + +setting signal 13: Success +getting signal 13: Success + +setting signal 14: Success +getting signal 14: Success + +setting signal 15: Success +getting signal 15: Success + +setting signal 16: Success +getting signal 16: Success + +setting signal 17: Success +getting signal 17: Success + +setting signal 18: Success +getting signal 18: Success + +setting signal 19: Warning: ignored attempt to set SIGSTOP handler in sigaction(); + the SIGSTOP signal is uncatchable +Invalid argument +getting signal 19: Success + +setting signal 20: Success +getting signal 20: Success + +setting signal 21: Success +getting signal 21: Success + +setting signal 22: Success +getting signal 22: Success + +setting signal 23: Success +getting signal 23: Success + +setting signal 24: Success +getting signal 24: Success + +setting signal 25: Success +getting signal 25: Success + +setting signal 26: Success +getting signal 26: Success + +setting signal 27: Success +getting signal 27: Success + +setting signal 28: Success +getting signal 28: Success + +setting signal 29: Success +getting signal 29: Success + +setting signal 30: Success +getting signal 30: Success + +setting signal 31: Success +getting signal 31: Success + +setting signal 34: Success +getting signal 34: Success + +setting signal 35: Success +getting signal 35: Success + +setting signal 36: Success +getting signal 36: Success + +setting signal 37: Success +getting signal 37: Success + +setting signal 38: Success +getting signal 38: Success + +setting signal 39: Success +getting signal 39: Success + +setting signal 40: Success +getting signal 40: Success + +setting signal 41: Success +getting signal 41: Success + +setting signal 42: Success +getting signal 42: Success + +setting signal 43: Success +getting signal 43: Success + +setting signal 44: Success +getting signal 44: Success + +setting signal 45: Success +getting signal 45: Success + +setting signal 46: Success +getting signal 46: Success + +setting signal 47: Success +getting signal 47: Success + +setting signal 48: Success +getting signal 48: Success + +setting signal 49: Success +getting signal 49: Success + +setting signal 50: Success +getting signal 50: Success + +setting signal 51: Success +getting signal 51: Success + +setting signal 52: Success +getting signal 52: Success + +setting signal 53: Success +getting signal 53: Success + +setting signal 54: Success +getting signal 54: Success + +setting signal 55: Success +getting signal 55: Success + +setting signal 56: Success +getting signal 56: Success + +setting signal 57: Success +getting signal 57: Success + +setting signal 58: Success +getting signal 58: Success + +setting signal 59: Success +getting signal 59: Success + +setting signal 60: Success +getting signal 60: Success + +setting signal 61: Success +getting signal 61: Success + +setting signal 62: Success +getting signal 62: Success + +setting signal 65: Invalid argument +getting signal 65: Invalid argument + + +HEAP SUMMARY: + in use at exit: ... bytes in ... blocks + total heap usage: ... allocs, ... frees, ... bytes allocated + +For a detailed leak analysis, rerun with: --leak-check=full + +For counts of detected and suppressed errors, rerun with: -v +ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) |
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From: Mark W. <ma...@so...> - 2018-12-06 19:55:25
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a0d97e88ec6d71239d30a5a4b2b129e094150873 commit a0d97e88ec6d71239d30a5a4b2b129e094150873 Author: Mark Wielaard <ma...@kl...> Date: Thu Dec 6 20:52:22 2018 +0100 Bug 401822 Fix asm constraints for ppc64 jm-vmx jm-insns.c test. The mfvscr and vor instructions in jm-insns.c had a "=vr" constraint. This should have been an "=v" constraint. This resolved assembler warnings and the testcase failing on ppc64le with gcc 8.2 and binutils 2.30. Diff: --- NEWS | 1 + none/tests/ppc32/jm-insns.c | 82 ++++++++++++++++++++++----------------------- 2 files changed, 42 insertions(+), 41 deletions(-) diff --git a/NEWS b/NEWS index edf0f72..e6770cf 100644 --- a/NEWS +++ b/NEWS @@ -61,6 +61,7 @@ where XXXXXX is the bug number as listed below. 385411 s390x: z13 vector floating-point instructions not implemented 401578 drd: crashes sometimes on fork() 401627 memcheck errors with glibc avx2 optimized wcsncmp +401822 none/tests/ppc64/jm-vmx fails and produces assembler warnings Release 3.14.0 (9 October 2018) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index e1a7da9..be02425 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -6269,7 +6269,7 @@ static void test_av_int_one_arg (const char* name, test_func_t func, for (i=0; i<nb_viargs; i++) { /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); vec_in = (vector unsigned int)viargs[i]; vec_out = (vector unsigned int){ 0,0,0,0 }; @@ -6287,11 +6287,11 @@ static void test_av_int_one_arg (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6333,7 +6333,7 @@ static void test_av_int_two_args (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6349,11 +6349,11 @@ static void test_av_int_two_args (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6401,7 +6401,7 @@ static void test_av_int_three_args (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6418,11 +6418,11 @@ static void test_av_int_three_args (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6475,7 +6475,7 @@ static void vs128_cb (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6491,11 +6491,11 @@ static void vs128_cb (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6548,7 +6548,7 @@ static void vsplt_cb (const char* name, test_func_t func_IN, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6563,11 +6563,11 @@ static void vsplt_cb (const char* name, test_func_t func_IN, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6615,7 +6615,7 @@ static void vspltis_cb (const char* name, test_func_t func_IN, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6627,11 +6627,11 @@ static void vspltis_cb (const char* name, test_func_t func_IN, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6677,7 +6677,7 @@ static void vsldoi_cb (const char* name, test_func_t func_IN, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6693,11 +6693,11 @@ static void vsldoi_cb (const char* name, test_func_t func_IN, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6750,7 +6750,7 @@ static void lvs_cb (const char *name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6762,11 +6762,11 @@ static void lvs_cb (const char *name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6870,7 +6870,7 @@ static void test_av_int_ld_two_regs (const char *name, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6882,11 +6882,11 @@ static void test_av_int_ld_two_regs (const char *name, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -6956,7 +6956,7 @@ static void test_av_int_st_three_regs (const char *name, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -6974,7 +6974,7 @@ static void test_av_int_st_three_regs (const char *name, // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -7037,7 +7037,7 @@ static void test_av_float_one_arg (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -7052,11 +7052,11 @@ static void test_av_float_one_arg (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -7099,7 +7099,7 @@ static void test_av_float_two_args (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -7115,11 +7115,11 @@ static void test_av_float_two_args (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -7168,7 +7168,7 @@ static void test_av_float_three_args (const char* name, test_func_t func, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -7185,11 +7185,11 @@ static void test_av_float_three_args (const char* name, test_func_t func, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); @@ -7276,7 +7276,7 @@ static void vcvt_cb (const char* name, test_func_t func_IN, /* Save flags */ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr)); // reset VSCR and CR vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR }; @@ -7291,11 +7291,11 @@ static void vcvt_cb (const char* name, test_func_t func_IN, (*func)(); // retrieve output <- r17 - __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out)); + __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out)); // get CR,VSCR flags __asm__ __volatile__ ("mfcr %0" : "=r" (flags)); - __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr)); + __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr)); /* Restore flags */ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr)); |
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From: Mark W. <ma...@so...> - 2018-12-06 15:41:12
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=cf00e0e59def011e40e2c7993aab23970841dd03 commit cf00e0e59def011e40e2c7993aab23970841dd03 Author: Mark Wielaard <ma...@kl...> Date: Sat Dec 1 23:54:40 2018 +0100 Bug 401627 - Add wcsncmp override and testcase. glibc 2.28 added an avx2 optimized variant of wstrncmp which memcheck cannot proof correct. Add a simple override in vg_replace_strmem.c. Diff: --- NEWS | 1 + memcheck/tests/wcs.c | 7 +++++-- memcheck/tests/wcs.stderr.exp | 1 + shared/vg_replace_strmem.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 7b784a8..edf0f72 100644 --- a/NEWS +++ b/NEWS @@ -60,6 +60,7 @@ where XXXXXX is the bug number as listed below. 401112 LLVM 5.0 generates comparison against partially initialized data 385411 s390x: z13 vector floating-point instructions not implemented 401578 drd: crashes sometimes on fork() +401627 memcheck errors with glibc avx2 optimized wcsncmp Release 3.14.0 (9 October 2018) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/memcheck/tests/wcs.c b/memcheck/tests/wcs.c index 15730ad..538304b 100644 --- a/memcheck/tests/wcs.c +++ b/memcheck/tests/wcs.c @@ -1,5 +1,6 @@ -// Uses various wchar_t * functions that have hand written SSE assembly -// implementations in glibc. wcslen, wcscpy, wcscmp, wcsrchr, wcschr. +// Uses various wchar_t * functions that have hand written SSE and/or AVX2 +// assembly implementations in glibc. +// wcslen, wcscpy, wcscmp, wcsncmp, wcsrchr, wcschr. #include <stdio.h> #include <stdlib.h> @@ -18,6 +19,8 @@ int main(int argc, char **argv) c = wcscpy (b, a); fprintf (stderr, "wcscmp equal: %d\n", wcscmp (a, b)); // wcscmp equal: 0 + fprintf (stderr, + "wcsncmp equal: %d\n", wcsncmp (a, b, l)); // wcsncmp equal: 0 d = wcsrchr (a, L'd'); e = wcschr (a, L'd'); diff --git a/memcheck/tests/wcs.stderr.exp b/memcheck/tests/wcs.stderr.exp index 41d74c8..d5b5959 100644 --- a/memcheck/tests/wcs.stderr.exp +++ b/memcheck/tests/wcs.stderr.exp @@ -1,3 +1,4 @@ wcslen: 53 wcscmp equal: 0 +wcsncmp equal: 0 wcsrchr == wcschr: 1 diff --git a/shared/vg_replace_strmem.c b/shared/vg_replace_strmem.c index d6927f0..89a7dcc 100644 --- a/shared/vg_replace_strmem.c +++ b/shared/vg_replace_strmem.c @@ -103,6 +103,7 @@ 20420 STPNCPY 20430 WMEMCHR 20440 WCSNLEN + 20450 WSTRNCMP */ #if defined(VGO_solaris) @@ -1927,6 +1928,36 @@ static inline void my_exit ( int x ) WCSCMP(VG_Z_LIBC_SONAME, wcscmp) #endif +/*---------------------- wcsncmp ----------------------*/ + +// This is a wchar_t equivalent to strncmp. We don't +// have wchar_t available here, but in the GNU C Library +// wchar_t is always 32 bits wide and wcsncmp uses signed +// comparison, not unsigned as in strncmp function. + +#define WCSNCMP(soname, fnname) \ + int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \ + ( const Int* s1, const Int* s2, SizeT nmax ); \ + int VG_REPLACE_FUNCTION_EZU(20450,soname,fnname) \ + ( const Int* s1, const Int* s2, SizeT nmax ) \ + { \ + SizeT n = 0; \ + while (True) { \ + if (n >= nmax) return 0; \ + if (*s1 == 0 && *s2 == 0) return 0; \ + if (*s1 == 0) return -1; \ + if (*s2 == 0) return 1; \ + \ + if (*s1 < *s2) return -1; \ + if (*s1 > *s2) return 1; \ + \ + s1++; s2++; n++; \ + } \ + } +#if defined(VGO_linux) + WCSNCMP(VG_Z_LIBC_SONAME, wcsncmp) +#endif + /*---------------------- wcscpy ----------------------*/ // This is a wchar_t equivalent to strcpy. We don't |
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From: Bart V. A. <bva...@ac...> - 2018-12-06 02:17:28
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On 12/5/18 8:07 AM, Andreas Arnez wrote: > Subject: [PATCH v3] Add Emacs configuration files v3 has been applied. Thanks for the patch! Bart. |