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From: Petar J. <pe...@so...> - 2018-02-01 18:06:29
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=9fc2bfba5c9ad9b8b6c31990b81ba205b7abc565 commit 9fc2bfba5c9ad9b8b6c31990b81ba205b7abc565 Author: Petar Jovanovic <mip...@gm...> Date: Thu Feb 1 18:37:28 2018 +0100 mips: add tests for mips32/mips64 R6 This set of tests covers MIPS r6 specific instructions: none/tests/mips32/MIPS32r6int none/tests/mips32/branch_pc none/tests/mips32/branches_r6 none/tests/mips32/fp_r6 none/tests/mips32/pc_instructions_r6 none/tests/mips64/MIPS64r6int none/tests/mips64/branch_pc none/tests/mips64/branches_r6 none/tests/mips64/fp_r6 none/tests/mips64/pc_instructions_r6 none/tests/mips64/r6_instructions The following tests had to be changed to be applicaple for Rev6: none/tests/libvex_test.c none/tests/mips32/LoadStore none/tests/mips32/LoadStore1 none/tests/mips32/MIPS32int none/tests/mips32/MoveIns none/tests/mips32/branches none/tests/mips32/change_fp_mode none/tests/mips32/mips32_dsp none/tests/mips32/vfp none/tests/mips64/arithmetic_instruction none/tests/mips64/branches none/tests/mips64/fpu_arithmetic none/tests/mips64/fpu_load_store none/tests/mips64/load_store none/tests/mips64/load_store_multiple none/tests/mips64/move_instructions The following tests are not applicable for Rev6: none/tests/mips32/fpu_branches none/tests/mips32/unaligned_load_store none/tests/mips64/branch_and_jump_instructions none/tests/mips64/change_fp_mode none/tests/mips64/fpu_branches none/tests/mips64/load_store_unaligned none/tests/mips64/unaligned_load none/tests/mips64/unaligned_load_store. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410. Diff: --- .gitignore | 6 + none/tests/libvex_test.c | 5 + none/tests/mips32/LoadStore.c | 2 + none/tests/mips32/LoadStore.stdout.exp-r6-BE | 171 + none/tests/mips32/LoadStore.stdout.exp-r6-LE | 171 + none/tests/mips32/LoadStore1.c | 2 + none/tests/mips32/LoadStore1.stdout.exp-r6-BE | 171 + none/tests/mips32/LoadStore1.stdout.exp-r6-LE | 171 + none/tests/mips32/MIPS32int.c | 10 + none/tests/mips32/MIPS32int.stdout.exp-mips32r6-BE | 1325 ++ none/tests/mips32/MIPS32int.stdout.exp-mips32r6-LE | 1325 ++ none/tests/mips32/MIPS32r6int.c | 2903 ++++ none/tests/mips32/MIPS32r6int.stderr.exp | 0 none/tests/mips32/MIPS32r6int.stdout.exp | 2801 ++++ none/tests/mips32/MIPS32r6int.vgtest | 3 + none/tests/mips32/Makefile.am | 24 +- none/tests/mips32/MoveIns.c | 2 + none/tests/mips32/MoveIns.stdout.exp-mips32r6-BE | 146 + none/tests/mips32/MoveIns.stdout.exp-mips32r6-LE | 146 + none/tests/mips32/SignalException.c | 3 +- none/tests/mips32/branch_pc.c | 90 + none/tests/mips32/branch_pc.stderr.exp | 0 none/tests/mips32/branch_pc.stdout.exp | 37 + none/tests/mips32/branch_pc.vgtest | 3 + none/tests/mips32/branches.c | 66 +- none/tests/mips32/branches.stdout.exp | 10 +- none/tests/mips32/branches.stdout.exp-r6 | 261 + none/tests/mips32/branches_r6.c | 548 + none/tests/mips32/branches_r6.stderr.exp | 0 none/tests/mips32/branches_r6.stdout.exp | 374 + none/tests/mips32/branches_r6.vgtest | 3 + none/tests/mips32/change_fp_mode.c | 65 +- none/tests/mips32/change_fp_mode.stdout.exp-r6 | 6 + none/tests/mips32/fp_r6.c | 7300 +++++++++ none/tests/mips32/fp_r6.stderr.exp | 0 none/tests/mips32/fp_r6.stdout.exp | 7509 ++++++++++ none/tests/mips32/fp_r6.vgtest | 3 + none/tests/mips32/fpu_branches.c | 3 +- none/tests/mips32/fpu_branches.vgtest | 2 +- none/tests/mips32/mips32_dsp.c | 4 +- none/tests/mips32/pc_instructions_r6.c | 114 + none/tests/mips32/pc_instructions_r6.stderr.exp | 0 none/tests/mips32/pc_instructions_r6.stdout.exp | 39 + none/tests/mips32/pc_instructions_r6.vgtest | 3 + none/tests/mips32/unaligned_load_store.c | 3 +- none/tests/mips32/unaligned_load_store.vgtest | 1 + none/tests/mips32/vfp.c | 13 +- none/tests/mips64/MIPS64r6int.c | 1 + none/tests/mips64/MIPS64r6int.stderr.exp | 1 + none/tests/mips64/MIPS64r6int.stdout.exp | 1 + none/tests/mips64/MIPS64r6int.vgtest | 3 + none/tests/mips64/Makefile.am | 26 +- none/tests/mips64/arithmetic_instruction.c | 28 +- .../arithmetic_instruction.stdout.exp-mips64r6 | 6926 +++++++++ none/tests/mips64/branch_and_jump_instructions.c | 4 +- .../mips64/branch_and_jump_instructions.vgtest | 1 + none/tests/mips64/branch_pc.c | 1 + none/tests/mips64/branch_pc.stderr.exp | 1 + none/tests/mips64/branch_pc.stdout.exp | 1 + none/tests/mips64/branch_pc.vgtest | 1 + none/tests/mips64/branches.c | 65 +- none/tests/mips64/branches.stdout.exp-r6 | 260 + none/tests/mips64/branches_r6.c | 1 + none/tests/mips64/branches_r6.stderr.exp | 1 + none/tests/mips64/branches_r6.stdout.exp | 1 + none/tests/mips64/branches_r6.vgtest | 1 + none/tests/mips64/change_fp_mode.c | 3 +- none/tests/mips64/change_fp_mode.vgtest | 2 +- none/tests/mips64/fp_r6.c | 1 + none/tests/mips64/fp_r6.stderr.exp | 1 + none/tests/mips64/fp_r6.stdout.exp | 1 + none/tests/mips64/fp_r6.vgtest | 1 + none/tests/mips64/fpu_arithmetic.c | 10 +- none/tests/mips64/fpu_arithmetic.stdout.exp-r6 | 1729 +++ none/tests/mips64/fpu_branches.c | 2 +- none/tests/mips64/fpu_branches.vgtest | 2 +- none/tests/mips64/fpu_load_store.c | 19 +- none/tests/mips64/fpu_load_store.stdout.exp-BE-r2 | 3078 ++++ none/tests/mips64/fpu_load_store.stdout.exp-BE-r6 | 1539 ++ none/tests/mips64/fpu_load_store.stdout.exp-LE-r2 | 3078 ++++ none/tests/mips64/fpu_load_store.stdout.exp-LE-r6 | 1539 ++ none/tests/mips64/load_store.c | 12 +- none/tests/mips64/load_store.stdout.exp-BE-r6 | 14961 +++++++++++++++++++ none/tests/mips64/load_store.stdout.exp-LE-r6 | 14961 +++++++++++++++++++ none/tests/mips64/load_store_multiple.c | 4 + .../mips64/load_store_multiple.stdout.exp-BE-r6 | 171 + .../mips64/load_store_multiple.stdout.exp-LE-r6 | 171 + none/tests/mips64/load_store_unaligned.c | 2 + none/tests/mips64/load_store_unaligned.vgtest | 2 +- none/tests/mips64/macro_fpu.h | 8 +- none/tests/mips64/move_instructions.c | 7 +- none/tests/mips64/move_instructions.stdout.exp-r6 | 1024 ++ none/tests/mips64/pc_instructions_r6.c | 1 + none/tests/mips64/pc_instructions_r6.stderr.exp | 1 + none/tests/mips64/pc_instructions_r6.stdout.exp | 39 + none/tests/mips64/pc_instructions_r6.vgtest | 1 + none/tests/mips64/r6_instructions.c | 355 + none/tests/mips64/r6_instructions.stderr.exp | 0 none/tests/mips64/r6_instructions.stdout.exp-BE | 243 + none/tests/mips64/r6_instructions.stdout.exp-LE | 243 + none/tests/mips64/r6_instructions.vgtest | 3 + none/tests/mips64/unaligned_load.c | 2 + none/tests/mips64/unaligned_load.vgtest | 1 + none/tests/mips64/unaligned_load_store.c | 2 + none/tests/mips64/unaligned_load_store.vgtest | 1 + tests/mips_features.c | 6 + 106 files changed, 76275 insertions(+), 119 deletions(-) diff --git a/.gitignore b/.gitignore index 81bbc1d..e8a2860 100644 --- a/.gitignore +++ b/.gitignore @@ -1593,9 +1593,12 @@ /none/tests/mips32/.deps /none/tests/mips32/allexec /none/tests/mips32/block_size +/none/tests/mips32/branch_pc /none/tests/mips32/branches +/none/tests/mips32/branches_r6 /none/tests/mips32/bug320057-mips32 /none/tests/mips32/change_fp_mode +/none/tests/mips32/fp_r6 /none/tests/mips32/fpu_branches /none/tests/mips32/FPUarithmetic /none/tests/mips32/LoadStore @@ -1603,6 +1606,7 @@ /none/tests/mips32/mips32_dsp /none/tests/mips32/mips32_dspr2 /none/tests/mips32/MIPS32int +/none/tests/mips32/MIPS32r6int /none/tests/mips32/MoveIns /none/tests/mips32/msa_arithmetic /none/tests/mips32/msa_comparison @@ -1611,6 +1615,7 @@ /none/tests/mips32/msa_logical_and_shift /none/tests/mips32/msa_shuffle /none/tests/mips32/LoadStore1 +/none/tests/mips32/pc_instructions_r6 /none/tests/mips32/round /none/tests/mips32/round_fpu64 /none/tests/mips32/SignalException @@ -1619,6 +1624,7 @@ /none/tests/mips32/unaligned_load_store /none/tests/mips32/vfp + # /none/tests/mips64/ /none/tests/mips64/Makefile /none/tests/mips64/Makefile.in diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c index 39fe715..a39930f 100644 --- a/none/tests/libvex_test.c +++ b/none/tests/libvex_test.c @@ -126,8 +126,13 @@ static UInt arch_hwcaps (VexArch va) { case VexArchPPC32: return 0; case VexArchPPC64: return 0; case VexArchS390X: return VEX_HWCAPS_S390X_LDISP; +#if (__mips_isa_rev>=6) + case VexArchMIPS32: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M32R6; + case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M64R6; +#else case VexArchMIPS32: return VEX_PRID_COMP_MIPS; case VexArchMIPS64: return VEX_PRID_COMP_MIPS; +#endif default: failure_exit(); } } diff --git a/none/tests/mips32/LoadStore.c b/none/tests/mips32/LoadStore.c index 38574ef..cd1e17c 100644 --- a/none/tests/mips32/LoadStore.c +++ b/none/tests/mips32/LoadStore.c @@ -223,6 +223,7 @@ int main() ppMem(mem1, 16); ppMem1(mem, 16); +#if (__mips_isa_rev < 6) printf("swl\n"); TESTINST1("swl $t0, 0($t1)", 0, 0, t0, t1); TESTINST1("swl $t0, 0($t1)", 0x31415927, 0, t0, t1); @@ -350,5 +351,6 @@ int main() ppMem0(mem2, 12); TESTINSTsw(0x2aaee700, 32, t0, t1); ppMem0(mem2, 12); +#endif return 0; } diff --git a/none/tests/mips32/LoadStore.stdout.exp-r6-BE b/none/tests/mips32/LoadStore.stdout.exp-r6-BE new file mode 100644 index 0000000..b57a0dc --- /dev/null +++ b/none/tests/mips32/LoadStore.stdout.exp-r6-BE @@ -0,0 +1,171 @@ +sb +sb $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x0, out: 0x1f1e1f +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f1e1f +sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff1f1e1f +sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x1f1e1f +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1f0000 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff03ffff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff00 +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff03 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f001f +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x1f001f +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000 +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f1f001f +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000 +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x711f001f +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000 +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf1f001f +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000 +sb $t0, 0($t1) :: RTval: 0x1, out: 0x11f001f +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x351f001f +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000 +sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff343f3e +sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff000000 +sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff353d3c +sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x273a3c3b +sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff373b3a +sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x4f4e45 +sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f000000 +sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f464d46 +MEM1: +0x3500ff00, 0xff00, 0xff00ff00, 0x0 +0x0, 0x0, 0x0, 0x0 +0xffffffff, 0xff000000, 0x27000000, 0xff000000 +0x0, 0x8f000000, 0x0, 0x0 +MEM: +0x351fff1f, 0xff00, 0xff00ff03, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0xff343f3e, 0xff353d3c, 0x273a3c3b, 0xff373b3a +0x4f4e45, 0x8f464d46, 0x474d474c, 0x4a484a4c +sh +sh $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x0, out: 0x1e1f +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59271e1f +sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff1e1f +sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x1e1f +sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000 +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000 +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff3f3e +sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff3d3c +sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59273c3b +sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff3b3a +sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x4e45 +sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f0000 +sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f4d46 +MEM1: +0x35ffff, 0xffff, 0xffffffff, 0x0 +0x0, 0x0, 0x0, 0x0 +0xffff0000, 0xffff0000, 0x59270000, 0xffff0000 +0x0, 0x28f0000, 0x0, 0x0 +MEM: +0x35ffff, 0xffff, 0xffffffff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0xffff3f3e, 0xffff3d3c, 0x59273c3b, 0xffff3b3a +0x4e45, 0x28f4d46, 0x474d474c, 0x4a484a4c +sw +sw $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f +MEM1: +0xffff, 0xffff7fff, 0xffffffff, 0xffff0000 +0x0, 0x0, 0x0, 0x0 +0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff +0x80000000, 0x28f, 0x0, 0x0 +MEM: +0xffff, 0xffff7fff, 0xffffffff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff +0x80000000, 0x28f, 0x474d474c, 0x4a484a4c diff --git a/none/tests/mips32/LoadStore.stdout.exp-r6-LE b/none/tests/mips32/LoadStore.stdout.exp-r6-LE new file mode 100644 index 0000000..b6275c8 --- /dev/null +++ b/none/tests/mips32/LoadStore.stdout.exp-r6-LE @@ -0,0 +1,171 @@ +sb +sb $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e00 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e27 +sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1eff +sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e00 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1200 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x300ff +sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff00ff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x12001e27 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x12001e00 +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x12001e8f +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71 +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x12001e71 +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf +sb $t0, 0($t1) :: RTval: 0xf, out: 0x12001e0f +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sb $t0, 0($t1) :: RTval: 0x1, out: 0x12001e01 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x12001e35 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff +sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343fff +sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff +sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353dff +sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c27 +sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373bff +sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e00 +sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f +sb $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d8f +MEM1: +0xff0035, 0xff0000, 0xff00ff, 0x0 +0x0, 0x0, 0x0, 0x0 +0xffffffff, 0xff, 0x27, 0xff +0x0, 0x8f, 0x0, 0x0 +MEM: +0x12ff1e35, 0xff0000, 0xff00ff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0x3f343fff, 0x3e353dff, 0x363a3c27, 0x3b373bff +0x454f4e00, 0x4e464d8f, 0x474d474c, 0x4a484a4c +sh +sh $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x0, out: 0x121f0000 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f5927 +sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121fffff +sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f0000 +sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff +sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71 +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf +sh $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f34ffff +sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e35ffff +sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a5927 +sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b37ffff +sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f0000 +sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f +sh $t0, 52($t1) :: RTval: 0x28f, out: 0x4e46028f +MEM1: +0xffff0035, 0xffff0000, 0xffffffff, 0x0 +0x0, 0x0, 0x0, 0x0 +0xffff, 0xffff, 0x5927, 0xffff +0x0, 0x28f, 0x0, 0x0 +MEM: +0xffff0035, 0xffff0000, 0xffffffff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0x3f34ffff, 0x3e35ffff, 0x363a5927, 0x3b37ffff +0x454f0000, 0x4e46028f, 0x474d474c, 0x4a484a4c +sw +sw $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 0($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f +MEM1: +0xffff0035, 0xffffffff, 0xffffffff, 0x7fff +0x0, 0x0, 0x0, 0x0 +0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff +0x80000000, 0x28f, 0x0, 0x0 +MEM: +0xffff0035, 0xffffffff, 0xffffffff, 0xffff7fff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a +0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff +0x80000000, 0x28f, 0x474d474c, 0x4a484a4c diff --git a/none/tests/mips32/LoadStore1.c b/none/tests/mips32/LoadStore1.c index 6a54303..c2da240 100644 --- a/none/tests/mips32/LoadStore1.c +++ b/none/tests/mips32/LoadStore1.c @@ -223,6 +223,7 @@ int main() ppMem(mem1, 16); ppMem1(mem, 16); +#if (__mips_isa_rev < 6) printf("swl\n"); TESTINST1("swl $t0, 1($t1)", 0, 1, t0, t1); TESTINST1("swl $t0, 3($t1)", 0x31415927, 3, t0, t1); @@ -350,6 +351,7 @@ int main() ppMem0(mem2, 12); TESTINSTsw(0x2aaee700, 32, t0, t1); ppMem0(mem2, 12); +#endif return 0; } diff --git a/none/tests/mips32/LoadStore1.stdout.exp-r6-BE b/none/tests/mips32/LoadStore1.stdout.exp-r6-BE new file mode 100644 index 0000000..da77746 --- /dev/null +++ b/none/tests/mips32/LoadStore1.stdout.exp-r6-BE @@ -0,0 +1,171 @@ +sb +sb $t0, 3($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 3($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1e0000 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000 +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000 +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000 +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000 +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000 +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000 +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000 +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027 +sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff3f343f +sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff000000 +sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff3e353d +sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27000000 +sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x273c3b3b +sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff000000 +sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff3b3b37 +sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x3b3a45 +sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f000000 +sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f4e464d +MEM1: +0x3500ff00, 0x27ffff, 0xff0000ff, 0x0 +0x0, 0x0, 0x0, 0xff +0xffffffff, 0x0, 0x27ff00, 0x0 +0x8f, 0x0, 0x0, 0x0 +MEM: +0x3500ff00, 0x27ffff, 0xff0000ff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff +0x3f343fff, 0x3e353d3c, 0x3627ff3b, 0x3b003b3a +0x454f4e8f, 0x4e464d46, 0x474d474c, 0x4a484a4c +sh +sh $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sh $t0, 1($t1) :: RTval: 0x0, out: 0x1f00 +sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x3ff +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059 +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059 +sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff +sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff343f +sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff0000 +sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff353d +sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59270000 +sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59273b3b +sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff0000 +sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff4f4e +sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x454e +sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f0000 +sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f464d +MEM1: +0x35ffff, 0x27ffffff, 0xffff00ff, 0xff000000 +0x0, 0x0, 0x0, 0xff +0xff0000ff, 0xff000000, 0x592700, 0xff +0xff000002, 0x8f000000, 0x0, 0x0 +MEM: +0x35ffff, 0x27ffffff, 0xffff00ff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff +0xff343fff, 0xff353d3c, 0x3659273b, 0x3b373bff +0xff000002, 0x8f464d46, 0x474d474c, 0x4a484a4c +sw +sw $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x0 +sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f +MEM1: +0xffff, 0xffff7fff, 0xffffffff, 0x7f +0xffffff00, 0x0, 0x0, 0xff +0xffffff00, 0xffffff, 0xff7fff80, 0x0 +0x314100, 0x28f00, 0x0, 0x0 +MEM: +0xffff, 0xffff7fff, 0xffffffff, 0xffff7f +0xffffff2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff +0xffffff3e, 0x3effffff, 0xff7fff80, 0x3a +0x45314100, 0x28f46, 0x474d474c, 0x4a484a4c diff --git a/none/tests/mips32/LoadStore1.stdout.exp-r6-LE b/none/tests/mips32/LoadStore1.stdout.exp-r6-LE new file mode 100644 index 0000000..01e2e03 --- /dev/null +++ b/none/tests/mips32/LoadStore1.stdout.exp-r6-LE @@ -0,0 +1,171 @@ +sb +sb $t0, 3($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 3($t1) :: RTval: 0x0, out: 0x0 +sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027 +sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff +sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000 +sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000 +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff +sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff +sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff +sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0 +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f +sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71 +sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71 +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf +sb $t0, 0($t1) :: RTval: 0xf, out: 0xf +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sb $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sb $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff +sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff +sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343f3eff +sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff +sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353d3cff +sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27 +sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a363a27 +sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff +sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0x3b3a36ff +sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0 +sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x453b3700 +sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f +sb $t0, 51($t1) :: RTval: 0x28f, out: 0x464d468f +MEM1: +0xff0035, 0xffff2700, 0xff0000ff, 0x0 +0x0, 0x0, 0x0, 0xff000000 +0xffffffff, 0x0, 0xff2700, 0x0 +0x8f000000, 0x0, 0x0, 0x0 +MEM: +0xff0035, 0xffff2700, 0xff0000ff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a +0xff343f3e, 0x3e353d3c, 0x36ff273b, 0x3b37003a +0x8f4f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c +sh +sh $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sh $t0, 1($t1) :: RTval: 0x0, out: 0x120000 +sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x300ffff +sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000000 +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff +sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927 +sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000 +sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000 +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f +sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71 +sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71 +sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f +sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f +sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001 +sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035 +sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035 +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff +sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff +sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343fffff +sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff +sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353dffff +sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x5927 +sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a365927 +sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff +sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0x4f4effff +sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0 +sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x46450000 +sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f +sh $t0, 51($t1) :: RTval: 0x28f, out: 0x464d028f +MEM1: +0xffff0035, 0xffffff59, 0xff00ffff, 0xff +0x0, 0x0, 0x0, 0xff000000 +0xff0000ff, 0xff, 0x592700, 0xff000000 +0x8f0000ff, 0x2, 0x0, 0x0 +MEM: +0xffff0035, 0xffffff59, 0xff00ffff, 0xffffffff +0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a +0xff343fff, 0x3e353dff, 0x3659273b, 0xff373b3a +0x8f0000ff, 0x4e464d02, 0x474d474c, 0x4a484a4c +sw +sw $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 1($t1) :: RTval: 0x0, out: 0x0 +sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x8000 +sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff8000 +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000 +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71 +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0xf, out: 0xf +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x1, out: 0x1 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 0($t1) :: RTval: 0x35, out: 0x35 +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff +sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927 +sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff +sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000 +sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f +sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f +MEM1: +0xffff0035, 0xffffffff, 0xffffffff, 0xff000080 +0x7fffff, 0x0, 0x0, 0xff000000 +0xffffff, 0xffffff00, 0xffffff, 0x800000 +0x8f592700, 0x2, 0x0, 0x0 +MEM: +0xffff0035, 0xffffffff, 0xffffffff, 0xffffff80 +0x237fffff, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a +0x3fffffff, 0xffffff3c, 0xffffff, 0x3b800000 +0x8f592745, 0x4e000002, 0x474d474c, 0x4a484a4c diff --git a/none/tests/mips32/MIPS32int.c b/none/tests/mips32/MIPS32int.c index 02d0815..e6f3b59 100644 --- a/none/tests/mips32/MIPS32int.c +++ b/none/tests/mips32/MIPS32int.c @@ -143,6 +143,7 @@ int main(int argc, char **argv) TESTINST1("add $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2); TESTINST1("add $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2); +#if (__mips_isa_rev < 6) printf("ADDI\n"); TESTINST2("addi $t0, $t1, 0", 0, 0, t0, t1); TESTINST2("addi $t0, $t1, 1", 0, 1, t0, t1); @@ -153,6 +154,7 @@ int main(int argc, char **argv) TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1); TESTINST2("addi $t0, $t1, 0", -1, 0, t0, t1); TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1); +#endif printf("ADDIU\n"); TESTINST2("addiu $t0, $t1, 0", 0, 0, t0, t1); @@ -234,6 +236,7 @@ int main(int argc, char **argv) TESTINST3("clz $t0, $t1", 0x10, t0, t1); TESTINST3("clz $t0, $t1", 0xffffffff, t0, t1); +#if (__mips_isa_rev < 6) printf("DIV\n"); TESTINST3a("div $t0, $t1", 0x6, 0x2, t0, t1); TESTINST3a("div $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1); @@ -248,6 +251,7 @@ int main(int argc, char **argv) TESTINST3a("divu $t0, $t1", 0x1, 0xffffffff, t0, t1); TESTINST3a("divu $t0, $t1", 0x2, 0x6, t0, t1); TESTINST3a("divu $t0, $t1", 0x0, 0x2, t0, t1); +#endif #if (__mips==32) && (__mips_isa_rev>=2) printf("EXT\n"); @@ -797,6 +801,7 @@ int main(int argc, char **argv) TESTINSN5LOAD("lw $t0, 34($t1)", 0, 34, t0); TESTINSN5LOAD("lw $t0, 38($t1)", 0, 38, t0); +#if (__mips_isa_rev < 6) printf("LWL\n"); TESTINSN5LOAD("lwl $t0, 3($t1)", 0, 3, t0); TESTINSN5LOAD("lwl $t0, 6($t1)", 0, 6, t0); @@ -959,6 +964,7 @@ int main(int argc, char **argv) TESTINST3a("msubu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1); TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1); TESTINST3a("msubu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1); +#endif printf("MUL\n"); TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2); @@ -993,6 +999,7 @@ int main(int argc, char **argv) TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2); TESTINST1("mul $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2); +#if (__mips_isa_rev < 6) printf("MULT\n"); TESTINST3a("mult $t0, $t1", 0x31415927, 0xffffffff, t0, t1); TESTINST3a("mult $t0, $t1", 0x31415927, 0xee00ee00, t0, t1); @@ -1058,6 +1065,7 @@ int main(int argc, char **argv) TESTINST3a("multu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1); TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1); TESTINST3a("multu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1); +#endif printf("NOR\n"); TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2); @@ -1763,6 +1771,7 @@ int main(int argc, char **argv) TESTINST2("xori $t0, $t1, 0x7fff", 0x7fffffff, 0x7fff, t0, t1); TESTINST2("xori $t0, $t1, 0x0000", 0x0000ffff, 0x0000, t0, t1); +#if (__mips_isa_rev < 6) printf("MFHI MFLO\n"); TESTINSN_HILO(0x31415927); TESTINSN_HILO(0); @@ -1774,6 +1783,7 @@ int main(int argc, char **argv) TESTINSN_HILO(0x7fff); TESTINSN_HILO(0x0dd0); TESTINSN_HILO(0xff00); +#endif return 0; } diff --git a/none/tests/mips32/MIPS32int.stdout.exp-mips32r6-BE b/none/tests/mips32/MIPS32int.stdout.exp-mips32r6-BE new file mode 100644 index 0000000..a1428fa --- /dev/null +++ b/none/tests/mips32/MIPS32int.stdout.exp-mips32r6-BE @@ -0,0 +1,1325 @@ +ADD +add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 +add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 +add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 +add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 +add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff +add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff +add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 +add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 +add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 +add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 +add $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000 +add $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000 +ADDIU +addiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000 +addiu $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001 +addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000 +addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001 +addiu $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff +addiu $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff +addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000 +addiu $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000 +addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000 +ADDU +addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 +addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001 +addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff +addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff +addu $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728 +addu $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728 +addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001 +addu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff +addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000 +addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000 +addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000 +addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000 +addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0x7fffffff +addu $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff +AND +and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff +and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff +and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000 +and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000 +and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff +and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000 +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000 +and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000 +and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000 +ANDI +andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001 +andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000 +andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001 +andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000 +andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000 +andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145 +CLO +clo $t0, $t1 :: rd 0x00000000 rs 0x00000000 +clo $t0, $t1 :: rd 0x00000000 rs 0x00000001 +clo $t0, $t1 :: rd 0x00000000 rs 0x00000010 +clo $t0, $t1 :: rd 0x00000020 rs 0xffffffff +CLZ +clz $t0, $t1 :: rd 0x00000020 rs 0x00000000 +clz $t0, $t1 :: rd 0x0000001f rs 0x00000001 +clz $t0, $t1 :: rd 0x0000001b rs 0x00000010 +clz $t0, $t1 :: rd 0x00000000 rs 0xffffffff +EXT +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x98765432, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x98765432, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x98765432, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000000 rs 0x98765432, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 1 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000001 +ext $t0, $t1, 0, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000002 rs 0x98765432, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000002 rs 0x98765432, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000002 rs 0x98765432, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000002 rs 0x98765432, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 4 :: rt 0x00000001 rs 0xff865421, pos 0x00000000, size 0x00000004 +ext $t0, $t1, 0, 16 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x0000ffff rs 0xffffffff, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005432 rs 0x98765432, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005421 rs 0xff865421, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x0000ffff rs 0xffffffff, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005432 rs 0x98765432, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005421 rs 0xff865421, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x0000ffff rs 0xffffffff, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005432 rs 0x98765432, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005421 rs 0xff865421, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x0000ffff rs 0xffffffff, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005432 rs 0x98765432, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 16 :: rt 0x00005421 rs 0xff865421, pos 0x00000000, size 0x00000010 +ext $t0, $t1, 0, 32 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xffffffff rs 0xffffffff, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x98765432 rs 0x98765432, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xff865421 rs 0xff865421, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xffffffff rs 0xffffffff, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x98765432 rs 0x98765432, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xff865421 rs 0xff865421, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xffffffff rs 0xffffffff, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x98765432 rs 0x98765432, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xff865421 rs 0xff865421, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x00000000 rs 0x00000000, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xffffffff rs 0xffffffff, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0x98765432 rs 0x98765432, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 0, 32 :: rt 0xff865421 rs 0xff865421, pos 0x00000000, size 0x00000020 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0x98765432, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0xff865421, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0x98765432, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0xff865421, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0x98765432, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0xff865421, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0xffffffff, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000001 rs 0x98765432, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 1 :: rt 0x00000000 rs 0xff865421, pos 0x00000004, size 0x00000001 +ext $t0, $t1, 4, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000003 rs 0x98765432, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000002 rs 0xff865421, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000003 rs 0x98765432, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000002 rs 0xff865421, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x00000000 rs 0x00000000, pos 0x00000004, size 0x00000004 +ext $t0, $t1, 4, 4 :: rt 0x0000000f rs 0xffffffff, pos 0x00000004, size 0x0... [truncated message content] |
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From: Petar J. <pe...@so...> - 2018-02-01 18:06:27
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bc770c08c88eff826af74e5b26f2b06cc563d2be commit bc770c08c88eff826af74e5b26f2b06cc563d2be Author: Petar Jovanovic <mip...@gm...> Date: Thu Feb 1 18:57:00 2018 +0100 mips: update NEWS about MIPS32/64 Revision 6 support Spread the word about MIPS Rev6 support. Related BZ issue - #387410. Diff: --- NEWS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/NEWS b/NEWS index ee853d5..4bdffbc 100644 --- a/NEWS +++ b/NEWS @@ -22,6 +22,7 @@ support for X86/macOS 10.13, AMD64/macOS 10.13. * ================== PLATFORM CHANGES ================= * Preliminary support for macOS 10.13 has been added. +* mips: support for MIPS32/MIPS64 Revision 6 has been added. * mips: support for MIPS SIMD architecture (MSA) has been added. * ==================== TOOL CHANGES ==================== @@ -84,6 +85,7 @@ where XXXXXX is the bug number as listed below. 385912 none/tests/rlimit_nofile fails on newer glibc/kernel. 385939 Optionally exit on the first error 386397 PPC64, valgrind truncates powerpc timebase to 32-bits. +387410 MIPSr6 support 387712 s390x cgijnl reports Conditional jump depends on uninitialised value 387773 .gnu_debugaltlink paths resolve relative to .debug file, not symlink 389065 valgrind meets gcc flag -Wlogical-op |
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From: Petar J. <pe...@so...> - 2018-02-01 18:06:20
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6e7f9c9ef405e8d5289fbb6d960e220311ebe110 commit 6e7f9c9ef405e8d5289fbb6d960e220311ebe110 Author: Petar Jovanovic <mip...@gm...> Date: Thu Feb 1 18:19:24 2018 +0100 mips: add support for mips32/mips64 R6 to VEX Full support of MIPS R6 instruction set. Special implementation for MIPS R6 has been added for following IOPs: Iop_Max32U, Iop_Mul32, Iop_Mul64, Iop_MullS32, Iop_MullU32, Iop_MullU8, Iop_MullS8, Iop_MullU16, Iop_MullS16, Iop_CmpF64, Iop_DivModU32to32, Iop_DivModS32to32, Iop_DivS32, Iop_DivU32, Iop_DivS64, Iop_DivU64, Iop_MullU64, Iop_MullS64, Iop_DivModU64to64, Iop_DivModS64to64, Iop_Shr64, Iop_Shl64, Iop_Sar64, Iop_RoundF32toInt, Iop_RoundF64toInt, Iop_MAddF32, Iop_MAddF64, Iop_MSubF32, Iop_MSubF64 Following IOPs have been implemented using MIPS R6 instructions: Iop_MaxNumF32, Iop_MaxNumF64 Iop_MinNumF32, Iop_MinNumF64, Iop_CmpF32, Iop_Rotx32, Iop_Rotx64 Following IOPs have been implemented without using MIPS R6 instructions: Iop_F64toI64S, Iop_F32toI32S, Iop_I64StoF64. Part of MIPS32/64 Revision 6 changes. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410. Diff: --- VEX/priv/guest_mips_defs.h | 6 +- VEX/priv/guest_mips_helpers.c | 45 + VEX/priv/guest_mips_toIR.c | 2989 ++++++++++++++++++++++++++++++++++++----- VEX/priv/host_mips_defs.c | 512 ++++++- VEX/priv/host_mips_defs.h | 65 +- VEX/priv/host_mips_isel.c | 775 ++++++++--- VEX/pub/libvex.h | 8 +- VEX/pub/libvex_guest_mips32.h | 10 +- 8 files changed, 3833 insertions(+), 577 deletions(-) diff --git a/VEX/priv/guest_mips_defs.h b/VEX/priv/guest_mips_defs.h index 6ee6728..bbdbc4d 100644 --- a/VEX/priv/guest_mips_defs.h +++ b/VEX/priv/guest_mips_defs.h @@ -91,7 +91,11 @@ typedef enum { CVTDS, CVTDW, CVTSD, CVTSW, CVTWS, CVTWD, CVTDL, CVTLS, CVTLD, CVTSL, ADDS, ADDD, - SUBS, SUBD, DIVS + SUBS, SUBD, DIVS, + RINTS, RINTD, + MAXS, MAXD, MINS, MIND, + MAXAS, MAXAD, MINAS, MINAD, + CMPAFS, CMPAFD, CMPSAFS, CMPSAFD, } flt_op; typedef enum { diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c index 3f21512..4f74593 100644 --- a/VEX/priv/guest_mips_helpers.c +++ b/VEX/priv/guest_mips_helpers.c @@ -172,6 +172,7 @@ void LibVEX_GuestMIPS32_initialise( /*OUT*/ VexGuestMIPS32State * vex_state) vex_state->guest_COND = 0; vex_state->guest_CP0_status = 0; + vex_state->guest_CP0_Config5 = 0; vex_state->guest_LLaddr = 0xFFFFFFFF; vex_state->guest_LLdata = 0; @@ -812,6 +813,50 @@ extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* gs, UInt fs, UInt ft, case DIVS: ASM_VOLATILE_BINARY64(div.s) break; +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) + case RINTS: + ASM_VOLATILE_UNARY64(rint.s) + break; + case RINTD: + ASM_VOLATILE_UNARY64(rint.d) + break; + case MAXS: + ASM_VOLATILE_BINARY64(max.s) + break; + case MAXD: + ASM_VOLATILE_BINARY64(max.d) + break; + case MINS: + ASM_VOLATILE_BINARY64(min.s) + break; + case MIND: + ASM_VOLATILE_BINARY64(min.d) + break; + case MAXAS: + ASM_VOLATILE_BINARY64(maxa.s) + break; + case MAXAD: + ASM_VOLATILE_BINARY64(maxa.d) + break; + case MINAS: + ASM_VOLATILE_BINARY64(mina.s) + break; + case MINAD: + ASM_VOLATILE_BINARY64(mina.d) + break; + case CMPAFS: + ASM_VOLATILE_BINARY64(cmp.af.s) + break; + case CMPAFD: + ASM_VOLATILE_BINARY64(cmp.af.d) + break; + case CMPSAFS: + ASM_VOLATILE_BINARY64(cmp.saf.s) + break; + case CMPSAFD: + ASM_VOLATILE_BINARY64(cmp.saf.d) + break; +#endif default: vassert(0); break; diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index 0063ae3..8421126 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -75,6 +75,9 @@ static Bool mode64 = False; /* CPU has FPU and 32 dbl. prec. FP registers. */ static Bool fp_mode64 = False; +/* FPU works in FRE mode */ +static Bool fp_mode64_fre = False; + /* CPU has MSA unit */ static Bool has_msa = False; @@ -1076,6 +1079,17 @@ static Bool branch_or_jump(const UChar * addr) if (fmt == 0x0b) { return True; } + + /* R6 branches */ + /* bc1eqz */ + if (fmt == 0x09) { + return True; + } + + /* bc1nez */ + if (fmt == 0x0D) { + return True; + } } /* bposge32 */ @@ -1105,7 +1119,7 @@ static Bool is_Branch_or_Jump_and_Link(const UChar * addr) return True; } - /* bgezal */ + /* bgezal or bal(r6) */ if (opcode == 0x01 && rt == 0x11) { return True; } @@ -1265,6 +1279,12 @@ static IRExpr *genRORV32(IRExpr * src, IRExpr * rs) binop(Iop_Shr32, src, mkexpr(t0))); } + +static UShort extend_s_9to16(UInt x) +{ + return (UShort) ((((Int) x) << 23) >> 23); +} + static UShort extend_s_10to16(UInt x) { return (UShort) ((((Int) x) << 22) >> 22); @@ -1290,6 +1310,21 @@ static UInt extend_s_18to32(UInt x) return (UInt) ((((Int) x) << 14) >> 14); } +static UInt extend_s_19to32(UInt x) +{ + return (UInt) ((((Int) x) << 13) >> 13); +} + +static UInt extend_s_23to32(UInt x) +{ + return (UInt) ((((Int) x) << 9) >> 9); +} + +static UInt extend_s_26to32(UInt x) +{ + return (UInt) ((((Int) x) << 6) >> 6); +} + static ULong extend_s_16to64 ( UInt x ) { return (ULong) ((((Long) x) << 48) >> 48); @@ -1300,6 +1335,21 @@ static ULong extend_s_18to64 ( UInt x ) return (ULong) ((((Long) x) << 46) >> 46); } +static ULong extend_s_19to64(UInt x) +{ + return (ULong) ((((Long) x) << 45) >> 45); +} + +static ULong extend_s_23to64(UInt x) +{ + return (ULong) ((((Long) x) << 41) >> 41); +} + +static ULong extend_s_26to64(UInt x) +{ + return (ULong) ((((Long) x) << 38) >> 38); +} + static ULong extend_s_32to64 ( UInt x ) { return (ULong) ((((Long) x) << 32) >> 32); @@ -1757,6 +1807,13 @@ static IRExpr *getLoFromF64(IRType ty, IRExpr * src) return src; } +static inline IRExpr *getHiFromF64(IRExpr * src) +{ + vassert(typeOfIRExpr(irsb->tyenv, src) == Ity_F64); + return unop(Iop_ReinterpI32asF32, unop(Iop_64HIto32, + unop(Iop_ReinterpF64asI64, src))); +} + static IRExpr *mkWidenFromF32(IRType ty, IRExpr * src) { vassert(ty == Ity_F32 || ty == Ity_F64); @@ -1848,6 +1905,51 @@ static void dis_branch(Bool link, IRExpr * guard, UInt imm, IRStmt ** set) (UInt) branch_offset), OFFB_PC); } +static void dis_branch_compact(Bool link, IRExpr * guard, UInt imm, + DisResult *dres) +{ + ULong branch_offset; + IRTemp t0; + + if (link) { /* LR (GPR31) = addr of the instr after branch instr */ + if (mode64) + putIReg(31, mkU64(guest_PC_curr_instr + 4)); + else + putIReg(31, mkU32(guest_PC_curr_instr + 4)); + dres->jk_StopHere = Ijk_Call; + } else { + dres->jk_StopHere = Ijk_Boring; + } + + dres->whatNext = Dis_StopHere; + + /* PC = PC + (SignExtend(signed_immed_24) << 2) + An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) + is added to the address of the instruction following + the branch (not the branch itself), in the branch delay slot, to form + a PC-relative effective target address. */ + + if (mode64) + branch_offset = extend_s_18to64(imm << 2); + else + branch_offset = extend_s_18to32(imm << 2); + + t0 = newTemp(Ity_I1); + assign(t0, guard); + + if (mode64) { + stmt(IRStmt_Exit(mkexpr(t0), link ? Ijk_Call : Ijk_Boring, + IRConst_U64(guest_PC_curr_instr + 4 + branch_offset), + OFFB_PC)); + putPC(mkU64(guest_PC_curr_instr + 4)); + } else { + stmt(IRStmt_Exit(mkexpr(t0), link ? Ijk_Call : Ijk_Boring, + IRConst_U32(guest_PC_curr_instr + 4 + + (UInt) branch_offset), OFFB_PC)); + putPC(mkU32(guest_PC_curr_instr + 4)); + } +} + static IRExpr *getFReg(UInt fregNo) { vassert(fregNo < 32); @@ -1887,11 +1989,28 @@ static void putFReg(UInt dregNo, IRExpr * e) vassert(dregNo < 32); IRType ty = fp_mode64 ? Ity_F64 : Ity_F32; vassert(typeOfIRExpr(irsb->tyenv, e) == ty); - stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e)); + + if (fp_mode64_fre) { + IRTemp t0 = newTemp(Ity_F32); + assign(t0, getLoFromF64(ty, e)); +#if defined (_MIPSEL) + stmt(IRStmt_Put(floatGuestRegOffset(dregNo), mkexpr(t0))); + if (dregNo & 1) + stmt(IRStmt_Put(floatGuestRegOffset(dregNo) - 4, mkexpr(t0))); +#else + stmt(IRStmt_Put(floatGuestRegOffset(dregNo) + 4, mkexpr(t0))); + if (dregNo & 1) + stmt(IRStmt_Put(floatGuestRegOffset(dregNo & (~1)), mkexpr(t0))); +#endif + } else { + stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e)); + } + if (has_msa && fp_mode64) { stmt(IRStmt_Put(msaGuestRegOffset(dregNo), binop(Iop_64HLtoV128, - mkU64(0), unop(Iop_ReinterpF64asI64, e)))); + unop(Iop_ReinterpF64asI64, e), + unop(Iop_ReinterpF64asI64, e)))); } } @@ -1902,10 +2021,29 @@ static void putDReg(UInt dregNo, IRExpr * e) IRType ty = Ity_F64; vassert(typeOfIRExpr(irsb->tyenv, e) == ty); stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e)); + if (fp_mode64_fre) { + IRTemp t0 = newTemp(Ity_F32); + if (dregNo & 1) { + assign(t0, getLoFromF64(ty, e)); +#if defined (_MIPSEL) + stmt(IRStmt_Put(floatGuestRegOffset(dregNo) - 4, mkexpr(t0))); +#else + stmt(IRStmt_Put(floatGuestRegOffset(dregNo & (~1)), mkexpr(t0))); +#endif + } else { + assign(t0, getHiFromF64(e)); +#if defined (_MIPSEL) + stmt(IRStmt_Put(floatGuestRegOffset(dregNo | 1), mkexpr(t0))); +#else + stmt(IRStmt_Put(floatGuestRegOffset(dregNo | 1) + 4, mkexpr(t0))); +#endif + } + } if (has_msa) stmt(IRStmt_Put(msaGuestRegOffset(dregNo), binop(Iop_64HLtoV128, - mkU64(0), unop(Iop_ReinterpF64asI64, e)))); + unop(Iop_ReinterpF64asI64, e), + unop(Iop_ReinterpF64asI64, e)))); } else { vassert(dregNo < 32); vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); @@ -24645,19 +24783,13 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ mkU64(0xC3E0000000000000), mkU64(0xC3E0000000000000))))); assign(t1, - unop(Iop_ReinterpF64asI64, - binop(Iop_RoundF64toInt, - mkU32(0x3), - unop(Iop_ReinterpI64asF64, - unop(Iop_V128to64, - mkexpr(t3)))))); + binop(Iop_F64toI64S, mkU32(0x3), + unop(Iop_ReinterpI64asF64, + unop(Iop_V128to64, mkexpr(t3))))); assign(t2, - unop(Iop_ReinterpF64asI64, - binop(Iop_RoundF64toInt, - mkU32(0x3), - unop(Iop_ReinterpI64asF64, - unop(Iop_V128HIto64, - mkexpr(t3)))))); + binop(Iop_F64toI64S, mkU32(0x3), + unop(Iop_ReinterpI64asF64, + unop(Iop_V128HIto64, mkexpr(t3))))); putWReg(wd, binop(Iop_64HLtoV128, mkexpr(t2), mkexpr(t1))); @@ -24825,13 +24957,10 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ tmp[i] = newTemp(Ity_I32); assign(tmp[i], unop(Iop_ReinterpF32asI32, - binop(Iop_I32StoF32, rm, - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - mkexpr(t1), - mkU8(i)))))))); + binop(Iop_RoundF32toInt, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + mkexpr(t1), mkU8(i)))))); } putWReg(wd, @@ -24909,13 +25038,10 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ tmp[i] = newTemp(Ity_I64); assign(tmp[i], unop(Iop_ReinterpF64asI64, - binop(Iop_I64StoF64, rm, - unop(Iop_ReinterpF64asI64, - binop(Iop_RoundF64toInt, rm, - unop(Iop_ReinterpI64asF64, - binop(Iop_GetElem64x2, - mkexpr(t1), - mkU8(i)))))))); + binop(Iop_RoundF64toInt, rm, + unop(Iop_ReinterpI64asF64, + binop(Iop_GetElem64x2, + mkexpr(t1), mkU8(i)))))); } putWReg(wd, @@ -25274,32 +25400,24 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ IRExpr *rm = get_IR_roundingmode_MSA(); assign(t1, binop(Iop_32HLto64, - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - mkexpr(t3), - mkU8(1))))), - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - mkexpr(t3), - mkU8(0))))))); + binop(Iop_F32toI32S, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + mkexpr(t3), mkU8(1)))), + binop(Iop_F32toI32S, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + mkexpr(t3), mkU8(0)))))); assign(t2, binop(Iop_32HLto64, - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - mkexpr(t3), - mkU8(3))))), - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - mkexpr(t3), - mkU8(2))))))); + binop(Iop_F32toI32S, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + mkexpr(t3), mkU8(3)))), + binop(Iop_F32toI32S, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + mkexpr(t3), mkU8(2)))))); putWReg(wd, binop(Iop_64HLtoV128, mkexpr(t2), mkexpr(t1))); @@ -25325,17 +25443,13 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ mkU64(0xC3E0000000000000))))); IRExpr *rm = get_IR_roundingmode_MSA(); assign(t1, - unop(Iop_ReinterpF64asI64, - binop(Iop_RoundF64toInt, rm, - unop(Iop_ReinterpI64asF64, - unop(Iop_V128to64, - mkexpr(t3)))))); + binop(Iop_F64toI64S, rm, + unop(Iop_ReinterpI64asF64, + unop(Iop_V128to64, mkexpr(t3))))); assign(t2, - unop(Iop_ReinterpF64asI64, - binop(Iop_RoundF64toInt, rm, - unop(Iop_ReinterpI64asF64, - unop(Iop_V128HIto64, - mkexpr(t3)))))); + binop(Iop_F64toI64S, rm, + unop(Iop_ReinterpI64asF64, + unop(Iop_V128HIto64, mkexpr(t3))))); putWReg(wd, binop(Iop_64HLtoV128, mkexpr(t2), mkexpr(t1))); @@ -25361,32 +25475,24 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */ IRExpr *rm = get_IR_roundingmode_MSA(); assign(t1, binop(Iop_32HLto64, - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - getWReg(ws), - mkU8(1))))), - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - getWReg(ws), - mkU8(0))))))); + binop(Iop_F32toI32U, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + getWReg(ws), mkU8(1)))), + binop(Iop_F32toI32U, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + getWReg(ws), mkU8(0)))))); assign(t2, binop(Iop_32HLto64, - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - getWReg(ws), - mkU8(3))))), - unop(Iop_ReinterpF32asI32, - binop(Iop_RoundF32toInt, rm, - unop(Iop_ReinterpI32asF32, - binop(Iop_GetElem32x4, - getWReg(ws), - mkU8(2))))))); + binop(Iop_F32toI32U, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + getWReg(ws), mkU8(3)))), + binop(Iop_F32toI32U, rm, + unop(Iop_ReinterpI32asF32, + binop(Iop_GetElem32x4, + getWReg(ws), mkU8(2)))))); assign(t3, unop(Iop_NotV128, binop(Iop_SarN32x4, @@ -25991,39 +26097,39 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, case 0x11: { /* COP1 */ if (fmt == 0x3 && fd == 0 && function == 0) { /* MFHC1 */ DIP("mfhc1 r%u, f%u", rt, fs); - if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps)) { + if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps) || + VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { if (fp_mode64) { t0 = newTemp(Ity_I64); t1 = newTemp(Ity_I32); assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs))); assign(t1, unop(Iop_64HIto32, mkexpr(t0))); putIReg(rt, mkWidenFrom32(ty, mkexpr(t1), True)); - break; } else { putIReg(rt, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32, getFReg(fs | 1)), True)); - break; } + } else { + ILLEGAL_INSTRUCTON; } - ILLEGAL_INSTRUCTON; break; } else if (fmt == 0x7 && fd == 0 && function == 0) { /* MTHC1 */ DIP("mthc1 r%u, f%u", rt, fs); - if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps)) { + if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps) || + VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { if (fp_mode64) { t0 = newTemp(Ity_I64); assign(t0, binop(Iop_32HLto64, mkNarrowTo32(ty, getIReg(rt)), unop(Iop_ReinterpF32asI32, getLoFromF64(Ity_F64, getDReg(fs))))); putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0))); - break; } else { putFReg(fs | 1, unop(Iop_ReinterpI32asF32, mkNarrowTo32(ty, getIReg(rt)))); - break; } + } else { + ILLEGAL_INSTRUCTON; } - ILLEGAL_INSTRUCTON; break; } else if (fmt == 0x8) { /* BC */ /* FcConditionalCode(bc1_cc) */ @@ -26189,7 +26295,437 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, unop(Iop_V128HIto64, mkexpr(t1)))))); dis_branch(False, binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0)), imm, &bstmt); + } else if (fmt == 0x09) { /* BC1EQZ */ + if (VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { + DIP("bc1eqz f%u, %u", ft, imm); + t1 = newTemp(Ity_I1); + if (mode64) { + assign(t1, binop(Iop_CmpEQ64, + binop(Iop_And64, + unop(Iop_ReinterpF64asI64, getDReg(ft)), + mkU64(1)), + mkU64(0))); + } else { + assign(t1, binop(Iop_CmpEQ32, + binop(Iop_And32, + unop(Iop_64to32, + unop(Iop_ReinterpF64asI64, getDReg(ft))), + mkU32(1)), + mkU32(0))); + } + dis_branch(False, mkexpr(t1), imm, &bstmt); + } else { + ILLEGAL_INSTRUCTON; + } + } else if (fmt == 0x0D) { /* BC1NEZ */ + if (VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { + DIP("bc1nez f%u, %u", ft, imm); + t1 = newTemp(Ity_I1); + if (mode64) { + assign(t1, binop(Iop_CmpNE64, + binop(Iop_And64, + unop(Iop_ReinterpF64asI64, getDReg(ft)), + mkU64(1)), + mkU64(0))); + } else { + assign(t1, binop(Iop_CmpNE32, + binop(Iop_And32, + unop(Iop_64to32, + unop(Iop_ReinterpF64asI64, getDReg(ft))), + mkU32(1)), + mkU32(0))); + } + dis_branch(False, mkexpr(t1), imm, &bstmt); + } else { + ILLEGAL_INSTRUCTON; + } } else { + if (fmt == 0x15) { /* CMP.cond.d */ + Bool comparison = True; + UInt signaling = CMPAFD; + DIP("cmp.cond.d f%u, f%u, f%u, cond %u", fd, fs, ft, function); + t0 = newTemp(Ity_I32); + /* Conditions starting with S should signal exception on QNaN inputs. */ + switch (function) { + case 8: /* SAF */ + signaling = CMPSAFD; + case 0: /* AF */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0))); + break; + case 9: /* SUN */ + signaling = CMPSAFD; + case 1: /* UN */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x45)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)))); + break; + case 0x19: /* SOR */ + signaling = CMPSAFD; + case 0x11: /* OR */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x45)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)))); + break; + case 0xa: /* SEQ */ + signaling = CMPSAFD; + case 2: /* EQ */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)))); + break; + case 0x1A: /* SNEQ */ + signaling = CMPSAFD; + case 0x12: /* NEQ */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)))); + break; + case 0xB: /* SUEQ */ + signaling = CMPSAFD; + case 0x3: /* UEQ */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0), mkU32(0x45)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), + mkU64(0))))); + break; + case 0x1B: /* SNEQ */ + signaling = CMPSAFD; + case 0x13: /* NEQ */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0),mkU32(0x01)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0),mkU32(0x00)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), + mkU64(0))))); + break; + case 0xC: /* SLT */ + signaling = CMPSAFD; + case 0x4: /* LT */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x01)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)))); + break; + case 0xD: /* SULT */ + signaling = CMPSAFD; + case 0x5: /* ULT */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x01)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0), mkU32(0x45)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), + mkU64(0))))); + break; + case 0xE: /* SLE */ + signaling = CMPSAFD; + case 0x6: /* LE */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0),mkU32(0x01)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0),mkU32(0x40)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), + mkU64(0))))); + break; + case 0xF: /* SULE */ + signaling = CMPSAFD; + case 0x7: /* ULE */ + assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); + calculateFCSR(fs, ft, signaling, False, 2); + putDReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x0)), + binop(Iop_I64StoF64, + get_IR_roundingmode(), mkU64(0)), + unop(Iop_ReinterpI64asF64, + mkU64(0xFFFFFFFFFFFFFFFFULL)))); + break; + default: + comparison = False; + } + if (comparison) { + if (!VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { + ILLEGAL_INSTRUCTON; + } + break; + } + + } else if (fmt == 0x14) { + Bool comparison = True; + UInt signaling = CMPAFS; + DIP("cmp.cond.s f%u, f%u, f%u, cond %u", fd, fs, ft, function); + t0 = newTemp(Ity_I32); + /* Conditions starting with S should signal exception on QNaN inputs. */ + switch (function) { + case 8: /* SAF */ + signaling = CMPSAFS; + case 0: /* AF */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), mkU32(0)))); + break; + case 9: /* SUN */ + signaling = CMPSAFS; + case 1: /* UN */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x45)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))))); + break; + case 0x19: /* SOR */ + signaling = CMPSAFS; + case 0x11: /* OR */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x45)), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))))); + break; + case 0xa: /* SEQ */ + signaling = CMPSAFS; + case 2: /* EQ */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))))); + break; + case 0x1A: /* SNEQ */ + signaling = CMPSAFS; + case 0x12: /* NEQ */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))))); + break; + case 0xB: /* SUEQ */ + signaling = CMPSAFS; + case 0x3: /* UEQ */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x40)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0), mkU32(0x45)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0)))))); + break; + case 0x1B: /* SNEQ */ + signaling = CMPSAFS; + case 0x13: /* NEQ */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0),mkU32(0x01)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0),mkU32(0x00)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0)))))); + break; + case 0xC: /* SLT */ + signaling = CMPSAFS; + case 0x4: /* LT */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x01)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))))); + break; + case 0xD: /* SULT */ + signaling = CMPSAFS; + case 0x5: /* ULT */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x01)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0), mkU32(0x45)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0)))))); + break; + case 0xE: /* SLE */ + signaling = CMPSAFS; + case 0x6: /* LE */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0),mkU32(0x01)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + IRExpr_ITE(binop(Iop_CmpEQ32, + mkexpr(t0),mkU32(0x40)), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0)))))); + break; + case 0xF: /* SULE */ + signaling = CMPSAFS; + case 0x7: /* ULE */ + assign(t0, binop(Iop_CmpF32, + getLoFromF64(Ity_F64, getFReg(fs)), + getLoFromF64(Ity_F64, getFReg(ft)))); + calculateFCSR(fs, ft, signaling, True, 2); + putFReg(fd, + IRExpr_ITE(binop(Iop_CmpEQ32, mkexpr(t0), mkU32(0x0)), + mkWidenFromF32(tyF, + binop(Iop_I32StoF32, + get_IR_roundingmode(), + mkU32(0))), + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + mkU32(0xFFFFFFFFU))))); + break; + default: + comparison = False; + } + if (comparison) { + if (!VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { + ILLEGAL_INSTRUCTON; + } + break; + } + } + switch (function) { case 0x4: { /* SQRT.fmt */ switch (fmt) { @@ -26350,8 +26886,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, DIP("round.l.d f%u, f%u", fd, fs); if (fp_mode64) { calculateFCSR(fs, 0, ROUNDLD, False, 1); - putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x0), - getDReg(fs))); + putDReg(fd, unop(Iop_ReinterpI64asF64, + binop(Iop_F64toI64S, + mkU32(0x0), + getDReg(fs)))); } else { ILLEGAL_INSTRUCTON; } @@ -26381,8 +26919,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, DIP("trunc.l.d f%u, f%u", fd, fs); if (fp_mode64) { calculateFCSR(fs, 0, TRUNCLD, False, 1); - putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x3), - getDReg(fs))); + putDReg(fd, unop(Iop_ReinterpI64asF64, + binop(Iop_F64toI64S, + mkU32(0x3), + getDReg(fs)))); } else { ILLEGAL_INSTRUCTON; } @@ -26923,10 +27463,11 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, calculateFCSR(fs, 0, CVTWS, True, 1); putFReg(fd, mkWidenFromF32(tyF, - binop(Iop_RoundF32toInt, - get_IR_roundingmode(), - getLoFromF64(tyF, getFReg(fs)))) - ); + unop(Iop_ReinterpI32asF32, + binop(Iop_F32toI32S, + get_IR_roundingmode(), + getLoFromF64(tyF, + getFReg(fs)))))); break; case 0x11: @@ -26967,8 +27508,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, DIP("cvt.l.d %u, %u", fd, fs); if (fp_mode64) { calculateFCSR(fs, 0, CVTLD, False, 1); - putDReg(fd, binop(Iop_RoundF64toInt, - get_IR_roundingmode(), getDReg(fs))); + putDReg(fd, unop(Iop_ReinterpI64asF64, + binop(Iop_F64toI64S, + get_IR_roundingmode(), + getDReg(fs)))); } else { ILLEGAL_INSTRUCTON; } @@ -27001,8 +27544,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, DIP("floor.l.d %u, %u", fd, fs); if (fp_mode64) { calculateFCSR(fs, 0, FLOORLD, False, 1); - putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x1), - getDReg(fs))); + putDReg(fd, unop(Iop_ReinterpI64asF64, + binop(Iop_F64toI64S, + mkU32(0x01), + getDReg(fs)))); } else { ILLEGAL_INSTRUCTON; } @@ -27017,25 +27562,13 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, case 0x10: /* S */ DIP("round.w.s f%u, f%u", fd, fs); calculateFCSR(fs, 0, ROUNDWS, True, 1); - if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); - t4 = newTemp(Ity_F32); - /* get lo half of FPR */ - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - - assign(t1, unop(Iop_64to32, mkexpr(t0))); - - assign(t3, unop(Iop_ReinterpI32asF32, mkexpr(t1))); - - assign(t4, binop(Iop_RoundF32toInt, mkU32(0x0), - mkexpr(t3))); - - putFReg(fd, mkWidenFromF32(tyF, mkexpr(t4))); - } else - putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x0), - getFReg(fs))); + putFReg(fd, + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + binop(Iop_F32toI32S, + mkU32(0x0), + getLoFromF64(tyF, + getFReg(fs)))))); break; case 0x11: /* D */ @@ -27067,25 +27600,13 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, case 0x10: /* S */ DIP("floor.w.s f%u, f%u", fd, fs); calculateFCSR(fs, 0, FLOORWS, True, 1); - if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); - t4 = newTemp(Ity_F32); - /* get lo half of FPR */ - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - - assign(t1, unop(Iop_64to32, mkexpr(t0))); - - assign(t3, unop(Iop_ReinterpI32asF32, mkexpr(t1))); - - assign(t4, binop(Iop_RoundF32toInt, mkU32(0x1), - mkexpr(t3))); - - putFReg(fd, mkWidenFromF32(tyF, mkexpr(t4))); - } else - putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x1), - getFReg(fs))); + putFReg(fd, + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + binop(Iop_F32toI32S, + mkU32(0x1), + getLoFromF64(tyF, + getFReg(fs)))))); break; case 0x11: /* D */ @@ -27118,25 +27639,13 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, case 0x10: /* S */ DIP("trunc.w.s %u, %u", fd, fs); calculateFCSR(fs, 0, TRUNCWS, True, 1); - if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); - t4 = newTemp(Ity_F32); - /* get lo half of FPR */ - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - - assign(t1, unop(Iop_64to32, mkexpr(t0))); - - assign(t3, unop(Iop_ReinterpI32asF32, mkexpr(t1))); - - assign(t4, binop(Iop_RoundF32toInt, mkU32(0x3), - mkexpr(t3))); - - putFReg(fd, mkWidenFromF32(tyF, mkexpr(t4))); - } else - putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x3), - getFReg(fs))); + putFReg(fd, + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + binop(Iop_F32toI32S, + mkU32(0x3), + getLoFromF64(tyF, + getFReg(fs)))))); break; case 0x11: /* D */ DIP("trunc.w.d %u, %u", fd, fs); @@ -27169,26 +27678,14 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, case 0x10: /* S */ DIP("ceil.w.s %u, %u", fd, fs); calculateFCSR(fs, 0, CEILWS, True, 1); - if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); - t4 = newTemp(Ity_F32); - /* get lo half of FPR */ - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - - assign(t1, unop(Iop_64to32, mkexpr(t0))); - - assign(t3, unop(Iop_ReinterpI32asF32, mkexpr(t1))); - - assign(t4, binop(Iop_RoundF32toInt, mkU32(0x2), - mkexpr(t3))); - - putFReg(fd, mkWidenFromF32(tyF, mkexpr(t4))); - } else - putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x2), - getFReg(fs))); - break; + putFReg(fd, + mkWidenFromF32(tyF, + unop(Iop_ReinterpI32asF32, + binop(Iop_F32toI32S, + mkU32(0x2), + getLoFromF64(tyF, + getFReg(fs)))))); + break; case 0x11: /* D */ DIP("ceil.w.d %u, %u", fd, fs); @@ -27206,6 +27703,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, unop(Iop_ReinterpI32asF32, mkexpr(t0)))); } break; + default: goto decode_failure; @@ -27233,8 +27731,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, DIP("ceil.l.d %u, %u", fd, fs); if (fp_mode64) { calculateFCSR(fs, 0, CEILLD, False, 1); - putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x2), - getDReg(fs))); + putDReg(fd, unop(Iop_ReinterpI64asF64, + binop(Iop_F64toI64S, + mkU32(0x2), + getDReg(fs)))); } else { ILLEGAL_INSTRUCT... [truncated message content] |
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From: Petar J. <pe...@so...> - 2018-02-01 18:06:17
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fd120874fbee2715a36e9eaaceccf6166c6d45c5 commit fd120874fbee2715a36e9eaaceccf6166c6d45c5 Author: Petar Jovanovic <mip...@gm...> Date: Thu Feb 1 18:26:01 2018 +0100 mips: add support for mips32/mips64 R6 to coregrind Changes in PRE(sys_prctl), necessary to support new floating-point modes in MIPS R6. Part of MIPS32/64 Revision 6 changes. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410. Diff: --- coregrind/m_redir.c | 11 +++++ coregrind/m_syswrap/syswrap-mips32-linux.c | 65 +++++++++++++++++++++--------- coregrind/m_translate.c | 6 ++- 3 files changed, 61 insertions(+), 21 deletions(-) diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c index 992427a..aa65eaf 100644 --- a/coregrind/m_redir.c +++ b/coregrind/m_redir.c @@ -1611,6 +1611,17 @@ void VG_(redir_initialise) ( void ) (Addr)&VG_(mips64_linux_REDIR_FOR_index), complain_about_stripped_glibc_ldso ); + + add_hardwired_spec( + "ld-linux-mipsn8.so.1", "strlen", + (Addr)&VG_(mips64_linux_REDIR_FOR_strlen), + complain_about_stripped_glibc_ldso + ); + add_hardwired_spec( + "ld-linux-mipsn8.so.1", "index", + (Addr)&VG_(mips64_linux_REDIR_FOR_index), + complain_about_stripped_glibc_ldso + ); } # elif defined(VGP_x86_solaris) diff --git a/coregrind/m_syswrap/syswrap-mips32-linux.c b/coregrind/m_syswrap/syswrap-mips32-linux.c index 3dd43dd..aecffe8 100644 --- a/coregrind/m_syswrap/syswrap-mips32-linux.c +++ b/coregrind/m_syswrap/syswrap-mips32-linux.c @@ -656,40 +656,65 @@ PRE(sys_prctl) case VKI_PR_SET_FP_MODE: { VexArchInfo vai; + Int known_bits = VKI_PR_FP_MODE_FR | VKI_PR_FP_MODE_FRE; VG_(machine_get_VexArchInfo)(NULL, &vai); /* Reject unsupported modes */ - if ((ARG2 & ~VKI_PR_FP_MODE_FR) || - ((ARG2 & VKI_PR_FP_MODE_FR) && - !VEX_MIPS_HOST_FP_MODE(vai.hwcaps))) { + if (ARG2 & ~known_bits) { SET_STATUS_Failure(VKI_EOPNOTSUPP); - } else { - if (!(VG_(threads)[tid].arch.vex.guest_CP0_status & - MIPS_CP0_STATUS_FR) != !(ARG2 & VKI_PR_FP_MODE_FR)) { - ThreadId t; - for (t = 1; t < VG_N_THREADS; t++) { - if (VG_(threads)[t].status != VgTs_Empty) { - if (ARG2 & VKI_PR_FP_MODE_FR) { - VG_(threads)[t].arch.vex.guest_CP0_status |= + return; + } + if ((ARG2 & VKI_PR_FP_MODE_FR) && !VEX_MIPS_HOST_FP_MODE(vai.hwcaps)) { + SET_STATUS_Failure(VKI_EOPNOTSUPP); + return; + } + if ((ARG2 & VKI_PR_FP_MODE_FRE) && !VEX_MIPS_CPU_HAS_MIPSR6(vai.hwcaps)) { + SET_STATUS_Failure(VKI_EOPNOTSUPP); + return; + } + if (!(ARG2 & VKI_PR_FP_MODE_FR) && VEX_MIPS_CPU_HAS_MIPSR6(vai.hwcaps)) { + SET_STATUS_Failure(VKI_EOPNOTSUPP); + return; + } + + if ((!(VG_(threads)[tid].arch.vex.guest_CP0_status & + MIPS_CP0_STATUS_FR) != !(ARG2 & VKI_PR_FP_MODE_FR)) || + (!(VG_(threads)[tid].arch.vex.guest_CP0_Config5 & + MIPS_CONF5_FRE) != !(ARG2 & VKI_PR_FP_MODE_FRE))) { + ThreadId t; + for (t = 1; t < VG_N_THREADS; t++) { + if (VG_(threads)[t].status != VgTs_Empty) { + if (ARG2 & VKI_PR_FP_MODE_FRE) { + VG_(threads)[t].arch.vex.guest_CP0_Config5 |= + MIPS_CONF5_FRE; + } else { + VG_(threads)[t].arch.vex.guest_CP0_Config5 &= + ~MIPS_CONF5_FRE; + } + if (ARG2 & VKI_PR_FP_MODE_FR) { + VG_(threads)[t].arch.vex.guest_CP0_status |= MIPS_CP0_STATUS_FR; - } else { - VG_(threads)[t].arch.vex.guest_CP0_status &= + } else { + VG_(threads)[t].arch.vex.guest_CP0_status &= ~MIPS_CP0_STATUS_FR; - } } } - /* Discard all translations */ - VG_(discard_translations)(0, 0xfffffffful, "prctl(PR_SET_FP_MODE)"); + /* Discard all translations */ + VG_(discard_translations)(0, 0xfffffffful, "prctl(PR_SET_FP_MODE)"); } - SET_STATUS_Success(0); + SET_STATUS_Success(0); } break; } case VKI_PR_GET_FP_MODE: + { + UInt ret = 0; if (VG_(threads)[tid].arch.vex.guest_CP0_status & MIPS_CP0_STATUS_FR) - SET_STATUS_Success(VKI_PR_FP_MODE_FR); - else - SET_STATUS_Success(0); + ret |= VKI_PR_FP_MODE_FR; + if (VG_(threads)[tid].arch.vex.guest_CP0_Config5 & MIPS_CONF5_FRE) + ret |= VKI_PR_FP_MODE_FRE; + SET_STATUS_Success(ret); break; + } default: WRAPPER_PRE_NAME(linux, sys_prctl)(tid, layout, arrghs, status, flags); break; diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c index 480a259..cfa279d 100644 --- a/coregrind/m_translate.c +++ b/coregrind/m_translate.c @@ -1706,8 +1706,12 @@ Bool VG_(translate) ( ThreadId tid, # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) ThreadArchState* arch = &VG_(threads)[tid].arch; - vex_abiinfo.guest_mips_fp_mode64 = + vex_abiinfo.guest_mips_fp_mode = !!(arch->vex.guest_CP0_status & MIPS_CP0_STATUS_FR); +# if defined(VGP_mips32_linux) + vex_abiinfo.guest_mips_fp_mode |= + (!!(arch->vex.guest_CP0_Config5 & MIPS_CONF5_FRE)) << 1; +# endif /* Compute guest__use_fallback_LLSC, overiding any settings of VG_(clo_fallback_llsc) that we know would cause the guest to fail (loop). */ |
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From: Petar J. <pe...@so...> - 2018-02-01 18:06:16
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2671481a5f88329d5ad31545513fe925629fb973 commit 2671481a5f88329d5ad31545513fe925629fb973 Author: Petar Jovanovic <mip...@gm...> Date: Thu Feb 1 18:09:56 2018 +0100 add Iops Iop_Rotx32 and Iop_Rotx64 Part of MIPS32/64 Revision 6 changes. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410. Diff: --- VEX/priv/ir_defs.c | 6 ++++++ VEX/pub/libvex_ir.h | 1 + memcheck/mc_translate.c | 29 +++++++++++++++++++++++++++++ memcheck/tests/vbit-test/irops.c | 2 ++ 4 files changed, 38 insertions(+) diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 8627beb..2cffd0b 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -1297,6 +1297,8 @@ void ppIROp ( IROp op ) case Iop_BCDSub: vex_printf("BCDSub"); return; case Iop_I128StoBCD128: vex_printf("bcdcfsq."); return; case Iop_BCD128toI128S: vex_printf("bcdctsq."); return; + case Iop_Rotx32: vex_printf("bitswap"); return; + case Iop_Rotx64: vex_printf("dbitswap"); return; case Iop_PwBitMtxXpose64x2: vex_printf("BitMatrixTranspose64x2"); return; @@ -3578,6 +3580,10 @@ void typeOfPrimop ( IROp op, case Iop_ShrN64x4: case Iop_SarN16x16: case Iop_SarN32x8: BINARY(Ity_V256,Ity_I8, Ity_V256); + case Iop_Rotx32: + QUATERNARY(Ity_I32, Ity_I8, Ity_I8, Ity_I8, Ity_I32); + case Iop_Rotx64: + QUATERNARY(Ity_I64, Ity_I8, Ity_I8, Ity_I8, Ity_I64); default: ppIROp(op); diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index ed7d52b..2b07afd 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -1936,6 +1936,7 @@ typedef Iop_Max32Fx8, Iop_Min32Fx8, Iop_Max64Fx4, Iop_Min64Fx4, + Iop_Rotx32, Iop_Rotx64, Iop_LAST /* must be the last enumerator */ } IROp; diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index ae7e472..6667191 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -2012,6 +2012,30 @@ IRAtom* mkLazy4 ( MCEnv* mce, IRType finalVty, return at; } + if (t1 == Ity_I32 && t2 == Ity_I8 && t3 == Ity_I8 && t4 == Ity_I8 + && finalVty == Ity_I32) { + if (0) VG_(printf)("mkLazy4: I32 x I8 x I8 x I8 -> I32\n"); + at = mkPCastTo(mce, Ity_I8, va1); + /* Now fold in 2nd, 3rd, 4th args. */ + at = mkUifU(mce, Ity_I8, at, va2); + at = mkUifU(mce, Ity_I8, at, va3); + at = mkUifU(mce, Ity_I8, at, va4); + at = mkPCastTo(mce, Ity_I32, at); + return at; + } + + if (t1 == Ity_I64 && t2 == Ity_I8 && t3 == Ity_I8 && t4 == Ity_I8 + && finalVty == Ity_I64) { + if (0) VG_(printf)("mkLazy4: I64 x I8 x I8 x I8 -> I64\n"); + at = mkPCastTo(mce, Ity_I8, va1); + /* Now fold in 2nd, 3rd, 4th args. */ + at = mkUifU(mce, Ity_I8, at, va2); + at = mkUifU(mce, Ity_I8, at, va3); + at = mkUifU(mce, Ity_I8, at, va4); + at = mkPCastTo(mce, Ity_I64, at); + return at; + } + if (1) { VG_(printf)("mkLazy4: "); ppIRType(t1); @@ -3020,6 +3044,11 @@ IRAtom* expr2vbits_Qop ( MCEnv* mce, return assignNew('V', mce, Ity_V256, IRExpr_Qop(op, vatom1, vatom2, vatom3, vatom4)); + /* I32/I64 x I8 x I8 x I8 -> I32/I64 */ + case Iop_Rotx32: + return mkLazy4(mce, Ity_I32, vatom1, vatom2, vatom3, vatom4); + case Iop_Rotx64: + return mkLazy4(mce, Ity_I64, vatom1, vatom2, vatom3, vatom4); default: ppIROp(op); VG_(tool_panic)("memcheck:expr2vbits_Qop"); diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index a969a14..adc7845 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -1128,6 +1128,8 @@ static irop_t irops[] = { { DEFOP(Iop_NCipherLV128, UNDEF_ALL_64x2), .ppc64 = 1, .ppc32 = 1 }, { DEFOP(Iop_SHA512, UNDEF_SOME), .ppc64 = 1, .ppc32 = 1 }, { DEFOP(Iop_SHA256, UNDEF_SOME), .ppc64 = 1, .ppc32 = 1 }, + { DEFOP(Iop_Rotx32, UNDEF_ALL), }, + { DEFOP(Iop_Rotx64, UNDEF_ALL), }, { DEFOP(Iop_PwBitMtxXpose64x2, UNDEF_64x2_TRANSPOSE), .ppc64 = 1, .ppc32 = 1 }, }; |