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From: Mark W. <ma...@so...> - 2017-12-12 23:24:34
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=be82bb5f9dfecd854c53eda321d1914f28f19790 commit be82bb5f9dfecd854c53eda321d1914f28f19790 Author: Mark Wielaard <ma...@kl...> Date: Sat Dec 9 23:01:29 2017 +0100 Fix gnu debug alt file resolving. https://bugs.kde.org/show_bug.cgi?id=387773 The path to the alt file is relative to the actual debug file. Make sure that we got the real file, not a (build-id) symlink. Also handle the case where a debug or alt file is an absolute path. Diff: --- NEWS | 1 + coregrind/m_debuginfo/readelf.c | 68 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index de4f668..e27c3ea 100644 --- a/NEWS +++ b/NEWS @@ -78,6 +78,7 @@ where XXXXXX is the bug number as listed below. 385939 Optionally exit on the first error 386397 PPC64, valgrind truncates powerpc timebase to 32-bits. 387712 s390x cgijnl reports Conditional jump depends on uninitialised value +387773 .gnu_debugaltlink paths resolve relative to .debug file, not symlink n-i-bz Fix missing workq_ops operations (macOS) n-i-bz fix bug in strspn replacement diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c index e612250..c19ff21 100644 --- a/coregrind/m_debuginfo/readelf.c +++ b/coregrind/m_debuginfo/readelf.c @@ -33,6 +33,7 @@ #include "pub_core_basics.h" #include "pub_core_vki.h" +#include "pub_core_vkiscnums.h" #include "pub_core_debuginfo.h" #include "pub_core_libcbase.h" #include "pub_core_libcprint.h" @@ -40,6 +41,7 @@ #include "pub_core_machine.h" /* VG_ELF_CLASS */ #include "pub_core_options.h" #include "pub_core_oset.h" +#include "pub_core_syscall.h" #include "pub_core_tooliface.h" /* VG_(needs) */ #include "pub_core_xarray.h" #include "priv_misc.h" /* dinfo_zalloc/free/strdup */ @@ -1323,6 +1325,12 @@ DiImage* find_debug_file( struct _DebugInfo* di, + (extrapath ? VG_(strlen)(extrapath) : 0) + (serverpath ? VG_(strlen)(serverpath) : 0)); + if (debugname[0] == '/') { + VG_(sprintf)(debugpath, "%s", debugname); + dimg = open_debug_file(debugpath, buildid, crc, rel_ok, NULL); + if (dimg != NULL) goto dimg_ok; + } + VG_(sprintf)(debugpath, "%s/%s", objdir, debugname); dimg = open_debug_file(debugpath, buildid, crc, rel_ok, NULL); if (dimg != NULL) goto dimg_ok; @@ -1527,6 +1535,56 @@ static Bool check_compression(ElfXX_Shdr* h, DiSlice* s) { return True; } +/* Helper function to get the readlink path. Returns a copy of path if the + file wasn't a symbolic link. Returns NULL on error. Unless NULL is + returned the result needs to be released with dinfo_free. +*/ +static HChar* readlink_path (const HChar *path) +{ + SizeT bufsiz = VG_(strlen)(path); + HChar *buf = ML_(dinfo_strdup)("readlink_path.strdup", path); + UInt tries = 6; + + while (tries > 0) { + SysRes res; +#if defined(VGP_arm64_linux) + res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, + (UWord)path, (UWord)buf, bufsiz); +#elif defined(VGO_linux) || defined(VGO_darwin) + res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz); +#elif defined(VGO_solaris) + res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, (UWord)path, + (UWord)buf, bufsiz); +#else +# error Unknown OS +#endif + if (sr_isError(res)) { + if (sr_Err(res) == VKI_EINVAL) + return buf; // It wasn't a symbolic link, return the strdup result. + ML_(dinfo_free)(buf); + return NULL; + } + + SSizeT r = sr_Res(res); + if (r < 0) break; + if (r == bufsiz) { // buffer too small; increase and retry + bufsiz *= 2 + 16; + buf = ML_(dinfo_realloc)("readlink_path.realloc", buf, bufsiz); + tries--; + continue; + } + buf[r] = '\0'; + break; + } + + if (tries == 0) { // We tried, but weird long path? + ML_(dinfo_free)(buf); + return NULL; + } + + return buf; +} + /* The central function for reading ELF debug info. For the object/exe specified by the DebugInfo, find ELF sections, then read the symbols, line number info, file name info, CFA (stack-unwind @@ -2926,8 +2984,12 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) (debugaltlink_escn.szB - buildid_offset) * 2 + 1); - /* The altfile might be relative to the debug file or main file. */ + /* The altfile might be relative to the debug file or main file. + Make sure that we got the real file, not a symlink. */ HChar *dbgname = di->fsm.dbgname ? di->fsm.dbgname : di->fsm.filename; + HChar* rdbgname = readlink_path (dbgname); + if (rdbgname == NULL) + rdbgname = ML_(dinfo_strdup)("rdbgname", dbgname); for (j = 0; j < debugaltlink_escn.szB - buildid_offset; j++) VG_(sprintf)( @@ -2937,9 +2999,11 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) + buildid_offset + j)); /* See if we can find a matching debug file */ - aimg = find_debug_file( di, dbgname, altbuildid, + aimg = find_debug_file( di, rdbgname, altbuildid, altfile_str_m, 0, True ); + ML_(dinfo_free)(rdbgname); + if (altfile_str_m) ML_(dinfo_free)(altfile_str_m); ML_(dinfo_free)(altbuildid); |
|
From: Mark W. <ma...@so...> - 2017-12-12 21:43:18
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d6a810760ec61ddedf15445457edbbe288536a2f commit d6a810760ec61ddedf15445457edbbe288536a2f Author: Julian Seward <js...@ac...> Date: Tue Dec 12 22:31:54 2017 +0100 Fix false positive with s390x cgijnl instruction testing against sign bit. https://bugs.kde.org/show_bug.cgi?id=387712 When the cgij "compare immediate and branch relative" instruction compares 0 <=signed dep1, that means dep1 >=signed 0, so it is a test against the most significant bit of dep1. So only that bit needs to be defined. Diff: --- NEWS | 1 + VEX/priv/guest_s390_helpers.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/NEWS b/NEWS index bb3d6c2..de4f668 100644 --- a/NEWS +++ b/NEWS @@ -77,6 +77,7 @@ where XXXXXX is the bug number as listed below. 385912 none/tests/rlimit_nofile fails on newer glibc/kernel. 385939 Optionally exit on the first error 386397 PPC64, valgrind truncates powerpc timebase to 32-bits. +387712 s390x cgijnl reports Conditional jump depends on uninitialised value n-i-bz Fix missing workq_ops operations (macOS) n-i-bz fix bug in strspn replacement diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c index 4cccdec..aacd833 100644 --- a/VEX/priv/guest_s390_helpers.c +++ b/VEX/priv/guest_s390_helpers.c @@ -1818,6 +1818,13 @@ isC64(const IRExpr *expr) return expr->tag == Iex_Const && expr->Iex.Const.con->tag == Ico_U64; } +static inline Bool +isC64_exactly(const IRExpr *expr, ULong n) +{ + return expr->tag == Iex_Const && expr->Iex.Const.con->tag == Ico_U64 + && expr->Iex.Const.con->Ico.U64 == n; +} + /* The returned expression is NULL if no specialization was found. In that case the helper function will be called. Otherwise, the expression has @@ -1895,9 +1902,25 @@ guest_s390x_spechelper(const HChar *function_name, IRExpr **args, } /* cc_dep1 > cc_dep2 ----> cc_dep2 < cc_dep1 */ if (cond == 2 || cond == 2 + 1) { + /* If we ever need the counterpart of the bug387712 fix just + below, then here is the place. We'll need to give an + alternative expression for the case "cc_dep2 <s 0". From a + bit of simple testing, I've yet to see any such cases, + however. */ return unop(Iop_1Uto32, binop(Iop_CmpLT64S, cc_dep2, cc_dep1)); } if (cond == 8 + 2 || cond == 8 + 2 + 1) { + if (isC64_exactly(cc_dep2, 0)) { + /* 0 <=signed dep1 + --> dep1 >=signed 0 + --> m.s.bit of dep1 == 0 */ + /* See bug 387712. This is an old trick from gcc to extract + the most significant bit of a word. */ + return unop(Iop_64to32, + binop(Iop_Xor64, + binop(Iop_Shr64, cc_dep1, mkU8(63)), + mkU64(1))); + } return unop(Iop_1Uto32, binop(Iop_CmpLE64S, cc_dep2, cc_dep1)); } if (cond == 8 + 4 + 2 || cond == 8 + 4 + 2 + 1) { |
|
From: Mark W. <ma...@so...> - 2017-12-12 18:18:33
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c5218ff4c1215ceaee76bc8bafadbc23484d4be0 commit c5218ff4c1215ceaee76bc8bafadbc23484d4be0 Author: Mark Wielaard <ma...@kl...> Date: Tue Dec 12 19:13:08 2017 +0100 Remove old Haskell and orig diff files. These files haven't been used for the last 20 years. Diff: --- VEX/orig_amd64/Compare.hs | 63 - VEX/orig_amd64/SortedToOrig.hs | 29 - VEX/orig_amd64/test1.orig | 5281 -- VEX/orig_amd64/test1.sorted | 1318 - VEX/orig_amd64/test2.orig | 23917 ------- VEX/orig_amd64/test2.sorted | 5978 -- VEX/orig_arm/nanoarm | 7 - VEX/orig_arm/nanoarm.orig | 19 - VEX/orig_ppc32/date.orig | 138635 -------------------------------------- VEX/orig_ppc32/loadsafp.orig | 22354 ------ VEX/orig_ppc32/morefp.orig | 6944 -- VEX/orig_ppc32/return0.orig | 60452 ----------------- VEX/orig_x86/exit42.orig | 12580 ---- VEX/orig_x86/fpu_mmx_sse.orig | 35448 ---------- VEX/orig_x86/manyfp.orig | 9635 --- auxprogs/DotToScc.hs | 271 - auxprogs/Merge3Way.hs | 66 - 17 files changed, 322997 deletions(-) diff --git a/VEX/orig_amd64/Compare.hs b/VEX/orig_amd64/Compare.hs deleted file mode 100644 index 6641267..0000000 --- a/VEX/orig_amd64/Compare.hs +++ /dev/null @@ -1,63 +0,0 @@ - -module Main where - -import Char ( isSpace ) - -{- Compares a .sorted file with a raw printout of instructions - and shows differences. - - First file (REF) is has lines of format - - hex-digits SPACEs insn(possibly with spaces) - - Second file (TEST) has lines of format - - insn(possibly with spaces) - - Purpose is to extract the insn (text), remove spaces, and compare. - - How to use: -(cd .. && make) && (../vex test1.orig | grep LALALA | cut -b 22- > out.txt) -/home/sewardj/Tools/HugsInst/bin/runhugs Compare.hs | grep FAIL --} - -main = mayn "test2.sorted" "out.txt" - -mayn :: String -> String -> IO () - -mayn sorted_fn dump_fn - = do sorted <- readFile sorted_fn - dump <- readFile dump_fn - let ress = zipWith check (lines (deTab sorted)) - (lines (deTab dump)) - putStrLn (unlines ress) - - -check :: String -> String -> String -check ref test - = let ref_clean = dropWhile isHex ref - ok = compere ref_clean test - summary = grok ("REF: " ++ trim ref_clean) - ++ " " ++ grok ("TEST: " ++ trim test) - in - if ok - then "pass: " ++ summary - else "FAIL: " ++ summary - -trim = reverse . dropWhile isSpace . reverse . dropWhile isSpace - -compere s1 s2 = filter (not . isSpace) s1 == filter (not . isSpace) s2 - -isHex c = c `elem` "ABCDEF0123456789abcdef" - -grok str - = let n = length str - limit = 40 - in - if n >= limit - then str - else take limit (str ++ repeat ' ') - -deTab [] = [] -deTab (c:cs) = if c == '\t' then " " ++ deTab cs - else c: deTab cs diff --git a/VEX/orig_amd64/SortedToOrig.hs b/VEX/orig_amd64/SortedToOrig.hs deleted file mode 100644 index 0d947b6..0000000 --- a/VEX/orig_amd64/SortedToOrig.hs +++ /dev/null @@ -1,29 +0,0 @@ - -module Main where - -main - = do x1 <- readFile "test2.sorted" - let x2 = lines x1 - x3 = zip [1 ..] x2 - x4 = concat (map qq x3) - --putStr x4 - writeFile "test2.orig" x4 - - -qq :: (Int, String) -> String -qq (n, s0) - = let ws = words s0 - bytes = head ws - rest = unwords (tail ws) - bytes2 = foo bytes - in - unlines [ - "", - rest, - ". " ++ show n ++ " 0x12345678 " ++ show (1 + (length bytes `div` 2)), - ". " ++ bytes2 ++ "C3" - ] - - -foo [] = [] -foo (x:y:rest) = x:y:' ':foo rest diff --git a/VEX/orig_amd64/test1.orig b/VEX/orig_amd64/test1.orig deleted file mode 100644 index 68258c0..0000000 --- a/VEX/orig_amd64/test1.orig +++ /dev/null @@ -1,5281 +0,0 @@ - -addl 1052(%rsp,%rdx,4), %eax -. 1 0x12345678 8 -. 03 84 94 1C 04 00 00 C3 - -addl 108(%rbx), %ecx -. 2 0x12345678 4 -. 03 4B 6C C3 - -addl $2, %eax -. 3 0x12345678 4 -. 83 C0 02 C3 - -addl $2, %edx -. 4 0x12345678 4 -. 83 C2 02 C3 - -addl $32, %ecx -. 5 0x12345678 4 -. 83 C1 20 C3 - -addl $32, %esi -. 6 0x12345678 4 -. 83 C6 20 C3 - -addl $49, %r12d -. 7 0x12345678 5 -. 41 83 C4 31 C3 - -addl $4, %ecx -. 8 0x12345678 4 -. 83 C1 04 C3 - -addl -4(%rbp,%rdx,4), %eax -. 9 0x12345678 5 -. 03 44 95 FC C3 - -addl 51640(%rax), %ecx -. 10 0x12345678 7 -. 03 88 B8 C9 00 00 C3 - -addl 51640(%rbp,%rax), %ecx -. 11 0x12345678 8 -. 03 8C 05 B8 C9 00 00 C3 - -addl 51640(%rdx), %ecx -. 12 0x12345678 7 -. 03 8A B8 C9 00 00 C3 - -addl 51644(%rax), %esi -. 13 0x12345678 7 -. 03 B0 BC C9 00 00 C3 - -addl 51644(%rdx), %esi -. 14 0x12345678 7 -. 03 B2 BC C9 00 00 C3 - -addl 51648(%rax), %edi -. 15 0x12345678 7 -. 03 B8 C0 C9 00 00 C3 - -addl 51648(%rdx), %edi -. 16 0x12345678 7 -. 03 BA C0 C9 00 00 C3 - -addl $5, %eax -. 17 0x12345678 4 -. 83 C0 05 C3 - -addl $5, %r14d -. 18 0x12345678 5 -. 41 83 C6 05 C3 - -addl 672(%rbp,%rax,4), %r13d -. 19 0x12345678 9 -. 44 03 AC 85 A0 02 00 00 C3 - -addl %ebx, %eax -. 20 0x12345678 3 -. 01 D8 C3 - -addl %ecx, %r9d -. 21 0x12345678 4 -. 41 01 C9 C3 - -addl %edx, %eax -. 22 0x12345678 3 -. 01 D0 C3 - -addl %r12d, %eax -. 23 0x12345678 4 -. 44 01 E0 C3 - -addl %r12d, %r13d -. 24 0x12345678 4 -. 45 01 E5 C3 - -addl %r13d, %eax -. 25 0x12345678 4 -. 44 01 E8 C3 - -addl (%rbp,%rax,4), %edi -. 26 0x12345678 5 -. 03 7C 85 00 C3 - -addq $104, %rsp -. 27 0x12345678 5 -. 48 83 C4 68 C3 - -addq $1304, %rsp -. 28 0x12345678 8 -. 48 81 C4 18 05 00 00 C3 - -addq $2104, %rsp -. 29 0x12345678 8 -. 48 81 C4 38 08 00 00 C3 - -addq $264, %rsp -. 30 0x12345678 8 -. 48 81 C4 08 01 00 00 C3 - -addq 32(%rbx), %rax -. 31 0x12345678 5 -. 48 03 43 20 C3 - -addq $3400, %rsp -. 32 0x12345678 8 -. 48 81 C4 48 0D 00 00 C3 - -addq $56, %rsp -. 33 0x12345678 5 -. 48 83 C4 38 C3 - -addq $72, %rsp -. 34 0x12345678 5 -. 48 83 C4 48 C3 - -addq $824, %rsp -. 35 0x12345678 8 -. 48 81 C4 38 03 00 00 C3 - -addq $8, %rsp -. 36 0x12345678 5 -. 48 83 C4 08 C3 - -addq %rax, %rax -. 37 0x12345678 4 -. 48 01 C0 C3 - -addq %rax, %rdi -. 38 0x12345678 4 -. 48 01 C7 C3 - -addq %rax, %rdx -. 39 0x12345678 4 -. 48 01 C2 C3 - -addq %rbp, %rax -. 40 0x12345678 4 -. 48 01 E8 C3 - -addq %rbp, %rdx -. 41 0x12345678 4 -. 48 01 EA C3 - -addq %rbp, %rsi -. 42 0x12345678 4 -. 48 01 EE C3 - -addq %rcx, %rax -. 43 0x12345678 4 -. 48 01 C8 C3 - -addq %rdx, %rax -. 44 0x12345678 4 -. 48 01 D0 C3 - -addq %rdx, %rdx -. 45 0x12345678 4 -. 48 01 D2 C3 - -addq %rsi, %rdx -. 46 0x12345678 4 -. 48 01 F2 C3 - -addw %dx, 80(%rsp,%rax,2) -. 47 0x12345678 6 -. 66 01 54 44 50 C3 - -andl $-2097153, %eax -. 48 0x12345678 6 -. 25 FF FF DF FF C3 - -andl $-2097153, %edx -. 49 0x12345678 7 -. 81 E2 FF FF DF FF C3 - -andl $-2097153, %r12d -. 50 0x12345678 8 -. 41 81 E4 FF FF DF FF C3 - -andl $-2097153, %r15d -. 51 0x12345678 8 -. 41 81 E7 FF FF DF FF C3 - -andl $-2097153, %r8d -. 52 0x12345678 8 -. 41 81 E0 FF FF DF FF C3 - -andl $255, %r8d -. 53 0x12345678 8 -. 41 81 E0 FF 00 00 00 C3 - -andl $-2, %eax -. 54 0x12345678 4 -. 83 E0 FE C3 - -andl $31, %ecx -. 55 0x12345678 4 -. 83 E1 1F C3 - -andl $32767, %eax -. 56 0x12345678 6 -. 25 FF 7F 00 00 C3 - -andl %edx, %eax -. 57 0x12345678 3 -. 21 D0 C3 - -andl %edx, (%rbx,%rax,4) -. 58 0x12345678 4 -. 21 14 83 C3 - -andl %esi, %edx -. 59 0x12345678 3 -. 21 F2 C3 - -call lalala -. 60 0x12345678 5 -. E8 62 16 00 00 - -cltd -. 61 0x12345678 2 -. 99 C3 - -cltq -. 62 0x12345678 3 -. 48 98 C3 - -cmova %ecx, %edx -. 63 0x12345678 4 -. 0F 47 D1 C3 - -cmovae %eax, %edi -. 64 0x12345678 4 -. 0F 43 F8 C3 - -cmovae %eax, %esi -. 65 0x12345678 4 -. 0F 43 F0 C3 - -cmovg %eax, %ecx -. 66 0x12345678 4 -. 0F 4F C8 C3 - -cmovg %eax, %edi -. 67 0x12345678 4 -. 0F 4F F8 C3 - -cmovg %eax, %esi -. 68 0x12345678 4 -. 0F 4F F0 C3 - -cmovg %eax, %r12d -. 69 0x12345678 5 -. 44 0F 4F E0 C3 - -cmovge %eax, %ecx -. 70 0x12345678 4 -. 0F 4D C8 C3 - -cmovg %r13d, %eax -. 71 0x12345678 5 -. 41 0F 4F C5 C3 - -cmovl %eax, %r13d -. 72 0x12345678 5 -. 44 0F 4C E8 C3 - -cmovle %eax, %ecx -. 73 0x12345678 4 -. 0F 4E C8 C3 - -cmovle %eax, %esi -. 74 0x12345678 4 -. 0F 4E F0 C3 - -cmovne %eax, %edx -. 75 0x12345678 4 -. 0F 45 D0 C3 - -cmovne %edi, %edx -. 76 0x12345678 4 -. 0F 45 D7 C3 - -cmpb $0, 128(%rbp,%rax) -. 77 0x12345678 9 -. 80 BC 05 80 00 00 00 00 C3 - -cmpb $0, 128(%rdi,%rdx) -. 78 0x12345678 9 -. 80 BC 17 80 00 00 00 00 C3 - -cmpb $0, 19706(%rbp,%rax) -. 79 0x12345678 9 -. 80 BC 05 FA 4C 00 00 00 C3 - -cmpb $0, 2112(%rsp,%rax) -. 80 0x12345678 9 -. 80 BC 04 40 08 00 00 00 C3 - -cmpb $0, 2112(%rsp,%rsi) -. 81 0x12345678 9 -. 80 BC 34 40 08 00 00 00 C3 - -cmpb $0, 32(%rsp,%rax) -. 82 0x12345678 6 -. 80 7C 04 20 00 C3 - -cmpb %al, %r10b -. 83 0x12345678 4 -. 41 38 C2 C3 - -cmpb %cl, %sil -. 84 0x12345678 4 -. 40 38 CE C3 - -cmpb %dl, %cl -. 85 0x12345678 3 -. 38 D1 C3 - -cmpb %sil, %cl -. 86 0x12345678 4 -. 40 38 F1 C3 - -cmpb %sil, %dl -. 87 0x12345678 4 -. 40 38 F2 C3 - -cmpb %sil, (%rsp) -. 88 0x12345678 5 -. 40 38 34 24 C3 - -cmpl $0, 1088(%rsp,%rdx,4) -. 89 0x12345678 9 -. 83 BC 94 40 04 00 00 00 C3 - -cmpl $0, 108(%rbx) -. 90 0x12345678 5 -. 83 7B 6C 00 C3 - -cmpl $0, 108(%rdi) -. 91 0x12345678 5 -. 83 7F 6C 00 C3 - -cmpl $0, 12(%rsp) -. 92 0x12345678 6 -. 83 7C 24 0C 00 C3 - -cmpl $0, 20(%rsp) -. 93 0x12345678 6 -. 83 7C 24 14 00 C3 - -cmpl $0, 24(%rsp) -. 94 0x12345678 6 -. 83 7C 24 18 00 C3 - -cmpl $0, 32(%rsp,%rax,4) -. 95 0x12345678 6 -. 83 7C 84 20 00 C3 - -cmpl $0, 644(%rdi) -. 96 0x12345678 8 -. 83 BF 84 02 00 00 00 C3 - -cmpl $0, 668(%rbp) -. 97 0x12345678 8 -. 83 BD 9C 02 00 00 00 C3 - -cmpl $0, (%r14,%rax,4) -. 98 0x12345678 6 -. 41 83 3C 86 00 C3 - -cmpl $0, (%rax) -. 99 0x12345678 4 -. 83 38 00 C3 - -cmpl $0, (%rbx,%rax,4) -. 100 0x12345678 5 -. 83 3C 83 00 C3 - -cmpl $0, (%rdi) -. 101 0x12345678 4 -. 83 3F 00 C3 - -cmpl $0, (%rsi) -. 102 0x12345678 4 -. 83 3E 00 C3 - -cmpl $101, %ecx -. 103 0x12345678 4 -. 83 F9 65 C3 - -cmpl 1088(%rsp,%rdi,4), %r12d -. 104 0x12345678 9 -. 44 3B A4 BC 40 04 00 00 C3 - -cmpl 1088(%rsp,%rdx,4), %r12d -. 105 0x12345678 9 -. 44 3B A4 94 40 04 00 00 C3 - -cmpl 108(%rbx), %edx -. 106 0x12345678 4 -. 3B 53 6C C3 - -cmpl 108(%rbx), %r9d -. 107 0x12345678 5 -. 44 3B 4B 6C C3 - -cmpl $1199, 668(%rbp) -. 108 0x12345678 11 -. 81 BD 9C 02 00 00 AF 04 00 00 C3 - -cmpl 124(%rbx), %r8d -. 109 0x12345678 5 -. 44 3B 43 7C C3 - -cmpl 12(%rsp), %edx -. 110 0x12345678 5 -. 3B 54 24 0C C3 - -cmpl $-1, 48(%rbx) -. 111 0x12345678 5 -. 83 7B 30 FF C3 - -cmpl $14, %r13d -. 112 0x12345678 5 -. 41 83 FD 0E C3 - -cmpl $15, %edi -. 113 0x12345678 4 -. 83 FF 0F C3 - -cmpl $15, %r8d -. 114 0x12345678 5 -. 41 83 F8 0F C3 - -cmpl $1, 656(%rbx) -. 115 0x12345678 8 -. 83 BB 90 02 00 00 01 C3 - -cmpl $1, 660(%rbx) -. 116 0x12345678 8 -. 83 BB 94 02 00 00 01 C3 - -cmpl $1, 660(%rdi) -. 117 0x12345678 8 -. 83 BF 94 02 00 00 01 C3 - -cmpl 16(%rsp), %edx -. 118 0x12345678 5 -. 3B 54 24 10 C3 - -cmpl $17, %r12d -. 119 0x12345678 5 -. 41 83 FC 11 C3 - -cmpl $18002, 24(%rsp) -. 120 0x12345678 9 -. 81 7C 24 18 52 46 00 00 C3 - -cmpl $199, 668(%rbp) -. 121 0x12345678 11 -. 81 BD 9C 02 00 00 C7 00 00 00 C3 - -cmpl $19, %eax -. 122 0x12345678 4 -. 83 F8 13 C3 - -cmpl $1, %ebx -. 123 0x12345678 4 -. 83 FB 01 C3 - -cmpl $-1, %ecx -. 124 0x12345678 4 -. 83 F9 FF C3 - -cmpl $1, %edi -. 125 0x12345678 4 -. 83 FF 01 C3 - -cmpl $1, %edx -. 126 0x12345678 4 -. 83 FA 01 C3 - -cmpl $-1, %esi -. 127 0x12345678 4 -. 83 FE FF C3 - -cmpl $1, %esi -. 128 0x12345678 4 -. 83 FE 01 C3 - -cmpl $-1, %r13d -. 129 0x12345678 5 -. 41 83 FD FF C3 - -cmpl $1, %r13d -. 130 0x12345678 5 -. 41 83 FD 01 C3 - -cmpl $-1, %r9d -. 131 0x12345678 5 -. 41 83 F9 FF C3 - -cmpl $-1, (%rbx,%rax,4) -. 132 0x12345678 5 -. 83 3C 83 FF C3 - -cmpl 20(%rsp), %edi -. 133 0x12345678 5 -. 3B 7C 24 14 C3 - -cmpl 20(%rsp), %edx -. 134 0x12345678 5 -. 3B 54 24 14 C3 - -cmpl $2399, 668(%rbp) -. 135 0x12345678 11 -. 81 BD 9C 02 00 00 5F 09 00 00 C3 - -cmpl 24(%rsp), %ebx -. 136 0x12345678 5 -. 3B 5C 24 18 C3 - -cmpl 24(%rsp), %edi -. 137 0x12345678 5 -. 3B 7C 24 18 C3 - -cmpl $254, %ebx -. 138 0x12345678 7 -. 81 FB FE 00 00 00 C3 - -cmpl $255, %ebx -. 139 0x12345678 7 -. 81 FB FF 00 00 00 C3 - -cmpl $255, %ecx -. 140 0x12345678 7 -. 81 F9 FF 00 00 00 C3 - -cmpl $255, %edi -. 141 0x12345678 7 -. 81 FF FF 00 00 00 C3 - -cmpl $255, %edx -. 142 0x12345678 7 -. 81 FA FF 00 00 00 C3 - -cmpl $255, %r12d -. 143 0x12345678 8 -. 41 81 FC FF 00 00 00 C3 - -cmpl $256, %edi -. 144 0x12345678 7 -. 81 FF 00 01 00 00 C3 - -cmpl $256, %esi -. 145 0x12345678 7 -. 81 FE 00 01 00 00 C3 - -cmpl $2, 656(%rbp) -. 146 0x12345678 8 -. 83 BD 90 02 00 00 02 C3 - -cmpl $2, 656(%rdi) -. 147 0x12345678 8 -. 83 BF 90 02 00 00 02 C3 - -cmpl 28(%rsp), %edi -. 148 0x12345678 5 -. 3B 7C 24 1C C3 - -cmpl 28(%rsp), %r12d -. 149 0x12345678 6 -. 44 3B 64 24 1C C3 - -cmpl 28(%rsp), %r13d -. 150 0x12345678 6 -. 44 3B 6C 24 1C C3 - -cmpl $2, %ebx -. 151 0x12345678 4 -. 83 FB 02 C3 - -cmpl $2, %r13d -. 152 0x12345678 5 -. 41 83 FD 02 C3 - -cmpl $31, %edi -. 153 0x12345678 4 -. 83 FF 1F C3 - -cmpl $3, 20(%rsp) -. 154 0x12345678 6 -. 83 7C 24 14 03 C3 - -cmpl $3, 32(%rsp) -. 155 0x12345678 6 -. 83 7C 24 20 03 C3 - -cmpl $33, %ebx -. 156 0x12345678 4 -. 83 FB 21 C3 - -cmpl $33, %r9d -. 157 0x12345678 5 -. 41 83 F9 21 C3 - -cmpl $3, %eax -. 158 0x12345678 4 -. 83 F8 03 C3 - -cmpl $3, %r13d -. 159 0x12345678 5 -. 41 83 FD 03 C3 - -cmpl $3, %r8d -. 160 0x12345678 5 -. 41 83 F8 03 C3 - -cmpl $3, %r9d -. 161 0x12345678 5 -. 41 83 F9 03 C3 - -cmpl $49, %eax -. 162 0x12345678 4 -. 83 F8 31 C3 - -cmpl $599, 668(%rbp) -. 163 0x12345678 11 -. 81 BD 9C 02 00 00 57 02 00 00 C3 - -cmpl $5, %ebx -. 164 0x12345678 4 -. 83 FB 05 C3 - -cmpl 64(%rsp,%rax,4), %r12d -. 165 0x12345678 6 -. 44 3B 64 84 40 C3 - -cmpl 64(%rsp,%rdi,4), %r12d -. 166 0x12345678 6 -. 44 3B 64 BC 40 C3 - -cmpl 64(%rsp,%rdx,4), %eax -. 167 0x12345678 5 -. 3B 44 94 40 C3 - -cmpl $65534, %eax -. 168 0x12345678 6 -. 3D FE FF 00 00 C3 - -cmpl $65534, %edx -. 169 0x12345678 7 -. 81 FA FE FF 00 00 C3 - -cmpl $65535, %eax -. 170 0x12345678 6 -. 3D FF FF 00 00 C3 - -cmpl $65536, %ebx -. 171 0x12345678 7 -. 81 FB 00 00 01 00 C3 - -cmpl 668(%rbp), %edx -. 172 0x12345678 7 -. 3B 95 9C 02 00 00 C3 - -cmpl 668(%rbp), %r12d -. 173 0x12345678 8 -. 44 3B A5 9C 02 00 00 C3 - -cmpl $6, %r14d -. 174 0x12345678 5 -. 41 83 FE 06 C3 - -cmpl $7, 644(%r11) -. 175 0x12345678 9 -. 41 83 BB 84 02 00 00 07 C3 - -cmpl $7, 644(%rbp) -. 176 0x12345678 8 -. 83 BD 84 02 00 00 07 C3 - -cmpl $7, 644(%rbx) -. 177 0x12345678 8 -. 83 BB 84 02 00 00 07 C3 - -cmpl $7, 644(%rdi) -. 178 0x12345678 8 -. 83 BF 84 02 00 00 07 C3 - -cmpl $7, 644(%rsi) -. 179 0x12345678 8 -. 83 BE 84 02 00 00 07 C3 - -cmpl $7, %r14d -. 180 0x12345678 5 -. 41 83 FE 07 C3 - -cmpl $99, 12(%rsp) -. 181 0x12345678 6 -. 83 7C 24 0C 63 C3 - -cmpl $99, 24(%rsp) -. 182 0x12345678 6 -. 83 7C 24 18 63 C3 - -cmpl $9999, %ebp -. 183 0x12345678 7 -. 81 FD 0F 27 00 00 C3 - -cmpl $9, %eax -. 184 0x12345678 4 -. 83 F8 09 C3 - -cmpl %eax, 64(%rsp,%rdx,4) -. 185 0x12345678 5 -. 39 44 94 40 C3 - -cmpl %eax, %ecx -. 186 0x12345678 3 -. 39 C1 C3 - -cmpl %eax, %edi -. 187 0x12345678 3 -. 39 C7 C3 - -cmpl %eax, %edx -. 188 0x12345678 3 -. 39 C2 C3 - -cmpl %eax, %esi -. 189 0x12345678 3 -. 39 C6 C3 - -cmpl %eax, %r13d -. 190 0x12345678 4 -. 41 39 C5 C3 - -cmpl %eax, %r8d -. 191 0x12345678 4 -. 41 39 C0 C3 - -cmpl %ebp, %edi -. 192 0x12345678 3 -. 39 EF C3 - -cmpl %ebp, %r12d -. 193 0x12345678 4 -. 41 39 EC C3 - -cmpl %ecx, %eax -. 194 0x12345678 3 -. 39 C8 C3 - -cmpl %ecx, %r13d -. 195 0x12345678 4 -. 41 39 CD C3 - -cmpl %edi, %eax -. 196 0x12345678 3 -. 39 F8 C3 - -cmpl %edi, %r10d -. 197 0x12345678 4 -. 41 39 FA C3 - -cmpl %edx, %ecx -. 198 0x12345678 3 -. 39 D1 C3 - -cmpl %edx, %edi -. 199 0x12345678 3 -. 39 D7 C3 - -cmpl %edx, 0x12345678(%rip) -. 200 0x12345678 7 -. 39 15 78 56 34 12 C3 - -cmpl %edx, %r12d -. 201 0x12345678 4 -. 41 39 D4 C3 - -cmpl %edx, %r9d -. 202 0x12345678 4 -. 41 39 D1 C3 - -cmpl %edx, (%rcx,%rax,4) -. 203 0x12345678 4 -. 39 14 81 C3 - -cmpl %r10d, %r9d -. 204 0x12345678 4 -. 45 39 D1 C3 - -cmpl (%r10,%rax,4), %r8d -. 205 0x12345678 5 -. 45 3B 04 82 C3 - -cmpl %r11d, %ecx -. 206 0x12345678 4 -. 44 39 D9 C3 - -cmpl %r12d, %eax -. 207 0x12345678 4 -. 44 39 E0 C3 - -cmpl %r12d, %ebp -. 208 0x12345678 4 -. 44 39 E5 C3 - -cmpl %r12d, %edi -. 209 0x12345678 4 -. 44 39 E7 C3 - -cmpl %r13d, 16(%rsp) -. 210 0x12345678 6 -. 44 39 6C 24 10 C3 - -cmpl %r13d, %eax -. 211 0x12345678 4 -. 44 39 E8 C3 - -cmpl %r13d, %ebp -. 212 0x12345678 4 -. 44 39 ED C3 - -cmpl %r13d, %edi -. 213 0x12345678 4 -. 44 39 EF C3 - -cmpl %r13d, %edx -. 214 0x12345678 4 -. 44 39 EA C3 - -cmpl %r13d, %r12d -. 215 0x12345678 4 -. 45 39 EC C3 - -cmpl %r14d, %eax -. 216 0x12345678 4 -. 44 39 F0 C3 - -cmpl %r14d, %ebx -. 217 0x12345678 4 -. 44 39 F3 C3 - -cmpl %r14d, %edi -. 218 0x12345678 4 -. 44 39 F7 C3 - -cmpl %r14d, %r12d -. 219 0x12345678 4 -. 45 39 F4 C3 - -cmpl %r14d, %r13d -. 220 0x12345678 4 -. 45 39 F5 C3 - -cmpl %r15d, %r14d -. 221 0x12345678 4 -. 45 39 FE C3 - -cmpl %r8d, %edi -. 222 0x12345678 4 -. 44 39 C7 C3 - -cmpl %r8d, %esi -. 223 0x12345678 4 -. 44 39 C6 C3 - -cmpl %r9d, %edx -. 224 0x12345678 4 -. 44 39 CA C3 - -cmpw %ax, %r10w -. 225 0x12345678 5 -. 66 41 39 C2 C3 - -decl 12(%rsp) -. 226 0x12345678 5 -. FF 4C 24 0C C3 - -decl 24(%rsp) -. 227 0x12345678 5 -. FF 4C 24 18 C3 - -decl 32(%rsp,%rax,4) -. 228 0x12345678 5 -. FF 4C 84 20 C3 - -decl %eax -. 229 0x12345678 3 -. FF C8 C3 - -decl %ebp -. 230 0x12345678 3 -. FF CD C3 - -decl %ebx -. 231 0x12345678 3 -. FF CB C3 - -decl %ecx -. 232 0x12345678 3 -. FF C9 C3 - -decl %edi -. 233 0x12345678 3 -. FF CF C3 - -decl %esi -. 234 0x12345678 3 -. FF CE C3 - -decl %r10d -. 235 0x12345678 4 -. 41 FF CA C3 - -decl %r11d -. 236 0x12345678 4 -. 41 FF CB C3 - -decl %r12d -. 237 0x12345678 4 -. 41 FF CC C3 - -decl %r8d -. 238 0x12345678 4 -. 41 FF C8 C3 - -decl (%r9) -. 239 0x12345678 4 -. 41 FF 09 C3 - -idivl %ebx -. 240 0x12345678 3 -. F7 FB C3 - -imull $7621, 8(%rsp), %eax -. 241 0x12345678 9 -. 69 44 24 08 C5 1D 00 00 C3 - -imull %eax, %r12d -. 242 0x12345678 5 -. 44 0F AF E0 C3 - -imulq $1431655766, %rax, %rax -. 243 0x12345678 8 -. 48 69 C0 56 55 55 55 C3 - -imulq %rdx, %rax -. 244 0x12345678 5 -. 48 0F AF C2 C3 - -incl 1056(%rsp,%rax,4) -. 245 0x12345678 8 -. FF 84 84 20 04 00 00 C3 - -incl 116(%r11) -. 246 0x12345678 5 -. 41 FF 43 74 C3 - -incl 116(%rdi) -. 247 0x12345678 4 -. FF 47 74 C3 - -incl 116(%rsi) -. 248 0x12345678 4 -. FF 46 74 C3 - -incl 124(%rdi) -. 249 0x12345678 4 -. FF 47 7C C3 - -incl 12(%rsp) -. 250 0x12345678 5 -. FF 44 24 0C C3 - -incl 24(%rsp) -. 251 0x12345678 5 -. FF 44 24 18 C3 - -incl 45448(%rbp,%rax,4) -. 252 0x12345678 8 -. FF 84 85 88 B1 00 00 C3 - -incl 45448(%rbp,%rdx,4) -. 253 0x12345678 8 -. FF 84 95 88 B1 00 00 C3 - -incl 48(%rsp,%rsi,4) -. 254 0x12345678 5 -. FF 44 B4 30 C3 - -incl 672(%rbx) -. 255 0x12345678 7 -. FF 83 A0 02 00 00 C3 - -incl 672(%rbx,%rax,4) -. 256 0x12345678 8 -. FF 84 83 A0 02 00 00 C3 - -incl 676(%rbx) -. 257 0x12345678 7 -. FF 83 A4 02 00 00 C3 - -incl 676(%rbx,%rax,4) -. 258 0x12345678 8 -. FF 84 83 A4 02 00 00 C3 - -incl %eax -. 259 0x12345678 3 -. FF C0 C3 - -incl %ebp -. 260 0x12345678 3 -. FF C5 C3 - -incl %ebx -. 261 0x12345678 3 -. FF C3 C3 - -incl %ecx -. 262 0x12345678 3 -. FF C1 C3 - -incl %edi -. 263 0x12345678 3 -. FF C7 C3 - -incl %edx -. 264 0x12345678 3 -. FF C2 C3 - -incl %esi -. 265 0x12345678 3 -. FF C6 C3 - -incl %r10d -. 266 0x12345678 4 -. 41 FF C2 C3 - -incl %r11d -. 267 0x12345678 4 -. 41 FF C3 C3 - -incl %r12d -. 268 0x12345678 4 -. 41 FF C4 C3 - -incl %r13d -. 269 0x12345678 4 -. 41 FF C5 C3 - -incl %r14d -. 270 0x12345678 4 -. 41 FF C6 C3 - -incl %r8d -. 271 0x12345678 4 -. 41 FF C0 C3 - -incl %r9d -. 272 0x12345678 4 -. 41 FF C1 C3 - -incl (%rbp,%rax,4) -. 273 0x12345678 5 -. FF 44 85 00 C3 - -incq %rdx -. 274 0x12345678 4 -. 48 FF C2 C3 - -ja lalala -. 275 0x12345678 6 -. 0F 87 DD 12 00 00 - -jbe lalala -. 276 0x12345678 6 -. 0F 86 D7 12 00 00 - -je lalala -. 277 0x12345678 6 -. 0F 84 D1 12 00 00 - -jge lalala -. 278 0x12345678 6 -. 0F 8D CB 12 00 00 - -jg lalala -. 279 0x12345678 6 -. 0F 8F C5 12 00 00 - -jle lalala -. 280 0x12345678 6 -. 0F 8E BF 12 00 00 - -jl lalala -. 281 0x12345678 6 -. 0F 8C B9 12 00 00 - -jmp lalala -. 282 0x12345678 5 -. E9 B4 12 00 00 - -jne lalala -. 283 0x12345678 6 -. 0F 85 AE 12 00 00 - -jns lalala -. 284 0x12345678 6 -. 0F 89 A8 12 00 00 - -js lalala -. 285 0x12345678 6 -. 0F 88 A2 12 00 00 - -leal -1(%r11), %edi -. 286 0x12345678 5 -. 41 8D 7B FF C3 - -leal -1(%r12,%rax), %eax -. 287 0x12345678 6 -. 41 8D 44 04 FF C3 - -leal 1(%r13), %eax -. 288 0x12345678 5 -. 41 8D 45 01 C3 - -leal 1(%r13), %edx -. 289 0x12345678 5 -. 41 8D 55 01 C3 - -leal 1(%r8), %edx -. 290 0x12345678 5 -. 41 8D 50 01 C3 - -leal 1(%rax), %esi -. 291 0x12345678 4 -. 8D 70 01 C3 - -leal -1(%rax), %r14d -. 292 0x12345678 5 -. 44 8D 70 FF C3 - -leal 1(%rax,%r8), %r8d -. 293 0x12345678 6 -. 46 8D 44 00 01 C3 - -leal 1(%rax,%rcx), %ecx -. 294 0x12345678 5 -. 8D 4C 08 01 C3 - -leal 1(%rbp), %esi -. 295 0x12345678 4 -. 8D 75 01 C3 - -leal -1(%rbx), %eax -. 296 0x12345678 4 -. 8D 43 FF C3 - -leal -1(%rcx), %eax -. 297 0x12345678 4 -. 8D 41 FF C3 - -leal 1(%rcx), %eax -. 298 0x12345678 4 -. 8D 41 01 C3 - -leal 1(%rdi), %eax -. 299 0x12345678 4 -. 8D 47 01 C3 - -leal 1(%rdi), %ecx -. 300 0x12345678 4 -. 8D 4F 01 C3 - -leal -1(%rdx), %eax -. 301 0x12345678 4 -. 8D 42 FF C3 - -leal 1(%rdx), %eax -. 302 0x12345678 4 -. 8D 42 01 C3 - -leal -1(%rsi), %ebp -. 303 0x12345678 4 -. 8D 6E FF C3 - -leal -1(%rsi), %r12d -. 304 0x12345678 5 -. 44 8D 66 FF C3 - -leal -1(%rsi), %r9d -. 305 0x12345678 5 -. 44 8D 4E FF C3 - -leal -2(%rbx), %eax -. 306 0x12345678 4 -. 8D 43 FE C3 - -leal -2(%rdi), %eax -. 307 0x12345678 4 -. 8D 47 FE C3 - -leal 31(%r13), %eax -. 308 0x12345678 5 -. 41 8D 45 1F C3 - -leal 34(%rbp), %edx -. 309 0x12345678 4 -. 8D 55 22 C3 - -leal 35(%rbp), %eax -. 310 0x12345678 4 -. 8D 45 23 C3 - -leal -3(%rbx), %eax -. 311 0x12345678 4 -. 8D 43 FD C3 - -leal 48(%rax), %esi -. 312 0x12345678 4 -. 8D 70 30 C3 - -leal -4(%r14), %edi -. 313 0x12345678 5 -. 41 8D 7E FC C3 - -leal 4(%rdi), %ecx -. 314 0x12345678 4 -. 8D 4F 04 C3 - -leal 7(%rcx), %eax -. 315 0x12345678 4 -. 8D 41 07 C3 - -leal 8(%r8), %r11d -. 316 0x12345678 5 -. 45 8D 58 08 C3 - -leal (%r10,%r13), %ecx -. 317 0x12345678 5 -. 43 8D 0C 2A C3 - -leal (%r12,%r8), %eax -. 318 0x12345678 5 -. 43 8D 04 04 C3 - -leal (%r13,%rdi,2), %edx -. 319 0x12345678 6 -. 41 8D 54 7D 00 C3 - -leal (%r13,%rsi), %eax -. 320 0x12345678 6 -. 41 8D 44 35 00 C3 - -leal (%r14,%r13), %eax -. 321 0x12345678 5 -. 43 8D 04 2E C3 - -leal (%r8,%r10), %eax -. 322 0x12345678 5 -. 43 8D 04 10 C3 - -leal (%r8,%rdx), %eax -. 323 0x12345678 5 -. 41 8D 04 10 C3 - -leal (%r9,%r15), %edi -. 324 0x12345678 5 -. 43 8D 3C 39 C3 - -leal (%rax,%r10), %eax -. 325 0x12345678 5 -. 42 8D 04 10 C3 - -leal (%rax,%r14), %r15d -. 326 0x12345678 5 -. 46 8D 3C 30 C3 - -leal (%rax,%r8), %eax -. 327 0x12345678 5 -. 42 8D 04 00 C3 - -leal (%rax,%r9), %eax -. 328 0x12345678 5 -. 42 8D 04 08 C3 - -leal (%rax,%rax,2), %eax -. 329 0x12345678 4 -. 8D 04 40 C3 - -leal (%rax,%rdi), %eax -. 330 0x12345678 4 -. 8D 04 38 C3 - -leal (%rax,%rdx), %eax -. 331 0x12345678 4 -. 8D 04 10 C3 - -leal (%rcx,%r9), %eax -. 332 0x12345678 5 -. 42 8D 04 09 C3 - -leal (%rdi,%r13), %eax -. 333 0x12345678 5 -. 42 8D 04 2F C3 - -leal (%rdx,%r13), %eax -. 334 0x12345678 5 -. 42 8D 04 2A C3 - -leal (%rdx,%r8), %edx -. 335 0x12345678 5 -. 42 8D 14 02 C3 - -leal (%rdx,%r9), %edx -. 336 0x12345678 5 -. 42 8D 14 0A C3 - -leal (%rdx,%rcx), %eax -. 337 0x12345678 4 -. 8D 04 0A C3 - -leal (%rdx,%rdi), %edx -. 338 0x12345678 4 -. 8D 14 3A C3 - -leal (%rsi,%r13), %eax -. 339 0x12345678 5 -. 42 8D 04 2E C3 - -leal (%rsi,%r15), %eax -. 340 0x12345678 5 -. 42 8D 04 3E C3 - -leal (%rsi,%rcx), %eax -. 341 0x12345678 4 -. 8D 04 0E C3 - -leal (%rsi,%rsi,2), %eax -. 342 0x12345678 4 -. 8D 04 76 C3 - -leaq 1(%r11), %rdx -. 343 0x12345678 5 -. 49 8D 53 01 C3 - -leaq 20(%rsp), %rax -. 344 0x12345678 6 -. 48 8D 44 24 14 C3 - -leaq 37696(%rcx,%rax), %r10 -. 345 0x12345678 9 -. 4C 8D 94 01 40 93 00 00 C3 - -leaq 37696(%rcx,%rax), %r9 -. 346 0x12345678 9 -. 4C 8D 8C 01 40 93 00 00 C3 - -leaq 37708(%rbp,%rax,2), %rdi -. 347 0x12345678 9 -. 48 8D BC 45 4C 93 00 00 C3 - -leaq 37708(%rbp,%rdi,2), %rdi -. 348 0x12345678 9 -. 48 8D BC 7D 4C 93 00 00 C3 - -leaq 37708(%rbp,%rdi,2), %rsi -. 349 0x12345678 9 -. 48 8D B4 7D 4C 93 00 00 C3 - -leaq 39256(%rbp,%rax,8), %r8 -. 350 0x12345678 9 -. 4C 8D 84 C5 58 99 00 00 C3 - -leaq 39256(%rbp,%rdi,8), %rdi -. 351 0x12345678 9 -. 48 8D BC FD 58 99 00 00 C3 - -leaq 45448(%rbp,%rdi,8), %rsi -. 352 0x12345678 9 -. 48 8D B4 FD 88 B1 00 00 C3 - -leaq (%rax,%rax), %rdx -. 353 0x12345678 5 -. 48 8D 14 00 C3 - -leaq (%rax,%rdx), %rax -. 354 0x12345678 5 -. 48 8D 04 10 C3 - -leaq (%rbp,%rax,2), %r13 -. 355 0x12345678 6 -. 4C 8D 6C 45 00 C3 - -leaq (%rbp,%rax,2), %rax -. 356 0x12345678 6 -. 48 8D 44 45 00 C3 - -leaq (%rbp,%rax,2), %rcx -. 357 0x12345678 6 -. 48 8D 4C 45 00 C3 - -leaq (%rbp,%rax,2), %rdx -. 358 0x12345678 6 -. 48 8D 54 45 00 C3 - -leaq (%rbp,%rax), %rdx -. 359 0x12345678 6 -. 48 8D 54 05 00 C3 - -leaq (%rbp,%rdx,2), %rdx -. 360 0x12345678 6 -. 48 8D 54 55 00 C3 - -leaq (%rdx,%rsi), %rdx -. 361 0x12345678 5 -. 48 8D 14 32 C3 - -movb $0, 2112(%rsp,%rax) -. 362 0x12345678 9 -. C6 84 04 40 08 00 00 00 C3 - -movb $0, 32(%rsp,%rax) -. 363 0x12345678 6 -. C6 44 04 20 00 C3 - -movb $0, 37450(%rax,%rcx) -. 364 0x12345678 9 -. C6 84 08 4A 92 00 00 00 C3 - -movb $1, 2112(%rsp,%rax) -. 365 0x12345678 9 -. C6 84 04 40 08 00 00 01 C3 - -movb $1, 32(%rsp,%rcx) -. 366 0x12345678 6 -. C6 44 0C 20 01 C3 - -movb $15, 37450(%rax,%rcx) -. 367 0x12345678 9 -. C6 84 08 4A 92 00 00 0F C3 - -movb $15, 37708(%rax,%rdx) -. 368 0x12345678 9 -. C6 84 10 4C 93 00 00 0F C3 - -movb %al, 1(%rsp) -. 369 0x12345678 5 -. 88 44 24 01 C3 - -movb %al, 384(%rdi,%rdx) -. 370 0x12345678 8 -. 88 84 17 80 01 00 00 C3 - -movb %al, (%rcx,%rdx) -. 371 0x12345678 4 -. 88 04 11 C3 - -movb %al, (%rdx) -. 372 0x12345678 3 -. 88 02 C3 - -movb %cl, 32(%rsp) -. 373 0x12345678 5 -. 88 4C 24 20 C3 - -movb %cl, (%rsp) -. 374 0x12345678 4 -. 88 0C 24 C3 - -movb %dil, 32(%rsp,%rax) -. 375 0x12345678 6 -. 40 88 7C 04 20 C3 - -movb %dl, 1704(%rbp,%rax) -. 376 0x12345678 8 -. 88 94 05 A8 06 00 00 C3 - -movb %dl, 32(%rsp,%rax) -. 377 0x12345678 5 -. 88 54 04 20 C3 - -movb %dl, (%rax,%rsi) -. 378 0x12345678 4 -. 88 14 30 C3 - -movb %r8b, 19706(%rbp,%rax) -. 379 0x12345678 9 -. 44 88 84 05 FA 4C 00 00 C3 - -movb %r9b, (%rsp,%rax) -. 380 0x12345678 5 -. 44 88 0C 04 C3 - -mov %eax, %eax -. 381 0x12345678 3 -. 89 C0 C3 - -mov %edi, %eax -. 382 0x12345678 3 -. 89 F8 C3 - -mov %esi, %eax -. 383 0x12345678 3 -. 89 F0 C3 - -movl $0, 1056(%rsp,%rax,4) -. 384 0x12345678 12 -. C7 84 84 20 04 00 00 00 00 00 00 C3 - -movl $0, 116(%rdi) -. 385 0x12345678 8 -. C7 47 74 00 00 00 00 C3 - -movl $0, 124(%rdi) -. 386 0x12345678 8 -. C7 47 7C 00 00 00 00 C3 - -movl $0, 12(%rsp) -. 387 0x12345678 9 -. C7 44 24 0C 00 00 00 00 C3 - -movl $0, 24(%rsp) -. 388 0x12345678 9 -. C7 44 24 18 00 00 00 00 C3 - -movl $0, 28(%rsp) -. 389 0x12345678 9 -. C7 44 24 1C 00 00 00 00 C3 - -movl $0, 45448(%rbp,%rax,4) -. 390 0x12345678 12 -. C7 84 85 88 B1 00 00 00 00 00 00 C3 - -movl $0, 48(%rsp,%rax,4) -. 391 0x12345678 9 -. C7 44 84 30 00 00 00 00 C3 - -movl $0, 640(%rdi) -. 392 0x12345678 11 -. C7 87 80 02 00 00 00 00 00 00 C3 - -movl $0, 644(%rdi) -. 393 0x12345678 11 -. C7 87 84 02 00 00 00 00 00 00 C3 - -movl $0, 672(%rbx,%rax,4) -. 394 0x12345678 12 -. C7 84 83 A0 02 00 00 00 00 00 00 C3 - -movl $0, 8(%rsp) -. 395 0x12345678 9 -. C7 44 24 08 00 00 00 00 C3 - -movl $0, %eax -. 396 0x12345678 6 -. B8 00 00 00 00 C3 - -movl $0, %ebx -. 397 0x12345678 6 -. BB 00 00 00 00 C3 - -movl $0, %ecx -. 398 0x12345678 6 -. B9 00 00 00 00 C3 - -movl $0, %edi -. 399 0x12345678 6 -. BF 00 00 00 00 C3 - -movl $0, %edx -. 400 0x12345678 6 -. BA 00 00 00 00 C3 - -movl $0, %r12d -. 401 0x12345678 7 -. 41 BC 00 00 00 00 C3 - -movl $0, %r13d -. 402 0x12345678 7 -. 41 BD 00 00 00 00 C3 - -movl $0, %r8d -. 403 0x12345678 7 -. 41 B8 00 00 00 00 C3 - -movl $0, %r9d -. 404 0x12345678 7 -. 41 B9 00 00 00 00 C3 - -movl $0, (%rbp,%rax,4) -. 405 0x12345678 9 -. C7 44 85 00 00 00 00 00 C3 - -movl $0, (%rbx,%rax,4) -. 406 0x12345678 8 -. C7 04 83 00 00 00 00 C3 - -movl $1001, %edi -. 407 0x12345678 6 -. BF E9 03 00 00 C3 - -movl $1002, %edi -. 408 0x12345678 6 -. BF EA 03 00 00 C3 - -movl $1003, %edi -. 409 0x12345678 6 -. BF EB 03 00 00 C3 - -movl $1004, %edi -. 410 0x12345678 6 -. BF EC 03 00 00 C3 - -movl $1005, %edi -. 411 0x12345678 6 -. BF ED 03 00 00 C3 - -movl $1006, %edi -. 412 0x12345678 6 -. BF EE 03 00 00 C3 - -movl $1007, %edi -. 413 0x12345678 6 -. BF EF 03 00 00 C3 - -movl $100, %eax -. 414 0x12345678 6 -. B8 64 00 00 00 C3 - -movl $104, %esi -. 415 0x12345678 6 -. BE 68 00 00 00 C3 - -movl 1056(%rsp,%rax,4), %ecx -. 416 0x12345678 8 -. 8B 8C 84 20 04 00 00 C3 - -movl 1056(%rsp,%rax,4), %esi -. 417 0x12345678 8 -. 8B B4 84 20 04 00 00 C3 - -movl 1056(%rsp,%rdx,4), %eax -. 418 0x12345678 8 -. 8B 84 94 20 04 00 00 C3 - -movl 1088(%rsp,%rdx,4), %eax -. 419 0x12345678 8 -. 8B 84 94 40 04 00 00 C3 - -movl 1088(%rsp,%rsi,4), %eax -. 420 0x12345678 8 -. 8B 84 B4 40 04 00 00 C3 - -movl 108(%rbx), %r9d -. 421 0x12345678 5 -. 44 8B 4B 6C C3 - -movl 108(%rdi), %ebp -. 422 0x12345678 4 -. 8B 6F 6C C3 - -movl 108(%rdi), %edx -. 423 0x12345678 4 -. 8B 57 6C C3 - -movl $10, %edi -. 424 0x12345678 6 -. BF 0A 00 00 00 C3 - -movl $1, 12(%rsp) -. 425 0x12345678 9 -. C7 44 24 0C 01 00 00 00 C3 - -movl 112(%rsp), %eax -. 426 0x12345678 5 -. 8B 44 24 70 C3 - -movl 112(%rsp), %edi -. 427 0x12345678 5 -. 8B 7C 24 70 C3 - -movl $114, %esi -. 428 0x12345678 6 -. BE 72 00 00 00 C3 - -movl 116(%rbp), %eax -. 429 0x12345678 4 -. 8B 45 74 C3 - -movl 116(%rbp), %edx -. 430 0x12345678 4 -. 8B 55 74 C3 - -movl $1, 16(%rsp) -. 431 0x12345678 9 -. C7 44 24 10 01 00 00 00 C3 - -movl 124(%rbp), %eax -. 432 0x12345678 4 -. 8B 45 7C C3 - -movl 124(%rbx), %edx -. 433 0x12345678 4 -. 8B 53 7C C3 - -movl 124(%rbx), %r10d -. 434 0x12345678 5 -. 44 8B 53 7C C3 - -movl 124(%rdi), %r8d -. 435 0x12345678 5 -. 44 8B 47 7C C3 - -movl $1, 24(%rsp) -. 436 0x12345678 9 -. C7 44 24 18 01 00 00 00 C3 - -movl 12(%rsp), %eax -. 437 0x12345678 5 -. 8B 44 24 0C C3 - -movl 12(%rsp), %edx -. 438 0x12345678 5 -. 8B 54 24 0C C3 - -movl 12(%rsp), %r8d -. 439 0x12345678 6 -. 44 8B 44 24 0C C3 - -movl 1360(%rsp), %eax -. 440 0x12345678 8 -. 8B 84 24 50 05 00 00 C3 - -movl $144, %esi -. 441 0x12345678 6 -. BE 90 00 00 00 C3 - -movl $-1, 48(%rbx) -. 442 0x12345678 8 -. C7 43 30 FF FF FF FF C3 - -movl $15, %r8d -. 443 0x12345678 7 -. 41 B8 0F 00 00 00 C3 - -movl 16(%rsp), %edx -. 444 0x12345678 5 -. 8B 54 24 10 C3 - -movl 16(%rsp,%rax,4), %r14d -. 445 0x12345678 6 -. 44 8B 74 84 10 C3 - -movl $17, %ecx -. 446 0x12345678 6 -. B9 11 00 00 00 C3 - -movl $1, %eax -. 447 0x12345678 6 -. B8 01 00 00 00 C3 - -movl $-1, %ebp -. 448 0x12345678 6 -. BD FF FF FF FF C3 - -movl $1, %ebx -. 449 0x12345678 6 -. BB 01 00 00 00 C3 - -movl $-1, %ecx -. 450 0x12345678 6 -. B9 FF FF FF FF C3 - -movl $1, %edi -. 451 0x12345678 6 -. BF 01 00 00 00 C3 - -movl $-1, %edx -. 452 0x12345678 6 -. BA FF FF FF FF C3 - -movl $1, %edx -. 453 0x12345678 6 -. BA 01 00 00 00 C3 - -movl $1, %esi -. 454 0x12345678 6 -. BE 01 00 00 00 C3 - -movl $1, %r14d -. 455 0x12345678 7 -. 41 BE 01 00 00 00 C3 - -movl $1, %r8d -. 456 0x12345678 7 -. 41 B8 01 00 00 00 C3 - -movl $1, %r9d -. 457 0x12345678 7 -. 41 B9 01 00 00 00 C3 - -movl $-2097153, %esi -. 458 0x12345678 6 -. BE FF FF DF FF C3 - -movl 20(%rsp), %eax -. 459 0x12345678 5 -. 8B 44 24 14 C3 - -movl 20(%rsp), %ecx -. 460 0x12345678 5 -. 8B 4C 24 14 C3 - -movl 20(%rsp), %edx -. 461 0x12345678 5 -. 8B 54 24 14 C3 - -movl 20(%rsp), %esi -. 462 0x12345678 5 -. 8B 74 24 14 C3 - -movl 20(%rsp), %r11d -. 463 0x12345678 6 -. 44 8B 5C 24 14 C3 - -movl 20(%rsp), %r12d -. 464 0x12345678 6 -. 44 8B 64 24 14 C3 - -movl 20(%rsp), %r8d -. 465 0x12345678 6 -. 44 8B 44 24 14 C3 - -movl 20(%rsp), %r9d -. 466 0x12345678 6 -. 44 8B 4C 24 14 C3 - -movl 2368(%rsp,%rax,4), %eax -. 467 0x12345678 8 -. 8B 84 84 40 09 00 00 C3 - -movl 2368(%rsp,%rax,4), %edx -. 468 0x12345678 8 -. 8B 94 84 40 09 00 00 C3 - -movl 2368(%rsp,%rax,4), %r13d -. 469 0x12345678 9 -. 44 8B AC 84 40 09 00 00 C3 - -movl 2368(%rsp,%rax,4), %r8d -. 470 0x12345678 9 -. 44 8B 84 84 40 09 00 00 C3 - -movl $23, %esi -. 471 0x12345678 6 -. BE 17 00 00 00 C3 - -movl $24, %r8d -. 472 0x12345678 7 -. 41 B8 18 00 00 00 C3 - -movl 24(%rsp), %ecx -. 473 0x12345678 5 -. 8B 4C 24 18 C3 - -movl 24(%rsp), %edi -. 474 0x12345678 5 -. 8B 7C 24 18 C3 - -movl 24(%rsp), %r8d -. 475 0x12345678 6 -. 44 8B 44 24 18 C3 - -movl $27, %edx -. 476 0x12345678 6 -. BA 1B 00 00 00 C3 - -movl $2863311531, %edx -. 477 0x12345678 6 -. BA AB AA AA AA C3 - -movl 28(%rsp), %ecx -. 478 0x12345678 5 -. 8B 4C 24 1C C3 - -movl 28(%rsp), %edi -. 479 0x12345678 5 -. 8B 7C 24 1C C3 - -movl 28(%rsp), %edx -. 480 0x12345678 5 -. 8B 54 24 1C C3 - -movl 28(%rsp), %r12d -. 481 0x12345678 6 -. 44 8B 64 24 1C C3 - -movl $2, %r10d -. 482 0x12345678 7 -. 41 BA 02 00 00 00 C3 - -movl $2, %r14d -. 483 0x12345678 7 -. 41 BE 02 00 00 00 C3 - -movl $2, %r9d -. 484 0x12345678 7 -. 41 B9 02 00 00 00 C3 - -movl $2, (%rsp) -. 485 0x12345678 8 -. C7 04 24 02 00 00 00 C3 - -movl $3001, %edi -. 486 0x12345678 6 -. BF B9 0B 00 00 C3 - -movl $3002, %edi -. 487 0x12345678 6 -. BF BA 0B 00 00 C3 - -movl $3003, %edi -. 488 0x12345678 6 -. BF BB 0B 00 00 C3 - -movl $3004, %edi -. 489 0x12345678 6 -. BF BC 0B 00 00 C3 - -movl $3005, %edi -. 490 0x12345678 6 -. BF BD 0B 00 00 C3 - -movl $3006, %edi -. 491 0x12345678 6 -. BF BE 0B 00 00 C3 - -movl $3007, %edi -. 492 0x12345678 6 -. BF BF 0B 00 00 C3 - -movl $32, %r13d -. 493 0x12345678 7 -. 41 BD 20 00 00 00 C3 - -movl 32(%rsp), %eax -. 494 0x12345678 5 -. 8B 44 24 20 C3 - -movl 32(%rsp), %r13d -. 495 0x12345678 6 -. 44 8B 6C 24 20 C3 - -movl $33, %edx -. 496 0x12345678 6 -. BA 21 00 00 00 C3 - -movl 36(%rsp), %eax -. 497 0x12345678 5 -. 8B 44 24 24 C3 - -movl 36(%rsp), %ebx -. 498 0x12345678 5 -. 8B 5C 24 24 C3 - -movl 36(%rsp), %ecx -. 499 0x12345678 5 -. 8B 4C 24 24 C3 - -movl 36(%rsp), %edx -. 500 0x12345678 5 -. 8B 54 24 24 C3 - -movl 36(%rsp), %esi -. 501 0x12345678 5 -. 8B 74 24 24 C3 - -movl 36(%rsp), %r8d -. 502 0x12345678 6 -. 44 8B 44 24 24 C3 - -movl $38, %esi -. 503 0x12345678 6 -. BE 26 00 00 00 C3 - -movl 39256(%rbp,%rax,4), %r9d -. 504 0x12345678 9 -. 44 8B 8C 85 58 99 00 00 C3 - -movl $3, %r12d -. 505 0x12345678 7 -. 41 BC 03 00 00 00 C3 - -movl $3, %r14d -. 506 0x12345678 7 -. 41 BE 03 00 00 00 C3 - -movl $3, %r8d -. 507 0x12345678 7 -. 41 B8 03 00 00 00 C3 - -movl 416(%rsp,%rax,4), %r13d -. 508 0x12345678 9 -. 44 8B AC 84 A0 01 00 00 C3 - -movl 48(%rbx), %edi -. 509 0x12345678 4 -. 8B 7B 30 C3 - -movl 48(%rsp), %eax -. 510 0x12345678 5 -. 8B 44 24 30 C3 - -movl 48(%rsp), %edx -. 511 0x12345678 5 -. 8B 54 24 30 C3 - -movl 48(%rsp,%rax,4), %edx -. 512 0x12345678 5 -. 8B 54 84 30 C3 - -movl 496(%rsp,%rax,4), %edx -. 513 0x12345678 8 -. 8B 94 84 F0 01 00 00 C3 - -movl $49, %esi -. 514 0x12345678 6 -. BE 31 00 00 00 C3 - -movl $4, %r14d -. 515 0x12345678 7 -. 41 BE 04 00 00 00 C3 - -movl 4(%rbp,%rax,4), %eax -. 516 0x12345678 5 -. 8B 44 85 04 C3 - -movl 4(%rbp,%rdx,4), %eax -. 517 0x12345678 5 -. 8B 44 95 04 C3 - -movl 51640(%rax), %ecx -. 518 0x12345678 7 -. 8B 88 B8 C9 00 00 C3 - -movl 51644(%rax), %esi -. 519 0x12345678 7 -. 8B B0 BC C9 00 00 C3 - -movl 51648(%rax), %edi -. 520 0x12345678 7 -. 8B B8 C0 C9 00 00 C3 - -movl 52(%rsp), %eax -. 521 0x12345678 5 -. 8B 44 24 34 C3 - -movl 52(%rsp), %edx -. 522 0x12345678 5 -. 8B 54 24 34 C3 - -movl $53, %edx -. 523 0x12345678 6 -. BA 35 00 00 00 C3 - -movl $56, %esi -. 524 0x12345678 6 -. BE 38 00 00 00 C3 - -movl 56(%rsp), %eax -. 525 0x12345678 5 -. 8B 44 24 38 C3 - -movl 644(%r11), %eax -. 526 0x12345678 8 -. 41 8B 83 84 02 00 00 C3 - -movl 644(%rdi), %eax -. 527 0x12345678 7 -. 8B 87 84 02 00 00 C3 - -movl 644(%rsi), %eax -. 528 0x12345678 7 -. 8B 86 84 02 00 00 C3 - -movl 644(%rsi), %edx -. 529 0x12345678 7 -. 8B 96 84 02 00 00 C3 - -movl 648(%rbx), %ecx -. 530 0x12345678 7 -. 8B 8B 88 02 00 00 C3 - -movl 648(%rbx), %esi -. 531 0x12345678 7 -. 8B B3 88 02 00 00 C3 - -movl 648(%rdi), %edx -. 532 0x12345678 7 -. 8B 97 88 02 00 00 C3 - -movl 64(%rsp), %eax -. 533 0x12345678 5 -. 8B 44 24 40 C3 - -movl 64(%rsp), %r8d -. 534 0x12345678 6 -. 44 8B 44 24 40 C3 - -movl 64(%rsp,%rsi,4), %eax -. 535 0x12345678 5 -. 8B 44 B4 40 C3 - -movl 652(%rbx), %edx -. 536 0x12345678 7 -. 8B 93 8C 02 00 00 C3 - -movl 652(%rbx), %esi -. 537 0x12345678 7 -. 8B B3 8C 02 00 00 C3 - -movl 652(%rbx), %r8d -. 538 0x12345678 8 -. 44 8B 83 8C 02 00 00 C3 - -movl 652(%rdi), %eax -. 539 0x12345678 7 -. 8B 87 8C 02 00 00 C3 - -movl $65536, %ebx -. 540 0x12345678 6 -. BB 00 00 01 00 C3 - -movl 656(%rdi), %r13d -. 541 0x12345678 8 -. 44 8B AF 90 02 00 00 C3 - -movl $65, %esi -. 542 0x12345678 6 -. BE 41 00 00 00 C3 - -movl 660(%rbx), %edx -. 543 0x12345678 7 -. 8B 93 94 02 00 00 C3 - -movl 668(%rbp), %edx -. 544 0x12345678 7 -. 8B 95 9C 02 00 00 C3 - -movl 668(%rbp), %r12d -. 545 0x12345678 8 -. 44 8B A5 9C 02 00 00 C3 - -movl 668(%rdi), %ecx -. 546 0x12345678 7 -. 8B 8F 9C 02 00 00 C3 - -movl $66, %esi -. 547 0x12345678 6 -. BE 42 00 00 00 C3 - -movl 68(%rsp), %eax -. 548 0x12345678 5 -. 8B 44 24 44 C3 - -movl 68(%rsp), %esi -. 549 0x12345678 5 -. 8B 74 24 44 C3 - -###movl 68(%rsp), %r8d -###. 550 0x12345678 5 -###. 44 8B 44 24 C3 - -movl $69, %esi -. 551 0x12345678 6 -. BE 45 00 00 00 C3 - -movl 72(%rsp), %eax -. 552 0x12345678 5 -. 8B 44 24 48 C3 - -movl 72(%rsp), %esi -. 553 0x12345678 5 -. 8B 74 24 48 C3 - -movl $80, %esi -. 554 0x12345678 6 -. BE 50 00 00 00 C3 - -movl 80(%rsp), %eax -. 555 0x12345678 5 -. 8B 44 24 50 C3 - -movl 80(%rsp), %edi -. 556 0x12345678 5 -. 8B 7C 24 50 C3 - -movl $83, %esi -. 557 0x12345678 6 -. BE 53 00 00 00 C3 - -movl 84(%rsp), %eax -. 558 0x12345678 5 -. 8B 44 24 54 C3 - -movl 84(%rsp), %ecx -. 559 0x12345678 5 -. 8B 4C 24 54 C3 - -movl 84(%rsp), %edi -. 560 0x12345678 5 -. 8B 7C 24 54 C3 - -movl 88(%rdi), %ecx -. 561 0x12345678 4 -. 8B 4F 58 C3 - -movl 88(%rsp), %eax -. 562 0x12345678 5 -. 8B 44 24 58 C3 - -movl 88(%rsp), %ecx -. 563 0x12345678 5 -. 8B 4C 24 58 C3 - -movl 896(%rsp,%rax,4), %r15d -. 564 0x12345678 9 -. 44 8B BC 84 80 03 00 00 C3 - -movl $89, %esi -. 565 0x12345678 6 -. BE 59 00 00 00 C3 - -movl $8, %r8d -. 566 0x12345678 7 -. 41 B8 08 00 00 00 C3 - -movl $8, %r9d -. 567 0x12345678 7 -. 41 B9 08 00 00 00 C3 - -movl 8(%rsp), %edx -. 568 0x12345678 5 -. 8B 54 24 08 C3 - -movl $90, %esi -. 569 0x12345678 6 -. BE 5A 00 00 00 C3 - -movl 96(%rsp,%rax,4), %r13d -. 570 0x12345678 6 -. 44 8B 6C 84 60 C3 - -movl $999999999, %ecx -. 571 0x12345678 6 -. B9 FF C9 9A 3B C3 - -movl %eax, 1056(%rsp,%rdx,4) -. 572 0x12345678 8 -. 89 84 94 20 04 00 00 C3 - -movl %eax, 1088(%rsp,%rsi,4) -. 573 0x12345678 8 -. 89 84 B4 40 04 00 00 C3 - -movl %eax, 12(%rsp) -. 574 0x12345678 5 -. 89 44 24 0C C3 - -movl %eax, -16(%rsi,%rdx,4) -. 575 0x12345678 5 -. 89 44 96 F0 C3 - -movl %eax, 16(%rsp) -. 576 0x12345678 5 -. 89 44 24 10 C3 - -movl %eax, 20(%rsp) -. 577 0x12345678 5 -. 89 44 24 14 C3 - -movl %eax, 2368(%rsp,%rcx,4) -. 578 0x12345678 8 -. 89 84 8C 40 09 00 00 C3 - -movl %eax, 28(%rsp) -. 579 0x12345678 5 -. 89 44 24 1C C3 - -movl %eax, 32(%rsp,%rdx,4) -. 580 0x12345678 5 -. 89 44 94 20 C3 - -movl %eax, 48(%rsp) -. 581 0x12345678 5 -. 89 44 24 30 C3 - -movl %eax, 496(%rsp,%rdx,4) -. 582 0x12345678 8 -. 89 84 94 F0 01 00 00 C3 - -movl %eax, -4(%rsi,%rdx,4) -. 583 0x12345678 5 -. 89 44 96 FC C3 - -movl %eax, 51640(%rsi) -. 584 0x12345678 7 -. 89 86 B8 C9 00 00 C3 - -movl %eax, 51644(%rsi) -. 585 0x12345678 7 -. 89 86 BC C9 00 00 C3 - -movl %eax, 51648(%rsi) -. 586 0x12345678 7 -. 89 86 C0 C9 00 00 C3 - -movl %eax, 52(%rsp) -. 587 0x12345678 5 -. 89 44 24 34 C3 - -movl %eax, 56(%rsp) -. 588 0x12345678 5 -. 89 44 24 38 C3 - -movl %eax, 644(%r11) -. 589 0x12345678 8 -. 41 89 83 84 02 00 00 C3 - -movl %eax, 644(%rdi) -. 590 0x12345678 7 -. 89 87 84 02 00 00 C3 - -movl %eax, 644(%rsi) -. 591 0x12345678 7 -. 89 86 84 02 00 00 C3 - -movl %eax, 64(%rsp,%rcx,4) -. 592 0x12345678 5 -. 89 44 8C 40 C3 - -movl %eax, 64(%rsp,%rsi,4) -. 593 0x12345678 5 -. 89 44 B4 40 C3 - -movl %eax, 652(%rdi) -. 594 0x12345678 7 -. 89 87 8C 02 00 00 C3 - -movl %eax, 72(%rsp) -. 595 0x12345678 5 -. 89 44 24 48 C3 - -movl %eax, 88(%rsp) -. 596 0x12345678 5 -. 89 44 24 58 C3 - -movl %eax, 896(%rsp,%rdx,4) -. 597 0x12345678 8 -. 89 84 94 80 03 00 00 C3 - -movl %eax, 8(%rsp) -. 598 0x12345678 5 -. 89 44 24 08 C3 - -movl %eax, 96(%rsp) -. 599 0x12345678 5 -. 89 44 24 60 C3 - -movl %eax, 96(%rsp,%rdx,4) -. 600 0x12345678 5 -. 89 44 94 60 C3 - -movl %eax, %ecx -. 601 0x12345678 3 -. 89 C1 C3 - -movl %eax, %edi -. 602 0x12345678 3 -. 89 C7 C3 - -movl %eax, %edx -. 603 0x12345678 3 -. 89 C2 C3 - -movl %eax, %esi -. 604 0x12345678 3 -. 89 C6 C3 - -movl %eax, %r15d -. 605 0x12345678 4 -. 41 89 C7 C3 - -movl %eax, (%rbp,%rcx,4) -. 606 0x12345678 5 -. 89 44 8D 00 C3 - -movl %eax, (%rbp,%rdx,4) -. 607 0x12345678 5 -. 89 44 95 00 C3 - -movl %eax, (%rbx,%rcx,4) -. 608 0x12345678 4 -. 89 04 8B C3 - -movl %eax, (%rbx,%rsi,4) -. 609 0x12345678 4 -. 89 04 B3 C3 - -movl %eax, (%rdi,%rdx,4) -. 610 0x12345678 4 -. 89 04 97 C3 - -movl %ebp, %eax -. 611 0x12345678 3 -. 89 E8 C3 - -movl %ebp, %ecx -. 612 0x12345678 3 -. 89 E9 C3 - -movl %ebp, %esi -. 613 0x12345678 3 -. 89 EE C3 - -movl %ebp, %r12d -. 614 0x12345678 4 -. 41 89 EC C3 - -movl %ebp, %r8d -. 615 0x12345678 4 -. 41 89 E8 C3 - -movl %ebx, 2368(%rsp,%rax,4) -. 616 0x12345678 8 -. 89 9C 84 40 09 00 00 C3 - -movl %ebx, %eax -. 617 0x12345678 3 -. 89 D8 C3 - -movl %ebx, %edx -. 618 0x12345678 3 -. 89 DA C3 - -movl %ebx, %esi -. 619 0x12345678 3 -. 89 DE C3 - -movl %ebx, %r12d -. 620 0x12345678 4 -. 41 89 DC C3 - -movl %ebx, %r8d -. 621 0x12345678 4 -. 41 89 D8 C3 - -movl %ebx, (%rdi,%rax,4) -. 622 0x12345678 4 -. 89 1C 87 C3 - -movl %ecx, 16(%rsp) -. 623 0x12345678 5 -. 89 4C 24 10 C3 - -movl %ecx, 16(%rsp,%rax,4) -. 624 0x12345678 5 -. 89 4C 84 10 C3 - -movl %ecx, 24(%rsp) -. 625 0x12345678 5 -. 89 4C 24 18 C3 - -movl %ecx, 28(%rsp) -. 626 0x12345678 5 -. 89 4C 24 1C C3 - -movl %ecx, 36(%rsp) -. 627 0x12345678 5 -. 89 4C 24 24 C3 - -movl %ecx, 80(%rsp) -. 628 0x12345678 5 -. 89 4C 24 50 C3 - -movl %ecx, 84(%rsp) -. 629 0x12345678 5 -. 89 4C 24 54 C3 - -movl %ecx, %eax -. 630 0x12345678 3 -. 89 C8 C3 - -movl %ecx, %ebx -. 631 0x12345678 3 -. 89 CB C3 - -movl %ecx, %edi -. 632 0x12345678 3 -. 89 CF C3 - -movl %ecx, %edx -. 633 0x12345678 3 -. 89 CA C3 - -movl %ecx, %r12d -. 634 0x12345678 4 -. 41 89 CC C3 - -movl %ecx, %r13d -. 635 0x12345678 4 -. 41 89 CD C3 - -movl %ecx, %r8d -. 636 0x12345678 4 -. 41 89 C8 C3 - -movl %ecx, (%r8,%rdx,4) -. 637 0x12345678 5 -. 41 89 0C 90 C3 - -movl %ecx, (%rbx,%rdx,4) -. 638 0x12345678 4 -. 89 0C 93 C3 - -movl %edi, 64(%rsp) -. 639 0x12345678 5 -. 89 7C 24 40 C3 - -movl %edi, 68(%rsp) -. 640 0x12345678 5 -. 89 7C 24 44 C3 - -movl %edi, 84(%rsp) -. 641 0x12345678 5 -. 89 7C 24 54 C3 - -movl %edi, 88(%rsp) -. 642 0x12345678 5 -. 89 7C 24 58 C3 - -movl %edi, %eax -. 643 0x12345678 3 -. 89 F8 C3 - -movl %edi, %ecx -. 644 0x12345678 3 -. 89 F9 C3 - -movl %edi, %edx -. 645 0x12345678 3 -. 89 FA C3 - -movl %edi, %r10d -. 646 0x12345678 4 -. 41 89 FA C3 - -movl %edi, %r11d -. 647 0x12345678 4 -. 41 89 FB C3 - -movl %edi, (%rsi,%rax,4) -. 648 0x12345678 4 -. 89 3C 86 C3 - -movl %edx, 1088(%rsp,%rcx,4) -. 649 0x12345678 8 -. 89 94 8C 40 04 00 00 C3 - -movl %edx, 12(%rsp) -. 650 0x12345678 5 -. 89 54 24 0C C3 - -movl %edx, 16(%rsp) -. 651 0x12345678 5 -. 89 54 24 10 C3 - -movl %edx, 20(%rsp) -. 652 0x12345678 5 -. 89 54 24 14 C3 - -movl %edx, 416(%rsp) -. 653 0x12345678 8 -. 89 94 24 A0 01 00 00 C3 - -movl %edx, 48(%rbx) -. 654 0x12345678 4 -. 89 53 30 C3 - -movl %edx, 496(%rsp,%rax,4) -. 655 0x12345678 8 -. 89 94 84 F0 01 00 00 C3 - -movl %edx, 52(%rsp) -. 656 0x12345678 5 -. 89 54 24 34 C3 - -movl %edx, 56(%rsp) -. 657 0x12345678 5 -. 89 54 24 38 C3 - -movl %edx, 644(%rsi) -. 658 0x12345678 7 -. 89 96 84 02 00 00 C3 - -movl %edx, 648(%rdi) -. 659 0x12345678 7 -. 89 97 88 02 00 00 C3 - -movl %edx, 96(%rsp,%rax,4) -. 660 0x12345678 5 -. 89 54 84 60 C3 - -movl %edx, %eax -. 661 0x12345678 3 -. 89 D0 C3 - -movl %edx, %ebp -. 662 0x12345678 3 -. 89 D5 C3 - -movl %edx, %ebx -. 663 0x12345678 3 -. 89 D3 C3 - -movl %edx, %ecx -. 664 0x12345678 3 -. 89 D1 C3 - -movl %edx, %edi -. 665 0x12345678 3 -. 89 D7 C3 - -movl %edx, %esi -. 666 0x12345678 3 -. 89 D6 C3 - -movl %edx, %r12d -. 667 0x12345678 4 -. 41 89 D4 C3 - -movl %edx, (%r15,%rax,4) -. 668 0x12345678 5 -. 41 89 14 87 C3 - -movl %esi, 1056(%rsp,%rax,4) -. 669 0x12345678 8 -. 89 B4 84 20 04 00 00 C3 - -movl %esi, 416(%rsp,%rax,4) -. 670 0x12345678 8 -. 89 B4 84 A0 01 00 00 C3 - -movl %esi, 64(%rsp) -. 671 0x12345678 5 -. 89 74 24 40 C3 - -movl %esi, 68(%rsp) -. 672 0x12345678 5 -. 89 74 24 44 C3 - -movl %esi, %eax -. 673 0x12345678 3 -. 89 F0 C3 - -movl %esi, %ebp -. 674 0x12345678 3 -. 89 F5 C3 - -movl %esi, %ebx -. 675 0x12345678 3 -. 89 F3 C3 - -movl %esi, %ecx -. 676 0x12345678 3 -. 89 F1 C3 - -movl %esi, %edx -. 677 0x12345678 3 -. 89 F2 C3 - -movl %esi, %r8d -. 678 0x12345678 4 -. 41 89 F0 C3 - -movl %esi, (%rbx,%rdx,4) -. 679 0x12345678 4 -. 89 34 93 C3 - -movl 12345(,%rax,4), %r12d -. 680 0x12345678 9 -. 44 8B 24 85 39 30 00 00 C3 - -movl $0x12345678, %esi -. 681 0x12345678 6 -. BE 78 56 34 12 C3 - -movl %r10d, %ecx -. 682 0x12345678 4 -. 44 89 D1 C3 - -movl %r10d, %r11d -. 683 0x12345678 4 -. 45 89 D3 C3 - -movl %r10d, %r9d -. 684 0x12345678 4 -. 45 89 D1 C3 - -movl (%r10,%rax,4), %r8d -. 685 0x12345678 5 -. 45 8B 04 82 C3 - -movl %r12d, 20(%rsp) -. 686 0x12345678 6 -. 44 89 64 24 14 C3 - -movl %r12d, 28(%rsp) -. 687 0x12345678 6 -. 44 89 64 24 1C C3 - -movl %r12d, %eax -. 688 0x12345678 4 -. 44 89 E0 C3 - -movl %r12d, %ecx -. 689 0x12345678 4 -. 44 89 E1 C3 - -movl %r12d, %edi -. 690 0x12345678 4 -. 44 89 E7 C3 - -movl %r12d, %edx -. 691 0x12345678 4 -. 44 89 E2 C3 - -movl %r12d, %esi -. 692 0x12345678 4 -. 44 89 E6 C3 - -movl %r12d, %r10d -. 693 0x12345678 4 -. 45 89 E2 C3 - -movl %r12d, %r8d -. 694 0x12345678 4 -. 45 89 E0 C3 - -movl %r12d, (%rbp,%rax,4) -. 695 0x12345678 6 -. 44 89 64 85 00 C3 - -movl (%r12,%rax,4), %ecx -. 696 0x12345678 5 -. 41 8B 0C 84 C3 - -movl %r13d, 416(%rsp,%rax,4) -. 697 0x12345678 9 -. 44 89 AC 84 A0 01 00 00 C3 - -movl %r13d, 48(%rsp) -. 698 0x12345678 6 -. 44 89 6C 24 30 C3 - -movl %r13d, 52(%rsp) -. 699 0x12345678 6 -. 44 89 6C 24 34 C3 - -movl %r13d, %eax -. 700 0x12345678 4 -. 44 89 E8 C3 - -movl %r13d, %ebp -. 701 0x12345678 4 -. 44 89 ED C3 - -movl %r13d, %ebx -. 702 0x12345678 4 -. 44 89 EB C3 - -movl %r13d, %edx -. 703 0x12345678 4 -. 44 89 EA C3 - -movl %r13d, %r10d -. 704 0x12345678 4 -. 45 89 EA C3 - -movl %r13d, %r11d -. 705 0x12345678 4 -. 45 89 EB C3 - -movl %r13d, %r12d -. 706 0x12345678 4 -. 45 89 EC C3 - -movl %r13d, %r8d -. 707 0x12345678 4 -. 45 89 E8 C3 - -movl %r13d, %r9d -. 708 0x12345678 4 -. 45 89 E9 C3 - -movl %r13d, (%rsp) -. 709 0x12345678 5 -. 44 89 2C 24 C3 - -movl %r14d, 16(%rsp,%rax,4) -. 710 0x12345678 6 -. 44 89 74 84 10 C3 - -movl %r14d, %eax -. 711 0x12345678 4 -. 44 89 F0 C3 - -movl %r14d, %ebp -. 712 0x12345678 4 -. 44 89 F5 C3 - -movl %r14d, %ebx -. 713 0x12345678 4 -. 44 89 F3 C3 - -movl %r14d, %edi -. 714 0x12345678 4 -. 44 89 F7 C3 - -movl %r14d, %edx -. 715 0x12345678 4 -. 44 89 F2 C3 - -movl %r14d, %esi -. 716 0x12345678 4 -. 44 89 F6 C3 - -movl %r14d, %r11d -. 717 0x12345678 4 -. 45 89 F3 C3 - -movl %r14d, %r8d -. 718 0x12345678 4 -. 45 89 F0 C3 - -movl %r14d, %r9d -. 719 0x12345678 4 -. 45 89 F1 C3 - -movl %r14d, (%rbp,%rax,4) -. 720 0x12345678 6 -. 44 89 74 85 00 C3 - -movl %r15d, 80(%rsp) -. 721 0x12345678 6 -. 44 89 7C 24 50 C3 - -movl %r15d, 84(%rsp) -. 722 0x12345678 6 -. 44 89 7C 24 54 C3 - -movl %r15d, 896(%rsp,%rax,4) -. 723 0x12345678 9 -. 44 89 BC 84 80 03 00 00 C3 - -movl %r15d, %ebp -. 724 0x12345678 4 -. 44 89 FD C3 - -movl %r15d, %esi -. 725 0x12345678 4 -. 44 89 FE C3 - -movl %r15d, %r14d -. 726 0x12345678 4 -. 45 89 FE C3 - -movl %r15d, %r8d -. 727 0x12345678 4 -. 45 89 F8 C3 - -movl %r15d, %r9d -. 728 0x12345678 4 -. 45 89 F9 C3 - -movl (%r15,%rax,4), %eax -. 729 0x12345678 5 -. 41 8B 04 87 C3 - -movl (%r15,%rax,4), %edx -. 730 0x12345678 5 -. 41 8B 14 87 C3 - -movl (%r15,%rax,4), %r8d -. 731 0x12345678 5 -. 45 8B 04 87 C3 - -movl %r8d, 12(%rsp) -. 732 0x12345678 6 -. 44 89 44 24 0C C3 - -movl %r8d, 20(%rsp) -. 733 0x12345678 6 -. 44 89 44 24 14 C3 - -movl %r8d, 2368(%rsp,%rax,4) -. 734 0x12345678 9 -. 44 89 84 84 40 09 00 00 C3 - -movl %r8d, 32(%rsp) -. 735 0x12345678 6 -. 44 89 44 24 20 C3 - -movl %r8d, 36(%rsp) -. 736 0x12345678 6 -. 44 89 44 24 24 C3 - -movl %r8d, 668(%rbx) -. 737 0x12345678 8 -. 44 89 83 9C 02 00 00 C3 - -movl %r8d, 68(%rsp) -. 738 0x12345678 6 -. 44 89 44 24 44 C3 - -movl %r8d, 72(%rsp) -. 739 0x12345678 6 -. 44 89 44 24 48 C3 - -movl %r8d, 896(%rsp) -. 740 0x12345678 9 -. 44 89 84 24 80 03 00 00 C3 - -movl %r8d, %edx -. 741 0x12345678 4 -. 44 89 C2 C3 - -movl %r8d, %esi -. 742 0x12345678 4 -. 44 89 C6 C3 - -movl (%r8,%rax,4), %ecx -. 743 0x12345678 5 -. 41 8B 0C 80 C3 - -movl (%r8,%rax,4), %r10d -. 744 0x12345678 5 -. 45 8B 14 80 C3 - -movl (%r8,%rax,4), %r8d -. 745 0x12345678 5 -. 45 8B 04 80 C3 - -movl %r9d, -16(%rsi,%rax,4) -. 746 0x12345678 6 -. 44 89 4C 86 F0 C3 - -movl %r9d, 28(%rsp) -. 747 0x12345678 6 -. 44 89 4C 24 1C C3 - -movl %r9d, 32(%rsp) -. 748 0x12345678 6 -. 44 89 4C 24 20 C3 - -movl %r9d, 496(%rsp) -. 749 0x12345678 9 -. 44 89 8C 24 F0 01 00 00 C3 - -movl %r9d, -4(%rsi,%rax,4) -. 750 0x12345678 6 -. 44 89 4C 86 FC C3 - -movl %r9d, %ebp -. 751 0x12345678 4 -. 44 89 CD C3 - -movl %r9d, %ecx -. 752 0x12345678 4 -. 44 89 C9 C3 - -movl %r9d, %edi -. 753 0x12345678 4 -. 44 89 CF C3 - -movl %r9d, %edx -. 754 0x12345678 4 -. 44 89 CA C3 - -movl %r9d, %r8d -. 755 0x12345678 4 -. 45 89 C8 C3 - -movl (%rbp,%rax,4), %eax -. 756 0x12345678 5 -. 8B 44 85 00 C3 - -movl (%rbp,%rax,4), %edx -. 757 0x12345678 5 -. 8B 54 85 00 C3 - -movl (%rbp,%rax,4), %r12d -. 758 0x12345678 6 -. 44 8B 64 85 00 C3 - -movl (%rbp,%rax,4), %r14d -. 759 0x12345678 6 -. 44 8B 74 85 00 C3 - -movl (%rbp,%rax), %eax -. 760 0x12345678 5 -. 8B 44 05 00 C3 - -movl (%rbp,%rax), %edx -. 761 0x12345678 5 -. 8B 54 05 00 C3 - -movl (%rbp,%rax), %r12d -. 762 0x12345678 6 -. 44 8B 64 05 00 C3 - -movl (%rbp,%rax), %r8d -. 763 0x12345678 6 -. 44 8B 44 05 00 C3 - -movl (%rbp,%rdx,4), %eax -. 764 0x12345678 5 -. 8B 44 95 00 C3 - -movl (%rbp,%rdx), %edx -. 765 0x12345678 5 -. 8B 54 15 00 C3 - -movl (%rbx,%rax,4), %edi -. 766 0x12345678 4 -. 8B 3C 83 C3 - -movl (%rbx,%rax,4), %edx -. 767 0x12345678 4 -. 8B 14 83 C3 - -movl (%rbx,%rcx,4), %esi -. 768 0x12345678 4 -. 8B 34 8B C3 - -movl (%rbx,%rdx,4), %eax -. 769 0x12345678 4 -. 8B 04 93 C3 - -movl (%rbx,%rsi,4), %ecx -. 770 0x12345678 4 -. 8B 0C B3 C3 - -movl (%rdx,%rax,4), %ecx -. 771 0x12345678 4 -. 8B 0C 82 C3 - -movl (%rsi,%rax,4), %r9d -. 772 0x12345678 5 -. 44 8B 0C 86 C3 - -movl (%rsi,%rdx,4), %eax -. 773 0x12345678 4 -. 8B 04 96 C3 - -movq 120(%rsp), %r9 -. 774 0x12345678 6 -. 4C 8B 4C 24 78 C3 - -movq 120(%rsp), %rax -. 775 0x12345678 6 -. 48 8B 44 24 78 C3 - -movq 1368(%rsp), %rdi -. 776 0x12345678 9 -. 48 8B BC 24 58 05 00 00 C3 - -movq 1368(%rsp), %rsi -. 777 0x12345678 9 -. 48 8B B4 24 58 05 00 00 C3 - -movq 24(%rbx), %rdi -. 778 0x12345678 5 -. 48 8B 7B 18 C3 - -movq 24(%rsp), %rbp -. 779 0x12345678 6 -. 48 8B 6C 24 18 C3 - -movq 24(%rsp), %rbx -. 780 0x12345678 6 -. 48 8B 5C 24 18 C3 - -movq 24(%rsp), %rcx -. 781 0x12345678 6 -. 48 8B 4C 24 18 C3 - -movq 24(%rsp), %rdi -. 782 0x12345678 6 -. 48 8B 7C 24 18 C3 - -movq 24(%rsp), %rdx -. 783 0x12345678 6 -. 48 8B 54 24 18 C3 - -movq 24(%rsp), %rsi -. 784 0x12345678 6 -. 48 8B 74 24 18 C3 - -movq 32(%rbx), %rsi -. 785 0x12345678 5 -. 48 8B 73 20 C3 - -movq 32(%rsp), %rbp -. 786 0x12345678 6 -. 48 8B 6C 24 20 C3 - -movq 32(%rsp), %rdx -. 787 0x12345678 6 -. 48 8B 54 24 20 C3 - -movq 3456(%rsp), %rdx -. 788 0x12345678 9 -. 48 8B 94 24 80 0D 00 00 C3 - -movq 3456(%rsp), %rsi -. 789 0x12345678 9 -. 48 8B B4 24 80 0D 00 00 C3 - -movq 40(%rdi), %r15 -. 790 0x12345678 5 -. 4C 8B 7F 28 C3 - -movq 40(%rsp), %r12 -. 791 0x12345678 6 -. 4C 8B 64 24 28 C3 - -movq 40(%rsp), %r8 -. 792 0x12345678 6 -. 4C 8B 44 24 28 C3 - -movq 40(%rsp), %rcx -. 793 0x12345678 6 -. 48 8B 4C 24 28 C3 - -movq 40(%rsp), %rdi -. 794 0x12345678 6 -. 48 8B 7C 24 28 C3 - -movq 40(%rsp), %rdx -. 795 0x12345678 6 -. 48 8B 54 24 28 C3 - -movq 40(%rsp), %rsi -. 796 0x12345678 6 -. 48 8B 74 24 28 C3 - -movq 48(%rsp), %r13 -. 797 0x12345678 6 -. 4C 8B 6C 24 30 C3 - -movq 48(%rsp), %r8 -. 798 0x12345678 6 -. 4C 8B 44 24 30 C3 - -movq 48(%rsp), %rax -. 799 0x12345678 6 -. 48 8B 44 24 30 C3 - -movq 48(%rsp), %rcx -. 800 0x12345678 6 -. 48 8B 4C 24 30 C3 - -movq 48(%rsp), %rdx -. 801 0x12345678 6 -. 48 8B 54 24 30 C3 - -movq 48(%rsp), %rsi -. 802 0x12345678 6 -. 48 8B 74 24 30 C3 - -movq 56(%rdi), %r12 -. 803 0x12345678 5 -. 4C 8B 67 38 C3 - -movq 56(%rdi), %r14 -. 804 0x12345678 5 -. 4C 8B 77 38 C3 - -movq 56(%rsp), %r14 -. 805 0x12345678 6 -. 4C 8B 74 24 38 C3 - -movq 56(%rsp), %r8 -. 806 0x12345678 6 -. 4C 8B 44 24 38 C3 - -movq 56(%rsp), %rdi -. 807 0x12345678 6 -. 48 8B 7C 24 38 C3 - -movq 56(%rsp), %rdx -. 808 0x12345678 6 -. 48 8B 54 24 38 C3 - -movq 56(%rsp), %rsi -. 809 0x12345678 6 -. 48 8B 74 24 38 C3 - -movq 64(%rdi), %r13 -. 810 0x12345678 5 -. 4C 8B 6F 40 C3 - -movq 64(%rdi), %rsi -. 811 0x12345678 5 -. 48 8B 77 40 C3 - -movq 64(%rsp), %r15 -. 812 0x12345678 6 -. 4C 8B 7C 24 40 C3 - -movq 72(%rdi), %r15 -. 813 0x12345678 5 -. 4C 8B 7F 48 C3 - -movq 72(%rdi), %rbp -. 814 0x12345678 5 -. 48 8B 6F 48 C3 - -movq 80(%r11), %rdx -. 815 0x12345678 5 -. 49 8B 53 50 C3 - -movq 80(%rdi), %rdx -. 816 0x12345678 5 -. 48 8B 57 50 C3 - -movq 80(%rsi), %rdx -. 817 0x12345678 5 -. 48 8B 56 50 C3 - -movq %r12, -32(%rsp) -. 818 0x12345678 6 -. 4C 89 64 24 E0 C3 - -movq %r13, -24(%rsp) -. 819 0x12345678 6 -. 4C 89 6C 24 E8 C3 - -movq %r14, -16(%rsp) -. 820 0x12345678 6 -. 4C 89 74 24 F0 C3 - -movq %r14, %rdi -. 821 0x12345678 4 -. 4C 89 F7 C3 - -movq %r15, -8(%rsp) -. 822 0x12345678 6 -. 4C 89 7C 24 F8 C3 - -movq %r15, %r10 -. 823 0x12345678 4 -. 4D 89 FA C3 - -movq %r15, %rcx -. 824 0x12345678 4 -. 4C 89 F9 C3 - -movq %r15, %rdx -. 825 0x12345678 4 -. 4C 89 FA C3 - -movq %r15, %rsi -. 826 0x12345678 4 -. 4C 89 FE C3 - -movq %rax, 80(%rbx) -. 827 0x12345678 5 -. 48 89 43 50 C3 - -movq %rax, %r10 -. 828 0x12345678 4 -. 49 89 C2 C3 - -movq %rax, %rcx -. 829 0x12345678 4 -. 48 89 C1 C3 - -movq %rax, %rdi -. 830 0x12345678 4 -. 48 89 C7 C3 - -movq %rax, %rdx -. 831 0x12345678 4 -. 48 89 C2 C3 - -movq %rax, (%rsp) -. 832 0x12345678 5 -. 48 89 04 24 C3 - -movq %rbp, -40(%rsp) -. 833 0x12345678 6 -. 48 89 6C 24 D8 C3 - -movq %rbp, %r11 -. 834 0x12345678 4 -. 49 89 EB C3 - -movq %rbp, %rsi -. 835 0x12345678 4 -. 48 89 EE C3 - -movq %rbx, -48(%rsp) -. 836 0x12345678 6 -. 48 89 5C 24 D0 C3 - -movq %rbx, %rdi -. 837 0x12345678 4 -. 48 89 DF C3 - -movq %rbx, %rsi -. 838 0x12345678 4 -. 48 89 DE C3 - -movq %rcx, %rbp -. 839 0x12345678 4 -. 48 89 CD C3 - -movq %rcx, %rsi -. 840 0x12345678 4 -. 48 89 CE C3 - -movq %rdi, 24(%rsp) -. 841 0x12345678 6 -. 48 89 7C 24 18 C3 - -movq %rdi, 56(%rsp) -. 842 0x12345678 6 -. 48 89 7C 24 38 C3 - -movq %rdi, %rbp -. 843 0x12345678 4 -. 48 89 FD C3 - -movq %rdi, %rbx -. 844 0x12345678 4 -. 48 89 FB C3 - -movq %rdi, %rsi -. 845 0x12345678 4 -. 48 89 FE C3 - -movq %rdx, 32(%rsp) -. 846 0x12345678 6 -. 48 89 54 24 20 C3 - -movq %rdx, 40(%rsp) -. 847 0x12345678 6 -. 48 89 54 24 28 C3 - -movq %rdx, 8(%rsp) -. 848 0x12345678 6 -. 48 89 54 24 08 C3 - -movq %rdx, %rax -. 849 0x12345678 4 -. 48 89 D0 C3 - -movq %rdx, %rbx -. 850 0x12345678 4 -. 48 89 D3 C3 - -movq %rdx, %rdi -. 851 0x12345678 4 -. 48 89 D7 C3 - -movq %rsi, 40(%rsp) -. 852 0x12345678 6 -. 48 89 74 24 28 C3 - -movq %rsi, 48(%rsp) -. 853 0x12345678 6 -. 48 89 74 24 30 C3 - -movq %rsi, 8(%rsp) -. 854 0x12345678 6 -. 48 89 74 24 08 C3 - -movq %rsi, %r15 -. 855 0x12345678 4 -. 49 89 F7 C3 - -movq %rsi, %rdx -. 856 0x12345678 4 -. 48 89 F2 C3 - -movq %rsi, (%rsp) -. 857 0x12345678 5 -. 48 89 34 24 C3 - -movq %rsp, %r11 -. 858 0x12345678 4 -. 49 89 E3 C3 - -movq (%rsp), %rcx -. 859 0x12345678 5 -. 48 8B 0C 24 C3 - -movq (%rsp), %rdx -. 860 0x12345678 5 -. 48 8B 14 24 C3 - -movq (%rsp), %rsi -. 861 0x12345678 5 -. 48 8B 34 24 C3 - -movq -999(%rip), %rcx -. 862 0x12345678 8 -. 48 8B 0D 19 FC FF FF C3 - -movq 1(%rip), %rdi -. 863 0x12345678 8 -. 48 8B 3D 01 00 00 00 C3 - -movq 2(%rip), %rsi -. 864 0x12345678 8 -. 48 8B 35 02 00 00 00 C3 - -mov (%rbx,%rax,4), %eax -. 865 0x12345678 4 -. 8B 04 83 C3 - -mov (%rbx,%rsi,4), %eax -. 866 0x12345678 4 -. 8B 04 B3 C3 - -mov (%rcx,%rax,4), %eax -. 867 0x12345678 4 -. 8B 04 81 C3 - -mov (%rdx,%rax,4), %eax -. 868 0x12345678 4 -. 8B 04 82 C3 - -mov (%rsi,%rax,4), %eax -. 869 0x12345678 4 -. 8B 04 86 C3 - -mov (%rsi,%rdx,4), %eax -. 870 0x12345678 4 -. 8B 04 96 C3 - -movslq 108(%rbx),%rax -. 871 0x12345678 5 -. 48 63 43 6C C3 - -movslq 116(%r11),%rcx -. 872 0x12345678 5 -. 49 63 4B 74 C3 - -movslq 116(%rdi),%rcx -. 873 0x12345678 5 -. 48 63 4F 74 C3 - -movslq 116(%rsi),%rcx -. 874 0x12345678 5 -. 48 63 4E 74 C3 - -movslq 12(%rsp),%rax -. 875 0x12345678 6 -. 48 63 44 24 0C C3 - -movslq 20(%rsp),%rax -. 876 0x12345678 6 -. 48 63 44 24 14 C3 - -movslq 24(%rsp),%rax -. 877 0x12345678 6 -. 48 63 44 24 18 C3 - -movslq 24(%rsp),%rdx -. 878 0x12345678 6 -. 48 63 54 24 18 C3 - -movslq 28(%rsp),%r8 -. 879 0x12345678 6 -. 4C 63 44 24 1C C3 - -movslq 28(%rsp),%rax -. 880 0x12345678 6 -. 48 63 44 24 1C C3 - -movslq 28(%rsp),%rcx -. 881 0x12345678 6 -. 48 63 4C 24 1C C3 - -movslq %eax,%rdx -. 882 0x12345678 4 -. 48 63 D0 C3 - -movslq %ebp,%rcx -. 883 0x12345678 4 -. 48 63 CD C3 - -movslq %ebp,%rdx -. 884 0x12345678 4 -. 48 63 D5 C3 - -movslq %ebx,%r10 -. 885 0x12345678 4 -. 4C 63 D3 C3 - -movslq %ebx,%rax -. 886 0x12345678 4 -. 48 63 C3 C3 - -movslq %ebx,%rcx -. 887 0x12345678 4 -. 48 63 CB C3 - -movslq %ebx,%rdx -. 888 0x12345678 4 -. 48 63 D3 C3 - -movslq %ecx,%rax -. 889 0x12345678 4 -. 48 63 C1 C3 - -movslq %ecx,%rdx -. 890 0x12345678 4 -. 48 63 D1 C3 - -movslq %edi,%rax -. 891 0x12345678 4 -. 48 63 C7 C3 - -movslq %edi,%rcx -. 892 0x12345678 4 -. 48 63 CF C3 - -movslq %edi,%rdx -. 893 0x12345678 4 -. 48 63 D7 C3 - -movslq %edi,%rsi -. 894 0x12345678 4 -. 48 63 F7 C3 - -movslq %edx,%rax -. 895 0x12345678 4 -. 48 63 C2 C3 - -movslq %edx,%rdx -. 896 0x12345678 4 -. 48 63 D2 C3 - -movslq %edx,%rsi -. 897 0x12345678 4 -. 48 63 F2 C3 - -movslq %esi,%rax -. 898 0x12345678 4 -. 48 63 C6 C3 - -movslq %r10d,%rax -. 899 0x12345678 4 -. 49 63 C2 C3 - -movslq %r10d,%rcx -. 900 0x12345678 4 -. 49 63 CA C3 - -movslq %r10d,%rdx -. 901 0x12345678 4 -. 49 63 D2 C3 - -movslq %r10d,%rsi -. 902 0x12345678 4 -. 49 63 F2 C3 - -movslq %r11d,%rcx -. 903 0x12345678 4 -. 49 63 CB C3 - -movslq %r11d,%rdx -. 904 0x12345678 4 -. 49 63 D3 C3 - -movslq %r12d,%rax -. 905 0x12345678 4 -. 49 63 C4 C3 - -movslq %r12d,%rcx -. 906 0x12345678 4 -. 49 63 CC C3 - -movslq %r12d,%rdx -. 907 0x12345678 4 -. 49 63 D4 C3 - -movslq %r13d,%rax -. 908 0x12345678 4 -. 49 63 C5 C3 - -movslq %r13d,%rdx -. 909 0x12345678 4 -. 49 63 D5 C3 - -movslq %r14d,%rax -. 910 0x12345678 4 -. 49 63 C6 C3 - -movslq %r14d,%rdx -. 911 0x12345678 4 -. 49 63 D6 C3 - -movslq %r15d,%rax -. 912 0x12345678 4 -. 49 63 C7 C3 - -movslq %r8d,%rax -. 913 0x12345678 4 -. 49 63 C0 C3 - -movslq %r8d,%rdx -. 914 0x12345678 4 -. 49 63 D0 C3 - -movslq %r9d,%rax -. 915 0x12345678 4 -. 49 63 C1 C3 - -movslq %r9d,%rcx -. 916 0x12345678 4 -. 49 63 C9 C3 - -movslq %r9d,%rdx -. 917 0x12345678 4 -. 49 63 D1 C3 - -movw $0, -2(%rdi,%rdx,2) -. 918 0x12345678 8 -. 66 C7 44 57 FE 00 00 C3 - -movw $0, -4(%rdi,%rdx,2) -. 919 0x12345678 8 -. 66 C7 44 57 FC 00 00 C3 - -movw $0, -6(%rdi,%rdx,2) -. 920 0x12345678 8 -. 66 C7 44 57 FA 00 00 C3 - -movw $0, 80(%rsp,%rax,2) -. 921 0x12345678 8 -. 66 C7 44 44 50 00 00 C3 - -movw $0, (%r8,%rax,2) -. 922 0x12345678 8 -. 66 41 C7 04 40 00 00 C3 - -movw $0, (%rbp,%rax,2) -. 923 0x12345678 8 -.... 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From: Julian S. <se...@so...> - 2017-12-12 09:24:55
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e847cb5429927317023d8410c3c56952aa47fb08 commit e847cb5429927317023d8410c3c56952aa47fb08 Author: Julian Seward <js...@ac...> Date: Tue Dec 12 10:22:51 2017 +0100 Bug 387664 - Memcheck: make expensive-definedness-checks be the default Memcheck tries to accurately track definedness at the bit level, at least for scalar integer operations. For many operations it is good enough to use approximations which may overstate the undefinedness of the result of an operation, provided that fully defined inputs still produce a fully defined output. For example, the standard analysis for an integer add is Add#(x#, y#) = Left(UifU(x#, y#)) which (as explained in the USENIX 05 paper http://valgrind.org/docs/memcheck2005.pdf) means: for an add, worst-case carry propagation is assumed. So all bits to the left of, and including, the rightmost undefined bit in either operand, are assumed to be undefined. As compilers have become increasingly aggressive, some of these approximations are no longer good enough. For example, LLVM for some years has used Add operations with partially undefined inputs, when it knows that the carry propagation will not pollute important parts of the result. Similarly, both GCC and LLVM will generate integer equality comparisons with partially undefined inputs in situations where it knows the result of the comparison will be defined. In both cases, Memcheck's default strategies give rise to false uninitialised-value errors, and the problem is getting worse as time goes by. Memcheck already has expensive (non-default) instrumentation for integer adds, subtracts, and equality comparisons. Currently these are only used if you specify --expensive-definedness-checks=yes, and in some rare cases to do with inlined string operations, as determined by analysing the block to be instrumented, and by default on MacOS. The performance hit from them can be quite high, up to 30% lossage. This patch makes the following changes: * During instrumentation, there is much finer control over which IROps get expensive instrumentation. The following groups can now be selected independently for expensive or cheap instrumentation: Iop_Add32 Iop_Add64 Iop_Sub32 Iop_Sub64 Iop_CmpEQ32 and Iop_CmpNE32 Iop_CmpEQ64 and Iop_CmpNE64 This makes it possible to only enable, on a given platform, only the minimal necessary set of expensive cases. * The default set of expensive cases can be set on a per-platform basis. This is set up in the first part of MC_(instrument). * There is a new pre-instrumentation analysis pass. It identifies Iop_Add32 and Iop_Add64 uses for which the expensive handling will give the same results as the cheap handling. This includes all adds that are used only to create memory addresses. Given that the expensive handling of adds is, well, expensive, and that most adds merely create memory addresses, this more than halves the extra costs of expensive Add handling. * The pre-existing "bogus literal" detection (0x80808080, etc) pass has been rolled into the new pre-instrumentation analysis. * The --expensive-definedness-checks= flag has been changed. Before, it had two settings, "no" and "yes", with "no" being the default. Now, it has three settings: no -- always use the cheapest handling auto -- use the minimum set of expensive handling needed to get reasonable results on this platform, and perform pre-instrumentation analysis so as to minimise the costs thereof yes -- always use the most expensive handling The default setting is now "auto". The user-visible effect of the new default is that there should (hopefully) be a drop in false positive rates but (unfortunately) also some drop in performance. Diff: --- memcheck/docs/mc-manual.xml | 36 ++- memcheck/mc_include.h | 16 +- memcheck/mc_main.c | 18 +- memcheck/mc_translate.c | 749 +++++++++++++++++++++++++++++++++++++------- 4 files changed, 686 insertions(+), 133 deletions(-) diff --git a/memcheck/docs/mc-manual.xml b/memcheck/docs/mc-manual.xml index de8c2ea..869a057 100644 --- a/memcheck/docs/mc-manual.xml +++ b/memcheck/docs/mc-manual.xml @@ -1028,19 +1028,33 @@ is <option>--errors-for-leak-kinds=definite,possible</option> <varlistentry id="opt.expensive-definedness-checks" xreflabel="--expensive-definedness-checks"> <term> - <option><![CDATA[--expensive-definedness-checks=<yes|no> [default: no] ]]></option> + <option><![CDATA[--expensive-definedness-checks=<no|auto|yes> [default: auto] ]]></option> </term> <listitem> - <para>Controls whether Memcheck should employ more precise but also more - expensive (time consuming) algorithms when checking the definedness of a - value. The default setting is not to do that and it is usually - sufficient. However, for highly optimised code valgrind may sometimes - incorrectly complain. - Invoking valgrind with <option>--expensive-definedness-checks=yes</option> - helps but comes at a performance cost. Runtime degradation of - 25% have been observed but the extra cost depends a lot on the - application at hand. - </para> + <para>Controls whether Memcheck should employ more precise but also + more expensive (time consuming) instrumentation when checking the + definedness of certain values. In particular, this affects the + instrumentation of integer adds, subtracts and equality + comparisons.</para> + <para>Selecting <option>--expensive-definedness-checks=yes</option> + causes Memcheck to use the most accurate analysis possible. This + minimises false error rates but can cause up to 30% performance + degradation.</para> + <para>Selecting <option>--expensive-definedness-checks=no</option> + causes Memcheck to use the cheapest instrumentation possible. This + maximises performance but will normally give an unusably high false + error rate.</para> + <para>The default + setting, <option>--expensive-definedness-checks=auto</option>, is + strongly recommended. This causes Memcheck to use the minimum of + expensive instrumentation needed to achieve the same false error + rate as <option>--expensive-definedness-checks=yes</option>. It + also enables an instrumentation-time analysis pass which aims to + further reduce the costs of accurate instrumentation. Overall, the + performance loss is generally around 5% relative to + <option>--expensive-definedness-checks=no</option>, although this is + strongly workload dependent. Note that the exact instrumentation + settings in this mode are architecture dependent.</para> </listitem> </varlistentry> diff --git a/memcheck/mc_include.h b/memcheck/mc_include.h index cffe627..e0f5fbe 100644 --- a/memcheck/mc_include.h +++ b/memcheck/mc_include.h @@ -718,9 +718,19 @@ extern Int MC_(clo_mc_level); /* Should we show mismatched frees? Default: YES */ extern Bool MC_(clo_show_mismatched_frees); -/* Should we use expensive definedness checking for add/sub and compare - operations? Default: NO */ -extern Bool MC_(clo_expensive_definedness_checks); +/* Indicates the level of detail for Vbit tracking through integer add, + subtract, and some integer comparison operations. */ +typedef + enum { + EdcNO = 1000, // All operations instrumented cheaply + EdcAUTO, // Chosen dynamically by analysing the block + EdcYES // All operations instrumented expensively + } + ExpensiveDefinednessChecks; + +/* Level of expense in definedness checking for add/sub and compare + operations. Default: EdcAUTO */ +extern ExpensiveDefinednessChecks MC_(clo_expensive_definedness_checks); /* Do we have a range of stack offsets to ignore? Default: NO */ extern Bool MC_(clo_ignore_range_below_sp); diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 892e503..15bf014 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -6023,7 +6023,10 @@ Int MC_(clo_free_fill) = -1; KeepStacktraces MC_(clo_keep_stacktraces) = KS_alloc_and_free; Int MC_(clo_mc_level) = 2; Bool MC_(clo_show_mismatched_frees) = True; -Bool MC_(clo_expensive_definedness_checks) = False; + +ExpensiveDefinednessChecks + MC_(clo_expensive_definedness_checks) = EdcAUTO; + Bool MC_(clo_ignore_range_below_sp) = False; UInt MC_(clo_ignore_range_below_sp__first_offset) = 0; UInt MC_(clo_ignore_range_below_sp__last_offset) = 0; @@ -6215,8 +6218,13 @@ static Bool mc_process_cmd_line_options(const HChar* arg) else if VG_BOOL_CLO(arg, "--show-mismatched-frees", MC_(clo_show_mismatched_frees)) {} - else if VG_BOOL_CLO(arg, "--expensive-definedness-checks", - MC_(clo_expensive_definedness_checks)) {} + + else if VG_XACT_CLO(arg, "--expensive-definedness-checks=no", + MC_(clo_expensive_definedness_checks), EdcNO) {} + else if VG_XACT_CLO(arg, "--expensive-definedness-checks=auto", + MC_(clo_expensive_definedness_checks), EdcAUTO) {} + else if VG_XACT_CLO(arg, "--expensive-definedness-checks=yes", + MC_(clo_expensive_definedness_checks), EdcYES) {} else if VG_BOOL_CLO(arg, "--xtree-leak", MC_(clo_xtree_leak)) {} @@ -6259,8 +6267,8 @@ static void mc_print_usage(void) " --undef-value-errors=no|yes check for undefined value errors [yes]\n" " --track-origins=no|yes show origins of undefined values? [no]\n" " --partial-loads-ok=no|yes too hard to explain here; see manual [yes]\n" -" --expensive-definedness-checks=no|yes\n" -" Use extra-precise definedness tracking [no]\n" +" --expensive-definedness-checks=no|auto|yes\n" +" Use extra-precise definedness tracking [auto]\n" " --freelist-vol=<number> volume of freed blocks queue [20000000]\n" " --freelist-big-blocks=<number> releases first blocks with size>= [1000000]\n" " --workaround-gcc296-bugs=no|yes self explanatory [no]. Deprecated.\n" diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 4fcf34b..91348b8 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -138,8 +138,14 @@ struct _MCEnv; +// See below for comments explaining what this is for. +typedef + enum __attribute__((packed)) { HuUnU=0, HuPCa=1, HuOth=2 } + HowUsed; + static IRType shadowTypeV ( IRType ty ); -static IRExpr* expr2vbits ( struct _MCEnv* mce, IRExpr* e ); +static IRExpr* expr2vbits ( struct _MCEnv* mce, IRExpr* e, + HowUsed hu/*use HuOth if unknown*/ ); static IRTemp findShadowTmpB ( struct _MCEnv* mce, IRTemp orig ); static IRExpr *i128_const_zero(void); @@ -149,6 +155,89 @@ static IRExpr *i128_const_zero(void); /*--- Memcheck running state, and tmp management. ---*/ /*------------------------------------------------------------*/ +/* For a few (maybe 1%) IROps, we have both a cheaper, less exact vbit + propagation scheme, and a more expensive, more precise vbit propagation + scheme. This enum describes, for such an IROp, which scheme to use. */ +typedef + enum { + // Use the cheaper, less-exact variant. + DLcheap=4, + // Choose between cheap and expensive based on analysis of the block + // to be instrumented. Note that the choice may be done on a + // per-instance basis of the IROp that this DetailLevel describes. + DLauto, + // Use the more expensive, more-exact variant. + DLexpensive + } + DetailLevel; + + +/* A readonly part of the running state. For IROps that have both a + less-exact and more-exact interpretation, records which interpretation is + to be used. */ +typedef + struct { + // For Add32/64 and Sub32/64, all 3 settings are allowed. For the + // DLauto case, a per-instance decision is to be made by inspecting + // the associated tmp's entry in MCEnv.tmpHowUsed. + DetailLevel dl_Add32; + DetailLevel dl_Add64; + DetailLevel dl_Sub32; + DetailLevel dl_Sub64; + // For Cmp{EQ,NE}{64,32,16,8}, only DLcheap and DLexpensive are + // allowed. + DetailLevel dl_CmpEQ64_CmpNE64; + DetailLevel dl_CmpEQ32_CmpNE32; + DetailLevel dl_CmpEQ16_CmpNE16; + DetailLevel dl_CmpEQ8_CmpNE8; + } + DetailLevelByOp; + +static void DetailLevelByOp__set_all ( /*OUT*/DetailLevelByOp* dlbo, + DetailLevel dl ) +{ + dlbo->dl_Add32 = dl; + dlbo->dl_Add64 = dl; + dlbo->dl_Sub32 = dl; + dlbo->dl_Sub64 = dl; + dlbo->dl_CmpEQ64_CmpNE64 = dl; + dlbo->dl_CmpEQ32_CmpNE32 = dl; + dlbo->dl_CmpEQ16_CmpNE16 = dl; + dlbo->dl_CmpEQ8_CmpNE8 = dl; +} + +static void DetailLevelByOp__check_sanity ( const DetailLevelByOp* dlbo ) +{ + tl_assert(dlbo->dl_Add32 >= DLcheap && dlbo->dl_Add32 <= DLexpensive); + tl_assert(dlbo->dl_Add64 >= DLcheap && dlbo->dl_Add64 <= DLexpensive); + tl_assert(dlbo->dl_Sub32 >= DLcheap && dlbo->dl_Sub32 <= DLexpensive); + tl_assert(dlbo->dl_Sub64 >= DLcheap && dlbo->dl_Sub64 <= DLexpensive); + tl_assert(dlbo->dl_CmpEQ64_CmpNE64 == DLcheap + || dlbo->dl_CmpEQ64_CmpNE64 == DLexpensive); + tl_assert(dlbo->dl_CmpEQ32_CmpNE32 == DLcheap + || dlbo->dl_CmpEQ32_CmpNE32 == DLexpensive); + tl_assert(dlbo->dl_CmpEQ16_CmpNE16 == DLcheap + || dlbo->dl_CmpEQ16_CmpNE16 == DLexpensive); + tl_assert(dlbo->dl_CmpEQ8_CmpNE8 == DLcheap + || dlbo->dl_CmpEQ8_CmpNE8 == DLexpensive); +} + +static UInt DetailLevelByOp__count ( const DetailLevelByOp* dlbo, + DetailLevel dl ) +{ + UInt n = 0; + n += (dlbo->dl_Add32 == dl ? 1 : 0); + n += (dlbo->dl_Add64 == dl ? 1 : 0); + n += (dlbo->dl_Sub32 == dl ? 1 : 0); + n += (dlbo->dl_Sub64 == dl ? 1 : 0); + n += (dlbo->dl_CmpEQ64_CmpNE64 == dl ? 1 : 0); + n += (dlbo->dl_CmpEQ32_CmpNE32 == dl ? 1 : 0); + n += (dlbo->dl_CmpEQ16_CmpNE16 == dl ? 1 : 0); + n += (dlbo->dl_CmpEQ8_CmpNE8 == dl ? 1 : 0); + return n; +} + + /* Carries info about a particular tmp. The tmp's number is not recorded, as this is implied by (equal to) its index in the tmpMap in MCEnv. The tmp's type is also not recorded, as this is present @@ -176,6 +265,32 @@ typedef TempMapEnt; +/* A |HowUsed| value carries analysis results about how values are used, + pertaining to whether we need to instrument integer adds expensively or + not. The running state carries a (readonly) mapping from original tmp to + a HowUsed value for it. A usage value can be one of three values, + forming a 3-point chain lattice. + + HuOth ("Other") used in some arbitrary way + | + HuPCa ("PCast") used *only* in effectively a PCast, in which all + | we care about is the all-defined vs not-all-defined distinction + | + HuUnU ("Unused") not used at all. + + The "safe" (don't-know) end of the lattice is "HuOth". See comments + below in |preInstrumentationAnalysis| for further details. +*/ +/* DECLARED ABOVE: +typedef + enum __attribute__((packed)) { HuUnU=0, HuPCa=1, HuOth=2 } + HowUsed; +*/ + +// Not actually necessary, but we don't want to waste D1 space. +STATIC_ASSERT(sizeof(HowUsed) == 1); + + /* Carries around state during memcheck instrumentation. */ typedef struct _MCEnv { @@ -200,15 +315,14 @@ typedef instrumentation process. */ XArray* /* of TempMapEnt */ tmpMap; - /* MODIFIED: indicates whether "bogus" literals have so far been - found. Starts off False, and may change to True. */ - Bool bogusLiterals; + /* READONLY: contains details of which ops should be expensively + instrumented. */ + DetailLevelByOp dlbo; - /* READONLY: indicates whether we should use expensive - interpretations of integer adds, since unfortunately LLVM - uses them to do ORs in some circumstances. Defaulted to True - on MacOS and False everywhere else. */ - Bool useLLVMworkarounds; + /* READONLY: for each original tmp, how the tmp is used. This is + computed by |preInstrumentationAnalysis|. Valid indices are + 0 .. #temps_in_sb-1 (same as for tmpMap). */ + HowUsed* tmpHowUsed; /* READONLY: the guest layout. This indicates which parts of the guest state should be regarded as 'always defined'. */ @@ -221,6 +335,7 @@ typedef } MCEnv; + /* SHADOW TMP MANAGEMENT. Shadow tmps are allocated lazily (on demand), as they are encountered. This is for two reasons. @@ -1303,7 +1418,7 @@ static void complainIfUndefined ( MCEnv* mce, IRAtom* atom, IRExpr *guard ) don't really care about the possibility that someone else may also create a V-interpretion for it. */ tl_assert(isOriginalAtom(mce, atom)); - vatom = expr2vbits( mce, atom ); + vatom = expr2vbits( mce, atom, HuOth ); tl_assert(isShadowAtom(mce, vatom)); tl_assert(sameKindedAtoms(atom, vatom)); @@ -1512,7 +1627,7 @@ void do_shadow_PUT ( MCEnv* mce, Int offset, if (atom) { tl_assert(!vatom); tl_assert(isOriginalAtom(mce, atom)); - vatom = expr2vbits( mce, atom ); + vatom = expr2vbits( mce, atom, HuOth ); } else { tl_assert(vatom); tl_assert(isShadowAtom(mce, vatom)); @@ -1562,7 +1677,7 @@ void do_shadow_PUTI ( MCEnv* mce, IRPutI *puti) return; tl_assert(isOriginalAtom(mce,atom)); - vatom = expr2vbits( mce, atom ); + vatom = expr2vbits( mce, atom, HuOth ); tl_assert(sameKindedAtoms(atom, vatom)); ty = descr->elemTy; tyS = shadowTypeV(ty); @@ -1957,7 +2072,7 @@ IRAtom* mkLazyN ( MCEnv* mce, } else { /* calculate the arg's definedness, and pessimistically merge it in. */ - here = mkPCastTo( mce, mergeTy, expr2vbits(mce, exprvec[i]) ); + here = mkPCastTo( mce, mergeTy, expr2vbits(mce, exprvec[i], HuOth) ); curr = mergeTy64 ? mkUifU64(mce, here, curr) : mkUifU32(mce, here, curr); @@ -2863,10 +2978,10 @@ IRAtom* expr2vbits_Qop ( MCEnv* mce, IRAtom* atom1, IRAtom* atom2, IRAtom* atom3, IRAtom* atom4 ) { - IRAtom* vatom1 = expr2vbits( mce, atom1 ); - IRAtom* vatom2 = expr2vbits( mce, atom2 ); - IRAtom* vatom3 = expr2vbits( mce, atom3 ); - IRAtom* vatom4 = expr2vbits( mce, atom4 ); + IRAtom* vatom1 = expr2vbits( mce, atom1, HuOth ); + IRAtom* vatom2 = expr2vbits( mce, atom2, HuOth ); + IRAtom* vatom3 = expr2vbits( mce, atom3, HuOth ); + IRAtom* vatom4 = expr2vbits( mce, atom4, HuOth ); tl_assert(isOriginalAtom(mce,atom1)); tl_assert(isOriginalAtom(mce,atom2)); @@ -2917,9 +3032,9 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, IROp op, IRAtom* atom1, IRAtom* atom2, IRAtom* atom3 ) { - IRAtom* vatom1 = expr2vbits( mce, atom1 ); - IRAtom* vatom2 = expr2vbits( mce, atom2 ); - IRAtom* vatom3 = expr2vbits( mce, atom3 ); + IRAtom* vatom1 = expr2vbits( mce, atom1, HuOth ); + IRAtom* vatom2 = expr2vbits( mce, atom2, HuOth ); + IRAtom* vatom3 = expr2vbits( mce, atom3, HuOth ); tl_assert(isOriginalAtom(mce,atom1)); tl_assert(isOriginalAtom(mce,atom2)); @@ -3042,15 +3157,16 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, static IRAtom* expr2vbits_Binop ( MCEnv* mce, IROp op, - IRAtom* atom1, IRAtom* atom2 ) + IRAtom* atom1, IRAtom* atom2, + HowUsed hu/*use HuOth if unknown*/ ) { IRType and_or_ty; IRAtom* (*uifu) (MCEnv*, IRAtom*, IRAtom*); IRAtom* (*difd) (MCEnv*, IRAtom*, IRAtom*); IRAtom* (*improve) (MCEnv*, IRAtom*, IRAtom*); - IRAtom* vatom1 = expr2vbits( mce, atom1 ); - IRAtom* vatom2 = expr2vbits( mce, atom2 ); + IRAtom* vatom1 = expr2vbits( mce, atom1, HuOth ); + IRAtom* vatom2 = expr2vbits( mce, atom2, HuOth ); tl_assert(isOriginalAtom(mce,atom1)); tl_assert(isOriginalAtom(mce,atom2)); @@ -4117,17 +4233,21 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, return mkLazy2(mce, Ity_I64, vatom1, vatom2); case Iop_Add32: - if (mce->bogusLiterals || mce->useLLVMworkarounds) - return expensiveAddSub(mce,True,Ity_I32, - vatom1,vatom2, atom1,atom2); - else - goto cheap_AddSub32; + if (mce->dlbo.dl_Add32 == DLexpensive + || (mce->dlbo.dl_Add32 == DLauto && hu == HuOth)) { + return expensiveAddSub(mce,True,Ity_I32, + vatom1,vatom2, atom1,atom2); + } else { + goto cheap_AddSub32; + } case Iop_Sub32: - if (mce->bogusLiterals) - return expensiveAddSub(mce,False,Ity_I32, - vatom1,vatom2, atom1,atom2); - else - goto cheap_AddSub32; + if (mce->dlbo.dl_Sub32 == DLexpensive + || (mce->dlbo.dl_Sub32 == DLauto && hu == HuOth)) { + return expensiveAddSub(mce,False,Ity_I32, + vatom1,vatom2, atom1,atom2); + } else { + goto cheap_AddSub32; + } cheap_AddSub32: case Iop_Mul32: @@ -4140,17 +4260,21 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, return doCmpORD(mce, op, vatom1,vatom2, atom1,atom2); case Iop_Add64: - if (mce->bogusLiterals || mce->useLLVMworkarounds) - return expensiveAddSub(mce,True,Ity_I64, - vatom1,vatom2, atom1,atom2); - else - goto cheap_AddSub64; + if (mce->dlbo.dl_Add64 == DLexpensive + || (mce->dlbo.dl_Add64 == DLauto && hu == HuOth)) { + return expensiveAddSub(mce,True,Ity_I64, + vatom1,vatom2, atom1,atom2); + } else { + goto cheap_AddSub64; + } case Iop_Sub64: - if (mce->bogusLiterals) - return expensiveAddSub(mce,False,Ity_I64, - vatom1,vatom2, atom1,atom2); - else - goto cheap_AddSub64; + if (mce->dlbo.dl_Sub64 == DLexpensive + || (mce->dlbo.dl_Sub64 == DLauto && hu == HuOth)) { + return expensiveAddSub(mce,False,Ity_I64, + vatom1,vatom2, atom1,atom2); + } else { + goto cheap_AddSub64; + } cheap_AddSub64: case Iop_Mul64: @@ -4168,7 +4292,10 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, ////---- CmpXX64 case Iop_CmpEQ64: case Iop_CmpNE64: - if (mce->bogusLiterals) goto expensive_cmp64; else goto cheap_cmp64; + if (mce->dlbo.dl_CmpEQ64_CmpNE64 == DLexpensive) + goto expensive_cmp64; + else + goto cheap_cmp64; expensive_cmp64: case Iop_ExpCmpNE64: @@ -4181,7 +4308,10 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, ////---- CmpXX32 case Iop_CmpEQ32: case Iop_CmpNE32: - if (mce->bogusLiterals) goto expensive_cmp32; else goto cheap_cmp32; + if (mce->dlbo.dl_CmpEQ32_CmpNE32 == DLexpensive) + goto expensive_cmp32; + else + goto cheap_cmp32; expensive_cmp32: case Iop_ExpCmpNE32: @@ -4194,7 +4324,10 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, ////---- CmpXX16 case Iop_CmpEQ16: case Iop_CmpNE16: - if (mce->bogusLiterals) goto expensive_cmp16; else goto cheap_cmp16; + if (mce->dlbo.dl_CmpEQ16_CmpNE16 == DLexpensive) + goto expensive_cmp16; + else + goto cheap_cmp16; expensive_cmp16: case Iop_ExpCmpNE16: @@ -4205,7 +4338,10 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, ////---- CmpXX8 case Iop_CmpEQ8: case Iop_CmpNE8: - if (mce->bogusLiterals) goto expensive_cmp8; else goto cheap_cmp8; + if (mce->dlbo.dl_CmpEQ8_CmpNE8 == DLexpensive) + goto expensive_cmp8; + else + goto cheap_cmp8; expensive_cmp8: return expensiveCmpEQorNE(mce,Ity_I8, vatom1,vatom2, atom1,atom2 ); @@ -4446,7 +4582,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) do_shadow_LoadG and should be kept in sync (in the very unlikely event that the interpretation of such widening ops changes in future). See comment in do_shadow_LoadG. */ - IRAtom* vatom = expr2vbits( mce, atom ); + IRAtom* vatom = expr2vbits( mce, atom, HuOth ); tl_assert(isOriginalAtom(mce,atom)); switch (op) { @@ -5053,9 +5189,9 @@ IRAtom* expr2vbits_ITE ( MCEnv* mce, tl_assert(isOriginalAtom(mce, iftrue)); tl_assert(isOriginalAtom(mce, iffalse)); - vbitsC = expr2vbits(mce, cond); - vbits1 = expr2vbits(mce, iftrue); - vbits0 = expr2vbits(mce, iffalse); + vbitsC = expr2vbits(mce, cond, HuOth); // could we use HuPCa here? + vbits1 = expr2vbits(mce, iftrue, HuOth); + vbits0 = expr2vbits(mce, iffalse, HuOth); ty = typeOfIRExpr(mce->sb->tyenv, vbits0); return @@ -5067,7 +5203,8 @@ IRAtom* expr2vbits_ITE ( MCEnv* mce, /* --------- This is the main expression-handling function. --------- */ static -IRExpr* expr2vbits ( MCEnv* mce, IRExpr* e ) +IRExpr* expr2vbits ( MCEnv* mce, IRExpr* e, + HowUsed hu/*use HuOth if unknown*/ ) { switch (e->tag) { @@ -5104,7 +5241,8 @@ IRExpr* expr2vbits ( MCEnv* mce, IRExpr* e ) return expr2vbits_Binop( mce, e->Iex.Binop.op, - e->Iex.Binop.arg1, e->Iex.Binop.arg2 + e->Iex.Binop.arg1, e->Iex.Binop.arg2, + hu ); case Iex_Unop: @@ -5218,7 +5356,7 @@ void do_shadow_Store ( MCEnv* mce, tl_assert(!vdata); tl_assert(isOriginalAtom(mce, data)); tl_assert(bias == 0); - vdata = expr2vbits( mce, data ); + vdata = expr2vbits( mce, data, HuOth ); } else { tl_assert(vdata); } @@ -5494,7 +5632,7 @@ void do_shadow_Dirty ( MCEnv* mce, IRDirty* d ) || UNLIKELY(is_IRExpr_VECRET_or_GSPTR(arg)) ) { /* ignore this arg */ } else { - here = mkPCastTo( mce, Ity_I32, expr2vbits(mce, arg) ); + here = mkPCastTo( mce, Ity_I32, expr2vbits(mce, arg, HuOth) ); curr = mkUifU32(mce, here, curr); } } @@ -5954,7 +6092,7 @@ static void do_shadow_CAS_single ( MCEnv* mce, IRCAS* cas ) /* 1. fetch data# (the proposed new value) */ tl_assert(isOriginalAtom(mce, cas->dataLo)); vdataLo - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataLo)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataLo, HuOth)); tl_assert(isShadowAtom(mce, vdataLo)); if (otrak) { bdataLo @@ -5965,7 +6103,7 @@ static void do_shadow_CAS_single ( MCEnv* mce, IRCAS* cas ) /* 2. fetch expected# (what we expect to see at the address) */ tl_assert(isOriginalAtom(mce, cas->expdLo)); vexpdLo - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdLo)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdLo, HuOth)); tl_assert(isShadowAtom(mce, vexpdLo)); if (otrak) { bexpdLo @@ -6062,9 +6200,9 @@ static void do_shadow_CAS_double ( MCEnv* mce, IRCAS* cas ) tl_assert(isOriginalAtom(mce, cas->dataHi)); tl_assert(isOriginalAtom(mce, cas->dataLo)); vdataHi - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataHi)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataHi, HuOth)); vdataLo - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataLo)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->dataLo, HuOth)); tl_assert(isShadowAtom(mce, vdataHi)); tl_assert(isShadowAtom(mce, vdataLo)); if (otrak) { @@ -6080,9 +6218,9 @@ static void do_shadow_CAS_double ( MCEnv* mce, IRCAS* cas ) tl_assert(isOriginalAtom(mce, cas->expdHi)); tl_assert(isOriginalAtom(mce, cas->expdLo)); vexpdHi - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdHi)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdHi, HuOth)); vexpdLo - = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdLo)); + = assignNew('V', mce, elemTy, expr2vbits(mce, cas->expdLo, HuOth)); tl_assert(isShadowAtom(mce, vexpdHi)); tl_assert(isShadowAtom(mce, vexpdLo)); if (otrak) { @@ -6286,7 +6424,7 @@ static void do_shadow_LoadG ( MCEnv* mce, IRLoadG* lg ) } IRAtom* vbits_alt - = expr2vbits( mce, lg->alt ); + = expr2vbits( mce, lg->alt, HuOth ); IRAtom* vbits_final = expr2vbits_Load_guarded_General(mce, lg->end, loadedTy, lg->addr, 0/*addr bias*/, @@ -7369,13 +7507,12 @@ void MC_(do_instrumentation_startup_checks)( void ) static Bool isBogusAtom ( IRAtom* at ) { - ULong n = 0; - IRConst* con; - tl_assert(isIRAtom(at)); if (at->tag == Iex_RdTmp) return False; tl_assert(at->tag == Iex_Const); - con = at->Iex.Const.con; + + ULong n = 0; + IRConst* con = at->Iex.Const.con; switch (con->tag) { case Ico_U1: return False; case Ico_U8: n = (ULong)con->Ico.U8; break; @@ -7391,6 +7528,10 @@ static Bool isBogusAtom ( IRAtom* at ) default: ppIRExpr(at); tl_assert(0); } /* VG_(printf)("%llx\n", n); */ + /* Shortcuts */ + if (LIKELY(n <= 0x0000000000001000ULL)) return False; + if (LIKELY(n >= 0xFFFFFFFFFFFFF000ULL)) return False; + /* The list of bogus atoms is: */ return (/*32*/ n == 0xFEFEFEFFULL /*32*/ || n == 0x80808080ULL /*32*/ || n == 0x7F7F7F7FULL @@ -7404,7 +7545,10 @@ static Bool isBogusAtom ( IRAtom* at ) ); } -static Bool checkForBogusLiterals ( /*FLAT*/ IRStmt* st ) + +/* Does 'st' mention any of the literals identified/listed in + isBogusAtom()? */ +static inline Bool containsBogusLiterals ( /*FLAT*/ IRStmt* st ) { Int i; IRExpr* e; @@ -7511,6 +7655,334 @@ static Bool checkForBogusLiterals ( /*FLAT*/ IRStmt* st ) } +/* This is the pre-instrumentation analysis. It does a backwards pass over + the stmts in |sb_in| to determine a HowUsed value for each tmp defined in + the block. + + Unrelatedly, it also checks all literals in the block with |isBogusAtom|, + as a positive result from that is a strong indication that we need to + expensively instrument add/sub in the block. We do both analyses in one + pass, even though they are independent, so as to avoid the overhead of + having to traverse the whole block twice. + + The usage pass proceeds as follows. Let max= be the max operation in the + HowUsed lattice, hence + + X max= Y means X = max(X, Y) + + then + + for t in original tmps . useEnv[t] = HuUnU + + for t used in the block's . next field + useEnv[t] max= HuPCa // because jmp targets are PCast-tested + + for st iterating *backwards* in the block + + match st + + case "t1 = load(t2)" // case 1 + useEnv[t2] max= HuPCa + + case "t1 = add(t2, t3)" // case 2 + useEnv[t2] max= useEnv[t1] + useEnv[t3] max= useEnv[t1] + + other + for t in st.usedTmps // case 3 + useEnv[t] max= HuOth + // same as useEnv[t] = HuOth + + The general idea is that we accumulate, in useEnv[], information about + how each tmp is used. That can be updated as we work further back + through the block and find more uses of it, but its HowUsed value can + only ascend the lattice, not descend. + + Initially we mark all tmps as unused. In case (1), if a tmp is seen to + be used as a memory address, then its use is at least HuPCa. The point + is that for a memory address we will add instrumentation to check if any + bit of the address is undefined, which means that we won't need expensive + V-bit propagation through an add expression that computed the address -- + cheap add instrumentation will be equivalent. + + Note in case (1) that if we have previously seen a non-memory-address use + of the tmp, then its use will already be HuOth and will be unchanged by + the max= operation. And if it turns out that the source of the tmp was + an add, then we'll have to expensively instrument the add, because we + can't prove that, for the previous non-memory-address use of the tmp, + cheap and expensive instrumentation will be equivalent. + + In case 2, we propagate the usage-mode of the result of an add back + through to its operands. Again, we use max= so as to take account of the + fact that t2 or t3 might later in the block (viz, earlier in the + iteration) have been used in a way that requires expensive add + instrumentation. + + In case 3, we deal with all other tmp uses. We assume that we'll need a + result that is as accurate as possible, so we max= HuOth into its use + mode. Since HuOth is the top of the lattice, that's equivalent to just + setting its use to HuOth. + + The net result of all this is that: + + tmps that are used either + - only as a memory address, or + - only as part of a tree of adds that computes a memory address, + and has no other use + are marked as HuPCa, and so we can instrument their generating Add + nodes cheaply, which is the whole point of this analysis + + tmps that are used any other way at all are marked as HuOth + + tmps that are unused are marked as HuUnU. We don't expect to see any + since we expect that the incoming IR has had all dead assignments + removed by previous optimisation passes. Nevertheless the analysis is + correct even in the presence of dead tmps. + + A final comment on dead tmps. In case 1 and case 2, we could actually + conditionalise the updates thusly: + + if (useEnv[t1] > HuUnU) { useEnv[t2] max= HuPCa } // case 1 + + if (useEnv[t1] > HuUnU) { useEnv[t2] max= useEnv[t1] } // case 2 + if (useEnv[t1] > HuUnU) { useEnv[t3] max= useEnv[t1] } // case 2 + + In other words, if the assigned-to tmp |t1| is never used, then there's + no point in propagating any use through to its operands. That won't + change the final HuPCa-vs-HuOth results, which is what we care about. + Given that we expect to get dead-code-free inputs, there's no point in + adding this extra refinement. +*/ + +/* Helper for |preInstrumentationAnalysis|. */ +static inline void noteTmpUsesIn ( /*MOD*/HowUsed* useEnv, + UInt tyenvUsed, + HowUsed newUse, IRAtom* at ) +{ + /* For the atom |at|, declare that for any tmp |t| in |at|, we will have + seen a use of |newUse|. So, merge that info into |t|'s accumulated + use info. */ + switch (at->tag) { + case Iex_GSPTR: + case Iex_Const: + return; + case Iex_RdTmp: { + IRTemp t = at->Iex.RdTmp.tmp; + tl_assert(t < tyenvUsed); // "is an original tmp" + // The "max" operation in the lattice + if (newUse > useEnv[t]) useEnv[t] = newUse; + return; + } + default: + // We should never get here -- it implies non-flat IR + ppIRExpr(at); + VG_(tool_panic)("noteTmpUsesIn"); + } + /*NOTREACHED*/ + tl_assert(0); +} + + +static void preInstrumentationAnalysis ( /*OUT*/HowUsed** useEnvP, + /*OUT*/Bool* hasBogusLiteralsP, + const IRSB* sb_in ) +{ + const UInt nOrigTmps = (UInt)sb_in->tyenv->types_used; + + // We've seen no bogus literals so far. + Bool bogus = False; + + // This is calloc'd, so implicitly all entries are initialised to HuUnU. + HowUsed* useEnv = VG_(calloc)("mc.preInstrumentationAnalysis.1", + nOrigTmps, sizeof(HowUsed)); + + // Firstly, roll in contributions from the final dst address. + bogus = isBogusAtom(sb_in->next); + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, sb_in->next); + + // Now work backwards through the stmts. + for (Int i = sb_in->stmts_used-1; i >= 0; i--) { + IRStmt* st = sb_in->stmts[i]; + + // Deal with literals. + if (LIKELY(!bogus)) { + bogus = containsBogusLiterals(st); + } + + // Deal with tmp uses. + switch (st->tag) { + case Ist_WrTmp: { + IRTemp dst = st->Ist.WrTmp.tmp; + IRExpr* rhs = st->Ist.WrTmp.data; + // This is the one place where we have to consider all possible + // tags for |rhs|, and can't just assume it is a tmp or a const. + switch (rhs->tag) { + case Iex_RdTmp: + // just propagate demand for |dst| into this tmp use. + noteTmpUsesIn(useEnv, nOrigTmps, useEnv[dst], rhs); + break; + case Iex_Unop: + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, rhs->Iex.Unop.arg); + break; + case Iex_Binop: + if (rhs->Iex.Binop.op == Iop_Add64 + || rhs->Iex.Binop.op == Iop_Add32) { + // propagate demand for |dst| through to the operands. + noteTmpUsesIn(useEnv, nOrigTmps, + useEnv[dst], rhs->Iex.Binop.arg1); + noteTmpUsesIn(useEnv, nOrigTmps, + useEnv[dst], rhs->Iex.Binop.arg2); + } else { + // just say that the operands are used in some unknown way. + noteTmpUsesIn(useEnv, nOrigTmps, + HuOth, rhs->Iex.Binop.arg1); + noteTmpUsesIn(useEnv, nOrigTmps, + HuOth, rhs->Iex.Binop.arg2); + } + break; + case Iex_Triop: { + // All operands are used in some unknown way. + IRTriop* tri = rhs->Iex.Triop.details; + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, tri->arg1); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, tri->arg2); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, tri->arg3); + break; + } + case Iex_Qop: { + // All operands are used in some unknown way. + IRQop* qop = rhs->Iex.Qop.details; + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, qop->arg1); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, qop->arg2); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, qop->arg3); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, qop->arg4); + break; + } + case Iex_Load: + // The address will be checked (== PCasted). + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, rhs->Iex.Load.addr); + break; + case Iex_ITE: + // The condition is PCasted, the then- and else-values + // aren't. + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, rhs->Iex.ITE.cond); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, rhs->Iex.ITE.iftrue); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, rhs->Iex.ITE.iffalse); + break; + case Iex_CCall: + // The args are used in unknown ways. + for (IRExpr** args = rhs->Iex.CCall.args; *args; args++) { + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, *args); + } + break; + case Iex_GetI: { + // The index will be checked/PCasted (see do_shadow_GETI) + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, rhs->Iex.GetI.ix); + break; + } + case Iex_Const: + case Iex_Get: + break; + default: + ppIRExpr(rhs); + VG_(tool_panic)("preInstrumentationAnalysis:" + " unhandled IRExpr"); + } + break; + } + case Ist_Store: + // The address will be checked (== PCasted). The data will be + // used in some unknown way. + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, st->Ist.Store.addr); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, st->Ist.Store.data); + break; + case Ist_Exit: + // The guard will be checked (== PCasted) + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, st->Ist.Exit.guard); + break; + case Ist_Put: + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, st->Ist.Put.data); + break; + case Ist_PutI: { + IRPutI* putI = st->Ist.PutI.details; + // The index will be checked/PCasted (see do_shadow_PUTI). The + // data will be used in an unknown way. + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, putI->ix); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, putI->data); + break; + } + case Ist_Dirty: { + IRDirty* d = st->Ist.Dirty.details; + // The guard will be checked (== PCasted) + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, d->guard); + // The args will be used in unknown ways. + for (IRExpr** args = d->args; *args; args++) { + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, *args); + } + break; + } + case Ist_CAS: { + IRCAS* cas = st->Ist.CAS.details; + // Address will be pcasted, everything else used as unknown + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, cas->addr); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, cas->expdLo); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, cas->dataLo); + if (cas->expdHi) + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, cas->expdHi); + if (cas->dataHi) + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, cas->dataHi); + break; + } + case Ist_AbiHint: + // Both exprs are used in unknown ways. TODO: can we safely + // just ignore AbiHints? + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, st->Ist.AbiHint.base); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, st->Ist.AbiHint.nia); + break; + case Ist_StoreG: { + // We might be able to do better, and use HuPCa for the addr. + // It's not immediately obvious that we can, because the address + // is regarded as "used" only when the guard is true. + IRStoreG* sg = st->Ist.StoreG.details; + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, sg->addr); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, sg->data); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, sg->guard); + break; + } + case Ist_LoadG: { + // Per similar comments to Ist_StoreG .. not sure whether this + // is really optimal. + IRLoadG* lg = st->Ist.LoadG.details; + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, lg->addr); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, lg->alt); + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, lg->guard); + break; + } + case Ist_LLSC: { + noteTmpUsesIn(useEnv, nOrigTmps, HuPCa, st->Ist.LLSC.addr); + if (st->Ist.LLSC.storedata) + noteTmpUsesIn(useEnv, nOrigTmps, HuOth, st->Ist.LLSC.storedata); + break; + } + case Ist_MBE: + case Ist_IMark: + case Ist_NoOp: + break; + default: { + ppIRStmt(st); + VG_(tool_panic)("preInstrumentationAnalysis: unhandled IRStmt"); + } + } + } // Now work backwards through the stmts. + + // Return the computed use env and the bogus-atom flag. + tl_assert(*useEnvP == NULL); + *useEnvP = useEnv; + + tl_assert(*hasBogusLiteralsP == False); + *hasBogusLiteralsP = bogus; +} + + IRSB* MC_(instrument) ( VgCallbackClosure* closure, IRSB* sb_in, const VexGuestLayout* layout, @@ -7552,21 +8024,90 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, mce.trace = verboze; mce.layout = layout; mce.hWordTy = hWordTy; - mce.bogusLiterals = False; - - /* Do expensive interpretation for Iop_Add32 and Iop_Add64 on - Darwin. 10.7 is mostly built with LLVM, which uses these for - bitfield inserts, and we get a lot of false errors if the cheap - interpretation is used, alas. Could solve this much better if - we knew which of such adds came from x86/amd64 LEA instructions, - since these are the only ones really needing the expensive - interpretation, but that would require some way to tag them in - the _toIR.c front ends, which is a lot of faffing around. So - for now just use the slow and blunt-instrument solution. */ - mce.useLLVMworkarounds = False; -# if defined(VGO_darwin) - mce.useLLVMworkarounds = True; -# endif + mce.tmpHowUsed = NULL; + + /* BEGIN decide on expense levels for instrumentation. */ + + /* Initially, select the cheap version of everything for which we have an + option. */ + DetailLevelByOp__set_all( &mce.dlbo, DLcheap ); + + /* Take account of the --expensive-definedness-checks= flag. */ + if (MC_(clo_expensive_definedness_checks) == EdcNO) { + /* We just selected 'cheap for everything', so we don't need to do + anything here. mce.tmpHowUsed remains NULL. */ + } + else if (MC_(clo_expensive_definedness_checks) == EdcYES) { + /* Select 'expensive for everything'. mce.tmpHowUsed remains NULL. */ + DetailLevelByOp__set_all( &mce.dlbo, DLexpensive ); + } + else { + tl_assert(MC_(clo_expensive_definedness_checks) == EdcAUTO); + /* We'll make our own selection, based on known per-target constraints + and also on analysis of the block to be instrumented. First, set + up default values for detail levels. + + On x86 and amd64, we'll routinely encounter code optimised by LLVM + 5 and above. Enable accurate interpretation of the following. + LLVM uses adds for some bitfield inserts, and we get a lot of false + errors if the cheap interpretation is used, alas. Could solve this + much better if we knew which of such adds came from x86/amd64 LEA + instructions, since these are the only ones really needing the + expensive interpretation, but that would require some way to tag + them in the _toIR.c front ends, which is a lot of faffing around. + So for now we use preInstrumentationAnalysis() to detect adds which + are used only to construct memory addresses, which is an + approximation to the above, and is self-contained.*/ +# if defined(VGA_x86) + mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; +# elif defined(VGA_amd64) + mce.dlbo.dl_Add64 = DLauto; + mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; +# endif + + /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then + fill it in. */ + Bool hasBogusLiterals = False; + preInstrumentationAnalysis( &mce.tmpHowUsed, &hasBogusLiterals, sb_in ); + + if (hasBogusLiterals) { + /* This happens very rarely. In this case just select expensive + for everything, and throw away the tmp-use analysis results. */ + DetailLevelByOp__set_all( &mce.dlbo, DLexpensive ); + VG_(free)( mce.tmpHowUsed ); + mce.tmpHowUsed = NULL; + } else { + /* Nothing. mce.tmpHowUsed contains tmp-use analysis results, + which will be used for some subset of Iop_{Add,Sub}{32,64}, + based on which ones are set to DLauto for this target. */ + } + } + + DetailLevelByOp__check_sanity( &mce.dlbo ); + + if (0) { + // Debug printing: which tmps have been identified as PCast-only use + if (mce.tmpHowUsed) { + VG_(printf)("Cheapies: "); + for (UInt q = 0; q < sb_in->tyenv->types_used; q++) { + if (mce.tmpHowUsed[q] == HuPCa) { + VG_(printf)("t%u ", q); + } + } + VG_(printf)("\n"); + } + + // Debug printing: number of ops by detail level + UChar nCheap = DetailLevelByOp__count( &mce.dlbo, DLcheap ); + UChar nAuto = DetailLevelByOp__count( &mce.dlbo, DLauto ); + UChar nExpensive = DetailLevelByOp__count( &mce.dlbo, DLexpensive ); + tl_assert(nCheap + nAuto + nExpensive == 8); + + VG_(printf)("%u,%u,%u ", nCheap, nAuto, nExpensive); + } + /* END decide on expense levels for instrumentation. */ + + /* Initialise the running the tmp environment. */ mce.tmpMap = VG_(newXA)( VG_(malloc), "mc.MC_(instrument).1", VG_(free), sizeof(TempMapEnt)); @@ -7580,36 +8121,7 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, } tl_assert( VG_(sizeXA)( mce.tmpMap ) == sb_in->tyenv->types_used ); - if (MC_(clo_expensive_definedness_checks)) { - /* For expensive definedness checking skip looking for bogus - literals. */ - mce.bogusLiterals = True; - } else { - /* Make a preliminary inspection of the statements, to see if there - are any dodgy-looking literals. If there are, we generate - extra-detailed (hence extra-expensive) instrumentation in - places. Scan the whole bb even if dodgyness is found earlier, - so that the flatness assertion is applied to all stmts. */ - Bool bogus = False; - - for (i = 0; i < sb_in->stmts_used; i++) { - st = sb_in->stmts[i]; - tl_assert(st); - tl_assert(isFlatIRStmt(st)); - - if (!bogus) { - bogus = checkForBogusLiterals(st); - if (0 && bogus) { - VG_(printf)("bogus: "); - ppIRStmt(st); - VG_(printf)("\n"); - } - if (bogus) break; - } - } - mce.bogusLiterals = bogus; - } - + /* Finally, begin instrumentation. */ /* Copy verbatim any IR preamble preceding the first IMark */ tl_assert(mce.sb == sb_out); @@ -7697,10 +8209,15 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, switch (st->tag) { - case Ist_WrTmp: + case Ist_WrTmp: { + IRTemp dst = st->Ist.WrTmp.tmp; + tl_assert(dst < (UInt)sb_in->tyenv->types_used); + HowUsed hu = mce.tmpHowUsed ? mce.tmpHowUsed[dst] + : HuOth/*we don't know, so play safe*/; assign( 'V', &mce, findShadowTmpV(&mce, st->Ist.WrTmp.tmp), - expr2vbits( &mce, st->Ist.WrTmp.data) ); + expr2vbits( &mce, st->Ist.WrTmp.data, hu )); break; + } case Ist_Put: do_shadow_PUT( &mce, @@ -7817,6 +8334,10 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, tl_assert( VG_(sizeXA)( mce.tmpMap ) == mce.sb->tyenv->types_used ); VG_(deleteXA)( mce.tmpMap ); + if (mce.tmpHowUsed) { + VG_(free)( mce.tmpHowUsed ); + } + tl_assert(mce.sb == sb_out); return sb_out; } |