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From: Petar J. <pe...@so...> - 2017-10-27 22:43:06
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0e1fa562e977c9ff86b56d7a29d12588b6a2c731 commit 0e1fa562e977c9ff86b56d7a29d12588b6a2c731 Author: Petar Jovanovic <mip...@gm...> Date: Fri Oct 27 16:26:24 2017 +0200 mips: MSA tests This set of tests covers the whole MSA instruction set: none/tests/mips32/msa_arithmetic none/tests/mips32/msa_comparison none/tests/mips32/msa_data_transfer none/tests/mips32/msa_fpu none/tests/mips32/msa_logical_and_shift none/tests/mips32/msa_shuffle none/tests/mips64/msa_arithmetic (symlink to mips32) none/tests/mips64/msa_comparison (symlink to mips32) none/tests/mips64/msa_data_transfer none/tests/mips64/msa_fpu (symlink to mips32) none/tests/mips64/msa_logical_and_shift (symlink to mips32) none/tests/mips64/msa_shuffle (symlink to mips32) Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #382563. Diff: --- .gitignore | 12 + configure.ac | 20 + none/tests/mips32/Makefile.am | 22 + none/tests/mips32/msa_arithmetic.c | 5794 ++++ none/tests/mips32/msa_arithmetic.stderr.exp | 0 none/tests/mips32/msa_arithmetic.stdout.exp | 5696 ++++ none/tests/mips32/msa_arithmetic.vgtest | 3 + none/tests/mips32/msa_comparison.c | 1706 ++ none/tests/mips32/msa_comparison.stderr.exp | 0 none/tests/mips32/msa_comparison.stdout.exp | 1600 + none/tests/mips32/msa_comparison.vgtest | 3 + none/tests/mips32/msa_data_transfer.c | 918 + none/tests/mips32/msa_data_transfer.stderr.exp | 0 none/tests/mips32/msa_data_transfer.stdout.exp | 768 + none/tests/mips32/msa_data_transfer.stdout.exp-BE | 768 + none/tests/mips32/msa_data_transfer.vgtest | 3 + none/tests/mips32/msa_fpu.c | 11629 ++++++++ none/tests/mips32/msa_fpu.stderr.exp | 0 none/tests/mips32/msa_fpu.stdout.exp | 29376 +++++++++++++++++++ none/tests/mips32/msa_fpu.vgtest | 3 + none/tests/mips32/msa_logical_and_shift.c | 3514 +++ none/tests/mips32/msa_logical_and_shift.stderr.exp | 0 none/tests/mips32/msa_logical_and_shift.stdout.exp | 3392 +++ none/tests/mips32/msa_logical_and_shift.vgtest | 3 + none/tests/mips32/msa_shuffle.c | 1797 ++ none/tests/mips32/msa_shuffle.stderr.exp | 0 none/tests/mips32/msa_shuffle.stdout.exp | 1632 ++ none/tests/mips32/msa_shuffle.vgtest | 3 + none/tests/mips64/Makefile.am | 21 + none/tests/mips64/msa_arithmetic.c | 1 + none/tests/mips64/msa_arithmetic.stderr.exp | 1 + none/tests/mips64/msa_arithmetic.stdout.exp | 1 + none/tests/mips64/msa_arithmetic.vgtest | 1 + none/tests/mips64/msa_comparison.c | 1 + none/tests/mips64/msa_comparison.stderr.exp | 1 + none/tests/mips64/msa_comparison.stdout.exp | 1 + none/tests/mips64/msa_comparison.vgtest | 1 + none/tests/mips64/msa_data_transfer.c | 1076 + none/tests/mips64/msa_data_transfer.stderr.exp | 0 none/tests/mips64/msa_data_transfer.stdout.exp | 896 + none/tests/mips64/msa_data_transfer.stdout.exp-BE | 896 + none/tests/mips64/msa_data_transfer.vgtest | 3 + none/tests/mips64/msa_fpu.c | 1 + none/tests/mips64/msa_fpu.stderr.exp | 1 + none/tests/mips64/msa_fpu.stdout.exp | 1 + none/tests/mips64/msa_fpu.vgtest | 1 + none/tests/mips64/msa_logical_and_shift.c | 1 + none/tests/mips64/msa_logical_and_shift.stderr.exp | 1 + none/tests/mips64/msa_logical_and_shift.stdout.exp | 1 + none/tests/mips64/msa_logical_and_shift.vgtest | 1 + none/tests/mips64/msa_shuffle.c | 1 + none/tests/mips64/msa_shuffle.stderr.exp | 1 + none/tests/mips64/msa_shuffle.stdout.exp | 1 + none/tests/mips64/msa_shuffle.vgtest | 1 + tests/mips_features.c | 11 +- 55 files changed, 71583 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index ec61217..97369ac 100644 --- a/.gitignore +++ b/.gitignore @@ -1596,6 +1596,12 @@ /none/tests/mips32/mips32_dspr2 /none/tests/mips32/MIPS32int /none/tests/mips32/MoveIns +/none/tests/mips32/msa_arithmetic +/none/tests/mips32/msa_comparison +/none/tests/mips32/msa_data_transfer +/none/tests/mips32/msa_fpu +/none/tests/mips32/msa_logical_and_shift +/none/tests/mips32/msa_shuffle /none/tests/mips32/LoadStore1 /none/tests/mips32/round /none/tests/mips32/round_fpu64 @@ -1630,6 +1636,12 @@ /none/tests/mips64/load_store_unaligned /none/tests/mips64/logical_instructions /none/tests/mips64/move_instructions +/none/tests/mips64/msa_arithmetic +/none/tests/mips64/msa_comparison +/none/tests/mips64/msa_data_transfer +/none/tests/mips64/msa_fpu +/none/tests/mips64/msa_logical_and_shift +/none/tests/mips64/msa_shuffle /none/tests/mips64/rotate_swap /none/tests/mips64/round /none/tests/mips64/shift_instructions diff --git a/configure.ac b/configure.ac index 4d45218..3cc9732 100644 --- a/configure.ac +++ b/configure.ac @@ -1837,6 +1837,26 @@ CFLAGS=$safe_CFLAGS AC_SUBST(FLAG_OCTEON2) +# does this compiler support -mmsa (MIPS MSA ASE) ? +AC_MSG_CHECKING([if gcc accepts -mmsa]) + +safe_CFLAGS=$CFLAGS +CFLAGS="$CFLAGS -mmsa -Werror" + +AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ + return 0; +]])], [ +FLAG_MSA="-mmsa" +AC_MSG_RESULT([yes]) +], [ +FLAG_MSA="" +AC_MSG_RESULT([no]) +]) +CFLAGS=$safe_CFLAGS + +AC_SUBST(FLAG_MSA) + + # does this compiler support -mmmx ? AC_MSG_CHECKING([if gcc accepts -mmmx]) diff --git a/none/tests/mips32/Makefile.am b/none/tests/mips32/Makefile.am index 6f9fd7a..526c06d 100644 --- a/none/tests/mips32/Makefile.am +++ b/none/tests/mips32/Makefile.am @@ -28,6 +28,14 @@ EXTRA_DIST = \ MoveIns.stdout.exp MoveIns.stdout.exp-BE \ MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \ MoveIns.stderr.exp MoveIns.vgtest \ + msa_arithmetic.stderr.exp msa_arithmetic.stdout.exp msa_arithmetic.vgtest \ + msa_comparison.stderr.exp msa_comparison.stdout.exp msa_comparison.vgtest \ + msa_data_transfer.stderr.exp msa_data_transfer.stdout.exp \ + msa_data_transfer.stdout.exp-BE msa_data_transfer.vgtest \ + msa_fpu.stderr.exp msa_fpu.stdout.exp msa_fpu.vgtest \ + msa_logical_and_shift.stderr.exp msa_logical_and_shift.stdout.exp \ + msa_logical_and_shift.vgtest msa_shuffle.stderr.exp msa_shuffle.stdout.exp \ + msa_shuffle.vgtest \ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \ round_fpu64.stderr.exp round_fpu64.vgtest \ round.stdout.exp round.stderr.exp round.vgtest \ @@ -41,6 +49,7 @@ EXTRA_DIST = \ vfp.stdout.exp-mips32r2-fpu_64-BE vfp.stdout.exp-mips32r2-fpu_64-LE \ vfp.vgtest + check_PROGRAMS = \ allexec \ block_size \ @@ -58,6 +67,12 @@ check_PROGRAMS = \ bug320057-mips32 \ mips32_dsp \ mips32_dspr2 \ + msa_arithmetic \ + msa_comparison \ + msa_data_transfer \ + msa_fpu \ + msa_logical_and_shift \ + msa_shuffle \ unaligned_load_store \ test_fcsr \ test_math \ @@ -69,6 +84,13 @@ AM_CXXFLAGS += @FLAG_M32@ AM_CCASFLAGS += @FLAG_M32@ allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ +msa_arithmetic_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ +msa_comparison_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ +msa_data_transfer_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ +msa_fpu_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ +msa_logical_and_shift_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ +msa_shuffle_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@ + bug320057_mips32_LDFLAGS = -lrt # C++ tests diff --git a/none/tests/mips32/msa_arithmetic.c b/none/tests/mips32/msa_arithmetic.c new file mode 100644 index 0000000..639bdcd --- /dev/null +++ b/none/tests/mips32/msa_arithmetic.c @@ -0,0 +1,5794 @@ +#include <stdio.h> + +unsigned long long data[32] = { + 0x0000000000000000ull, 0x0000000000000000ull, + 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x0000000080000000ull, 0x8000000000000000ull, + 0x8000800080008000ull, 0x7fff7fff7fff7fffull, + 0x8080808080808080ull, 0x8080808080808080ull, + 0x7070707070707070ull, 0x7070707070707070ull, + 0x7f7f7f7f7f7f7f7full, 0x7f7f7f7f7f7f7f7full, + 0x0706050403020100ull, 0x0f0e0d0c0b0a0908ull, + 0x77665544332211ffull, 0xeeddccbbaa998877ull, + 0x0000000000000001ull, 0x00000000000001ffull, + 0x0000000000000001ull, 0x00000000000000ffull, + 0xffffffffffffffffull, 0x0000000000000000ull, + 0x0000000100000001ull, 0x0000000100000001ull, + 0x1234567890abcdefull, 0xfedbca9876543210ull, + 0x0403020114131211ull, 0x2423222134333231ull, + 0x8483828194939291ull, 0xa4a3a2a1b4b3b2b1ull, +}; + +unsigned long long out[2]; + +#define TEST_3R(instruction, offset1, offset2, WD, WS, WT) \ +{ \ + __asm__ volatile ( \ + ".set push;\n\t" \ + ".set noreorder;\n\t" \ + "move $t0, %0\n\t" \ + "ld.d $"#WD", "#offset1"($t0)\n\t" \ + "xori.b $"#WD", $"#WD", 0xff\n\t" \ + "ld.d $"#WS", "#offset1"($t0)\n\t" \ + "ld.d $"#WT", "#offset2"($t0)\n\t" \ + instruction" $"#WD", $"#WS", $"#WT"\n\t" \ + "move $t0, %1\n\t" \ + "st.d $"#WD", 0($t0)\n\t" \ + ".set pop;\n\t" \ + : \ + : "r" (data), "r" (out) \ + : "t0", "memory" \ + ); \ + printf(instruction" $"#WD", $"#WS", $"#WT" "#WD":" \ + " %016llx%016llx "#WS": %016llx%016llx "#WT": " \ + "%016llx%016llx\n", out[1], out[0], data[offset1 / 8 + 1], \ + data[offset1 / 8], data[offset2 / 8 + 1], data[offset2 / 8]);\ +} + +#define TEST_BIT(instruction, offset, WD, WS, n) \ +{ \ + __asm__ volatile ( \ + ".set push;\n\t" \ + ".set noreorder;\n\t" \ + "move $t0, %0\n\t" \ + "ld.d $"#WD", "#offset"($t0)\n\t" \ + "xori.b $"#WD", $"#WD", 0xff\n\t" \ + "ld.d $"#WS", "#offset"($t0)\n\t" \ + instruction" $"#WD", $"#WS", "#n"\n\t" \ + "move $t0, %1\n\t" \ + "st.d $"#WD", 0($t0)\n\t" \ + ".set pop;\n\t" \ + : \ + : "r" (data), "r" (out) \ + : "t0", "memory" \ + ); \ + printf(instruction" $"#WD", $"#WS", "#n" "#WD":" \ + " %016llx%016llx "#WS": %016llx%016llx\n", \ + out[1], out[0], data[offset / 8 + 1], data[offset / 8]); \ +} + +#define TEST_I5(instruction, offset, WD, WS, imm) \ +{ \ + __asm__ volatile ( \ + ".set push;\n\t" \ + ".set noreorder;\n\t" \ + "move $t0, %0\n\t" \ + "ld.d $"#WD", "#offset"($t0)\n\t" \ + "xori.b $"#WD", $"#WD", 0xff\n\t" \ + "ld.d $"#WS", "#offset"($t0)\n\t" \ + instruction" $"#WD", $"#WS", "#imm"\n\t" \ + "move $t0, %1\n\t" \ + "st.d $"#WD", 0($t0)\n\t" \ + ".set pop;\n\t" \ + : \ + : "r" (data), "r" (out) \ + : "t0", "memory" \ + ); \ + printf(instruction" $"#WD", $"#WS", "#imm" "#WD":" \ + " %016llx%016llx "#WS": %016llx%016llx\n", \ + out[1], out[0], data[offset / 8 + 1], data[offset / 8]); \ +} + +int main(int argc, char **argv) { +#if defined(__mips_msa) + TEST_3R("add_a.b", 0, 144, w0, w0, w8); + TEST_3R("add_a.b", 8, 144, w1, w0, w27); + TEST_3R("add_a.b", 16, 64, w2, w11, w19); + TEST_3R("add_a.b", 24, 88, w3, w10, w9); + TEST_3R("add_a.b", 32, 24, w4, w19, w16); + TEST_3R("add_a.b", 40, 216, w5, w6, w29); + TEST_3R("add_a.b", 48, 104, w6, w9, w11); + TEST_3R("add_a.b", 56, 112, w7, w7, w7); + TEST_3R("add_a.b", 64, 192, w8, w6, w1); + TEST_3R("add_a.b", 72, 80, w9, w8, w9); + TEST_3R("add_a.b", 80, 216, w10, w18, w22); + TEST_3R("add_a.b", 88, 56, w11, w9, w22); + TEST_3R("add_a.b", 96, 232, w12, w14, w1); + TEST_3R("add_a.b", 104, 32, w13, w4, w11); + TEST_3R("add_a.b", 112, 168, w14, w2, w2); + TEST_3R("add_a.b", 120, 48, w15, w5, w14); + TEST_3R("add_a.b", 128, 8, w16, w2, w6); + TEST_3R("add_a.b", 136, 64, w17, w11, w13); + TEST_3R("add_a.b", 144, 104, w18, w21, w0); + TEST_3R("add_a.b", 152, 224, w19, w22, w21); + TEST_3R("add_a.b", 160, 64, w20, w30, w10); + TEST_3R("add_a.b", 168, 176, w21, w20, w7); + TEST_3R("add_a.b", 176, 56, w22, w10, w31); + TEST_3R("add_a.b", 184, 160, w23, w11, w19); + TEST_3R("add_a.b", 192, 96, w24, w0, w21); + TEST_3R("add_a.b", 200, 152, w25, w5, w3); + TEST_3R("add_a.b", 208, 32, w26, w7, w10); + TEST_3R("add_a.b", 216, 216, w27, w18, w23); + TEST_3R("add_a.b", 224, 80, w28, w8, w23); + TEST_3R("add_a.b", 232, 72, w29, w30, w13); + TEST_3R("add_a.b", 240, 16, w30, w29, w23); + TEST_3R("add_a.b", 232, 200, w31, w17, w28); + TEST_3R("add_a.h", 0, 72, w0, w0, w7); + TEST_3R("add_a.h", 8, 88, w1, w18, w30); + TEST_3R("add_a.h", 16, 104, w2, w7, w18); + TEST_3R("add_a.h", 24, 208, w3, w11, w21); + TEST_3R("add_a.h", 32, 184, w4, w13, w8); + TEST_3R("add_a.h", 40, 8, w5, w16, w3); + TEST_3R("add_a.h", 48, 80, w6, w14, w16); + TEST_3R("add_a.h", 56, 200, w7, w7, w7); + TEST_3R("add_a.h", 64, 112, w8, w3, w29); + TEST_3R("add_a.h", 72, 216, w9, w20, w9); + TEST_3R("add_a.h", 80, 96, w10, w5, w19); + TEST_3R("add_a.h", 88, 136, w11, w15, w6); + TEST_3R("add_a.h", 96, 160, w12, w24, w13); + TEST_3R("add_a.h", 104, 88, w13, w7, w24); + TEST_3R("add_a.h", 112, 232, w14, w28, w28); + TEST_3R("add_a.h", 120, 56, w15, w9, w4); + TEST_3R("add_a.h", 128, 152, w16, w15, w20); + TEST_3R("add_a.h", 136, 56, w17, w8, w3); + TEST_3R("add_a.h", 144, 96, w18, w27, w14); + TEST_3R("add_a.h", 152, 216, w19, w30, w11); + TEST_3R("add_a.h", 160, 176, w20, w18, w4); + TEST_3R("add_a.h", 168, 216, w21, w5, w17); + TEST_3R("add_a.h", 176, 72, w22, w3, w9); + TEST_3R("add_a.h", 184, 96, w23, w20, w16); + TEST_3R("add_a.h", 192, 88, w24, w16, w13); + TEST_3R("add_a.h", 200, 152, w25, w26, w17); + TEST_3R("add_a.h", 208, 176, w26, w9, w6); + TEST_3R("add_a.h", 216, 0, w27, w17, w9); + TEST_3R("add_a.h", 224, 104, w28, w12, w23); + TEST_3R("add_a.h", 232, 192, w29, w10, w3); + TEST_3R("add_a.h", 240, 0, w30, w28, w7); + TEST_3R("add_a.h", 56, 200, w31, w2, w12); + TEST_3R("add_a.w", 0, 144, w0, w0, w16); + TEST_3R("add_a.w", 8, 64, w1, w6, w4); + TEST_3R("add_a.w", 16, 72, w2, w24, w21); + TEST_3R("add_a.w", 24, 64, w3, w23, w15); + TEST_3R("add_a.w", 32, 80, w4, w15, w24); + TEST_3R("add_a.w", 40, 40, w5, w9, w15); + TEST_3R("add_a.w", 48, 16, w6, w22, w7); + TEST_3R("add_a.w", 56, 224, w7, w7, w7); + TEST_3R("add_a.w", 64, 104, w8, w10, w21); + TEST_3R("add_a.w", 72, 88, w9, w17, w9); + TEST_3R("add_a.w", 80, 160, w10, w31, w30); + TEST_3R("add_a.w", 88, 64, w11, w12, w14); + TEST_3R("add_a.w", 96, 136, w12, w19, w18); + TEST_3R("add_a.w", 104, 80, w13, w11, w7); + TEST_3R("add_a.w", 112, 160, w14, w2, w2); + TEST_3R("add_a.w", 120, 104, w15, w23, w17); + TEST_3R("add_a.w", 128, 56, w16, w30, w22); + TEST_3R("add_a.w", 136, 184, w17, w13, w30); + TEST_3R("add_a.w", 144, 40, w18, w20, w31); + TEST_3R("add_a.w", 152, 152, w19, w30, w20); + TEST_3R("add_a.w", 160, 216, w20, w16, w1); + TEST_3R("add_a.w", 168, 88, w21, w14, w23); + TEST_3R("add_a.w", 176, 8, w22, w27, w10); + TEST_3R("add_a.w", 184, 144, w23, w3, w21); + TEST_3R("add_a.w", 192, 72, w24, w26, w23); + TEST_3R("add_a.w", 200, 56, w25, w18, w8); + TEST_3R("add_a.w", 208, 112, w26, w16, w31); + TEST_3R("add_a.w", 216, 176, w27, w29, w1); + TEST_3R("add_a.w", 224, 112, w28, w15, w16); + TEST_3R("add_a.w", 232, 16, w29, w27, w0); + TEST_3R("add_a.w", 240, 208, w30, w5, w14); + TEST_3R("add_a.w", 160, 112, w31, w28, w10); + TEST_3R("add_a.d", 0, 16, w0, w0, w25); + TEST_3R("add_a.d", 8, 16, w1, w27, w15); + TEST_3R("add_a.d", 16, 32, w2, w18, w27); + TEST_3R("add_a.d", 24, 144, w3, w27, w22); + TEST_3R("add_a.d", 32, 96, w4, w26, w9); + TEST_3R("add_a.d", 40, 32, w5, w23, w10); + TEST_3R("add_a.d", 48, 112, w6, w20, w26); + TEST_3R("add_a.d", 56, 112, w7, w7, w7); + TEST_3R("add_a.d", 64, 128, w8, w21, w3); + TEST_3R("add_a.d", 72, 32, w9, w26, w9); + TEST_3R("add_a.d", 80, 24, w10, w30, w23); + TEST_3R("add_a.d", 88, 144, w11, w1, w29); + TEST_3R("add_a.d", 96, 176, w12, w8, w25); + TEST_3R("add_a.d", 104, 48, w13, w9, w11); + TEST_3R("add_a.d", 112, 96, w14, w28, w28); + TEST_3R("add_a.d", 120, 0, w15, w22, w31); + TEST_3R("add_a.d", 128, 200, w16, w0, w31); + TEST_3R("add_a.d", 136, 200, w17, w10, w18); + TEST_3R("add_a.d", 144, 80, w18, w4, w21); + TEST_3R("add_a.d", 152, 88, w19, w25, w24); + TEST_3R("add_a.d", 160, 168, w20, w10, w6); + TEST_3R("add_a.d", 168, 88, w21, w7, w8); + TEST_3R("add_a.d", 176, 128, w22, w28, w16); + TEST_3R("add_a.d", 184, 184, w23, w1, w25); + TEST_3R("add_a.d", 192, 48, w24, w1, w21); + TEST_3R("add_a.d", 200, 160, w25, w23, w20); + TEST_3R("add_a.d", 208, 120, w26, w23, w19); + TEST_3R("add_a.d", 216, 88, w27, w2, w5); + TEST_3R("add_a.d", 224, 40, w28, w6, w26); + TEST_3R("add_a.d", 232, 0, w29, w0, w19); + TEST_3R("add_a.d", 240, 176, w30, w20, w29); + TEST_3R("add_a.d", 8, 224, w31, w4, w7); + TEST_3R("adds_a.b", 0, 40, w0, w3, w29); + TEST_3R("adds_a.b", 8, 200, w1, w26, w17); + TEST_3R("adds_a.b", 16, 192, w2, w2, w18); + TEST_3R("adds_a.b", 24, 72, w3, w9, w20); + TEST_3R("adds_a.b", 32, 128, w4, w1, w26); + TEST_3R("adds_a.b", 40, 8, w5, w10, w26); + TEST_3R("adds_a.b", 48, 96, w6, w27, w14); + TEST_3R("adds_a.b", 56, 56, w7, w19, w13); + TEST_3R("adds_a.b", 64, 80, w8, w18, w8); + TEST_3R("adds_a.b", 72, 40, w9, w9, w9); + TEST_3R("adds_a.b", 80, 88, w10, w2, w30); + TEST_3R("adds_a.b", 88, 144, w11, w10, w20); + TEST_3R("adds_a.b", 96, 168, w12, w8, w29); + TEST_3R("adds_a.b", 104, 40, w13, w25, w27); + TEST_3R("adds_a.b", 112, 224, w14, w30, w4); + TEST_3R("adds_a.b", 120, 40, w15, w9, w6); + TEST_3R("adds_a.b", 128, 128, w16, w14, w21); + TEST_3R("adds_a.b", 136, 104, w17, w12, w4); + TEST_3R("adds_a.b", 144, 160, w18, w31, w17); + TEST_3R("adds_a.b", 152, 80, w19, w17, w6); + TEST_3R("adds_a.b", 160, 168, w20, w19, w4); + TEST_3R("adds_a.b", 168, 72, w21, w30, w24); + TEST_3R("adds_a.b", 176, 128, w22, w6, w6); + TEST_3R("adds_a.b", 184, 32, w23, w8, w31); + TEST_3R("adds_a.b", 192, 128, w24, w20, w30); + TEST_3R("adds_a.b", 200, 152, w25, w21, w7); + TEST_3R("adds_a.b", 208, 136, w26, w16, w21); + TEST_3R("adds_a.b", 216, 56, w27, w5, w24); + TEST_3R("adds_a.b", 224, 136, w28, w22, w23); + TEST_3R("adds_a.b", 232, 64, w29, w12, w8); + TEST_3R("adds_a.b", 240, 24, w30, w28, w6); + TEST_3R("adds_a.b", 160, 208, w31, w26, w30); + TEST_3R("adds_a.h", 0, 88, w0, w20, w31); + TEST_3R("adds_a.h", 8, 72, w1, w5, w20); + TEST_3R("adds_a.h", 16, 152, w2, w2, w27); + TEST_3R("adds_a.h", 24, 200, w3, w4, w22); + TEST_3R("adds_a.h", 32, 216, w4, w25, w2); + TEST_3R("adds_a.h", 40, 152, w5, w20, w26); + TEST_3R("adds_a.h", 48, 48, w6, w11, w17); + TEST_3R("adds_a.h", 56, 224, w7, w23, w26); + TEST_3R("adds_a.h", 64, 176, w8, w19, w8); + TEST_3R("adds_a.h", 72, 232, w9, w9, w9); + TEST_3R("adds_a.h", 80, 200, w10, w29, w16); + TEST_3R("adds_a.h", 88, 168, w11, w21, w16); + TEST_3R("adds_a.h", 96, 64, w12, w20, w15); + TEST_3R("adds_a.h", 104, 112, w13, w8, w30); + TEST_3R("adds_a.h", 112, 184, w14, w17, w20); + TEST_3R("adds_a.h", 120, 40, w15, w11, w23); + TEST_3R("adds_a.h", 128, 192, w16, w31, w17); + TEST_3R("adds_a.h", 136, 0, w17, w10, w3); + TEST_3R("adds_a.h", 144, 104, w18, w1, w29); + TEST_3R("adds_a.h", 152, 160, w19, w21, w3); + TEST_3R("adds_a.h", 160, 16, w20, w3, w12); + TEST_3R("adds_a.h", 168, 88, w21, w19, w9); + TEST_3R("adds_a.h", 176, 40, w22, w2, w2); + TEST_3R("adds_a.h", 184, 120, w23, w4, w15); + TEST_3R("adds_a.h", 192, 8, w24, w22, w1); + TEST_3R("adds_a.h", 200, 208, w25, w0, w12); + TEST_3R("adds_a.h", 208, 64, w26, w9, w11); + TEST_3R("adds_a.h", 216, 200, w27, w26, w22); + TEST_3R("adds_a.h", 224, 208, w28, w14, w23); + TEST_3R("adds_a.h", 232, 168, w29, w7, w12); + TEST_3R("adds_a.h", 240, 120, w30, w10, w31); + TEST_3R("adds_a.h", 72, 112, w31, w22, w6); + TEST_3R("adds_a.w", 0, 120, w0, w2, w19); + TEST_3R("adds_a.w", 8, 112, w1, w7, w2); + TEST_3R("adds_a.w", 16, 48, w2, w2, w29); + TEST_3R("adds_a.w", 24, 56, w3, w21, w29); + TEST_3R("adds_a.w", 32, 8, w4, w11, w7); + TEST_3R("adds_a.w", 40, 0, w5, w19, w1); + TEST_3R("adds_a.w", 48, 152, w6, w29, w16); + TEST_3R("adds_a.w", 56, 96, w7, w5, w23); + TEST_3R("adds_a.w", 64, 112, w8, w31, w8); + TEST_3R("adds_a.w", 72, 208, w9, w9, w9); + TEST_3R("adds_a.w", 80, 88, w10, w29, w23); + TEST_3R("adds_a.w", 88, 56, w11, w13, w22); + TEST_3R("adds_a.w", 96, 192, w12, w0, w2); + TEST_3R("adds_a.w", 104, 128, w13, w3, w25); + TEST_3R("adds_a.w", 112, 80, w14, w6, w30); + TEST_3R("adds_a.w", 120, 208, w15, w26, w5); + TEST_3R("adds_a.w", 128, 80, w16, w13, w7); + TEST_3R("adds_a.w", 136, 232, w17, w10, w23); + TEST_3R("adds_a.w", 144, 88, w18, w15, w14); + TEST_3R("adds_a.w", 152, 96, w19, w15, w12); + TEST_3R("adds_a.w", 160, 136, w20, w14, w25); + TEST_3R("adds_a.w", 168, 168, w21, w11, w26); + TEST_3R("adds_a.w", 176, 72, w22, w15, w15); + TEST_3R("adds_a.w", 184, 96, w23, w24, w16); + TEST_3R("adds_a.w", 192, 56, w24, w6, w14); + TEST_3R("adds_a.w", 200, 24, w25, w0, w20); + TEST_3R("adds_a.w", 208, 216, w26, w13, w27); + TEST_3R("adds_a.w", 216, 208, w27, w24, w18); + TEST_3R("adds_a.w", 224, 176, w28, w7, w0); + TEST_3R("adds_a.w", 232, 232, w29, w22, w15); + TEST_3R("adds_a.w", 240, 136, w30, w2, w21); + TEST_3R("adds_a.w", 192, 208, w31, w28, w17); + TEST_3R("adds_a.d", 0, 32, w0, w16, w18); + TEST_3R("adds_a.d", 8, 0, w1, w8, w2); + TEST_3R("adds_a.d", 16, 0, w2, w2, w15); + TEST_3R("adds_a.d", 24, 160, w3, w16, w15); + TEST_3R("adds_a.d", 32, 184, w4, w26, w29); + TEST_3R("adds_a.d", 40, 192, w5, w7, w21); + TEST_3R("adds_a.d", 48, 224, w6, w30, w28); + TEST_3R("adds_a.d", 56, 160, w7, w20, w19); + TEST_3R("adds_a.d", 64, 0, w8, w30, w8); + TEST_3R("adds_a.d", 72, 192, w9, w9, w9); + TEST_3R("adds_a.d", 80, 128, w10, w22, w17); + TEST_3R("adds_a.d", 88, 0, w11, w25, w7); + TEST_3R("adds_a.d", 96, 192, w12, w11, w26); + TEST_3R("adds_a.d", 104, 88, w13, w17, w15); + TEST_3R("adds_a.d", 112, 128, w14, w1, w30); + TEST_3R("adds_a.d", 120, 16, w15, w27, w2); + TEST_3R("adds_a.d", 128, 8, w16, w19, w0); + TEST_3R("adds_a.d", 136, 32, w17, w5, w21); + TEST_3R("adds_a.d", 144, 32, w18, w5, w19); + TEST_3R("adds_a.d", 152, 112, w19, w27, w10); + TEST_3R("adds_a.d", 160, 24, w20, w2, w3); + TEST_3R("adds_a.d", 168, 88, w21, w25, w15); + TEST_3R("adds_a.d", 176, 88, w22, w25, w25); + TEST_3R("adds_a.d", 184, 56, w23, w26, w8); + TEST_3R("adds_a.d", 192, 56, w24, w27, w7); + TEST_3R("adds_a.d", 200, 120, w25, w22, w2); + TEST_3R("adds_a.d", 208, 144, w26, w25, w19); + TEST_3R("adds_a.d", 216, 16, w27, w25, w0); + TEST_3R("adds_a.d", 224, 56, w28, w14, w0); + TEST_3R("adds_a.d", 232, 168, w29, w2, w21); + TEST_3R("adds_a.d", 240, 168, w30, w12, w28); + TEST_3R("adds_a.d", 40, 48, w31, w15, w11); + TEST_3R("adds_s.b", 0, 184, w0, w21, w9); + TEST_3R("adds_s.b", 8, 72, w1, w18, w31); + TEST_3R("adds_s.b", 16, 192, w2, w17, w24); + TEST_3R("adds_s.b", 24, 80, w3, w4, w18); + TEST_3R("adds_s.b", 32, 0, w4, w27, w0); + TEST_3R("adds_s.b", 40, 64, w5, w24, w2); + TEST_3R("adds_s.b", 48, 0, w6, w16, w14); + TEST_3R("adds_s.b", 56, 88, w7, w10, w30); + TEST_3R("adds_s.b", 64, 144, w8, w30, w28); + TEST_3R("adds_s.b", 72, 112, w9, w11, w23); + TEST_3R("adds_s.b", 80, 232, w10, w0, w13); + TEST_3R("adds_s.b", 88, 232, w11, w29, w31); + TEST_3R("adds_s.b", 96, 0, w12, w28, w17); + TEST_3R("adds_s.b", 104, 176, w13, w13, w14); + TEST_3R("adds_s.b", 112, 128, w14, w4, w4); + TEST_3R("adds_s.b", 120, 0, w15, w16, w4); + TEST_3R("adds_s.b", 128, 184, w16, w9, w7); + TEST_3R("adds_s.b", 136, 184, w17, w25, w21); + TEST_3R("adds_s.b", 144, 152, w18, w4, w19); + TEST_3R("adds_s.b", 152, 56, w19, w2, w16); + TEST_3R("adds_s.b", 160, 136, w20, w20, w20); + TEST_3R("adds_s.b", 168, 216, w21, w7, w0); + TEST_3R("adds_s.b", 176, 232, w22, w20, w26); + TEST_3R("adds_s.b", 184, 48, w23, w20, w6); + TEST_3R("adds_s.b", 192, 232, w24, w6, w20); + TEST_3R("adds_s.b", 200, 216, w25, w10, w20); + TEST_3R("adds_s.b", 208, 176, w26, w14, w6); + TEST_3R("adds_s.b", 216, 64, w27, w21, w27); + TEST_3R("adds_s.b", 224, 8, w28, w13, w11); + TEST_3R("adds_s.b", 232, 168, w29, w17, w30); + TEST_3R("adds_s.b", 240, 104, w30, w19, w14); + TEST_3R("adds_s.b", 104, 152, w31, w0, w22); + TEST_3R("adds_s.h", 0, 104, w0, w10, w20); + TEST_3R("adds_s.h", 8, 168, w1, w30, w8); + TEST_3R("adds_s.h", 16, 48, w2, w3, w14); + TEST_3R("adds_s.h", 24, 48, w3, w29, w24); + TEST_3R("adds_s.h", 32, 40, w4, w8, w7); + TEST_3R("adds_s.h", 40, 104, w5, w27, w28); + TEST_3R("adds_s.h", 48, 120, w6, w8, w7); + TEST_3R("adds_s.h", 56, 160, w7, w25, w6); + TEST_3R("adds_s.h", 64, 24, w8, w12, w20); + TEST_3R("adds_s.h", 72, 56, w9, w12, w10); + TEST_3R("adds_s.h", 80, 120, w10, w26, w21); + TEST_3R("adds_s.h", 88, 96, w11, w18, w19); + TEST_3R("adds_s.h", 96, 224, w12, w16, w23); + TEST_3R("adds_s.h", 104, 176, w13, w13, w3); + TEST_3R("adds_s.h", 112, 56, w14, w13, w13); + TEST_3R("adds_s.h", 120, 104, w15, w28, w20); + TEST_3R("adds_s.h", 128, 80, w16, w24, w7); + TEST_3R("adds_s.h", 136, 8, w17, w24, w18); + TEST_3R("adds_s.h", 144, 48, w18, w30, w8); + TEST_3R("adds_s.h", 152, 112, w19, w18, w23); + TEST_3R("adds_s.h", 160, 88, w20, w20, w20); + TEST_3R("adds_s.h", 168, 96, w21, w0, w13); + TEST_3R("adds_s.h", 176, 208, w22, w29, w31); + TEST_3R("adds_s.h", 184, 120, w23, w3, w15); + TEST_3R("adds_s.h", 192, 112, w24, w19, w17); + TEST_3R("adds_s.h", 200, 200, w25, w30, w13); + TEST_3R("adds_s.h", 208, 24, w26, w23, w5); + TEST_3R("adds_s.h", 216, 176, w27, w30, w27); + TEST_3R("adds_s.h", 224, 64, w28, w1, w16); + TEST_3R("adds_s.h", 232, 112, w29, w31, w24); + TEST_3R("adds_s.h", 240, 104, w30, w18, w15); + TEST_3R("adds_s.h", 200, 224, w31, w15, w6); + TEST_3R("adds_s.w", 0, 32, w0, w5, w6); + TEST_3R("adds_s.w", 8, 200, w1, w21, w3); + TEST_3R("adds_s.w", 16, 184, w2, w8, w20); + TEST_3R("adds_s.w", 24, 16, w3, w6, w1); + TEST_3R("adds_s.w", 32, 48, w4, w29, w7); + TEST_3R("adds_s.w", 40, 0, w5, w27, w13); + TEST_3R("adds_s.w", 48, 224, w6, w11, w13); + TEST_3R("adds_s.w", 56, 16, w7, w4, w19); + TEST_3R("adds_s.w", 64, 32, w8, w19, w13); + TEST_3R("adds_s.w", 72, 16, w9, w3, w19); + TEST_3R("adds_s.w", 80, 88, w10, w16, w25); + TEST_3R("adds_s.w", 88, 152, w11, w0, w14); + TEST_3R("adds_s.w", 96, 160, w12, w9, w22); + TEST_3R("adds_s.w", 104, 216, w13, w13, w22); + TEST_3R("adds_s.w", 112, 104, w14, w18, w18); + TEST_3R("adds_s.w", 120, 160, w15, w25, w13); + TEST_3R("adds_s.w", 128, 232, w16, w6, w30); + TEST_3R("adds_s.w", 136, 64, w17, w19, w15); + TEST_3R("adds_s.w", 144, 144, w18, w6, w23); + TEST_3R("adds_s.w", 152, 208, w19, w4, w26); + TEST_3R("adds_s.w", 160, 176, w20, w20, w20); + TEST_3R("adds_s.w", 168, 144, w21, w10, w0); + TEST_3R("adds_s.w", 176, 56, w22, w10, w14); + TEST_3R("adds_s.w", 184, 88, w23, w19, w4); + TEST_3R("adds_s.w", 192, 128, w24, w10, w0); + TEST_3R("adds_s.w", 200, 64, w25, w7, w9); + TEST_3R("adds_s.w", 208, 208, w26, w13, w15); + TEST_3R("adds_s.w", 216, 176, w27, w12, w27); + TEST_3R("adds_s.w", 224, 136, w28, w2, w16); + TEST_3R("adds_s.w", 232, 152, w29, w20, w7); + TEST_3R("adds_s.w", 240, 128, w30, w25, w1); + TEST_3R("adds_s.w", 112, 112, w31, w16, w11); + TEST_3R("adds_s.d", 0, 40, w0, w21, w17); + TEST_3R("adds_s.d", 8, 136, w1, w9, w21); + TEST_3R("adds_s.d", 16, 24, w2, w19, w21); + TEST_3R("adds_s.d", 24, 32, w3, w26, w14); + TEST_3R("adds_s.d", 32, 208, w4, w14, w27); + TEST_3R("adds_s.d", 40, 16, w5, w0, w7); + TEST_3R("adds_s.d", 48, 24, w6, w2, w23); + TEST_3R("adds_s.d", 56, 184, w7, w23, w30); + TEST_3R("adds_s.d", 64, 72, w8, w16, w31); + TEST_3R("adds_s.d", 72, 64, w9, w0, w10); + TEST_3R("adds_s.d", 80, 16, w10, w2, w0); + TEST_3R("adds_s.d", 88, 96, w11, w17, w9); + TEST_3R("adds_s.d", 96, 56, w12, w30, w28); + TEST_3R("adds_s.d", 104, 0, w13, w13, w27); + TEST_3R("adds_s.d", 112, 176, w14, w10, w10); + TEST_3R("adds_s.d", 120, 16, w15, w4, w5); + TEST_3R("adds_s.d", 128, 152, w16, w4, w13); + TEST_3R("adds_s.d", 136, 184, w17, w7, w4); + TEST_3R("adds_s.d", 144, 136, w18, w30, w3); + TEST_3R("adds_s.d", 152, 80, w19, w14, w2); + TEST_3R("adds_s.d", 160, 24, w20, w20, w20); + TEST_3R("adds_s.d", 168, 80, w21, w13, w8); + TEST_3R("adds_s.d", 176, 176, w22, w13, w26); + TEST_3R("adds_s.d", 184, 40, w23, w22, w2); + TEST_3R("adds_s.d", 192, 184, w24, w18, w30); + TEST_3R("adds_s.d", 200, 120, w25, w8, w9); + TEST_3R("adds_s.d", 208, 16, w26, w12, w14); + TEST_3R("adds_s.d", 216, 72, w27, w16, w27); + TEST_3R("adds_s.d", 224, 64, w28, w30, w23); + TEST_3R("adds_s.d", 232, 224, w29, w11, w21); + TEST_3R("adds_s.d", 240, 112, w30, w19, w3); + TEST_3R("adds_s.d", 16, 32, w31, w25, w18); + TEST_3R("adds_u.b", 0, 160, w0, w21, w30); + TEST_3R("adds_u.b", 8, 216, w1, w7, w28); + TEST_3R("adds_u.b", 16, 24, w2, w2, w2); + TEST_3R("adds_u.b", 24, 200, w3, w5, w25); + TEST_3R("adds_u.b", 32, 232, w4, w20, w20); + TEST_3R("adds_u.b", 40, 168, w5, w12, w15); + TEST_3R("adds_u.b", 48, 48, w6, w3, w15); + TEST_3R("adds_u.b", 56, 64, w7, w25, w18); + TEST_3R("adds_u.b", 64, 48, w8, w28, w24); + TEST_3R("adds_u.b", 72, 176, w9, w14, w10); + TEST_3R("adds_u.b", 80, 128, w10, w17, w30); + TEST_3R("adds_u.b", 88, 56, w11, w31, w28); + TEST_3R("adds_u.b", 96, 32, w12, w7, w25); + TEST_3R("adds_u.b", 104, 16, w13, w22, w30); + TEST_3R("adds_u.b", 112, 184, w14, w18, w27); + TEST_3R("adds_u.b", 120, 80, w15, w2, w4); + TEST_3R("adds_u.b", 128, 72, w16, w17, w25); + TEST_3R("adds_u.b", 136, 32, w17, w4, w0); + TEST_3R("adds_u.b", 144, 224, w18, w28, w1); + TEST_3R("adds_u.b", 152, 0, w19, w6, w4); + TEST_3R("adds_u.b", 160, 136, w20, w16, w2); + TEST_3R("adds_u.b", 168, 192, w21, w16, w31); + TEST_3R("adds_u.b", 176, 104, w22, w23, w24); + TEST_3R("adds_u.b", 184, 120, w23, w13, w22); + TEST_3R("adds_u.b", 192, 0, w24, w31, w9); + TEST_3R("adds_u.b", 200, 56, w25, w29, w11); + TEST_3R("adds_u.b", 208, 160, w26, w31, w28); + TEST_3R("adds_u.b", 216, 208, w27, w25, w0); + TEST_3R("adds_u.b", 224, 40, w28, w16, w28); + TEST_3R("adds_u.b", 232, 224, w29, w5, w22); + TEST_3R("adds_u.b", 240, 48, w30, w9, w12); + TEST_3R("adds_u.b", 192, 40, w31, w31, w11); + TEST_3R("adds_u.h", 0, 168, w0, w10, w28); + TEST_3R("adds_u.h", 8, 120, w1, w2, w22); + TEST_3R("adds_u.h", 16, 24, w2, w2, w2); + TEST_3R("adds_u.h", 24, 16, w3, w1, w7); + TEST_3R("adds_u.h", 32, 80, w4, w6, w6); + TEST_3R("adds_u.h", 40, 112, w5, w13, w16); + TEST_3R("adds_u.h", 48, 216, w6, w9, w19); + TEST_3R("adds_u.h", 56, 120, w7, w10, w23); + TEST_3R("adds_u.h", 64, 16, w8, w6, w28); + TEST_3R("adds_u.h", 72, 56, w9, w5, w16); + TEST_3R("adds_u.h", 80, 16, w10, w16, w8); + TEST_3R("adds_u.h", 88, 56, w11, w27, w4); + TEST_3R("adds_u.h", 96, 176, w12, w29, w27); + TEST_3R("adds_u.h", 104, 56, w13, w22, w28); + TEST_3R("adds_u.h", 112, 136, w14, w24, w2); + TEST_3R("adds_u.h", 120, 16, w15, w5, w19); + TEST_3R("adds_u.h", 128, 0, w16, w15, w6); + TEST_3R("adds_u.h", 136, 232, w17, w25, w29); + TEST_3R("adds_u.h", 144, 128, w18, w31, w25); + TEST_3R("adds_u.h", 152, 32, w19, w9, w30); + TEST_3R("adds_u.h", 160, 216, w20, w6, w15); + TEST_3R("adds_u.h", 168, 16, w21, w6, w10); + TEST_3R("adds_u.h", 176, 24, w22, w1, w7); + TEST_3R("adds_u.h", 184, 112, w23, w4, w30); + TEST_3R("adds_u.h", 192, 168, w24, w15, w22); + TEST_3R("adds_u.h", 200, 8, w25, w30, w28); + TEST_3R("adds_u.h", 208, 32, w26, w18, w11); + TEST_3R("adds_u.h", 216, 208, w27, w3, w4); + TEST_3R("adds_u.h", 224, 112, w28, w2, w28); + TEST_3R("adds_u.h", 232, 72, w29, w10, w5); + TEST_3R("adds_u.h", 240, 208, w30, w9, w24); + TEST_3R("adds_u.h", 120, 0, w31, w31, w24); + TEST_3R("adds_u.w", 0, 200, w0, w2, w21); + TEST_3R("adds_u.w", 8, 216, w1, w9, w16); + TEST_3R("adds_u.w", 16, 96, w2, w2, w2); + TEST_3R("adds_u.w", 24, 24, w3, w8, w14); + TEST_3R("adds_u.w", 32, 152, w4, w2, w2); + TEST_3R("adds_u.w", 40, 24, w5, w26, w15); + TEST_3R("adds_u.w", 48, 128, w6, w5, w2); + TEST_3R("adds_u.w", 56, 112, w7, w9, w19); + TEST_3R("adds_u.w", 64, 104, w8, w12, w30); + TEST_3R("adds_u.w", 72, 0, w9, w25, w7); + TEST_3R("adds_u.w", 80, 112, w10, w11, w31); + TEST_3R("adds_u.w", 88, 8, w11, w4, w1); + TEST_3R("adds_u.w", 96, 168, w12, w31, w10); + TEST_3R("adds_u.w", 104, 192, w13, w30, w18); + TEST_3R("adds_u.w", 112, 144, w14, w12, w16); + TEST_3R("adds_u.w", 120, 224, w15, w24, w10); + TEST_3R("adds_u.w", 128, 208, w16, w23, w15); + TEST_3R("adds_u.w", 136, 8, w17, w24, w10); + TEST_3R("adds_u.w", 144, 224, w18, w4, w8); + TEST_3R("adds_u.w", 152, 224, w19, w29, w15); + TEST_3R("adds_u.w", 160, 104, w20, w9, w14); + TEST_3R("adds_u.w", 168, 112, w21, w13, w15); + TEST_3R("adds_u.w", 176, 160, w22, w12, w25); + TEST_3R("adds_u.w", 184, 224, w23, w10, w11); + TEST_3R("adds_u.w", 192, 8, w24, w22, w27); + TEST_3R("adds_u.w", 200, 104, w25, w15, w5); + TEST_3R("adds_u.w", 208, 192, w26, w6, w20); + TEST_3R("adds_u.w", 216, 232, w27, w30, w12); + TEST_3R("adds_u.w", 224, 112, w28, w26, w28); + TEST_3R("adds_u.w", 232, 24, w29, w5, w31); + TEST_3R("adds_u.w", 240, 16, w30, w20, w4); + TEST_3R("adds_u.w", 208, 168, w31, w31, w2); + TEST_3R("adds_u.d", 0, 208, w0, w17, w5); + TEST_3R("adds_u.d", 8, 216, w1, w10, w5); + TEST_3R("adds_u.d", 16, 112, w2, w2, w2); + TEST_3R("adds_u.d", 24, 144, w3, w9, w18); + TEST_3R("adds_u.d", 32, 128, w4, w17, w17); + TEST_3R("adds_u.d", 40, 80, w5, w23, w14); + TEST_3R("adds_u.d", 48, 176, w6, w11, w1); + TEST_3R("adds_u.d", 56, 48, w7, w24, w30); + TEST_3R("adds_u.d", 64, 8, w8, w9, w3); + TEST_3R("adds_u.d", 72, 24, w9, w23, w4); + TEST_3R("adds_u.d", 80, 0, w10, w25, w3); + TEST_3R("adds_u.d", 88, 80, w11, w10, w8); + TEST_3R("adds_u.d", 96, 176, w12, w20, w14); + TEST_3R("adds_u.d", 104, 112, w13, w10, w23); + TEST_3R("adds_u.d", 112, 112, w14, w28, w8); + TEST_3R("adds_u.d", 120, 200, w15, w19, w22); + TEST_3R("adds_u.d", 128, 16, w16, w30, w23); + TEST_3R("adds_u.d", 136, 64, w17, w22, w21); + TEST_3R("adds_u.d", 144, 192, w18, w31, w24); + TEST_3R("adds_u.d", 152, 32, w19, w23, w15); + TEST_3R("adds_u.d", 160, 168, w20, w6, w8); + TEST_3R("adds_u.d", 168, 96, w21, w26, w18); + TEST_3R("adds_u.d", 176, 224, w22, w31, w7); + TEST_3R("adds_u.d", 184, 56, w23, w1, w17); + TEST_3R("adds_u.d", 192, 176, w24, w21, w13); + TEST_3R("adds_u.d", 200, 112, w25, w10, w0); + TEST_3R("adds_u.d", 208, 56, w26, w7, w31); + TEST_3R("adds_u.d", 216, 112, w27, w10, w21); + TEST_3R("adds_u.d", 224, 48, w28, w14, w28); + TEST_3R("adds_u.d", 232, 136, w29, w28, w17); + TEST_3R("adds_u.d", 240, 16, w30, w12, w24); + TEST_3R("adds_u.d", 120, 64, w31, w31, w20); + TEST_3R("addv.b", 0, 168, w0, w22, w12); + TEST_3R("addv.b", 8, 8, w1, w14, w13); + TEST_3R("addv.b", 16, 0, w2, w12, w13); + TEST_3R("addv.b", 24, 176, w3, w19, w12); + TEST_3R("addv.b", 32, 56, w4, w30, w2); + TEST_3R("addv.b", 40, 208, w5, w12, w23); + TEST_3R("addv.b", 48, 64, w6, w29, w3); + TEST_3R("addv.b", 56, 224, w7, w7, w7); + TEST_3R("addv.b", 64, 208, w8, w21, w23); + TEST_3R("addv.b", 72, 152, w9, w28, w13); + TEST_3R("addv.b", 80, 184, w10, w3, w25); + TEST_3R("addv.b", 88, 184, w11, w18, w11); + TEST_3R("addv.b", 96, 0, w12, w23, w1); + TEST_3R("addv.b", 104, 8, w13, w4, w7); + TEST_3R("addv.b", 112, 120, w14, w17, w17); + TEST_3R("addv.b", 120, 176, w15, w24, w19); + TEST_3R("addv.b", 128, 24, w16, w4, w10); + TEST_3R("addv.b", 136, 88, w17, w1, w13); + TEST_3R("addv.b", 144, 216, w18, w22, w2); + TEST_3R("addv.b", 152, 232, w19, w13, w3); + TEST_3R("addv.b", 160, 112, w20, w26, w15); + TEST_3R("addv.b", 168, 200, w21, w21, w30); + TEST_3R("addv.b", 176, 80, w22, w16, w3); + TEST_3R("addv.b", 184, 40, w23, w17, w9); + TEST_3R("addv.b", 192, 80, w24, w3, w29); + TEST_3R("addv.b", 200, 128, w25, w27, w16); + TEST_3R("addv.b", 208, 48, w26, w31, w16); + TEST_3R("addv.b", 216, 80, w27, w7, w26); + TEST_3R("addv.b", 224, 48, w28, w9, w26); + TEST_3R("addv.b", 232, 88, w29, w12, w22); + TEST_3R("addv.b", 240, 232, w30, w27, w28); + TEST_3R("addv.b", 64, 72, w31, w4, w13); + TEST_3R("addv.h", 0, 224, w0, w20, w29); + TEST_3R("addv.h", 8, 144, w1, w0, w21); + TEST_3R("addv.h", 16, 152, w2, w29, w9); + TEST_3R("addv.h", 24, 136, w3, w13, w16); + TEST_3R("addv.h", 32, 56, w4, w7, w1); + TEST_3R("addv.h", 40, 16, w5, w14, w27); + TEST_3R("addv.h", 48, 72, w6, w23, w21); + TEST_3R("addv.h", 56, 48, w7, w7, w7); + TEST_3R("addv.h", 64, 216, w8, w11, w31); + TEST_3R("addv.h", 72, 0, w9, w5, w3); + TEST_3R("addv.h", 80, 72, w10, w17, w9); + TEST_3R("addv.h", 88, 136, w11, w26, w11); + TEST_3R("addv.h", 96, 208, w12, w4, w14); + TEST_3R("addv.h", 104, 40, w13, w30, w21); + TEST_3R("addv.h", 112, 72, w14, w13, w13); + TEST_3R("addv.h", 120, 40, w15, w31, w28); + TEST_3R("addv.h", 128, 208, w16, w26, w2); + TEST_3R("addv.h", 136, 128, w17, w16, w12); + TEST_3R("addv.h", 144, 144, w18, w27, w21); + TEST_3R("addv.h", 152, 88, w19, w3, w26); + TEST_3R("addv.h", 160, 96, w20, w24, w11); + TEST_3R("addv.h", 168, 104, w21, w21, w2); + TEST_3R("addv.h", 176, 88, w22, w12, w31); + TEST_3R("addv.h", 184, 136, w23, w19, w12); + TEST_3R("addv.h", 192, 80, w24, w8, w10); + TEST_3R("addv.h", 200, 80, w25, w5, w9); + TEST_3R("addv.h", 208, 224, w26, w16, w4); + TEST_3R("addv.h", 216, 80, w27, w18, w20); + TEST_3R("addv.h", 224, 208, w28, w24, w15); + TEST_3R("addv.h", 232, 208, w29, w19, w0); + TEST_3R("addv.h", 240, 64, w30, w11, w12); + TEST_3R("addv.h", 152, 144, w31, w13, w6); + TEST_3R("addv.w", 0, 184, w0, w5, w31); + TEST_3R("addv.w", 8, 192, w1, w18, w24); + TEST_3R("addv.w", 16, 24, w2, w28, w30); + TEST_3R("addv.w", 24, 24, w3, w6, w0); + TEST_3R("addv.w", 32, 104, w4, w10, w5); + TEST_3R("addv.w", 40, 208, w5, w30, w23); + TEST_3R("addv.w", 48, 96, w6, w13, w29); + TEST_3R("addv.w", 56, 32, w7, w7, w7); + TEST_3R("addv.w", 64, 72, w8, w30, w24); + TEST_3R("addv.w", 72, 40, w9, w10, w16); + TEST_3R("addv.w", 80, 192, w10, w16, w20); + TEST_3R("addv.w", 88, 32, w11, w22, w11); + TEST_3R("addv.w", 96, 40, w12, w0, w8); + TEST_3R("addv.w", 104, 136, w13, w21, w4); + TEST_3R("addv.w", 112, 104, w14, w16, w16); + TEST_3R("addv.w", 120, 80, w15, w9, w26); + TEST_3R("addv.w", 128, 0, w16, w15, w23); + TEST_3R("addv.w", 136, 176, w17, w6, w13); + TEST_3R("addv.w", 144, 208, w18, w3, w0); + TEST_3R("addv.w", 152, 40, w19, w1, w24); + TEST_3R("addv.w", 160, 192, w20, w11, w8); + TEST_3R("addv.w", 168, 40, w21, w21, w28); + TEST_3R("addv.w", 176, 72, w22, w25, w18); + TEST_3R("addv.w", 184, 120, w23, w25, w26); + TEST_3R("addv.w", 192, 128, w24, w14, w30); + TEST_3R("addv.w", 200, 200, w25, w30, w9); + TEST_3R("addv.w", 208, 184, w26, w25, w29); + TEST_3R("addv.w", 216, 104, w27, w16, w2); + TEST_3R("addv.w", 224, 168, w28, w16, w5); + TEST_3R("addv.w", 232, 48, w29, w16, w7); + TEST_3R("addv.w", 240, 56, w30, w29, w18); + TEST_3R("addv.w", 72, 104, w31, w3, w14); + TEST_3R("addv.d", 0, 104, w0, w10, w21); + TEST_3R("addv.d", 8, 72, w1, w5, w3); + TEST_3R("addv.d", 16, 24, w2, w8, w21); + TEST_3R("addv.d", 24, 40, w3, w31, w17); + TEST_3R("addv.d", 32, 152, w4, w15, w19); + TEST_3R("addv.d", 40, 192, w5, w31, w25); + TEST_3R("addv.d", 48, 120, w6, w16, w0); + TEST_3R("addv.d", 56, 216, w7, w7, w7); + TEST_3R("addv.d", 64, 32, w8, w18, w27); + TEST_3R("addv.d", 72, 216, w9, w1, w22); + TEST_3R("addv.d", 80, 96, w10, w1, w0); + TEST_3R("addv.d", 88, 160, w11, w28, w11); + TEST_3R("addv.d", 96, 104, w12, w4, w21); + TEST_3R("addv.d", 104, 128, w13, w6, w23); + TEST_3R("addv.d", 112, 160, w14, w1, w1); + TEST_3R("addv.d", 120, 16, w15, w21, w13); + TEST_3R("addv.d", 128, 208, w16, w8, w22); + TEST_3R("addv.d", 136, 208, w17, w1, w28); + TEST_3R("addv.d", 144, 192, w18, w1, w25); + TEST_3R("addv.d", 152, 16, w19, w20, w18); + TEST_3R("addv.d", 160, 160, w20, w10, w30); + TEST_3R("addv.d", 168, 40, w21, w21, w10); + TEST_3R("addv.d", 176, 144, w22, w18, w16); + TEST_3R("addv.d", 184, 136, w23, w7, w30); + TEST_3R("addv.d", 192, 24, w24, w30, w1); + TEST_3R("addv.d", 200, 200, w25, w21, w22); + TEST_3R("addv.d", 208, 152, w26, w27, w31); + TEST_3R("addv.d", 216, 224, w27, w0, w11); + TEST_3R("addv.d", 224, 184, w28, w2, w4); + TEST_3R("addv.d", 232, 152, w29, w22, w24); + TEST_3R("addv.d", 240, 104, w30, w11, w2); + TEST_3R("addv.d", 48, 152, w31, w1, w13); + TEST_3R("asub_s.b", 0, 96, w0, w26, w28); + TEST_3R("asub_s.b", 8, 56, w1, w15, w19); + TEST_3R("asub_s.b", 16, 216, w2, w10, w18); + TEST_3R("asub_s.b", 24, 160, w3, w10, w18); + TEST_3R("asub_s.b", 32, 152, w4, w0, w20); + TEST_3R("asub_s.b", 40, 0, w5, w25, w10); + TEST_3R("asub_s.b", 48, 112, w6, w4, w21); + TEST_3R("asub_s.b", 56, 0, w7, w13, w23); + TEST_3R("asub_s.b", 64, 64, w8, w22, w11); + TEST_3R("asub_s.b", 72, 40, w9, w3, w6); + TEST_3R("asub_s.b", 80, 184, w10, w27, w0); + TEST_3R("asub_s.b", 88, 216, w11, w30, w15); + TEST_3R("asub_s.b", 96, 24, w12, w27, w25); + TEST_3R("asub_s.b", 104, 208, w13, w13, w6); + TEST_3R("asub_s.b", 112, 64, w14, w15, w29); + TEST_3R("asub_s.b", 120, 104, w15, w4, w25); + TEST_3R("asub_s.b", 128, 176, w16, w14, w13); + TEST_3R("asub_s.b", 136, 104, w17, w4, w3); + TEST_3R("asub_s.b", 144, 64, w18, w27, w7); + TEST_3R("asub_s.b", 152, 88, w19, w6, w7); + TEST_3R("asub_s.b", 160, 176, w20, w12, w3); + TEST_3R("asub_s.b", 168, 128, w21, w13, w27); + TEST_3R("asub_s.b", 176, 136, w22, w28, w6); + TEST_3R("asub_s.b", 184, 96, w23, w22, w22); + TEST_3R("asub_s.b", 192, 224, w24, w4, w26); + TEST_3R("asub_s.b", 200, 160, w25, w1, w30); + TEST_3R("asub_s.b", 208, 16, w26, w28, w5); + TEST_3R("asub_s.b", 216, 56, w27, w29, w27); + TEST_3R("asub_s.b", 224, 208, w28, w11, w12); + TEST_3R("asub_s.b", 232, 128, w29, w29, w29); + TEST_3R("asub_s.b", 240, 8, w30, w18, w10); + TEST_3R("asub_s.b", 104, 40, w31, w27, w22); + TEST_3R("asub_s.h", 0, 0, w0, w3, w23); + TEST_3R("asub_s.h", 8, 8, w1, w0, w29); + TEST_3R("asub_s.h", 16, 128, w2, w22, w0); + TEST_3R("asub_s.h", 24, 32, w3, w16, w19); + TEST_3R("asub_s.h", 32, 232, w4, w14, w9); + TEST_3R("asub_s.h", 40, 128, w5, w10, w14); + TEST_3R("asub_s.h", 48, 80, w6, w8, w23); + TEST_3R("asub_s.h", 56, 208, w7, w20, w27); + TEST_3R("asub_s.h", 64, 88, w8, w6, w5); + TEST_3R("asub_s.h", 72, 8, w9, w1, w28); + TEST_3R("asub_s.h", 80, 16, w10, w0, w31); + TEST_3R("asub_s.h", 88, 88, w11, w2, w31); + TEST_3R("asub_s.h", 96, 136, w12, w1, w21); + TEST_3R("asub_s.h", 104, 80, w13, w13, w4); + TEST_3R("asub_s.h", 112, 176, w14, w2, w8); + TEST_3R("asub_s.h", 120, 232, w15, w11, w7); + TEST_3R("asub_s.h", 128, 208, w16, w26, w14); + TEST_3R("asub_s.h", 136, 184, w17, w31, w27); + TEST_3R("asub_s.h", 144, 96, w18, w3, w1); + TEST_3R("asub_s.h", 152, 24, w19, w0, w3); + TEST_3R("asub_s.h", 160, 200, w20, w25, w3); + TEST_3R("asub_s.h", 168, 232, w21, w10, w5); + TEST_3R("asub_s.h", 176, 96, w22, w25, w6); + TEST_3R("asub_s.h", 184, 120, w23, w8, w8); + TEST_3R("asub_s.h", 192, 16, w24, w8, w10); + TEST_3R("asub_s.h", 200, 136, w25, w28, w21); + TEST_3R("asub_s.h", 208, 152, w26, w27, w15); + TEST_3R("asub_s.h", 216, 160, w27, w1, w27); + TEST_3R("asub_s.h", 224, 184, w28, w8, w14); + TEST_3R("asub_s.h", 232, 152, w29, w29, w29); + TEST_3R("asub_s.h", 240, 32, w30, w0, w11); + TEST_3R("asub_s.h", 56, 112, w31, w15, w4); + TEST_3R("asub_s.w", 0, 56, w0, w15, w10); + TEST_3R("asub_s.w", 8, 152, w1, w8, w16); + TEST_3R("asub_s.w", 16, 208, w2, w16, w27); + TEST_3R("asub_s.w", 24, 80, w3, w26, w14); + TEST_3R("asub_s.w", 32, 56, w4, w15, w8); + TEST_3R("asub_s.w", 40, 8, w5, w31, w17); + TEST_3R("asub_s.w", 48, 152, w6, w0, w25); + TEST_3R("asub_s.w", 56, 72, w7, w14, w4); + TEST_3R("asub_s.w", 64, 216, w8, w14, w15); + TEST_3R("asub_s.w", 72, 88, w9, w29, w19); + TEST_3R("asub_s.w", 80, 8, w10, w26, w2); + TEST_3R("asub_s.w", 88, 72, w11, w5, w10); + TEST_3R("asub_s.w", 96, 128, w12, w18, w26); + TEST_3R("asub_s.w", 104, 64, w13, w13, w8); + TEST_3R("asub_s.w", 112, 0, w14, w18, w27); + TEST_3R("asub_s.w", 120, 192, w15, w27, w8); + TEST_3R("asub_s.w", 128, 64, w16, w12, w23); + TEST_3R("asub_s.w", 136, 160, w17, w5, w3); + TEST_3R("asub_s.w", 144, 200, w18, w9, w12); + TEST_3R("asub_s.w", 152, 104, w19, w24, w23); + TEST_3R("asub_s.w", 160, 64, w20, w11, w6); + TEST_3R("asub_s.w", 168, 88, w21, w14, w31); + TEST_3R("asub_s.w", 176, 24, w22, w24, w8); + TEST_3R("asub_s.w", 184, 168, w23, w19, w19); + TEST_3R("asub_s.w", 192, 136, w24, w23, w7); + TEST_3R("asub_s.w", 200, 72, w25, w18, w11); + TEST_3R("asub_s.w", 208, 16, w26, w27, w14); + TEST_3R("asub_s.w", 216, 160, w27, w18, w27); + TEST_3R("asub_s.w", 224, 80, w28, w11, w21); + TEST_3R("asub_s.w", 232, 224, w29, w29, w29); + TEST_3R("asub_s.w", 240, 200, w30, w2, w12); + TEST_3R("asub_s.w", 136, 64, w31, w24, w22); + TEST_3R("asub_s.d", 0, 64, w0, w19, w30); + TEST_3R("asub_s.d", 8, 112, w1, w2, w17); + TEST_3R("asub_s.d", 16, 24, w2, w25, w19); + TEST_3R("asub_s.d", 24, 64, w3, w4, w13); + TEST_3R("asub_s.d", 32, 40, w4, w19, w20); + TEST_3R("asub_s.d", 40, 88, w5, w4, w31); + TEST_3R("asub_s.d", 48, 48, w6, w7, w20); + TEST_3R("asub_s.d", 56, 8, w7, w9, w0); + TEST_3R("asub_s.d", 64, 40, w8, w24, w9); + TEST_3R("asub_s.d", 72, 112, w9, w30, w7); + TEST_3R("asub_s.d", 80, 192, w10, w29, w13); + TEST_3R("asub_s.d", 88, 200, w11, w14, w1); + TEST_3R("asub_s.d", 96, 232, w12, w7, w20); + TEST_3R("asub_s.d", 104, 224, w13, w13, w12); + TEST_3R("asub_s.d", 112, 80, w14, w0, w31); + TEST_3R("asub_s.d", 120, 144, w15, w25, w3); + TEST_3R("asub_s.d", 128, 184, w16, w8, w10); + TEST_3R("asub_s.d", 136, 24, w17, w25, w19); + TEST_3R("asub_s.d", 144, 0, w18, w3, w27); + TEST_3R("asub_s.d", 152, 160, w19, w12, w26); + TEST_3R("asub_s.d", 160, 104, w20, w19, w11); + TEST_3R("asub_s.d", 168, 40, w21, w1, w31); + TEST_3R("asub_s.d", 176, 112, w22, w2, w12); + TEST_3R("asub_s.d", 184, 0, w23, w22, w22); + TEST_3R("asub_s.d", 192, 176, w24, w31, w23); + TEST_3R("asub_s.d", 200, 152, w25, w30, w13); + TEST_3R("asub_s.d", 208, 120, w26, w2, w7); + TEST_3R("asub_s.d", 216, 224, w27, w11, w27); + TEST_3R("asub_s.d", 224, 96, w28, w0, w20); + TEST_3R("asub_s.d", 232, 72, w29, w29, w29); + TEST_3R("asub_s.d", 240, 64, w30, w22, w16); + TEST_3R("asub_s.d", 112, 48, w31, w23, w4); + TEST_3R("asub_u.b", 0, 8, w0, w0, w20); + TEST_3R("asub_u.b", 8, 32, w1, w17, w19); + TEST_3R("asub_u.b", 16, 144, w2, w22, w18); + TEST_3R("asub_u.b", 24, 48, w3, w20, w27); + TEST_3R("asub_u.b", 32, 48, w4, w14, w28); + TEST_3R("asub_u.b", 40, 208, w5, w5, w5); + TEST_3R("asub_u.b", 48, 184, w6, w0, w28); + TEST_3R("asub_u.b", 56, 64, w7, w16, w7); + TEST_3R("asub_u.b", 64, 224, w8, w16, w20); + TEST_3R("asub_u.b", 72, 80, w9, w5, w25); + TEST_3R("asub_u.b", 80, 184, w10, w5, w0); + TEST_3R("asub_u.b", 88, 168, w11, w25, w29); + TEST_3R("asub_u.b", 96, 0, w12, w13, w13); + TEST_3R("asub_u.b", 104, 144, w13, w5, w31); + TEST_3R("asub_u.b", 112, 48, w14, w26, w19); + TEST_3R("asub_u.b", 120, 160, w15, w21, w19); + TEST_3R("asub_u.b", 128, 136, w16, w17, w20); + TEST_3R("asub_u.b", 136, 176, w17, w16, w2); + TEST_3R("asub_u.b", 144, 64, w18, w1, w22); + TEST_3R("asub_u.b", 152, 144, w19, w23, w16); + TEST_3R("asub_u.b", 160, 208, w20, w29, w16); + TEST_3R("asub_u.b", 168, 16, w21, w22, w14); + TEST_3R("asub_u.b", 176, 232, w22, w3, w0); + TEST_3R("asub_u.b", 184, 160, w23, w2, w19); + TEST_3R("asub_u.b", 192, 136, w24, w21, w10); + TEST_3R("asub_u.b", 200, 24, w25, w9, w16); + TEST_3R("asub_u.b", 208, 40, w26, w29, w24); + TEST_3R("asub_u.b", 216, 88, w27, w13, w26); + TEST_3R("asub_u.b", 224, 208, w28, w14, w13); + TEST_3R("asub_u.b", 232, 96, w29, w2, w4); + TEST_3R("asub_u.b", 240, 176, w30, w9, w1); + TEST_3R("asub_u.b", 16, 224, w31, w14, w24); + TEST_3R("asub_u.h", 0, 144, w0, w0, w27); + TEST_3R("asub_u.h", 8, 208, w1, w28, w30); + TEST_3R("asub_u.h", 16, 208, w2, w16, w19); + TEST_3R("asub_u.h", 24, 128, w3, w26, w28); + TEST_3R("asub_u.h", 32, 56, w4, w21, w25); + TEST_3R("asub_u.h", 40, 0, w5, w5, w5); + TEST_3R("asub_u.h", 48, 224, w6, w20, w16); + TEST_3R("asub_u.h", 56, 64, w7, w1, w7); + TEST_3R("asub_u.h", 64, 40, w8, w23, w6); + TEST_3R("asub_u.h", 72, 88, w9, w0, w7); + TEST_3R("asub_u.h", 80, 192, w10, w14, w31); + TEST_3R("asub_u.h", 88, 96, w11, w17, w27); + TEST_3R("asub_u.h", 96, 184, w12, w13, w13); + TEST_3R("asub_u.h", 104, 88, w13, w29, w30); + TEST_3R("asub_u.h", 112, 72, w14, w15, w24); + TEST_3R("asub_u.h", 120, 16, w15, w16, w13); + TEST_3R("asub_u.h", 128, 184, w16, w10, w14); + TEST_3R("asub_u.h", 136, 168, w17, w31, w30); + TEST_3R("asub_u.h", 144, 32, w18, w0, w19); + TEST_3R("asub_u.h", 152, 48, w19, w6, w29); + TEST_3R("asub_u.h", 160, 176, w20, w14, w13); + TEST_3R("asub_u.h", 168, 192, w21, w13, w16); + TEST_3R("asub_u.h", 176, 224, w22, w8, w6); + TEST_3R("asub_u.h", 184, 176, w23, w1, w4); + TEST_3R("asub_u.h", 192, 56, w24, w14, w19); + TEST_3R("asub_u.h", 200, 16, w25, w23, w3); + TEST_3R("asub_u.h", 208, 224, w26, w25, w14); + TEST_3R("asub_u.h", 216, 160, w27, w2, w13); + TEST_3R("asub_u.h", 224, 32, w28, w0, w13); + TEST_3R("asub_u.h", 232, 64, w29, w22, w20); + TEST_3R("asub_u.h", 240, 64, w30, w12, w2); + TEST_3R("asub_u.h", 64, 16, w31, w16, w15); + TEST_3R("asub_u.w", 0, 176, w0, w0, w24); + TEST_3R("asub_u.w", 8, 56, w1, w9, w25); + TEST_3R("asub_u.w", 16, 72, w2, w10, w7); + TEST_3R("asub_u.w", 24, 56, w3, w30, w2); + TEST_3R("asub_u.w", 32, 40, w4, w24, w16); + TEST_3R("asub_u.w", 40, 24, w5, w5, w5); + TEST_3R("asub_u.w", 48, 120, w6, w29, w16); + TEST_3R("asub_u.w", 56, 224, w7, w10, w7); + TEST_3R("asub_u.w", 64, 168, w8, w17, w30); + TEST_3R("asub_u.w", 72, 232, w9, w29, w0); + TEST_3R("asub_u.w", 80, 120, w10, w13, w16); + TEST_3R("asub_u.w", 88, 64, w11, w19, w8); + TEST_3R("asub_u.w", 96, 160, w12, w28, w28); + TEST_3R("asub_u.w", 104, 184, w13, w0, w6); + TEST_3R("asub_u.w", 112, 176, w14, w30, w9); + TEST_3R("asub_u.w", 120, 152, w15, w0, w18); + TEST_3R("asub_u.w", 128, 224, w16, w26, w13); + TEST_3R("asub_u.w", 136, 208, w17, w21, w24); + TEST_3R("asub_u.w", 144, 16, w18, w6, w22); + TEST_3R("asub_u.w", 152, 120, w19, w3, w23); + TEST_3R("asub_u.w", 160, 8, w20, w16, w7); + TEST_3R("asub_u.w", 168, 80, w21, w4, w15); + TEST_3R("asub_u.w", 176, 80, w22, w0, w16); + TEST_3R("asub_u.w", 184, 40, w23, w7, w25); + TEST_3R("asub_u.w", 192, 8, w24, w16, w1); + TEST_3R("asub_u.w", 200, 24, w25, w3, w0); + TEST_3R("asub_u.w", 208, 64, w26, w19, w29); + TEST_3R("asub_u.w", 216, 40, w27, w15, w21); + TEST_3R("asub_u.w", 224, 168, w28, w21, w11); + TEST_3R("asub_u.w", 232, 56, w29, w24, w2); + TEST_3R("asub_u.w", 240, 120, w30, w9, w7); + TEST_3R("asub_u.w", 104, 104, w31, w24, w7); + TEST_3R("asub_u.d", 0, 112, w0, w0, w7); + TEST_3R("asub_u.d", 8, 176, w1, w2, w6); + TEST_3R("asub_u.d", 16, 232, w2, w3, w5); + TEST_3R("asub_u.d", 24, 72, w3, w4, w20); + TEST_3R("asub_u.d", 32, 136, w4, w30, w17); + TEST_3R("asub_u.d", 40, 104, w5, w5, w5); + TEST_3R("asub_u.d", 48, 96, w6, w25, w3); + TEST_3R("asub_u.d", 56, 232, w7, w23, w7); + TEST_3R("asub_u.d", 64, 176, w8, w20, w19); + TEST_3R("asub_u.d", 72, 176, w9, w30, w26); + TEST_3R("asub_u.d", 80, 152, w10, w22, w2); + TEST_3R("asub_u.d", 88, 32, w11, w31, w9); + TEST_3R("asub_u.d", 96, 136, w12, w2, w2); + TEST_3R("asub_u.d", 104, 176, w13, w25, w5); + TEST_3R("asub_u.d", 112, 120, w14, w1, w9); + TEST_3R("asub_u.d", 120, 200, w15, w28, w8); + TEST_3R("asub_u.d", 128, 224, w16, w10, w22); + TEST_3R("asub_u.d", 136, 192, w17, w4, w25); + TEST_3R("asub_u.d", 144, 64, w18, w27, w21); + TEST_3R("asub_u.d", 152, 144, w19, w14, w26); + TEST_3R("asub_u.d", 160, 56, w20, w8, w12); + TEST_3R("asub_u.d", 168, 184, w21, w10, w12); + TEST_3R("asub_u.d", 176, 24, w22, w20, w0); + TEST_3R("asub_u.d", 184, 96, w23, w3, w25); + TEST_3R("asub_u.d", 192, 96, w24, w26, w12); + TEST_3R("asub_u.d", 200, 56, w25, w22, w20); + TEST_3R("asub_u.d", 208, 152, w26, w0, w10); + TEST_3R("asub_u.d", 216, 136, w27, w4, w15); + TEST_3R("asub_u.d", 224, 40, w28, w25, w23); + TEST_3R("asub_u.d", 232, 176, w29, w20, w28); + TEST_3R("asub_u.d", 240, 208, w30, w0, w24); + TEST_3R("asub_u.d", 120, 112, w31, w12, w20); + TEST_3R("ave_s.b", 0, 144, w0, w16, w31); + TEST_3R("ave_s.b", 8, 128, w1, w17, w21); + TEST_3R("ave_s.b", 16, 128, w2, w12, w22); + TEST_3R("ave_s.b", 24, 128, w3, w9, w26); + TEST_3R("ave_s.b", 32, 120, w4, w24, w26); + TEST_3R("ave_s.b", 40, 48, w5, w15, w5); + TEST_3R("ave_s.b", 48, 232, w6, w17, w12); + TEST_3R("ave_s.b", 56, 72, w7, w18, w4); + TEST_3R("ave_s.b", 64, 192, w8, w30, w24); + TEST_3R("ave_s.b", 72, 104, w9, w11, w10); + TEST_3R("ave_s.b", 80, 120, w10, w16, w30); + TEST_3R("ave_s.b", 88, 232, w11, w16, w31); + TEST_3R("ave_s.b", 96, 40, w12, w5, w21); + TEST_3R("ave_s.b", 104, 0, w13, w27, w21); + TEST_3R("ave_s.b", 112, 184, w14, w22, w25); + TEST_3R("ave_s.b", 120, 56, w15, w16, w22); + TEST_3R("ave_s.b", 128, 112, w16, w23, w8); + TEST_3R("ave_s.b", 136, 160, w17, w17, w17); + TEST_3R("ave_s.b", 144, 0, w18, w26, w25); + TEST_3R("ave_s.b", 152, 64, w19, w24, w18); + TEST_3R("ave_s.b", 160, 184, w20, w3, w3); + TEST_3R("ave_s.b", 168, 120, w21, w16, w20); + TEST_3R("ave_s.b", 176, 200, w22, w10, w4); + TEST_3R("ave_s.b", 184, 40, w23, w22, w9); + TEST_3R("ave_s.b", 192, 16, w24, w24, w14); + TEST_3R("ave_s.b", 200, 8, w25, w4, w15); + TEST_3R("ave_s.b", 208, 136, w26, w29, w8); + TEST_3R("ave_s.b", 216, 64, w27, w19, w17); + TEST_3R("ave_s.b", 224, 224, w28, w27, w6); + TEST_3R("ave_s.b", 232, 232, w29, w21, w0); + TEST_3R("ave_s.b", 240, 64, w30, w14, w18); + TEST_3R("ave_s.b", 128, 112, w31, w17, w14); + TEST_3R("ave_s.h", 0, 200, w0, w8, w10); + TEST_3R("ave_s.h", 8, 96, w1, w2, w0); + TEST_3R("ave_s.h", 16, 232, w2, w17, w14); + TEST_3R("ave_s.h", 24, 0, w3, w21, w29); + TEST_3R("ave_s.h", 32, 8, w4, w18, w6); + TEST_3R("ave_s.h", 40, 64, w5, w6, w5); + TEST_3R("ave_s.h", 48, 8, w6, w0, w1); + TEST_3R("ave_s.h", 56, 8, w7, w24, w23); + TEST_3R("ave_s.h", 64, 208, w8, w2, w5); + TEST_3R("ave_s.h", 72, 104, w9, w18, w22); + TEST_3R("ave_s.h", 80, 112, w10, w18, w28); + TEST_3R("ave_s.h", 88, 216, w11, w29, w5); + TEST_3R("ave_s.h", 96, 104, w12, w29, w24); + TEST_3R("ave_s.h", 104, 16, w13, w12, w16); + TEST_3R("ave_s.h", 112, 144, w14, w9, w3); + TEST_3R("ave_s.h", 120, 96, w15, w1, w8); + TEST_3R("ave_s.h", 128, 224, w16, w2, w10); + TEST_3R("ave_s.h", 136, 216, w17, w17, w17); + TEST_3R("ave_s.h", 144, 152, w18, w1, w3); + TEST_3R("ave_s.h", 152, 184, w19, w6, w15); + TEST_3R("ave_s.h", 160, 144, w20, w17, w17); + TEST_3R("ave_s.h", 168, 168, w21, w24, w23); + TEST_3R("ave_s.h", 176, 168, w22, w30, w0); + TEST_3R("ave_s.h", 184, 88, w23, w22, w27); + TEST_3R("ave_s.h", 192, 24, ... [truncated message content] |
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From: Petar J. <pe...@so...> - 2017-10-27 22:43:06
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=bf87528d109b4687f03ed0bcf3aa86127353be13 commit bf87528d109b4687f03ed0bcf3aa86127353be13 Author: Petar Jovanovic <mip...@gm...> Date: Sat Oct 28 00:39:16 2017 +0200 mips: update NEWS about MIPS MSA support Spread the word about MIPS MSA support. Related BZ issue - #382563. Diff: --- NEWS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/NEWS b/NEWS index 3bb9ba2..3fca968 100644 --- a/NEWS +++ b/NEWS @@ -17,6 +17,7 @@ support for X86/macOS 10.13, AMD64/macOS 10.13. * ================== PLATFORM CHANGES ================= * Preliminary support for macOS 10.13 has been added. +* mips: support for MIPS SIMD architecture (MSA) has been added. * ==================== TOOL CHANGES ==================== @@ -52,6 +53,7 @@ where XXXXXX is the bug number as listed below. 382256 gz compiler flag test doesn't work for gold 382407 vg_perf needs "--terse" command line option 382515 "Assertion 'di->have_dinfo' failed." on wine's dlls/mscoree/tests/mscoree.c +382563 MIPS MSA ASE support 382998 xml-socket doesn't work 383275 massif valgrind: m_xarray.c:162 (ensureSpaceXA): Assertion '!xa->arr' failed 384096 Mention AddrCheck at Memcheck's command line option --undef-value-errors=no |
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From: Petar J. <pe...@so...> - 2017-10-27 22:42:55
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4686886774a770acedd80951ebd71a8f834b8f30 commit 4686886774a770acedd80951ebd71a8f834b8f30 Author: Petar Jovanovic <mip...@gm...> Date: Fri Oct 27 15:10:37 2017 +0200 mips: add support for MSA regs in Memcheck Add support for MSA registers in Memcheck. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #382563. Diff: --- memcheck/mc_machine.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c index 1d57e0c..2f2afad 100644 --- a/memcheck/mc_machine.c +++ b/memcheck/mc_machine.c @@ -1162,6 +1162,39 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o == GOF(LLaddr) && sz == 4) return -1; /* slot unused */ if (o == GOF(LLdata) && sz == 4) return -1; /* slot unused */ + if (o >= GOF(w0) && o+sz <= GOF(w0) + SZB(w0)) return GOF(w0); + if (o >= GOF(w1) && o+sz <= GOF(w1) + SZB(w1)) return GOF(w1); + if (o >= GOF(w2) && o+sz <= GOF(w2) + SZB(w2)) return GOF(w2); + if (o >= GOF(w3) && o+sz <= GOF(w3) + SZB(w3)) return GOF(w3); + if (o >= GOF(w4) && o+sz <= GOF(w4) + SZB(w4)) return GOF(w4); + if (o >= GOF(w5) && o+sz <= GOF(w5) + SZB(w5)) return GOF(w5); + if (o >= GOF(w6) && o+sz <= GOF(w6) + SZB(w6)) return GOF(w6); + if (o >= GOF(w7) && o+sz <= GOF(w7) + SZB(w7)) return GOF(w7); + if (o >= GOF(w8) && o+sz <= GOF(w8) + SZB(w8)) return GOF(w8); + if (o >= GOF(w9) && o+sz <= GOF(w9) + SZB(w9)) return GOF(w9); + if (o >= GOF(w10) && o+sz <= GOF(w10) + SZB(w10)) return GOF(w10); + if (o >= GOF(w11) && o+sz <= GOF(w11) + SZB(w11)) return GOF(w11); + if (o >= GOF(w12) && o+sz <= GOF(w12) + SZB(w12)) return GOF(w12); + if (o >= GOF(w13) && o+sz <= GOF(w13) + SZB(w13)) return GOF(w13); + if (o >= GOF(w14) && o+sz <= GOF(w14) + SZB(w14)) return GOF(w14); + if (o >= GOF(w15) && o+sz <= GOF(w15) + SZB(w15)) return GOF(w15); + if (o >= GOF(w16) && o+sz <= GOF(w16) + SZB(w16)) return GOF(w16); + if (o >= GOF(w17) && o+sz <= GOF(w17) + SZB(w17)) return GOF(w17); + if (o >= GOF(w18) && o+sz <= GOF(w18) + SZB(w18)) return GOF(w18); + if (o >= GOF(w19) && o+sz <= GOF(w19) + SZB(w19)) return GOF(w19); + if (o >= GOF(w20) && o+sz <= GOF(w20) + SZB(w20)) return GOF(w20); + if (o >= GOF(w21) && o+sz <= GOF(w21) + SZB(w21)) return GOF(w21); + if (o >= GOF(w22) && o+sz <= GOF(w22) + SZB(w22)) return GOF(w22); + if (o >= GOF(w23) && o+sz <= GOF(w23) + SZB(w23)) return GOF(w23); + if (o >= GOF(w24) && o+sz <= GOF(w24) + SZB(w24)) return GOF(w24); + if (o >= GOF(w25) && o+sz <= GOF(w25) + SZB(w25)) return GOF(w25); + if (o >= GOF(w26) && o+sz <= GOF(w26) + SZB(w26)) return GOF(w26); + if (o >= GOF(w27) && o+sz <= GOF(w27) + SZB(w27)) return GOF(w27); + if (o >= GOF(w28) && o+sz <= GOF(w28) + SZB(w28)) return GOF(w28); + if (o >= GOF(w29) && o+sz <= GOF(w29) + SZB(w29)) return GOF(w29); + if (o >= GOF(w30) && o+sz <= GOF(w30) + SZB(w30)) return GOF(w30); + if (o >= GOF(w31) && o+sz <= GOF(w31) + SZB(w31)) return GOF(w31); + VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n", offset,szB); tl_assert(0); @@ -1244,6 +1277,39 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) if (o == GOF(LLaddr) && sz == 8) return -1; /* slot unused */ if (o == GOF(LLdata) && sz == 8) return -1; /* slot unused */ + if (o >= GOF(w0) && o+sz <= GOF(w0) + SZB(w0)) return GOF(w0); + if (o >= GOF(w1) && o+sz <= GOF(w1) + SZB(w1)) return GOF(w1); + if (o >= GOF(w2) && o+sz <= GOF(w2) + SZB(w2)) return GOF(w2); + if (o >= GOF(w3) && o+sz <= GOF(w3) + SZB(w3)) return GOF(w3); + if (o >= GOF(w4) && o+sz <= GOF(w4) + SZB(w4)) return GOF(w4); + if (o >= GOF(w5) && o+sz <= GOF(w5) + SZB(w5)) return GOF(w5); + if (o >= GOF(w6) && o+sz <= GOF(w6) + SZB(w6)) return GOF(w6); + if (o >= GOF(w7) && o+sz <= GOF(w7) + SZB(w7)) return GOF(w7); + if (o >= GOF(w8) && o+sz <= GOF(w8) + SZB(w8)) return GOF(w8); + if (o >= GOF(w9) && o+sz <= GOF(w9) + SZB(w9)) return GOF(w9); + if (o >= GOF(w10) && o+sz <= GOF(w10) + SZB(w10)) return GOF(w10); + if (o >= GOF(w11) && o+sz <= GOF(w11) + SZB(w11)) return GOF(w11); + if (o >= GOF(w12) && o+sz <= GOF(w12) + SZB(w12)) return GOF(w12); + if (o >= GOF(w13) && o+sz <= GOF(w13) + SZB(w13)) return GOF(w13); + if (o >= GOF(w14) && o+sz <= GOF(w14) + SZB(w14)) return GOF(w14); + if (o >= GOF(w15) && o+sz <= GOF(w15) + SZB(w15)) return GOF(w15); + if (o >= GOF(w16) && o+sz <= GOF(w16) + SZB(w16)) return GOF(w16); + if (o >= GOF(w17) && o+sz <= GOF(w17) + SZB(w17)) return GOF(w17); + if (o >= GOF(w18) && o+sz <= GOF(w18) + SZB(w18)) return GOF(w18); + if (o >= GOF(w19) && o+sz <= GOF(w19) + SZB(w19)) return GOF(w19); + if (o >= GOF(w20) && o+sz <= GOF(w20) + SZB(w20)) return GOF(w20); + if (o >= GOF(w21) && o+sz <= GOF(w21) + SZB(w21)) return GOF(w21); + if (o >= GOF(w22) && o+sz <= GOF(w22) + SZB(w22)) return GOF(w22); + if (o >= GOF(w23) && o+sz <= GOF(w23) + SZB(w23)) return GOF(w23); + if (o >= GOF(w24) && o+sz <= GOF(w24) + SZB(w24)) return GOF(w24); + if (o >= GOF(w25) && o+sz <= GOF(w25) + SZB(w25)) return GOF(w25); + if (o >= GOF(w26) && o+sz <= GOF(w26) + SZB(w26)) return GOF(w26); + if (o >= GOF(w27) && o+sz <= GOF(w27) + SZB(w27)) return GOF(w27); + if (o >= GOF(w28) && o+sz <= GOF(w28) + SZB(w28)) return GOF(w28); + if (o >= GOF(w29) && o+sz <= GOF(w29) + SZB(w29)) return GOF(w29); + if (o >= GOF(w30) && o+sz <= GOF(w30) + SZB(w30)) return GOF(w30); + if (o >= GOF(w31) && o+sz <= GOF(w31) + SZB(w31)) return GOF(w31); + VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n", offset,szB); tl_assert(0); |
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From: Petar J. <pe...@so...> - 2017-10-27 22:42:49
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=13577bb699a7ba28d184c98283fab4d27f06fba4 commit 13577bb699a7ba28d184c98283fab4d27f06fba4 Author: Petar Jovanovic <mip...@gm...> Date: Fri Oct 27 15:05:22 2017 +0200 mips: detect presence of MSA Detect presence of MSA capabilities. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Minor code-style rewrites by myself. Related BZ issue - #382563. Diff: --- coregrind/m_machine.c | 93 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 77 insertions(+), 16 deletions(-) diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 893c32e..395989b 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -453,7 +453,7 @@ Int VG_(machine_arm_archlevel) = 4; /* For hwcaps detection on ppc32/64, s390x, and arm we'll need to do SIGILL testing, so we need a VG_MINIMAL_JMP_BUF. */ #if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ - || defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32) + || defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32) || defined(VGA_mips64) #include "pub_core_libcsetjmp.h" static VG_MINIMAL_JMP_BUF(env_unsup_insn); static void handler_unsup_insn ( Int x ) { @@ -1697,7 +1697,7 @@ Bool VG_(machine_get_hwcaps)( void ) vki_sigaction_fromK_t saved_sigill_act; vki_sigaction_toK_t tmp_sigill_act; - volatile Bool have_DSP, have_DSPr2; + volatile Bool have_DSP, have_DSPr2, have_MSA; Int r; vg_assert(sizeof(vki_sigaction_fromK_t) == sizeof(vki_sigaction_toK_t)); @@ -1722,27 +1722,39 @@ Bool VG_(machine_get_hwcaps)( void ) VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); if (VEX_PRID_COMP_MIPS == VEX_MIPS_COMP_ID(vai.hwcaps)) { - /* DSPr2 instructions. */ - have_DSPr2 = True; + + /* MSA instructions. */ + have_MSA = True; if (VG_MINIMAL_SETJMP(env_unsup_insn)) { - have_DSPr2 = False; + have_MSA = False; } else { - __asm__ __volatile__(".word 0x7d095351"); /* precr.qb.ph t2, t0, t1 */ + __asm__ __volatile__(".word 0x7800088E"); /* addv.b w2, w1, w0 */ } - if (have_DSPr2) { - /* We assume it's 74K, since it can run DSPr2. */ - vai.hwcaps |= VEX_PRID_IMP_74K; + if (have_MSA) { + vai.hwcaps |= VEX_PRID_IMP_P5600; } else { - /* DSP instructions. */ - have_DSP = True; + /* DSPr2 instructions. */ + have_DSPr2 = True; if (VG_MINIMAL_SETJMP(env_unsup_insn)) { - have_DSP = False; + have_DSPr2 = False; } else { - __asm__ __volatile__(".word 0x7c3f44b8"); /* rddsp t0, 0x3f */ + __asm__ __volatile__(".word 0x7d095351"); /* precr.qb.ph t2, t0, t1 */ } - if (have_DSP) { - /* We assume it's 34K, since it has support for DSP. */ - vai.hwcaps |= VEX_PRID_IMP_34K; + if (have_DSPr2) { + /* We assume it's 74K, since it can run DSPr2. */ + vai.hwcaps |= VEX_PRID_IMP_74K; + } else { + /* DSP instructions. */ + have_DSP = True; + if (VG_MINIMAL_SETJMP(env_unsup_insn)) { + have_DSP = False; + } else { + __asm__ __volatile__(".word 0x7c3f44b8"); /* rddsp t0, 0x3f */ + } + if (have_DSP) { + /* We assume it's 34K, since it has support for DSP. */ + vai.hwcaps |= VEX_PRID_IMP_34K; + } } } } @@ -1806,6 +1818,55 @@ Bool VG_(machine_get_hwcaps)( void ) vai.hwcaps |= VEX_MIPS_HOST_FR; + /* Same instruction set detection algorithm as for ppc32/arm... */ + vki_sigset_t saved_set, tmp_set; + vki_sigaction_fromK_t saved_sigill_act; + vki_sigaction_toK_t tmp_sigill_act; + + volatile Bool have_MSA; + Int r; + + vg_assert(sizeof(vki_sigaction_fromK_t) == sizeof(vki_sigaction_toK_t)); + + VG_(sigemptyset)(&tmp_set); + VG_(sigaddset)(&tmp_set, VKI_SIGILL); + + r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set); + vg_assert(r == 0); + + r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act); + vg_assert(r == 0); + tmp_sigill_act = saved_sigill_act; + + /* NODEFER: signal handler does not return (from the kernel's point of + view), hence if it is to successfully catch a signal more than once, + we need the NODEFER flag. */ + tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND; + tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO; + tmp_sigill_act.sa_flags |= VKI_SA_NODEFER; + tmp_sigill_act.ksa_handler = handler_unsup_insn; + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + + if (VEX_PRID_COMP_MIPS == VEX_MIPS_COMP_ID(vai.hwcaps)) { + + /* MSA instructions */ + have_MSA = True; + if (VG_MINIMAL_SETJMP(env_unsup_insn)) { + have_MSA = False; + } else { + __asm__ __volatile__(".word 0x7800088E"); /* addv.b w2, w1, w0 */ + } + if (have_MSA) { + vai.hwcaps |= VEX_PRID_IMP_P5600; + } + } + + VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act); + VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); + VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); + + VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps); + VG_(machine_get_cache_info)(&vai); return True; |
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From: Petar J. <pe...@so...> - 2017-10-27 22:42:39
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=91373819a398722105111dab58e88dca21279cef commit 91373819a398722105111dab58e88dca21279cef Author: Petar Jovanovic <mip...@gm...> Date: Mon Oct 9 17:48:48 2017 +0200 mips: new Iops added to support MSA New Iops are defined: Iop_Scale2_32Fx4, Iop_Scale2_64Fx2, Iop_Log2_32Fx4, Iop_Log2_64Fx2, Iop_F32x4_2toQ16x8, Iop_F64x2_2toQ32x4, Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16, Iop_PackOddLanes16x8, Iop_PackEvenLanes16x8, Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #382563. Diff: --- VEX/priv/ir_defs.c | 25 +++++++++++++++++++++++++ VEX/pub/libvex_ir.h | 30 ++++++++++++++++++++++++++++++ memcheck/mc_translate.c | 22 ++++++++++++++++++++++ memcheck/tests/vbit-test/irops.c | 12 ++++++++++++ 4 files changed, 89 insertions(+) diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index 8822800..61ff837 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -690,6 +690,11 @@ void ppIROp ( IROp op ) case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return; case Iop_Sqrt32Fx8: vex_printf("Sqrt32Fx8"); return; case Iop_Sqrt64Fx4: vex_printf("Sqrt64Fx4"); return; + + case Iop_Scale2_32Fx4: vex_printf("Scale2_32Fx4"); return; + case Iop_Scale2_64Fx2: vex_printf("Scale2_64Fx2"); return; + case Iop_Log2_32Fx4: vex_printf("Log2_32Fx4"); return; + case Iop_Log2_64Fx2: vex_printf("Log2_64Fx2"); return; case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return; case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return; @@ -724,6 +729,9 @@ void ppIROp ( IROp op ) case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return; case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return; + case Iop_F32x4_2toQ16x8: vex_printf("F32x4_2toQ16x8"); return; + case Iop_F64x2_2toQ32x4: vex_printf("F64x2_2toQ32x4"); return; + case Iop_V128to64: vex_printf("V128to64"); return; case Iop_V128HIto64: vex_printf("V128HIto64"); return; case Iop_64HLtoV128: vex_printf("64HLtoV128"); return; @@ -1071,6 +1079,12 @@ void ppIROp ( IROp op ) case Iop_InterleaveEvenLanes8x16: vex_printf("InterleaveEvenLanes8x16"); return; case Iop_InterleaveEvenLanes16x8: vex_printf("InterleaveEvenLanes16x8"); return; case Iop_InterleaveEvenLanes32x4: vex_printf("InterleaveEvenLanes32x4"); return; + case Iop_PackOddLanes8x16: vex_printf("InterleavePackOddLanes8x16"); return; + case Iop_PackOddLanes16x8: vex_printf("InterleavePackOddLanes16x8"); return; + case Iop_PackOddLanes32x4: vex_printf("InterleavePackOddLanes32x4"); return; + case Iop_PackEvenLanes8x16: vex_printf("InterleavePackEvenLanes8x16"); return; + case Iop_PackEvenLanes16x8: vex_printf("InterleavePackEvenLanes16x8"); return; + case Iop_PackEvenLanes32x4: vex_printf("InterleavePackEvenLanes32x4"); return; case Iop_GetElem8x16: vex_printf("GetElem8x16"); return; case Iop_GetElem16x8: vex_printf("GetElem16x8"); return; @@ -2947,6 +2961,13 @@ void typeOfPrimop ( IROp op, case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128); + case Iop_Scale2_32Fx4: + case Iop_Scale2_64Fx2: + TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); + case Iop_Log2_32Fx4: + case Iop_Log2_64Fx2: + UNARY(Ity_V128, Ity_V128); + case Iop_V128to64: case Iop_V128HIto64: case Iop_NarrowUn16to8x8: case Iop_NarrowUn32to16x4: @@ -3076,6 +3097,9 @@ void typeOfPrimop ( IROp op, case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16: case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8: case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4: + case Iop_PackOddLanes8x16: case Iop_PackEvenLanes8x16: + case Iop_PackOddLanes16x8: case Iop_PackEvenLanes16x8: + case Iop_PackOddLanes32x4: case Iop_PackEvenLanes32x4: case Iop_Perm8x16: case Iop_Perm32x4: case Iop_RecipStep32Fx4: case Iop_RecipStep64Fx2: case Iop_RSqrtStep32Fx4: case Iop_RSqrtStep64Fx2: @@ -3243,6 +3267,7 @@ void typeOfPrimop ( IROp op, case Iop_Mul64Fx2: case Iop_Div64Fx2: case Iop_Add32Fx4: case Iop_Sub32Fx4: case Iop_Mul32Fx4: case Iop_Div32Fx4: + case Iop_F64x2_2toQ32x4: case Iop_F32x4_2toQ16x8: TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); case Iop_Add64Fx4: case Iop_Sub64Fx4: diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index 57fa9b6..5cc37e7 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -1351,6 +1351,13 @@ typedef square root of each element in the operand vector. */ Iop_RSqrtEst32Fx4, + /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */ + Iop_Scale2_32Fx4, + + /* Vector floating-point base 2 logarithm */ + Iop_Log2_32Fx4, + + /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. Note, that of one of the arguments is zero and another one is infiinty of arbitrary sign the result of the operation is 1.5. */ @@ -1375,9 +1382,16 @@ typedef /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */ Iop_F32toF16x4, Iop_F16toF32x4, /* F32x4 <-> F16x4 */ + + /* -- Double to/from half conversion -- */ Iop_F64toF16x2, Iop_F16toF64x2, + /* Values from two registers converted in smaller type and put in one + IRRoundingMode(I32) x (F32x4 | F32x4) -> Q16x8 */ + Iop_F32x4_2toQ16x8, + + /* --- 32x4 lowest-lane-only scalar FP --- */ /* In binary cases, upper 3/4 is copied from first operand. In @@ -1407,12 +1421,23 @@ typedef /* binary :: IRRoundingMode(I32) x V128 -> V128 */ Iop_Sqrt64Fx2, + /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */ + Iop_Scale2_64Fx2, + + /* Vector floating-point base 2 logarithm */ + Iop_Log2_64Fx2, + /* see 32Fx4 variants for description */ Iop_RecipEst64Fx2, // unary Iop_RecipStep64Fx2, // binary Iop_RSqrtEst64Fx2, // unary Iop_RSqrtStep64Fx2, // binary + + /* Values from two registers converted in smaller type and put in one + IRRoundingMode(I32) x (F64x2 | F64x2) -> Q32x4 */ + Iop_F64x2_2toQ32x4, + /* --- 64x2 lowest-lane-only scalar FP --- */ /* In binary cases, upper half is copied from first operand. In @@ -1761,6 +1786,11 @@ typedef Iop_InterleaveOddLanes16x8, Iop_InterleaveEvenLanes16x8, Iop_InterleaveOddLanes32x4, Iop_InterleaveEvenLanes32x4, + /* Pack even/odd lanes. */ + Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16, + Iop_PackOddLanes16x8, Iop_PackEvenLanes16x8, + Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4, + /* CONCATENATION -- build a new value by concatenating either the even or odd lanes of both operands. Note that Cat{Odd,Even}Lanes64x2 are identical to Interleave{HI,LO}64x2 diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 44b6a73..9d4f651 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -2996,12 +2996,14 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_Sub64Fx2: case Iop_Mul64Fx2: case Iop_Div64Fx2: + case Iop_Scale2_64Fx2: return binary64Fx2_w_rm(mce, vatom1, vatom2, vatom3); case Iop_Add32Fx4: case Iop_Sub32Fx4: case Iop_Mul32Fx4: case Iop_Div32Fx4: + case Iop_Scale2_32Fx4: return binary32Fx4_w_rm(mce, vatom1, vatom2, vatom3); case Iop_Add64Fx4: @@ -3016,6 +3018,18 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce, case Iop_Div32Fx8: return binary32Fx8_w_rm(mce, vatom1, vatom2, vatom3); + case Iop_F32x4_2toQ16x8: + return assignNew('V', mce, Ity_V128, + binop(Iop_PackEvenLanes16x8, + unary32Fx4_w_rm(mce, vatom1, vatom2), + unary32Fx4_w_rm(mce, vatom1, vatom3))); + case Iop_F64x2_2toQ32x4: + return assignNew('V', mce, Ity_V128, + binop(Iop_PackEvenLanes32x4, + unary64Fx2_w_rm(mce, vatom1, vatom2), + unary64Fx2_w_rm(mce, vatom1, vatom3))); + + default: ppIROp(op); VG_(tool_panic)("memcheck:expr2vbits_Triop"); @@ -3737,6 +3751,12 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, case Iop_InterleaveEvenLanes8x16: case Iop_InterleaveEvenLanes16x8: case Iop_InterleaveEvenLanes32x4: + case Iop_PackOddLanes8x16: + case Iop_PackOddLanes16x8: + case Iop_PackOddLanes32x4: + case Iop_PackEvenLanes8x16: + case Iop_PackEvenLanes16x8: + case Iop_PackEvenLanes32x4: return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2)); case Iop_GetElem8x16: @@ -4432,6 +4452,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Neg64Fx2: case Iop_RSqrtEst64Fx2: case Iop_RecipEst64Fx2: + case Iop_Log2_64Fx2: return unary64Fx2(mce, vatom); case Iop_Sqrt64F0x2: @@ -4458,6 +4479,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Abs32Fx4: case Iop_Neg32Fx4: case Iop_RSqrtEst32Fx4: + case Iop_Log2_32Fx4: return unary32Fx4(mce, vatom); case Iop_I32UtoFx2: diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 7f9ce90..242184b 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -623,6 +623,8 @@ static irop_t irops[] = { { DEFOP(Iop_PwMin32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Abs32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Scale2_32Fx4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Log2_32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipEst32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipStep32Fx4, UNDEF_UNKNOWN), }, @@ -646,6 +648,8 @@ static irop_t irops[] = { { DEFOP(Iop_F16toF32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_F64toF16x2, UNDEF_UNKNOWN), }, { DEFOP(Iop_F16toF64x2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_F32x4_2toQ16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_F64x2_2toQ32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Add32F0x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sub32F0x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Mul32F0x4, UNDEF_UNKNOWN), }, @@ -671,6 +675,8 @@ static irop_t irops[] = { { DEFOP(Iop_CmpUN64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Abs64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Sqrt64Fx2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Scale2_64Fx2, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Log2_64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_Neg64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipEst64Fx2, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipStep64Fx2, UNDEF_UNKNOWN), }, @@ -979,6 +985,12 @@ static irop_t irops[] = { { DEFOP(Iop_InterleaveEvenLanes16x8, UNDEF_UNKNOWN), }, { DEFOP(Iop_InterleaveOddLanes32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_InterleaveEvenLanes32x4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes8x16, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes8x16, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes16x8, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackOddLanes32x4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_PackEvenLanes32x4, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes8x16, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes16x8, UNDEF_UNKNOWN), }, { DEFOP(Iop_CatOddLanes32x4, UNDEF_UNKNOWN), }, |
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From: Phil L. <plo...@sa...> - 2017-10-27 14:18:00
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Yes, https://bitbucket.org/stass/valgrind-freebsd provides the freebsd port that I am using. Thanks for answering my questions. I will need to look at whether I can afford to provide maintenance. Phil -----Original Message----- From: Ivo Raisr [mailto:iv...@iv...] Sent: Wednesday, October 25, 2017 6:08 AM To: Phil Longstaff Cc: val...@li... Subject: Re: [Valgrind-developers] Valgrind on freebsd 2017-10-24 20:53 GMT+02:00 Phil Longstaff <plo...@sa...>: > There is a bitbucket.org project (mercurial) which adds freebsd > support to valgrind 3.10.1. I have cloned this and have now updated the base to 3.11.0. > I am planning to update the base to 3.13.0 and would then like to > merge the changes upstream to make freebsd a supported OS. > > > > Since valgrind now uses a git repository, probably the best route is: > > 1) Continue to use bitbucket.org to merge in 3.12.0 and 3.13.0 > > 2) Clone valgrind git repository to gitlab > > 3) Add my code as a “freebsd branch” > > 4) Start to feed changes upstream > > > > Comments? What standards do you have for taking changes? What > resources would you need to accept freebsd as a supported OS? Hello Phil, Thank you for taking this topic into valgrind-developers. Do you have in mind https://bitbucket.org/stass/valgrind-freebsd? Certainly new OS ports are welcome *iff* they are maintained. The list of requirements was discussed this year at FOSDEM 2017. There should be: * some users, * developer(s) doing maintenance * developer(s) reachable to answer simple questions about the port * access to a system to test/compile * nightly regression build sending results to valgrind-testresults alias * OS specific regression tests versioned in Valgrind GIT For Valgrind, just upstreaming the port is not the task end. You (or other developers) cannot disappear after that. There is an ongoing joint effort of the whole Valgrind community to keep Valgrind live on all supported OSes and platforms. See http://valgrind.org/info/platforms.html, Porting Plans. I have removed TileGx/Linux port this year because it did not satisfy any of the above. Few years ago, Petr Pavlu and I have successfully upstreamed the Solaris port. I have been maintaining it since then, keeping up with OS and Valgrind development. Also Tomas Jedlicka, Diane Meirowitz and I have attempted at porting Valgrind to sparc/Linux and sparc/Solaris. However even if the port was almost ready for upstreaming we decided not to pursue it any longer because of the required maintenance which we could not dedicate to. These questions must be cleared before considering taking in any of the changes. As regards the upstreaming process, we would like to see which FreeBSD versions, variants, architectures the port is targeting. Does it support all production Valgrind analysis tools? Experimental ones? Then we would like to see the output of 'make regtest' and finally some patches, preferably split into VEX changes, core changes, tool changes, FreeBSD-specific changes (most probably new files). If there are interface changes - they need to be either sweet & short or well understood. Unfortunately coding standards are not written anywhere - have a look at the existing files around for inspiration. Ideally send a small snapshot early and you will get some comments. I hope you'll find this useful. Do not hesitate to ask. Kind regards, I. |