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From: <sv...@va...> - 2017-05-03 18:15:13
|
Author: carll
Date: Wed May 3 19:15:01 2017
New Revision: 16330
Log:
Updated PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Forgot to add the new files.
Vex commit 3359 Has the source code changes for the instruction and OV32, CS32
support
Valgrind commit 16329 updated the existing files
This commit adds all the new files.
Valgrind bugzilla 378931
Added:
trunk/none/tests/ppc32/jm-int_other.stderr.exp
trunk/none/tests/ppc32/jm-int_other.stdout.exp
trunk/none/tests/ppc32/jm-int_other.vgtest
trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part3-div.vgtest
trunk/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0
trunk/none/tests/ppc64/jm-int_other.stderr.exp
trunk/none/tests/ppc64/jm-int_other.stdout.exp
trunk/none/tests/ppc64/jm-int_other.stdout.exp-LE
trunk/none/tests/ppc64/jm-int_other.vgtest
trunk/none/tests/ppc64/test_isa_2_06_part2-div.stderr.exp
trunk/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp
trunk/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0
trunk/none/tests/ppc64/test_isa_2_06_part2-div.vgtest
trunk/none/tests/ppc64/test_isa_2_06_part3-div.stderr.exp
trunk/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp
trunk/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0
trunk/none/tests/ppc64/test_isa_2_06_part3-div.vgtest
Added: trunk/none/tests/ppc32/jm-int_other.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.stderr.exp (added)
+++ trunk/none/tests/ppc32/jm-int_other.stderr.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/jm-int_other.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.stdout.exp (added)
+++ trunk/none/tests/ppc32/jm-int_other.stdout.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,969 @@
+PPC integer logical insns with two args:
+ and 00000000, 00000000 => 00000000 (00000000 00000000)
+ and 00000000, 000f423f => 00000000 (00000000 00000000)
+ and 00000000, ffffffff => 00000000 (00000000 00000000)
+ and 000f423f, 00000000 => 00000000 (00000000 00000000)
+ and 000f423f, 000f423f => 000f423f (00000000 00000000)
+ and 000f423f, ffffffff => 000f423f (00000000 00000000)
+ and ffffffff, 00000000 => 00000000 (00000000 00000000)
+ and ffffffff, 000f423f => 000f423f (00000000 00000000)
+ and ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ andc 00000000, 00000000 => 00000000 (00000000 00000000)
+ andc 00000000, 000f423f => 00000000 (00000000 00000000)
+ andc 00000000, ffffffff => 00000000 (00000000 00000000)
+ andc 000f423f, 00000000 => 000f423f (00000000 00000000)
+ andc 000f423f, 000f423f => 00000000 (00000000 00000000)
+ andc 000f423f, ffffffff => 00000000 (00000000 00000000)
+ andc ffffffff, 00000000 => ffffffff (00000000 00000000)
+ andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ andc ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ eqv 00000000, 00000000 => ffffffff (00000000 00000000)
+ eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ eqv 00000000, ffffffff => 00000000 (00000000 00000000)
+ eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+ eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
+ eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
+ eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
+ eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
+ eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ nand 00000000, 00000000 => ffffffff (00000000 00000000)
+ nand 00000000, 000f423f => ffffffff (00000000 00000000)
+ nand 00000000, ffffffff => ffffffff (00000000 00000000)
+ nand 000f423f, 00000000 => ffffffff (00000000 00000000)
+ nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+ nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+ nand ffffffff, 00000000 => ffffffff (00000000 00000000)
+ nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ nand ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ nor 00000000, 00000000 => ffffffff (00000000 00000000)
+ nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ nor 00000000, ffffffff => 00000000 (00000000 00000000)
+ nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+ nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+ nor 000f423f, ffffffff => 00000000 (00000000 00000000)
+ nor ffffffff, 00000000 => 00000000 (00000000 00000000)
+ nor ffffffff, 000f423f => 00000000 (00000000 00000000)
+ nor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ or 00000000, 00000000 => 00000000 (00000000 00000000)
+ or 00000000, 000f423f => 000f423f (00000000 00000000)
+ or 00000000, ffffffff => ffffffff (00000000 00000000)
+ or 000f423f, 00000000 => 000f423f (00000000 00000000)
+ or 000f423f, 000f423f => 000f423f (00000000 00000000)
+ or 000f423f, ffffffff => ffffffff (00000000 00000000)
+ or ffffffff, 00000000 => ffffffff (00000000 00000000)
+ or ffffffff, 000f423f => ffffffff (00000000 00000000)
+ or ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ orc 00000000, 00000000 => ffffffff (00000000 00000000)
+ orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+ orc 00000000, ffffffff => 00000000 (00000000 00000000)
+ orc 000f423f, 00000000 => ffffffff (00000000 00000000)
+ orc 000f423f, 000f423f => ffffffff (00000000 00000000)
+ orc 000f423f, ffffffff => 000f423f (00000000 00000000)
+ orc ffffffff, 00000000 => ffffffff (00000000 00000000)
+ orc ffffffff, 000f423f => ffffffff (00000000 00000000)
+ orc ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+ xor 00000000, 00000000 => 00000000 (00000000 00000000)
+ xor 00000000, 000f423f => 000f423f (00000000 00000000)
+ xor 00000000, ffffffff => ffffffff (00000000 00000000)
+ xor 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xor 000f423f, 000f423f => 00000000 (00000000 00000000)
+ xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+ xor ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+ xor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ slw 00000000, 00000000 => 00000000 (00000000 00000000)
+ slw 00000000, 000f423f => 00000000 (00000000 00000000)
+ slw 00000000, ffffffff => 00000000 (00000000 00000000)
+ slw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ slw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ slw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ slw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ slw ffffffff, 000f423f => 00000000 (00000000 00000000)
+ slw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+ sraw 00000000, 00000000 => 00000000 (00000000 00000000)
+ sraw 00000000, 000f423f => 00000000 (00000000 00000000)
+ sraw 00000000, ffffffff => 00000000 (00000000 00000000)
+ sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
+ sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
+
+ srw 00000000, 00000000 => 00000000 (00000000 00000000)
+ srw 00000000, 000f423f => 00000000 (00000000 00000000)
+ srw 00000000, ffffffff => 00000000 (00000000 00000000)
+ srw 000f423f, 00000000 => 000f423f (00000000 00000000)
+ srw 000f423f, 000f423f => 00000000 (00000000 00000000)
+ srw 000f423f, ffffffff => 00000000 (00000000 00000000)
+ srw ffffffff, 00000000 => ffffffff (00000000 00000000)
+ srw ffffffff, 000f423f => 00000000 (00000000 00000000)
+ srw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+PPC integer logical insns with two args with flags update:
+ and. 00000000, 00000000 => 00000000 (20000000 00000000)
+ and. 00000000, 000f423f => 00000000 (20000000 00000000)
+ and. 00000000, ffffffff => 00000000 (20000000 00000000)
+ and. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ and. 000f423f, 000f423f => 000f423f (40000000 00000000)
+ and. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ and. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ and. ffffffff, 000f423f => 000f423f (40000000 00000000)
+ and. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ andc. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andc. 00000000, 000f423f => 00000000 (20000000 00000000)
+ andc. 00000000, ffffffff => 00000000 (20000000 00000000)
+ andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
+ eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
+ eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+ eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
+ eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
+ eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ nand. 00000000, 00000000 => ffffffff (80000000 00000000)
+ nand. 00000000, 000f423f => ffffffff (80000000 00000000)
+ nand. 00000000, ffffffff => ffffffff (80000000 00000000)
+ nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
+ nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+ nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+ nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ nor. 00000000, 00000000 => ffffffff (80000000 00000000)
+ nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ nor. 00000000, ffffffff => 00000000 (20000000 00000000)
+ nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+ nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+ nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ or. 00000000, 00000000 => 00000000 (20000000 00000000)
+ or. 00000000, 000f423f => 000f423f (40000000 00000000)
+ or. 00000000, ffffffff => ffffffff (80000000 00000000)
+ or. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ or. 000f423f, 000f423f => 000f423f (40000000 00000000)
+ or. 000f423f, ffffffff => ffffffff (80000000 00000000)
+ or. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ or. ffffffff, 000f423f => ffffffff (80000000 00000000)
+ or. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ orc. 00000000, 00000000 => ffffffff (80000000 00000000)
+ orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+ orc. 00000000, ffffffff => 00000000 (20000000 00000000)
+ orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
+ orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
+ orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
+ orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
+ orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+ xor. 00000000, 00000000 => 00000000 (20000000 00000000)
+ xor. 00000000, 000f423f => 000f423f (40000000 00000000)
+ xor. 00000000, ffffffff => ffffffff (80000000 00000000)
+ xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+ xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+ xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ slw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ slw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ slw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+ sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
+ sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
+
+ srw. 00000000, 00000000 => 00000000 (20000000 00000000)
+ srw. 00000000, 000f423f => 00000000 (20000000 00000000)
+ srw. 00000000, ffffffff => 00000000 (20000000 00000000)
+ srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+ srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+ srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+ srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+ srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+ srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+PPC integer compare insns (two args):
+ cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
+ cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
+ cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
+ cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
+ cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
+ cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
+ cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+ cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
+ cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
+ cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
+ cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
+ cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
+ cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
+ cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+PPC integer compare with immediate insns (two args):
+ cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+ cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+ cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+ cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
+ cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
+ cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
+
+ cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
+ cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+ cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
+ cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+ cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+ cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
+ cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args:
+ ori 00000000, 00000000 => 00000000 (00000000 00000000)
+ ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+ ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+ ori 000f423f, 00000000 => 000f423f (00000000 00000000)
+ ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
+ ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
+ ori ffffffff, 00000000 => ffffffff (00000000 00000000)
+ ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
+ ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+ oris 00000000, 00000000 => 00000000 (00000000 00000000)
+ oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+ oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+ oris 000f423f, 00000000 => 000f423f (00000000 00000000)
+ oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
+ oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
+ oris ffffffff, 00000000 => ffffffff (00000000 00000000)
+ oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
+ oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+ xori 00000000, 00000000 => 00000000 (00000000 00000000)
+ xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+ xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+ xori 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
+ xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
+ xori ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
+ xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
+
+ xoris 00000000, 00000000 => 00000000 (00000000 00000000)
+ xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+ xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+ xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
+ xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
+ xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
+ xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
+ xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
+ xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
+
+PPC integer logical insns
+ with one register + one 16 bits immediate args with flags update:
+ andi. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
+ andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
+ andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
+ andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
+ andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
+ andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
+
+ andis. 00000000, 00000000 => 00000000 (20000000 00000000)
+ andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
+ andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
+ andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
+ andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
+ andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
+ andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
+ andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
+ andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
+
+PPC condition register logical insns - two operands:
+ crand 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crand 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crand 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
+ creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
+ creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
+ creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ cror 00000000, 00000000 => ffff0000 (00000000 00000000)
+ cror 00000000, 000f423f => ffff0000 (00000000 00000000)
+ cror 00000000, ffffffff => ffff0000 (00000000 00000000)
+ cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+ crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
+ crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
+ crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
+ crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
+ crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
+ crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
+ crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
+ crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
+ crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+ crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
+ crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
+ crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
+ crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
+ crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
+ crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
+ crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
+ crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
+ crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+PPC integer logical insns with one arg:
+ cntlzw 00000000 => 00000020 (00000000 00000000)
+ cntlzw 000f423f => 0000000c (00000000 00000000)
+ cntlzw ffffffff => 00000000 (00000000 00000000)
+
+ extsb 00000000 => 00000000 (00000000 00000000)
+ extsb 000f423f => 0000003f (00000000 00000000)
+ extsb ffffffff => ffffffff (00000000 00000000)
+
+ extsh 00000000 => 00000000 (00000000 00000000)
+ extsh 000f423f => 0000423f (00000000 00000000)
+ extsh ffffffff => ffffffff (00000000 00000000)
+
+ neg 00000000 => 00000000 (00000000 00000000)
+ neg 000f423f => fff0bdc1 (00000000 00000000)
+ neg ffffffff => 00000001 (00000000 00000000)
+
+ nego 00000000 => 00000000 (00000000 00000000)
+ nego 000f423f => fff0bdc1 (00000000 00000000)
+ nego ffffffff => 00000001 (00000000 00000000)
+
+PPC integer logical insns with one arg with flags update:
+ cntlzw. 00000000 => 00000020 (40000000 00000000)
+ cntlzw. 000f423f => 0000000c (40000000 00000000)
+ cntlzw. ffffffff => 00000000 (20000000 00000000)
+
+ extsb. 00000000 => 00000000 (20000000 00000000)
+ extsb. 000f423f => 0000003f (40000000 00000000)
+ extsb. ffffffff => ffffffff (80000000 00000000)
+
+ extsh. 00000000 => 00000000 (20000000 00000000)
+ extsh. 000f423f => 0000423f (40000000 00000000)
+ extsh. ffffffff => ffffffff (80000000 00000000)
+
+ neg. 00000000 => 00000000 (20000000 00000000)
+ neg. 000f423f => fff0bdc1 (80000000 00000000)
+ neg. ffffffff => 00000001 (40000000 00000000)
+
+ nego. 00000000 => 00000000 (20000000 00000000)
+ nego. 000f423f => fff0bdc1 (80000000 00000000)
+ nego. ffffffff => 00000001 (40000000 00000000)
+
+PPC logical insns with special forms:
+ rlwimi 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
+ rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+ rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000)
+ rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000)
+ rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
+ rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000)
+ rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
+ rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000)
+ rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000)
+ rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
+
+ rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
+ rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+ rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
+ rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
+ rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000)
+ rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
+ rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
+ rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000)
+ rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000)
+ rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
+ rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000)
+ rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
+
+ rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000)
+ rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000)
+ rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000)
+ rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+
+ srawi 00000000, 0 => 00000000 (00000000 00000000)
+ srawi 00000000, 31 => 00000000 (00000000 00000000)
+ srawi 000f423f, 0 => 000f423f (00000000 00000000)
+ srawi 000f423f, 31 => 00000000 (00000000 00000000)
+ srawi ffffffff, 0 => ffffffff (00000000 00000000)
+ srawi ffffffff, 31 => ffffffff (00000000 20000000)
+
+ mfcr (00000000) => 00000000 (00000000 00000000)
+ mfcr (000f423f) => 000f423f (000f423f 00000000)
+ mfcr (ffffffff) => ffffffff (ffffffff 00000000)
+
+ mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
+ mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
+ mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
+ mfspr 8 (00000000) -> mtlr -> mflr => 00000000
+ mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f
+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff
+ mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
+ mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
+
+
+PPC logical insns with special forms with flags update:
+ rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
+ rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+ rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000)
+ rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000)
+ rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
+ rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000)
+ rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
+ rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000)
+ rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000)
+ rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
+
+ rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
+ rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+ rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
+ rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
+ rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000)
+ rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
+ rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
+ rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000)
+ rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000)
+ rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
+ rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000)
+ rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
+
+ rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000)
+ rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
+ rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000)
+ rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000)
+ rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+ rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000)
+ rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+
+ srawi. 00000000, 0 => 00000000 (20000000 00000000)
+ srawi. 00000000, 31 => 00000000 (20000000 00000000)
+ srawi. 000f423f, 0 => 000f423f (40000000 00000000)
+ srawi. 000f423f, 31 => 00000000 (20000000 00000000)
+ srawi. ffffffff, 0 => ffffffff (80000000 00000000)
+ srawi. ffffffff, 31 => ffffffff (80000000 20000000)
+
+ mcrf 0, 0 (00000000) => (00000000 00000000)
+ mcrf 0, 7 (00000000) => (00000000 00000000)
+ mcrf 7, 0 (00000000) => (00000000 00000000)
+ mcrf 7, 7 (00000000) => (00000000 00000000)
+ mcrf 0, 0 (000f423f) => (000f423f 00000000)
+ mcrf 0, 7 (000f423f) => (f00f423f 00000000)
+ mcrf 7, 0 (000f423f) => (000f4230 00000000)
+ mcrf 7, 7 (000f423f) => (000f423f 00000000)
+ mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
+ mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
+ mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
+ mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
+
+ mcrxr 0 (00000000) => (00000000 00000000)
+ mcrxr 1 (00000000) => (00000000 00000000)
+ mcrxr 2 (00000000) => (00000000 00000000)
+ mcrxr 3 (00000000) => (00000000 00000000)
+ mcrxr 4 (00000000) => (00000000 00000000)
+ mcrxr 5 (00000000) => (00000000 00000000)
+ mcrxr 6 (00000000) => (00000000 00000000)
+ mcrxr 7 (00000000) => (00000000 00000000)
+ mcrxr 0 (10000000) => (00000000 00000000)
+ mcrxr 1 (10000000) => (00000000 00000000)
+ mcrxr 2 (10000000) => (00000000 00000000)
+ mcrxr 3 (10000000) => (00000000 00000000)
+ mcrxr 4 (10000000) => (00000000 00000000)
+ mcrxr 5 (10000000) => (00000000 00000000)
+ mcrxr 6 (10000000) => (00000000 00000000)
+ mcrxr 7 (10000000) => (00000000 00000000)
+ mcrxr 0 (20000000) => (20000000 00000000)
+ mcrxr 1 (20000000) => (02000000 00000000)
+ mcrxr 2 (20000000) => (00200000 00000000)
+ mcrxr 3 (20000000) => (00020000 00000000)
+ mcrxr 4 (20000000) => (00002000 00000000)
+ mcrxr 5 (20000000) => (00000200 00000000)
+ mcrxr 6 (20000000) => (00000020 00000000)
+ mcrxr 7 (20000000) => (00000002 00000000)
+ mcrxr 0 (30000000) => (20000000 00000000)
+ mcrxr 1 (30000000) => (02000000 00000000)
+ mcrxr 2 (30000000) => (00200000 00000000)
+ mcrxr 3 (30000000) => (00020000 00000000)
+ mcrxr 4 (30000000) => (00002000 00000000)
+ mcrxr 5 (30000000) => (00000200 00000000)
+ mcrxr 6 (30000000) => (00000020 00000000)
+ mcrxr 7 (30000000) => (00000002 00000000)
+ mcrxr 0 (40000000) => (40000000 00000000)
+ mcrxr 1 (40000000) => (04000000 00000000)
+ mcrxr 2 (40000000) => (00400000 00000000)
+ mcrxr 3 (40000000) => (00040000 00000000)
+ mcrxr 4 (40000000) => (00004000 00000000)
+ mcrxr 5 (40000000) => (00000400 00000000)
+ mcrxr 6 (40000000) => (00000040 00000000)
+ mcrxr 7 (40000000) => (00000004 00000000)
+ mcrxr 0 (50000000) => (40000000 00000000)
+ mcrxr 1 (50000000) => (04000000 00000000)
+ mcrxr 2 (50000000) => (00400000 00000000)
+ mcrxr 3 (50000000) => (00040000 00000000)
+ mcrxr 4 (50000000) => (00004000 00000000)
+ mcrxr 5 (50000000) => (00000400 00000000)
+ mcrxr 6 (50000000) => (00000040 00000000)
+ mcrxr 7 (50000000) => (00000004 00000000)
+ mcrxr 0 (60000000) => (60000000 00000000)
+ mcrxr 1 (60000000) => (06000000 00000000)
+ mcrxr 2 (60000000) => (00600000 00000000)
+ mcrxr 3 (60000000) => (00060000 00000000)
+ mcrxr 4 (60000000) => (00006000 00000000)
+ mcrxr 5 (60000000) => (00000600 00000000)
+ mcrxr 6 (60000000) => (00000060 00000000)
+ mcrxr 7 (60000000) => (00000006 00000000)
+ mcrxr 0 (70000000) => (60000000 00000000)
+ mcrxr 1 (70000000) => (06000000 00000000)
+ mcrxr 2 (70000000) => (00600000 00000000)
+ mcrxr 3 (70000000) => (00060000 00000000)
+ mcrxr 4 (70000000) => (00006000 00000000)
+ mcrxr 5 (70000000) => (00000600 00000000)
+ mcrxr 6 (70000000) => (00000060 00000000)
+ mcrxr 7 (70000000) => (00000006 00000000)
+ mcrxr 0 (80000000) => (80000000 00000000)
+ mcrxr 1 (80000000) => (08000000 00000000)
+ mcrxr 2 (80000000) => (00800000 00000000)
+ mcrxr 3 (80000000) => (00080000 00000000)
+ mcrxr 4 (80000000) => (00008000 00000000)
+ mcrxr 5 (80000000) => (00000800 00000000)
+ mcrxr 6 (80000000) => (00000080 00000000)
+ mcrxr 7 (80000000) => (00000008 00000000)
+ mcrxr 0 (90000000) => (80000000 00000000)
+ mcrxr 1 (90000000) => (08000000 00000000)
+ mcrxr 2 (90000000) => (00800000 00000000)
+ mcrxr 3 (90000000) => (00080000 00000000)
+ mcrxr 4 (90000000) => (00008000 00000000)
+ mcrxr 5 (90000000) => (00000800 00000000)
+ mcrxr 6 (90000000) => (00000080 00000000)
+ mcrxr 7 (90000000) => (00000008 00000000)
+ mcrxr 0 (a0000000) => (a0000000 00000000)
+ mcrxr 1 (a0000000) => (0a000000 00000000)
+ mcrxr 2 (a0000000) => (00a00000 00000000)
+ mcrxr 3 (a0000000) => (000a0000 00000000)
+ mcrxr 4 (a0000000) => (0000a000 00000000)
+ mcrxr 5 (a0000000) => (00000a00 00000000)
+ mcrxr 6 (a0000000) => (000000a0 00000000)
+ mcrxr 7 (a0000000) => (0000000a 00000000)
+ mcrxr 0 (b0000000) => (a0000000 00000000)
+ mcrxr 1 (b0000000) => (0a000000 00000000)
+ mcrxr 2 (b0000000) => (00a00000 00000000)
+ mcrxr 3 (b0000000) => (000a0000 00000000)
+ mcrxr 4 (b0000000) => (0000a000 00000000)
+ mcrxr 5 (b0000000) => (00000a00 00000000)
+ mcrxr 6 (b0000000) => (000000a0 00000000)
+ mcrxr 7 (b0000000) => (0000000a 00000000)
+ mcrxr 0 (c0000000) => (c0000000 00000000)
+ mcrxr 1 (c0000000) => (0c000000 00000000)
+ mcrxr 2 (c0000000) => (00c00000 00000000)
+ mcrxr 3 (c0000000) => (000c0000 00000000)
+ mcrxr 4 (c0000000) => (0000c000 00000000)
+ mcrxr 5 (c0000000) => (00000c00 00000000)
+ mcrxr 6 (c0000000) => (000000c0 00000000)
+ mcrxr 7 (c0000000) => (0000000c 00000000)
+ mcrxr 0 (d0000000) => (c0000000 00000000)
+ mcrxr 1 (d0000000) => (0c000000 00000000)
+ mcrxr 2 (d0000000) => (00c00000 00000000)
+ mcrxr 3 (d0000000) => (000c0000 00000000)
+ mcrxr 4 (d0000000) => (0000c000 00000000)
+ mcrxr 5 (d0000000) => (00000c00 00000000)
+ mcrxr 6 (d0000000) => (000000c0 00000000)
+ mcrxr 7 (d0000000) => (0000000c 00000000)
+ mcrxr 0 (e0000000) => (e0000000 00000000)
+ mcrxr 1 (e0000000) => (0e000000 00000000)
+ mcrxr 2 (e0000000) => (00e00000 00000000)
+ mcrxr 3 (e0000000) => (000e0000 00000000)
+ mcrxr 4 (e0000000) => (0000e000 00000000)
+ mcrxr 5 (e0000000) => (00000e00 00000000)
+ mcrxr 6 (e0000000) => (000000e0 00000000)
+ mcrxr 7 (e0000000) => (0000000e 00000000)
+ mcrxr 0 (f0000000) => (e0000000 00000000)
+ mcrxr 1 (f0000000) => (0e000000 00000000)
+ mcrxr 2 (f0000000) => (00e00000 00000000)
+ mcrxr 3 (f0000000) => (000e0000 00000000)
+ mcrxr 4 (f0000000) => (0000e000 00000000)
+ mcrxr 5 (f0000000) => (00000e00 00000000)
+ mcrxr 6 (f0000000) => (000000e0 00000000)
+ mcrxr 7 (f0000000) => (0000000e 00000000)
+
+ mtcrf 0, 00000000 => (00000000 00000000)
+ mtcrf 99, 00000000 => (00000000 00000000)
+ mtcrf 198, 00000000 => (00000000 00000000)
+ mtcrf 0, 000f423f => (00000000 00000000)
+ mtcrf 99, 000f423f => (0000003f 00000000)
+ mtcrf 198, 000f423f => (00000230 00000000)
+ mtcrf 0, ffffffff => (00000000 00000000)
+ mtcrf 99, ffffffff => (0ff000ff 00000000)
+ mtcrf 198, ffffffff => (ff000ff0 00000000)
+
+PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
+ lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
+ lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
+ lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
+ lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
+ lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lha 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
+ lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
+ lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lha -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
+ lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
+ lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+ lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
+ lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
+ lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+ lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
+ lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
+ lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
+ lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+ lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
+ lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
+ lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
+ lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
+ lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
+ lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
+ lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
+ lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
+ lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+PPC integer load insns with two register args:
+ lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
+ lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
+
+ lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
+ lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
+
+ lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+ lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
+
+ lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
+
+ lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
+ lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
+ lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+PPC integer store insns
+ with one register + one 16 bits immediate args with flags update:
+ stb 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 8 => ff000000, 0 (00000000 00000000)
+ stb 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, -4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ stbu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbu 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbu ffffffff, 8 => ff000000, 8 (00000000 00000000)
+ stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
+ stbu ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ sth 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+ sth 00000000, -8 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, -4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ sthu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthu 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthu ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+ sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
+ sthu ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ stw 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+ stw 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, -4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 0 => ffffffff, 0 (00000000 00000000)
+
+ stwu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwu 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwu ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+ stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
+ stwu ffffffff, 0 => ffffffff, 0 (00000000 00000000)
+
+PPC integer store insns with three register args:
+ stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
+
+ stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
+
+ sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+
+ sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+
+ stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+
+ stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+
+All done. Tested 92 different instructions
Added: trunk/none/tests/ppc32/jm-int_other.vgtest
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.vgtest (added)
+++ trunk/none/tests/ppc32/jm-int_other.vgtest Wed May 3 19:15:01 2017
@@ -0,0 +1 @@
+prog: jm-insns -l -L -c
Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest Wed May 3 19:15:01 2017
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part2 -d
Added: trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp Wed May 3 19:15:01 2017
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XE...
[truncated message content] |
|
From: <sv...@va...> - 2017-05-03 17:28:48
|
Author: carll
Date: Wed May 3 18:28:35 2017
New Revision: 16329
Log:
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0. The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions. So now the
instructions produce different results in the XER register. Thus we need pre
and post ISA 3.0 expect files. Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args. The instructions that have different XER results
are run using a different set of command line args. The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0. We then create ISA3.0 expect files only for the tests
that run differently. By doing this we minimized the size of the expect files
needed.
Vex commit 3359 Has the source code changes for the instruction and OV32, CS32
support
This commit is all the test case changes, adding the new test case files.
Valgrind bugzilla 378931
Modified:
trunk/NEWS
trunk/memcheck/mc_main.c
trunk/none/tests/ppc32/Makefile.am
trunk/none/tests/ppc32/jm-insns.c
trunk/none/tests/ppc32/jm-int.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part2.c
trunk/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part2.vgtest
trunk/none/tests/ppc32/test_isa_2_06_part3.c
trunk/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part3.vgtest
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/jm-int.stdout.exp
trunk/none/tests/ppc64/ppc64_helpers.h
trunk/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
trunk/none/tests/ppc64/test_isa_2_06_part2.vgtest
trunk/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
trunk/none/tests/ppc64/test_isa_2_06_part3.vgtest
trunk/none/tests/ppc64/test_isa_3_0.c
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
trunk/none/tests/ppc64/test_isa_3_0_other.vgtest
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed May 3 18:28:35 2017
@@ -163,6 +163,7 @@
379372 UNKNOWN task message [id 3447, to mach_task_self(), reply 0x603]
(task_register_dyld_shared_cache_image_info)
379390 unhandled syscall: mach:70 (host_create_mach_voucher_trap)
+378931 Add ISA 3.0B additional isnstructions, add OV32, CA32 setting support
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modified: trunk/memcheck/mc_main.c
==============================================================================
--- trunk/memcheck/mc_main.c (original)
+++ trunk/memcheck/mc_main.c Wed May 3 18:28:35 2017
@@ -4465,7 +4465,7 @@
static void mc_post_reg_write ( CorePart part, ThreadId tid,
PtrdiffT offset, SizeT size)
{
-# define MAX_REG_WRITE_SIZE 1712
+# define MAX_REG_WRITE_SIZE 1728
UChar area[MAX_REG_WRITE_SIZE];
tl_assert(size <= MAX_REG_WRITE_SIZE);
VG_(memset)(area, V_BITS8_DEFINED, size);
Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Wed May 3 18:28:35 2017
@@ -10,6 +10,7 @@
bug139050-ppc32.vgtest \
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
jm-vmx.vgtest \
@@ -32,6 +33,8 @@
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part2-div.stderr.exp test_isa_2_06_part2-div.stdout.exp test_isa_2_06_part2-div.vgtest \
+ test_isa_2_06_part3-div.stderr.exp test_isa_2_06_part3-div.stdout.exp test_isa_2_06_part3-div.vgtest \
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
test_dfp2.stdout.exp_Without_dcffix \
Modified: trunk/none/tests/ppc32/jm-insns.c
==============================================================================
--- trunk/none/tests/ppc32/jm-insns.c (original)
+++ trunk/none/tests/ppc32/jm-insns.c Wed May 3 18:28:35 2017
@@ -7620,7 +7620,10 @@
#else // #if !defined (USAGE_SIMPLE)
fprintf(stderr,
"Usage: jm-insns [OPTION]\n"
- "\t-i: test integer instructions (default)\n"
+ "\t-i: test integer arithmetic instructions (default)\n"
+ "\t-l: test integer logical instructions (default)\n"
+ "\t-c: test integer compare instructions (default)\n"
+ "\t-L: test integer load/store instructions (default)\n"
"\t-f: test floating point instructions\n"
"\t-a: test altivec instructions\n"
"\t-m: test miscellaneous instructions\n"
@@ -7767,7 +7770,8 @@
#else // #if !defined (USAGE_SIMPLE)
////////////////////////////////////////////////////////////////////////
/* Simple usage:
- ./jm-insns -i => int insns
+ ./jm-insns -i => int arithmetic insns
+ ./jm-insns -l => int logical insns
./jm-insns -f => fp insns
./jm-insns -a => av insns
./jm-insns -m => miscellaneous insns
@@ -7782,10 +7786,10 @@
flags.two_args = 1;
flags.three_args = 1;
// Type
- flags.arith = 1;
- flags.logical = 1;
- flags.compare = 1;
- flags.ldst = 1;
+ flags.arith = 0;
+ flags.logical = 0;
+ flags.compare = 0;
+ flags.ldst = 0;
// Family
flags.integer = 0;
flags.floats = 0;
@@ -7796,22 +7800,51 @@
// Flags
flags.cr = 2;
- while ((c = getopt(argc, argv, "ifmahvA")) != -1) {
+ while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) {
switch (c) {
case 'i':
+ flags.arith = 1;
+ flags.integer = 1;
+ break;
+ case 'l':
+ flags.logical = 1;
+ flags.integer = 1;
+ break;
+ case 'c':
+ flags.compare = 1;
+ flags.integer = 1;
+ break;
+ case 'L':
+ flags.ldst = 1;
flags.integer = 1;
break;
case 'f':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.floats = 1;
break;
case 'a':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.altivec = 1;
flags.faltivec = 1;
break;
case 'm':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.misc = 1;
break;
case 'A':
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
flags.integer = 1;
flags.floats = 1;
flags.altivec = 1;
Modified: trunk/none/tests/ppc32/jm-int.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int.stdout.exp (original)
+++ trunk/none/tests/ppc32/jm-int.stdout.exp Wed May 3 18:28:35 2017
@@ -450,270 +450,6 @@
subfeo. ffffffff, 000f423f => 000f4240 (40000000 00000000)
subfeo. ffffffff, ffffffff => 00000000 (20000000 20000000)
-PPC integer logical insns with two args:
- and 00000000, 00000000 => 00000000 (00000000 00000000)
- and 00000000, 000f423f => 00000000 (00000000 00000000)
- and 00000000, ffffffff => 00000000 (00000000 00000000)
- and 000f423f, 00000000 => 00000000 (00000000 00000000)
- and 000f423f, 000f423f => 000f423f (00000000 00000000)
- and 000f423f, ffffffff => 000f423f (00000000 00000000)
- and ffffffff, 00000000 => 00000000 (00000000 00000000)
- and ffffffff, 000f423f => 000f423f (00000000 00000000)
- and ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- andc 00000000, 00000000 => 00000000 (00000000 00000000)
- andc 00000000, 000f423f => 00000000 (00000000 00000000)
- andc 00000000, ffffffff => 00000000 (00000000 00000000)
- andc 000f423f, 00000000 => 000f423f (00000000 00000000)
- andc 000f423f, 000f423f => 00000000 (00000000 00000000)
- andc 000f423f, ffffffff => 00000000 (00000000 00000000)
- andc ffffffff, 00000000 => ffffffff (00000000 00000000)
- andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- andc ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- eqv 00000000, 00000000 => ffffffff (00000000 00000000)
- eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- eqv 00000000, ffffffff => 00000000 (00000000 00000000)
- eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
- eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
- eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
- eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
- eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
- eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- nand 00000000, 00000000 => ffffffff (00000000 00000000)
- nand 00000000, 000f423f => ffffffff (00000000 00000000)
- nand 00000000, ffffffff => ffffffff (00000000 00000000)
- nand 000f423f, 00000000 => ffffffff (00000000 00000000)
- nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
- nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
- nand ffffffff, 00000000 => ffffffff (00000000 00000000)
- nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- nand ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- nor 00000000, 00000000 => ffffffff (00000000 00000000)
- nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- nor 00000000, ffffffff => 00000000 (00000000 00000000)
- nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
- nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
- nor 000f423f, ffffffff => 00000000 (00000000 00000000)
- nor ffffffff, 00000000 => 00000000 (00000000 00000000)
- nor ffffffff, 000f423f => 00000000 (00000000 00000000)
- nor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- or 00000000, 00000000 => 00000000 (00000000 00000000)
- or 00000000, 000f423f => 000f423f (00000000 00000000)
- or 00000000, ffffffff => ffffffff (00000000 00000000)
- or 000f423f, 00000000 => 000f423f (00000000 00000000)
- or 000f423f, 000f423f => 000f423f (00000000 00000000)
- or 000f423f, ffffffff => ffffffff (00000000 00000000)
- or ffffffff, 00000000 => ffffffff (00000000 00000000)
- or ffffffff, 000f423f => ffffffff (00000000 00000000)
- or ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- orc 00000000, 00000000 => ffffffff (00000000 00000000)
- orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
- orc 00000000, ffffffff => 00000000 (00000000 00000000)
- orc 000f423f, 00000000 => ffffffff (00000000 00000000)
- orc 000f423f, 000f423f => ffffffff (00000000 00000000)
- orc 000f423f, ffffffff => 000f423f (00000000 00000000)
- orc ffffffff, 00000000 => ffffffff (00000000 00000000)
- orc ffffffff, 000f423f => ffffffff (00000000 00000000)
- orc ffffffff, ffffffff => ffffffff (00000000 00000000)
-
- xor 00000000, 00000000 => 00000000 (00000000 00000000)
- xor 00000000, 000f423f => 000f423f (00000000 00000000)
- xor 00000000, ffffffff => ffffffff (00000000 00000000)
- xor 000f423f, 00000000 => 000f423f (00000000 00000000)
- xor 000f423f, 000f423f => 00000000 (00000000 00000000)
- xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
- xor ffffffff, 00000000 => ffffffff (00000000 00000000)
- xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
- xor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- slw 00000000, 00000000 => 00000000 (00000000 00000000)
- slw 00000000, 000f423f => 00000000 (00000000 00000000)
- slw 00000000, ffffffff => 00000000 (00000000 00000000)
- slw 000f423f, 00000000 => 000f423f (00000000 00000000)
- slw 000f423f, 000f423f => 00000000 (00000000 00000000)
- slw 000f423f, ffffffff => 00000000 (00000000 00000000)
- slw ffffffff, 00000000 => ffffffff (00000000 00000000)
- slw ffffffff, 000f423f => 00000000 (00000000 00000000)
- slw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
- sraw 00000000, 00000000 => 00000000 (00000000 00000000)
- sraw 00000000, 000f423f => 00000000 (00000000 00000000)
- sraw 00000000, ffffffff => 00000000 (00000000 00000000)
- sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
- sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
- sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
- sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
- sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
- sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
-
- srw 00000000, 00000000 => 00000000 (00000000 00000000)
- srw 00000000, 000f423f => 00000000 (00000000 00000000)
- srw 00000000, ffffffff => 00000000 (00000000 00000000)
- srw 000f423f, 00000000 => 000f423f (00000000 00000000)
- srw 000f423f, 000f423f => 00000000 (00000000 00000000)
- srw 000f423f, ffffffff => 00000000 (00000000 00000000)
- srw ffffffff, 00000000 => ffffffff (00000000 00000000)
- srw ffffffff, 000f423f => 00000000 (00000000 00000000)
- srw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-PPC integer logical insns with two args with flags update:
- and. 00000000, 00000000 => 00000000 (20000000 00000000)
- and. 00000000, 000f423f => 00000000 (20000000 00000000)
- and. 00000000, ffffffff => 00000000 (20000000 00000000)
- and. 000f423f, 00000000 => 00000000 (20000000 00000000)
- and. 000f423f, 000f423f => 000f423f (40000000 00000000)
- and. 000f423f, ffffffff => 000f423f (40000000 00000000)
- and. ffffffff, 00000000 => 00000000 (20000000 00000000)
- and. ffffffff, 000f423f => 000f423f (40000000 00000000)
- and. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- andc. 00000000, 00000000 => 00000000 (20000000 00000000)
- andc. 00000000, 000f423f => 00000000 (20000000 00000000)
- andc. 00000000, ffffffff => 00000000 (20000000 00000000)
- andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
- andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
- andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
- andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
- andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
- eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
- eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
- eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
- eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
- eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
- eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
- eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- nand. 00000000, 00000000 => ffffffff (80000000 00000000)
- nand. 00000000, 000f423f => ffffffff (80000000 00000000)
- nand. 00000000, ffffffff => ffffffff (80000000 00000000)
- nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
- nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
- nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
- nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
- nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- nor. 00000000, 00000000 => ffffffff (80000000 00000000)
- nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- nor. 00000000, ffffffff => 00000000 (20000000 00000000)
- nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
- nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
- nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
- nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
- nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
- nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- or. 00000000, 00000000 => 00000000 (20000000 00000000)
- or. 00000000, 000f423f => 000f423f (40000000 00000000)
- or. 00000000, ffffffff => ffffffff (80000000 00000000)
- or. 000f423f, 00000000 => 000f423f (40000000 00000000)
- or. 000f423f, 000f423f => 000f423f (40000000 00000000)
- or. 000f423f, ffffffff => ffffffff (80000000 00000000)
- or. ffffffff, 00000000 => ffffffff (80000000 00000000)
- or. ffffffff, 000f423f => ffffffff (80000000 00000000)
- or. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- orc. 00000000, 00000000 => ffffffff (80000000 00000000)
- orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
- orc. 00000000, ffffffff => 00000000 (20000000 00000000)
- orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
- orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
- orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
- orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
- orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
- orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
- xor. 00000000, 00000000 => 00000000 (20000000 00000000)
- xor. 00000000, 000f423f => 000f423f (40000000 00000000)
- xor. 00000000, ffffffff => ffffffff (80000000 00000000)
- xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
- xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
- xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
- xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
- xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
- xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- slw. 00000000, 00000000 => 00000000 (20000000 00000000)
- slw. 00000000, 000f423f => 00000000 (20000000 00000000)
- slw. 00000000, ffffffff => 00000000 (20000000 00000000)
- slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
- slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
- sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
- sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
- sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
- sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
- sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
-
- srw. 00000000, 00000000 => 00000000 (20000000 00000000)
- srw. 00000000, 000f423f => 00000000 (20000000 00000000)
- srw. 00000000, ffffffff => 00000000 (20000000 00000000)
- srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
- srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
- srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
- srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
- srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
- srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-PPC integer compare insns (two args):
- cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
- cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
- cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
- cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
- cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
- cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
- cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
- cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
- cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
- cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
- cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
- cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
- cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
- cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
- cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
- cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
-PPC integer compare with immediate insns (two args):
- cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
- cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
- cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
- cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
- cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
- cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
- cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
- cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
-
- cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
- cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
- cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
- cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
- cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
- cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
- cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
- cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
- cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
-
PPC integer arith insns
with one register + one 16 bits immediate args:
addi 00000000, 00000000 => 00000000 (00000000 00000000)
@@ -778,151 +514,6 @@
addic. ffffffff, 000003e7 => 000003e6 (40000000 20000000)
addic. ffffffff, 0000ffff => fffffffe (80000000 20000000)
-PPC integer logical insns
- with one register + one 16 bits immediate args:
- ori 00000000, 00000000 => 00000000 (00000000 00000000)
- ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
- ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
- ori 000f423f, 00000000 => 000f423f (00000000 00000000)
- ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
- ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
- ori ffffffff, 00000000 => ffffffff (00000000 00000000)
- ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
- ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
- oris 00000000, 00000000 => 00000000 (00000000 00000000)
- oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
- oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
- oris 000f423f, 00000000 => 000f423f (00000000 00000000)
- oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
- oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
- oris ffffffff, 00000000 => ffffffff (00000000 00000000)
- oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
- oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
- xori 00000000, 00000000 => 00000000 (00000000 00000000)
- xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
- xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
- xori 000f423f, 00000000 => 000f423f (00000000 00000000)
- xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
- xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
- xori ffffffff, 00000000 => ffffffff (00000000 00000000)
- xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
- xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
-
- xoris 00000000, 00000000 => 00000000 (00000000 00000000)
- xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
- xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
- xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
- xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
- xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
- xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
- xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
- xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
-
-PPC integer logical insns
- with one register + one 16 bits immediate args with flags update:
- andi. 00000000, 00000000 => 00000000 (20000000 00000000)
- andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
- andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
- andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
- andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
- andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
- andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
- andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
- andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
-
- andis. 00000000, 00000000 => 00000000 (20000000 00000000)
- andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
- andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
- andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
- andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
- andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
- andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
- andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
- andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
-
-PPC condition register logical insns - two operands:
- crand 00000000, 00000000 => ffff0000 (00000000 00000000)
- crand 00000000, 000f423f => ffff0000 (00000000 00000000)
- crand 00000000, ffffffff => ffff0000 (00000000 00000000)
- crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
- crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
- crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
- crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
- creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
- creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
- creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
- creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
- creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
- creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
- creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
- creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
- crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
- crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
- crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
- crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
- crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
- crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- cror 00000000, 00000000 => ffff0000 (00000000 00000000)
- cror 00000000, 000f423f => ffff0000 (00000000 00000000)
- cror 00000000, ffffffff => ffff0000 (00000000 00000000)
- cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
- cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
- cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
- cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
- cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
- cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
- crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
- crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
- crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
- crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
- crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
- crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
- crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
- crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
- crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
- crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
- crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
- crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
- crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
- crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
- crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
- crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
- crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
- crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
PPC integer arith insns with one arg and carry:
addme 00000000 => ffffffff (00000000 00000000)
addme 000f423f => 000f423e (00000000 20000000)
@@ -1037,568 +628,9 @@
subfzeo. 000f423f => fff0bdc1 (80000000 00000000)
subfzeo. ffffffff => 00000001 (40000000 00000000)
-PPC integer logical insns with one arg:
- cntlzw 00000000 => 00000020 (00000000 00000000)
- cntlzw 000f423f => 0000000c (00000000 00000000)
- cntlzw ffffffff => 00000000 (00000000 00000000)
-
- extsb 00000000 => 00000000 (00000000 00000000)
- extsb 000f423f => 0000003f (00000000 00000000)
- extsb ffffffff => ffffffff (00000000 00000000)
-
- extsh 00000000 => 00000000 (00000000 00000000)
- extsh 000f423f => 0000423f (00000000 00000000)
- extsh ffffffff => ffffffff (00000000 00000000)
-
- neg 00000000 => 00000000 (00000000 00000000)
- neg 000f423f => fff0bdc1 (00000000 00000000)
- neg ffffffff => 00000001 (00000000 00000000)
-
- nego 00000000 => 00000000 (00000000 00000000)
- nego 000f423f => fff0bdc1 (00000000 00000000)
- nego ffffffff => 00000001 (00000000 00000000)
-
-PPC integer logical insns with one arg with flags update:
- cntlzw. 00000000 => 00000020 (40000000 00000000)
- cntlzw. 000f423f => 0000000c (40000000 00000000)
- cntlzw. ffffffff => 00000000 (20000000 00000000)
-
- extsb. 00000000 => 00000000 (20000000 00000000)
- extsb. 000f423f => 0000003f (40000000 00000000)
- extsb. ffffffff => ffffffff (80000000 00000000)
-
- extsh. 00000000 => 00000000 (20000000 00000000)
- extsh. 000f423f => 0000423f (40000000 00000000)
- extsh. ffffffff => ffffffff (80000000 00000000)
-
- neg. 00000000 => 00000000 (20000000 00000000)
- neg. 000f423f => fff0bdc1 (80000000 00000000)
- neg. ffffffff => 00000001 (40000000 00000000)
-
- nego. 00000000 => 00000000 (20000000 00000000)
- nego. 000f423f => fff0bdc1 (80000000 00000000)
- nego. ffffffff => 00000001 (40000000 00000000)
-
-PPC logical insns with special forms:
- rlwimi 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
- rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
- rlwimi 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwimi 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 0, 31, 0 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 0, 31, 31 => 000f423f (00000000 00000000)
- rlwimi 000f423f, 31, 0, 0 => 800f423f (00000000 00000000)
- rlwimi 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
- rlwimi 000f423f, 31, 31, 0 => 8007a11f (00000000 00000000)
- rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
- rlwimi ffffffff, 0, 0, 0 => 8007a11f (00000000 00000000)
- rlwimi ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 0, 31, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 0, 31, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 0, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 31, 0 => ffffffff (00000000 00000000)
- rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
-
- rlwinm 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 0, 31 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 31, 0 => 00000000 (00000000 00000000)
- rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
- rlwinm 000f423f, 0, 0, 0 => 00000000 (00000000 00000000)
- rlwinm 000f423f, 0, 0, 31 => 000f423f (00000000 00000000)
- rlwinm 000f423f, 0, 31, 0 => 00000001 (00000000 00000000)
- rlwinm 000f423f, 0, 31, 31 => 00000001 (00000000 00000000)
- rlwinm 000f423f, 31, 0, 0 => 80000000 (00000000 00000000)
- rlwinm 000f423f, 31, 0, 31 => 8007a11f (00000000 00000000)
- rlwinm 000f423f, 31, 31, 0 => 80000001 (00000000 00000000)
- rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
- rlwinm ffffffff, 0, 0, 0 => 80000000 (00000000 00000000)
- rlwinm ffffffff, 0, 0, 31 => ffffffff (00000000 00000000)
- rlwinm ffffffff, 0, 31, 0 => 80000001 (00000000 00000000)
- rlwinm ffffffff, 0, 31, 31 => 00000001 (00000000 00000000)
- rlwinm ffffffff, 31, 0, 0 => 80000000 (00000000 00000000)
- rlwinm ffffffff, 31, 0, 31 => ffffffff (00000000 00000000)
- rlwinm ffffffff, 31, 31, 0 => 80000001 (00000000 00000000)
- rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
-
- rlwnm 00000000, 00000000, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 0, 31 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 31, 0 => 00000000 (00000000 00000000)
- rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
- rlwnm 000f423f, 00000000, 0, 0 => 00000000 (00000000 00000000)
- rlwnm 000f423f, 00000000, 0, 31 => 000f423f (00000000 00000000)
- rlwnm 000f423f, 00000000, 31, 0 => 00000001 (00000000 00000000)
- rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 0, 0 => 80000000 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 0, 31 => 8007a11f (00000000 00000000)
- rlwnm 000f423f, 000f423f, 31, 0 => 80000001 (00000000 00000000)
- rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 0, 0 => 80000000 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 0, 31 => 8007a11f (00000000 00000000)
- rlwnm 000f423f, ffffffff, 31, 0 => 80000001 (00000000 00000000)
- rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, 00000000, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, 00000000, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, 00000000, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, 000f423f, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 0, 0 => 80000000 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 0, 31 => ffffffff (00000000 00000000)
- rlwnm ffffffff, ffffffff, 31, 0 => 80000001 (00000000 00000000)
- rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
-
- srawi 00000000, 0 => 00000000 (00000000 00000000)
- srawi 00000000, 31 => 00000000 (00000000 00000000)
- srawi 000f423f, 0 => 000f423f (00000000 00000000)
- srawi 000f423f, 31 => 00000000 (00000000 00000000)
- srawi ffffffff, 0 => ffffffff (00000000 00000000)
- srawi ffffffff, 31 => ffffffff (00000000 20000000)
-
- mfcr (00000000) => 00000000 (00000000 00000000)
- mfcr (000f423f) => 000f423f (000f423f 00000000)
- mfcr (ffffffff) => ffffffff (ffffffff 00000000)
-
- mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
- mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
- mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
- mfspr 8 (00000000) -> mtlr -> mflr => 00000000
- mfspr 8 (000f423f) -> mtlr -> mflr => 000f423f
- mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffff
- mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
- mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
- mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
-
-
-PPC logical insns with special forms with flags update:
- rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
- rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
- rlwimi. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwimi. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 0, 31, 0 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 0, 31, 31 => 000f423f (40000000 00000000)
- rlwimi. 000f423f, 31, 0, 0 => 800f423f (80000000 00000000)
- rlwimi. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
- rlwimi. 000f423f, 31, 31, 0 => 8007a11f (80000000 00000000)
- rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
- rlwimi. ffffffff, 0, 0, 0 => 8007a11f (80000000 00000000)
- rlwimi. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 0, 31, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 0, 31, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 0, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 31, 0 => ffffffff (80000000 00000000)
- rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
-
- rlwinm. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 0, 31 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 31, 0 => 00000000 (20000000 00000000)
- rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
- rlwinm. 000f423f, 0, 0, 0 => 00000000 (20000000 00000000)
- rlwinm. 000f423f, 0, 0, 31 => 000f423f (40000000 00000000)
- rlwinm. 000f423f, 0, 31, 0 => 00000001 (40000000 00000000)
- rlwinm. 000f423f, 0, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. 000f423f, 31, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. 000f423f, 31, 0, 31 => 8007a11f (80000000 00000000)
- rlwinm. 000f423f, 31, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. ffffffff, 0, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. ffffffff, 0, 0, 31 => ffffffff (80000000 00000000)
- rlwinm. ffffffff, 0, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. ffffffff, 0, 31, 31 => 00000001 (40000000 00000000)
- rlwinm. ffffffff, 31, 0, 0 => 80000000 (80000000 00000000)
- rlwinm. ffffffff, 31, 0, 31 => ffffffff (80000000 00000000)
- rlwinm. ffffffff, 31, 31, 0 => 80000001 (80000000 00000000)
- rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
-
- rlwnm. 00000000, 00000000, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 0, 31 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 31, 0 => 00000000 (20000000 00000000)
- rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
- rlwnm. 000f423f, 00000000, 0, 0 => 00000000 (20000000 00000000)
- rlwnm. 000f423f, 00000000, 0, 31 => 000f423f (40000000 00000000)
- rlwnm. 000f423f, 00000000, 31, 0 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, 000f423f, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 0, 31 => 8007a11f (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. 000f423f, ffffffff, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 0, 31 => 8007a11f (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, 00000000, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, 00000000, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, 00000000, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, 000f423f, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
- rlwnm. ffffffff, ffffffff, 0, 0 => 80000000 (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 0, 31 => ffffffff (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 31, 0 => 80000001 (80000000 00000000)
- rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
-
- srawi. 00000000, 0 => 00000000 (20000000 00000000)
- srawi. 00000000, 31 => 00000000 (20000000 00000000)
- srawi. 000f423f, 0 => 000f423f (40000000 00000000)
- srawi. 000f423f, 31 => 00000000 (20000000 00000000)
- srawi. ffffffff, 0 => ffffffff (80000000 00000000)
- srawi. ffffffff, 31 => ffffffff (80000000 20000000)
-
- mcrf 0, 0 (00000000) => (00000000 00000000)
- mcrf 0, 7 (00000000) => (00000000 00000000)
- mcrf 7, 0 (00000000) => (00000000 00000000)
- mcrf 7, 7 (00000000) => (00000000 00000000)
- mcrf 0, 0 (000f423f) => (000f423f 00000000)
- mcrf 0, 7 (000f423f) => (f00f423f 00000000)
- mcrf 7, 0 (000f423f) => (000f4230 00000000)
- mcrf 7, 7 (000f423f) => (000f423f 00000000)
- mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
- mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
- mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
- mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
-
- mcrxr 0 (00000000) => (00000000 00000000)
- mcrxr 1 (00000000) => (00000000 00000000)
- mcrxr 2 (00000000) => (00000000 00000000)
- mcrxr 3 (00000000) => (00000000 00000000)
- mcrxr 4 (00000000) => (00000000 00000000)
- mcrxr 5 (00000000) => (00000000 00000000)
- mcrxr 6 (00000000) => (00000000 00000000)
- mcrxr 7 (00000000) => (00000000 00000000)
- mcrxr 0 (10000000) => (00000000 00000000)
- mcrxr 1 (10000000) => (00000000 00000000)
- mcrxr 2 (10000000) => (00000000 00000000)
- mcrxr 3 (10000000) => (00000000 00000000)
- mcrxr 4 (10000000) => (00000000 00000000)
- mcrxr 5 (10000000) => (00000000 00000000)
- mcrxr 6 (10000000) => (00000000 00000000)
- mcrxr 7 (10000000) => (00000000 00000000)
- mcrxr 0 (20000000) => (20000000 00000000)
- mcrxr 1 (20000000) => (02000000 00000000)
- mcrxr 2 (20000000) => (00200000 00000000)
- mcrxr 3 (20000000) => (00020000 00000000)
- mcrxr 4 (20000000) => (00002000 00000000)
- mcrxr 5 (20000000) => (00000200 00000000)
- mcrxr 6 (20000000) => (00000020 00000000)
- mcrxr 7 (20000000) => (00000002 00000000)
- mcrxr 0 (30000000) => (20000000 00000000)
- mcrxr 1 (30000000) => (02000000 00000000)
- mcrxr 2 (30000000) => (00200000 00000000)
- mcrxr 3 (30000000) => (00020000 00000000)
- mcrxr 4 (30000000) => (00002000 00000000)
- mcrxr 5 (30000000) => (00000200 00000000)
- mcrxr 6 (30000000) => (00000020 00000000)
- mcrxr 7 (30000000) => (00000002 00000000)
- mcrxr 0 (40000000) => (40000000 00000000)
- mcrxr 1 (40000000) => (04000000 00000000)
- mcrxr 2 (40000000) => (00400000 00000000)
- mcrxr 3 (40000000) => (00040000 00000000)
- mcrxr 4 (40000000) => (00004000 00000000)
- mcrxr 5 (40000000) => (00000400 00000000)
- mcrxr 6 (40000000) => (00000040 00000000)
- mcrxr 7 (40000000) => (00000004 00000000)
- mcrxr 0 (50000000) => (40000000 00000000)
- mcrxr 1 (50000000) => (04000000 00000000)
- mcrxr 2 (50000000) => (00400000 00000000)
- mcrxr 3 (50000000) => (00040000 00000000)
- mcrxr 4 (50000000) => (00004000 00000000)
- mcrxr 5 (50000000) => (00000400 00000000)
- mcrxr 6 (50000000) => (00000040 00000000)
- mcrxr 7 (50000000) => (00000004 00000000)
- mcrxr 0 (60000000) => (60000000 00000000)
- mcrxr 1 (60000000) => (06000000 00000000)
- mcrxr 2 (60000000) => (00600000 00000000)
- mcrxr 3 (60000000) => (00060000 00000000)
- mcrxr 4 (60000000) => (00006000 00000000)
- mcrxr 5 (60000000) => (00000600 00000000)
- mcrxr 6 (60000000) => (00000060 00000000)
- mcrxr 7 (60000000) => (00000006 00000000)
- mcrxr 0 (70000000) => (60000000 00000000)
- mcrxr 1 (70000000) => (06000000 00000000)
- mcrxr 2 (70000000) => (00600000 00000000)
- mcrxr 3 (70000000) => (00060000 00000000)
- mcrxr 4 (70000000) => (00006000 00000000)
- mcrxr 5 (70000000) => (00000600 00000000)
- mcrxr 6 (70000000) => (00000060 00000000)
- mcrxr 7 (70000000) => (00000006 00000000)
- mcrxr 0 (80000000) => (80000000 00000000)
- mcrxr 1 (80000000) => (08000000 00000000)
- mcrxr 2 (80000000) => (00800000 00000000)
- mcrxr 3 (80000000) => (00080000 00000000)
- mcrxr 4 (80000000) => (00008000 00000000)
- mcrxr 5 (80000000) => (00000800 00000000)
- mcrxr 6 (80000000) => (00000080 00000000)
- mcrxr 7 (80000000) => (00000008 00000000)
- mcrxr 0 (90000000) => (80000000 00000000)
- mcrxr 1 (90000000) => (08000000 00000000)
- mcrxr 2 (90000000) => (00800000 00000000)
- mcrxr 3 (90000000) => (00080000 00000000)
- mcrxr 4 (90000000) => (00008000 00000000)
- mcrxr 5 (90000000) => (00000800 00000000)
- mcrxr 6 (90000000) => (00000080 00000000)
- mcrxr 7 (90000000) => (00000008 00000000)
- mcrxr 0 (a0000000) => (a0000000 00000000)
- mcrxr 1 (a0000000) => (0a000000 00000000)
- mcrxr 2 (a0000000) => (00a00000 00000000)
- mcrxr 3 (a0000000) => (000a0000 00000000)
- mcrxr 4 (a0000000) => (0000a000 00000000)
- mcrxr 5 (a0000000) => (00000a00 00000000)
- mcrxr 6 (a0000000) => (000000a0 00000000)
- mcrxr 7 (a0000000) => (0000000a 00000000)
- mcrxr 0 (b0000000) => (a0000000 00000000)
- mcrxr 1 (b0000000) => (0a000000 00000000)
- mcrxr 2 (b0000000) => (00a00000 00000000)
- mcrxr 3 (b0000000) => (000a0000 00000000)
- mcrxr 4 (b0000000) => (0000a000 00000000)
- mcrxr 5 (b0000000) => (00000a00 00000000)
- mcrxr 6 (b0000000) => (000000a0 00000000)
- mcrxr 7 (b0000000) => (0000000a 00000000)
- mcrxr 0 (c0000000) => (c0000000 00000000)
- mcrxr 1 (c0000000) => (0c000000 00000000)
- mcrxr 2 (c0000000) => (00c00000 00000000)
- mcrxr 3 (c0000000) => (000c0000 00000000)
- mcrxr 4 (c0000000) => (0000c000 00000000)
- mcrxr 5 (c0000000) => (00000c00 00000000)
- mcrxr 6 (c0000000) => (000000c0 00000000)
- mcrxr 7 (c0000000) => (0000000c 00000000)
- mcrxr 0 (d0000000) => (c0000000 00000000)
- mcrxr 1 (d0000000) => (0c000000 00000000)
- mcrxr 2 (d0000000) => (00c00000 00000000)
- mcrxr 3 (d0000000) => (000c0000 00000000)
- mcrxr 4 (d0000000) => (0000c000 00000000)
- mcrxr 5 (d0000000) => (00000c00 00000000)
- mcrxr 6 (d0000000) => (000000c0 00000000)
- mcrxr 7 (d0000000) => (0000000c 00000000)
- mcrxr 0 (e0000000) => (e0000000 00000000)
- mcrxr 1 (e0000000) => (0e000000 00000000)
- mcrxr 2 (e0000000) => (00e00000 00000000)
- mcrxr 3 (e0000000) => (000e0000 00000000)
- mcrxr 4 (e0000000) => (0000e000 00000000)
- mcrxr 5 (e0000000) => (00000e00 00000000)
- mcrxr 6 (e0000000) => (000000e0 00000000)
- mcrxr 7 (e0000000) => (0000000e 00000000)
- mcrxr 0 (f0000000) => (e0000000 00000000)
- mcrxr 1 (f0000000) => (0e000000 00000000)
- mcrxr 2 (f0000000) => (00e00000 00000000)
- mcrxr 3 (f0000000) => (000e0000 00000000)
- mcrxr 4 (f0000000) => (0000e000 00000000)
- mcrxr 5 (f0000000) => (00000e00 00000000)
- mcrxr 6 (f0000000) => (000000e0 00000000)
- mcrxr 7 (f0000000) => (0000000e 00000000)
-
- mtcrf 0, 00000000 => (00000000 00000000)
- mtcrf 99, 00000000 => (00000000 00000000)
- mtcrf 198, 00000000 => (00000000 00000000)
- mtcrf 0, 000f423f => (00000000 00000000)
- mtcrf 99, 000f423f => (0000003f 00000000)
- mtcrf 198, 000f423f => (00000230 00000000)
- mtcrf 0, ffffffff => (00000000 00000000)
- mtcrf 99, ffffffff => (0ff000ff 00000000)
- mtcrf 198, ffffffff => (ff000ff0 00000000)
-
-PPC integer load insns
- with one register + one 16 bits immediate args with flags update:
- lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
- lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
- lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
- lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
- lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
- lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
- lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lha 0, (00000000) => 00000000, 0 (00000000 00000000)
- lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
- lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
- lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lha -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
- lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
- lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
- lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
- lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
- lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
- lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
- lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
- lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
- lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
- lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
- lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
- lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
- lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
- lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
- lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
- lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
-
- lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
- lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
- lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
- lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
- lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
- lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-PPC integer load insns with two register args:
- lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
- lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
-
- lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
- lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
-
- lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
- lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
- lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
- lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
- lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
- lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
-
- lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
- lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
-
- lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
- lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
- lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
- lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
- lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
- lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
-PPC integer store insns
- with one register + one 16 bits immediate args with flags update:
- stb 00000000, 0 => 00000000, 0 (00000000 00000000)
- stb 000f423f, 4 => 3f000000, 0 (00000000 00000000)
- stb ffffffff, 8 => ff000000, 0 (00000000 00000000)
- stb 00000000, -8 => 00000000, 0 (00000000 00000000)
- stb 000f423f, -4 => 3f000000, 0 (00000000 00000000)
- stb ffffffff, 0 => ff000000, 0 (00000000 00000000)
-
- stbu 00000000, 0 => 00000000, 0 (00000000 00000000)
- stbu 000f423f, 4 => 3f000000, 4 (00000000 00000000)
- stbu ffffffff, 8 => ff000000, 8 (00000000 00000000)
- stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
- stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
- stbu ffffffff, 0 => ff000000, 0 (00000000 00000000)
-
- sth 0000000...
[truncated message content] |
|
From: <sv...@va...> - 2017-05-03 17:25:05
|
Author: carll
Date: Wed May 3 18:24:55 2017
New Revision: 3359
Log:
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0. The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions. So now the
instructions produce different results in the XER register. Thus we need pre
and post ISA 3.0 expect files. Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args. The instructions that have different XER results
are run using a different set of command line args. The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0. We then create ISA3.0 expect files only for the tests
that run differently. By doing this we minimized the size of the expect files
needed.
Valgrind bugzilla 378931
Modified:
trunk/priv/guest_ppc_helpers.c
trunk/priv/guest_ppc_toIR.c
trunk/pub/libvex_guest_ppc32.h
trunk/pub/libvex_guest_ppc64.h
Modified: trunk/priv/guest_ppc_helpers.c
==============================================================================
--- trunk/priv/guest_ppc_helpers.c (original)
+++ trunk/priv/guest_ppc_helpers.c Wed May 3 18:24:55 2017
@@ -537,6 +537,8 @@
w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
+ w |= ( (((UInt)vex_state->guest_XER_OV32) & 0x1) << 19 );
+ w |= ( (((UInt)vex_state->guest_XER_CA32) & 0x1) << 18 );
return w;
}
@@ -550,6 +552,8 @@
w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
+ w |= ( (((UInt)vex_state->guest_XER_OV32) & 0x1) << 19 );
+ w |= ( (((UInt)vex_state->guest_XER_CA32) & 0x1) << 18 );
return w;
}
@@ -562,6 +566,8 @@
vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_OV32 = toUChar((xer_native >> 19) & 0x1);
+ vex_state->guest_XER_CA32 = toUChar((xer_native >> 18) & 0x1);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -573,6 +579,8 @@
vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_OV32 = toUChar((xer_native >> 19) & 0x1);
+ vex_state->guest_XER_CA32 = toUChar((xer_native >> 18) & 0x1);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -696,6 +704,9 @@
vex_state->guest_XER_CA = 0;
vex_state->guest_XER_BC = 0;
+ vex_state->guest_XER_OV32 = 0;
+ vex_state->guest_XER_CA32 = 0;
+
vex_state->guest_CR0_321 = 0;
vex_state->guest_CR0_0 = 0;
vex_state->guest_CR1_321 = 0;
@@ -740,7 +751,7 @@
vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
vex_state->padding1 = 0;
- vex_state->padding2 = 0;
+ /* vex_state->padding2 = 0; currently not used */
}
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Wed May 3 18:24:55 2017
@@ -239,6 +239,9 @@
}
}
+/* The OV32 and CA32 bits were added with ISA3.0 */
+static Bool OV32_CA32_supported = False;
+
#define SIGN_BIT 0x8000000000000000ULL
#define SIGN_MASK 0x7fffffffffffffffULL
#define SIGN_BIT32 0x80000000
@@ -273,7 +276,9 @@
#define OFFB_CTR offsetofPPCGuestState(guest_CTR)
#define OFFB_XER_SO offsetofPPCGuestState(guest_XER_SO)
#define OFFB_XER_OV offsetofPPCGuestState(guest_XER_OV)
+#define OFFB_XER_OV32 offsetofPPCGuestState(guest_XER_OV32)
#define OFFB_XER_CA offsetofPPCGuestState(guest_XER_CA)
+#define OFFB_XER_CA32 offsetofPPCGuestState(guest_XER_CA32)
#define OFFB_XER_BC offsetofPPCGuestState(guest_XER_BC)
#define OFFB_FPROUND offsetofPPCGuestState(guest_FPROUND)
#define OFFB_DFPROUND offsetofPPCGuestState(guest_DFPROUND)
@@ -2201,20 +2206,48 @@
static void putXER_OV ( IRExpr* e )
{
+ /* Interface to write XER[OV] */
IRExpr* ov;
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ov = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_OV, ov ) );
}
+static void putXER_OV32 ( IRExpr* e )
+{
+ /*Interface to write XER[OV32] */
+ IRExpr* ov;
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
+ ov = binop(Iop_And8, e, mkU8(1));
+
+ /* The OV32 bit was added to XER in ISA 3.0. Do not write unless we
+ * ISA 3.0 or beyond is supported. */
+ if( OV32_CA32_supported )
+ stmt( IRStmt_Put( OFFB_XER_OV32, ov ) );
+}
+
static void putXER_CA ( IRExpr* e )
{
+ /* Interface to write XER[CA] */
IRExpr* ca;
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ca = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_CA, ca ) );
}
+static void putXER_CA32 ( IRExpr* e )
+{
+ /* Interface to write XER[CA32] */
+ IRExpr* ca;
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
+ ca = binop(Iop_And8, e, mkU8(1));
+
+ /* The CA32 bit was added to XER in ISA 3.0. Do not write unless we
+ * ISA 3.0 or beyond is supported. */
+ if( OV32_CA32_supported )
+ stmt( IRStmt_Put( OFFB_XER_CA32, ca ) );
+}
+
static void putXER_BC ( IRExpr* e )
{
IRExpr* bc;
@@ -2228,7 +2261,7 @@
return IRExpr_Get( OFFB_XER_SO, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_SO32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_SO_32 ( void )
{
return binop( Iop_And32, unop(Iop_8Uto32, getXER_SO()), mkU32(1) );
}
@@ -2238,23 +2271,43 @@
return IRExpr_Get( OFFB_XER_OV, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_OV32 ( void )
+static IRExpr* /* :: Ity_I8 */ getXER_OV32 ( void )
+{
+ return IRExpr_Get( OFFB_XER_OV32, Ity_I8 );
+}
+
+static IRExpr* /* :: Ity_I32 */ getXER_OV_32 ( void )
{
+ /* get XER[OV], 32-bit interface */
return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV()), mkU32(1) );
}
-static IRExpr* /* :: Ity_I32 */ getXER_CA32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_OV32_32 ( void )
{
+ /* get XER[OV32], 32-bit interface */
+ return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV32()), mkU32(1) );
+}
+
+static IRExpr* /* :: Ity_I32 */ getXER_CA_32 ( void )
+{
+ /* get XER[CA], 32-bit interface */
IRExpr* ca = IRExpr_Get( OFFB_XER_CA, Ity_I8 );
return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) );
}
+static IRExpr* /* :: Ity_I32 */ getXER_CA32_32 ( void )
+{
+ /* get XER[CA32], 32-bit interface */
+ IRExpr* ca = IRExpr_Get( OFFB_XER_CA32, Ity_I8 );
+ return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) );
+}
+
static IRExpr* /* :: Ity_I8 */ getXER_BC ( void )
{
return IRExpr_Get( OFFB_XER_BC, Ity_I8 );
}
-static IRExpr* /* :: Ity_I32 */ getXER_BC32 ( void )
+static IRExpr* /* :: Ity_I32 */ getXER_BC_32 ( void )
{
IRExpr* bc = IRExpr_Get( OFFB_XER_BC, Ity_I8 );
return binop( Iop_And32, unop(Iop_8Uto32, bc), mkU32(0x7F) );
@@ -2264,15 +2317,11 @@
/* RES is the result of doing OP on ARGL and ARGR. Set %XER.OV and
%XER.SO accordingly. */
-static void set_XER_OV_32( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static IRExpr* calculate_XER_OV_32( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
IRTemp t64;
IRExpr* xer_ov;
- vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
# define INT32_MIN 0x80000000
@@ -2381,15 +2430,11 @@
default:
- vex_printf("set_XER_OV: op = %u\n", op);
- vpanic("set_XER_OV(ppc)");
+ vex_printf("calculate_XER_OV_32: op = %u\n", op);
+ vpanic("calculate_XER_OV_32(ppc)");
}
-
- /* xer_ov MUST denote either 0 or 1, no other value allowed */
- putXER_OV( unop(Iop_32to8, xer_ov) );
- /* Update the summary overflow */
- putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+ return xer_ov;
# undef INT32_MIN
# undef AND3
@@ -2398,14 +2443,27 @@
# undef NOT
}
-static void set_XER_OV_64( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static void set_XER_OV_OV32_32( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
IRExpr* xer_ov;
+
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
+
+ xer_ov = calculate_XER_OV_32( op, res, argL, argR );
+
+ /* xer_ov MUST denote either 0 or 1, no other value allowed */
+ putXER_OV( unop(Iop_32to8, xer_ov) );
+ putXER_OV32( unop(Iop_32to8, xer_ov) );
+}
+
+static IRExpr* calculate_XER_OV_64( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ IRExpr* xer_ov;
# define INT64_MIN 0x8000000000000000ULL
@@ -2485,7 +2543,7 @@
= unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63)));
break;
- case PPCG_FLAG_OP_DIVDE:
+ case /* 14 */ PPCG_FLAG_OP_DIVDE:
/* If argR == 0, we must set the OV bit. But there's another condition
* where we can get overflow set for divde . . . when the
@@ -2499,7 +2557,7 @@
binop( Iop_CmpNE64, argR, mkU64( 0 ) ) ) ) );
break;
- case PPCG_FLAG_OP_DIVDEU:
+ case /* 17 */ PPCG_FLAG_OP_DIVDEU:
/* If argR == 0 or if argL >= argR, set OV. */
xer_ov = mkOR1( binop( Iop_CmpEQ64, argR, mkU64( 0 ) ),
binop( Iop_CmpLE64U, argR, argL ) );
@@ -2522,15 +2580,11 @@
}
default:
- vex_printf("set_XER_OV: op = %u\n", op);
- vpanic("set_XER_OV(ppc64)");
+ vex_printf("calculate_XER_OV_64: op = %u\n", op);
+ vpanic("calculate_XER_OV_64(ppc64)");
}
-
- /* xer_ov MUST denote either 0 or 1, no other value allowed */
- putXER_OV( unop(Iop_1Uto8, xer_ov) );
- /* Update the summary overflow */
- putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+ return xer_ov;
# undef INT64_MIN
# undef AND3
@@ -2539,13 +2593,62 @@
# undef NOT
}
-static void set_XER_OV ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
+static void set_XER_OV_64( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
{
- if (ty == Ity_I32)
- set_XER_OV_32( op, res, argL, argR );
- else
+ IRExpr* xer_ov;
+ vassert(op < PPCG_FLAG_OP_NUMBER);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+
+ /* xer_ov MUST denote either 0 or 1, no other value allowed */
+ xer_ov = calculate_XER_OV_64( op, res, argL, argR);
+ putXER_OV( unop(Iop_1Uto8, xer_ov) );
+
+ /* Update the summary overflow */
+ putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+}
+
+static void update_SO( void ) {
+ /* Update the summary overflow bit */
+ putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) );
+}
+
+static void copy_OV_to_OV32( void ) {
+ /* Update the OV32 to match OV */
+ putXER_OV32( getXER_OV() );
+}
+
+static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ if (ty == Ity_I32) {
+ set_XER_OV_OV32_32( op, res, argL, argR );
+ } else {
+ IRExpr* xer_ov_32;
set_XER_OV_64( op, res, argL, argR );
+ xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
+ unop(Iop_64to32, argL),
+ unop(Iop_64to32, argR));
+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+ }
+}
+
+static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR )
+{
+ if (ty == Ity_I32) {
+ set_XER_OV_OV32_32( op, res, argL, argR );
+ } else {
+ IRExpr* xer_ov_32;
+ set_XER_OV_64( op, res, argL, argR );
+ xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
+ unop(Iop_64to32, argL),
+ unop(Iop_64to32, argR));
+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+ }
+ update_SO();
}
@@ -2553,21 +2656,10 @@
/* RES is the result of doing OP on ARGL and ARGR with the old %XER.CA
value being OLDCA. Set %XER.CA accordingly. */
-static void set_XER_CA_32 ( UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+static IRExpr* calculate_XER_CA_32 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
IRExpr* xer_ca;
- vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
- vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32);
-
- /* Incoming oldca is assumed to hold the values 0 or 1 only. This
- seems reasonable given that it's always generated by
- getXER_CA32(), which masks it accordingly. In any case it being
- 0 or 1 is an invariant of the ppc guest state representation;
- if it has any other value, that invariant has been violated. */
switch (op) {
case /* 0 */ PPCG_FLAG_OP_ADD:
@@ -2667,26 +2759,36 @@
vpanic("set_XER_CA(ppc)");
}
- /* xer_ca MUST denote either 0 or 1, no other value allowed */
- putXER_CA( unop(Iop_32to8, xer_ca) );
+ return xer_ca;
}
-static void set_XER_CA_64 ( UInt op, IRExpr* res,
+static void set_XER_CA_32 ( UInt op, IRExpr* res,
IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
IRExpr* xer_ca;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
- vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32);
/* Incoming oldca is assumed to hold the values 0 or 1 only. This
seems reasonable given that it's always generated by
- getXER_CA32(), which masks it accordingly. In any case it being
+ getXER_CA_32(), which masks it accordingly. In any case it being
0 or 1 is an invariant of the ppc guest state representation;
if it has any other value, that invariant has been violated. */
+ xer_ca = calculate_XER_CA_32( op, res, argL, argR, oldca);
+
+ /* xer_ca MUST denote either 0 or 1, no other value allowed */
+ putXER_CA( unop(Iop_32to8, xer_ca) );
+}
+
+static IRExpr* calculate_XER_CA_64 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+{
+ IRExpr* xer_ca;
+
switch (op) {
case /* 0 */ PPCG_FLAG_OP_ADD:
/* res <u argL */
@@ -2843,17 +2945,39 @@
vpanic("set_XER_CA(ppc64)");
}
+ return xer_ca;
+}
+
+static void set_XER_CA_64 ( UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+{
+ IRExpr* xer_ca;
+ vassert(op < PPCG_FLAG_OP_NUMBER);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64);
+
+ /* Incoming oldca is assumed to hold the values 0 or 1 only. This
+ seems reasonable given that it's always generated by
+ getXER_CA_32(), which masks it accordingly. In any case it being
+ 0 or 1 is an invariant of the ppc guest state representation;
+ if it has any other value, that invariant has been violated. */
+
+ xer_ca = calculate_XER_CA_64( op, res, argL, argR, oldca );
+
/* xer_ca MUST denote either 0 or 1, no other value allowed */
putXER_CA( unop(Iop_32to8, xer_ca) );
}
-static void set_XER_CA ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR, IRExpr* oldca )
+static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
+ IRExpr* argL, IRExpr* argR, IRExpr* oldca )
{
- if (ty == Ity_I32)
+ if (ty == Ity_I32) {
set_XER_CA_32( op, res, argL, argR, oldca );
- else
+ } else {
set_XER_CA_64( op, res, argL, argR, oldca );
+ }
}
@@ -2913,11 +3037,15 @@
case PPC_GST_XER:
return binop(Iop_Or32,
binop(Iop_Or32,
- binop( Iop_Shl32, getXER_SO32(), mkU8(31)),
- binop( Iop_Shl32, getXER_OV32(), mkU8(30))),
+ binop(Iop_Or32,
+ binop( Iop_Shl32, getXER_SO_32(), mkU8(31)),
+ binop( Iop_Shl32, getXER_OV_32(), mkU8(30))),
+ binop(Iop_Or32,
+ binop( Iop_Shl32, getXER_CA_32(), mkU8(29)),
+ getXER_BC_32())),
binop(Iop_Or32,
- binop( Iop_Shl32, getXER_CA32(), mkU8(29)),
- getXER_BC32()));
+ binop( Iop_Shl32, getXER_OV32_32(), mkU8(19)),
+ binop( Iop_Shl32, getXER_CA32_32(), mkU8(18))));
case PPC_GST_TFHAR:
return IRExpr_Get( OFFB_TFHAR, ty );
@@ -3032,9 +3160,9 @@
vassert(fld ==7);
return binop(Iop_Or32,
binop(Iop_Or32,
- binop(Iop_Shl32, getXER_SO32(), mkU8(3)),
- binop(Iop_Shl32, getXER_OV32(), mkU8(2))),
- binop( Iop_Shl32, getXER_CA32(), mkU8(1)));
+ binop(Iop_Shl32, getXER_SO_32(), mkU8(3)),
+ binop(Iop_Shl32, getXER_OV_32(), mkU8(2))),
+ binop( Iop_Shl32, getXER_CA_32(), mkU8(1)));
break;
default:
@@ -3084,6 +3212,8 @@
putXER_SO( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(31))) );
putXER_OV( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(30))) );
putXER_CA( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(29))) );
+ putXER_OV32( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(19))) );
+ putXER_CA32( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(18))) );
putXER_BC( unop(Iop_32to8, src) );
break;
@@ -4858,18 +4988,18 @@
DIP("addic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
mkSzExtendS16(ty, uimm16) ) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
break;
case 0x0D: // addic. (Add Immediate Carrying and Record, PPC32 p352)
DIP("addic. r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
mkSzExtendS16(ty, uimm16) ) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
do_rc = True; // Always record to CR
flag_rC = 1;
break;
@@ -4917,9 +5047,9 @@
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkSzExtendS16(ty, uimm16),
mkexpr(rA)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFI,
- mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFI,
+ mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
break;
/* XO-Form */
@@ -4934,8 +5064,8 @@
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(rB) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -4945,12 +5075,12 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(rB)) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -4960,16 +5090,35 @@
flag_OE ? "o" : "", flag_rC ? ".":"",
rD_addr, rA_addr, rB_addr);
// rD = rA + rB + XER[CA]
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
binop( mkSzOp(ty, Iop_Add8),
mkexpr(rB), mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ }
+ break;
+ }
+
+ case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
+ DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
+ assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
+ binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
+ mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
+
+ /* CY bit is same as OE bit */
+ if (flag_OE == 0) {
+ /* Exception, do not set SO bit */
+ set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ } else {
+ /* CY=1, 2 and 3 (AKA flag_OE) are reserved */
+ vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
+ vpanic("addex instruction\n");
}
break;
}
@@ -4986,17 +5135,17 @@
rD_addr, rA_addr, rB_addr);
// rD = rA + (-1) + XER[CA]
// => Just another form of adde
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
min_one = mkSzImm(ty, (Long)-1);
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
binop( mkSzOp(ty, Iop_Add8),
min_one, mkexpr(old_xer_ca)) ));
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), min_one,
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), min_one,
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), min_one );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), min_one );
}
break;
}
@@ -5012,15 +5161,15 @@
rD_addr, rA_addr, rB_addr);
// rD = rA + (0) + XER[CA]
// => Just another form of adde
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
mkexpr(rA), mkexpr(old_xer_ca)) );
- set_XER_CA( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_ADDE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
}
break;
}
@@ -5042,14 +5191,14 @@
assign( rD, mk64lo32Uto64( binop(Iop_DivS64, dividend,
divisor) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), dividend, divisor );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), dividend, divisor );
}
} else {
assign( rD, binop(Iop_DivS32, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
/* Note:
@@ -5073,14 +5222,14 @@
assign( rD, mk64lo32Uto64( binop(Iop_DivU64, dividend,
divisor) ) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), dividend, divisor );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), dividend, divisor );
}
} else {
assign( rD, binop(Iop_DivU32, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
/* Note: ditto comment divw, for (x / 0) */
@@ -5141,17 +5290,17 @@
IRExpr *b = unop(Iop_64to32, mkexpr(rB) );
assign( rD, binop(Iop_MullS32, a, b) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLW,
- mkexpr(rD),
- unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_MULLW,
+ mkexpr(rD),
+ unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) );
}
} else {
assign( rD, unop(Iop_64to32,
binop(Iop_MullU32,
mkexpr(rA), mkexpr(rB))) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_MULLW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
}
break;
@@ -5169,8 +5318,8 @@
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA) ),
mkSzImm(ty, 1)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_NEG,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_NEG,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5182,8 +5331,8 @@
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkexpr(rB), mkexpr(rA)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBF,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBF,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5194,12 +5343,12 @@
// rD = rB - rA
assign( rD, binop( mkSzOp(ty, Iop_Sub8),
mkexpr(rB), mkexpr(rA)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFC,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFC,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFC,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFC,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
@@ -5209,17 +5358,17 @@
flag_OE ? "o" : "", flag_rC ? ".":"",
rD_addr, rA_addr, rB_addr);
// rD = (log not)rA + rB + XER[CA]
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
binop( mkSzOp(ty, Iop_Add8),
mkexpr(rB), mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
}
@@ -5236,18 +5385,18 @@
rD_addr, rA_addr);
// rD = (log not)rA + (-1) + XER[CA]
// => Just another form of subfe
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
min_one = mkSzImm(ty, (Long)-1);
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)),
binop( mkSzOp(ty, Iop_Add8),
min_one, mkexpr(old_xer_ca))) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), min_one,
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), min_one,
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), min_one );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), min_one );
}
break;
}
@@ -5263,16 +5412,16 @@
rD_addr, rA_addr);
// rD = (log not)rA + (0) + XER[CA]
// => Just another form of subfe
- assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA32(), False) );
+ assign( old_xer_ca, mkWidenFrom32(ty, getXER_CA_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8),
unop( mkSzOp(ty, Iop_Not8),
mkexpr(rA)), mkexpr(old_xer_ca)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
- mkexpr(old_xer_ca) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0),
+ mkexpr(old_xer_ca) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_SUBFE,
- mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_SUBFE,
+ mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) );
}
break;
}
@@ -5310,8 +5459,14 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_Mul64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_MULLD,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_64( PPCG_FLAG_OP_MULLD,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ /* OV is set to 1 if product isn't representable.
+ * In this case also need to set OV32 and SO to 1,
+ * i.e. copy OV to OV32 and SO.
+ */
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -5321,8 +5476,8 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_DivS64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVW,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVW,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
/* Note:
@@ -5336,8 +5491,8 @@
rD_addr, rA_addr, rB_addr);
assign( rD, binop(Iop_DivU64, mkexpr(rA), mkexpr(rB)) );
if (flag_OE) {
- set_XER_OV( ty, PPCG_FLAG_OP_DIVWU,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ set_XER_OV_OV32_SO( ty, PPCG_FLAG_OP_DIVWU,
+ mkexpr(rD), mkexpr(rA), mkexpr(rB) );
}
break;
/* Note: ditto comment divd, for (x / 0) */
@@ -5369,8 +5524,9 @@
}
if (flag_OE) {
- set_XER_OV_32( PPCG_FLAG_OP_DIVWEU,
- mkexpr(res), dividend, divisor );
+ set_XER_OV_OV32_32( PPCG_FLAG_OP_DIVWEU,
+ mkexpr(res), dividend, divisor );
+ update_SO( );
}
break;
}
@@ -5404,8 +5560,9 @@
}
if (flag_OE) {
- set_XER_OV_32( PPCG_FLAG_OP_DIVWE,
- mkexpr(res), dividend, divisor );
+ set_XER_OV_OV32_32( PPCG_FLAG_OP_DIVWE,
+ mkexpr(res), dividend, divisor );
+ update_SO( );
}
break;
}
@@ -5427,6 +5584,8 @@
if (flag_OE) {
set_XER_OV_64( PPCG_FLAG_OP_DIVDE, mkexpr( rD ),
mkexpr( rA ), mkexpr( rB ) );
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -5439,6 +5598,8 @@
if (flag_OE) {
set_XER_OV_64( PPCG_FLAG_OP_DIVDEU, mkexpr( rD ),
mkexpr( rA ), mkexpr( rB ) );
+ copy_OV_to_OV32();
+ update_SO();
}
break;
@@ -8862,11 +9023,11 @@
mkexpr(sh_amt)) ) );
assign( rA, mkWidenFrom32(ty, e_tmp, /* Signed */True) );
- set_XER_CA( ty, PPCG_FLAG_OP_SRAW,
- mkexpr(rA),
- mkWidenFrom32(ty, mkexpr(rS_lo32), True),
- mkWidenFrom32(ty, mkexpr(sh_amt), True ),
- mkWidenFrom32(ty, getXER_CA32(), True) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAW,
+ mkexpr(rA),
+ mkWidenFrom32(ty, mkexpr(rS_lo32), True),
+ mkWidenFrom32(ty, mkexpr(sh_amt), True ),
+ mkWidenFrom32(ty, getXER_CA_32(), True) );
break;
}
@@ -8884,11 +9045,11 @@
mkU8(sh_imm)) );
}
- set_XER_CA( ty, PPCG_FLAG_OP_SRAWI,
- mkexpr(rA),
- mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True),
- mkSzImm(ty, sh_imm),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAWI,
+ mkexpr(rA),
+ mkWidenFrom32(ty, mkexpr(rS_lo32), /* Syned */True),
+ mkSzImm(ty, sh_imm),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
case 0x218: // srw (Shift Right Word, PPC32 p508)
@@ -8959,9 +9120,9 @@
mkU64(63),
mkexpr(sh_amt)) ))
);
- set_XER_CA( ty, PPCG_FLAG_OP_SRAD,
- mkexpr(rA), mkexpr(rS), mkexpr(sh_amt),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRAD,
+ mkexpr(rA), mkexpr(rS), mkexpr(sh_amt),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
}
@@ -8972,11 +9133,11 @@
flag_rC ? ".":"", rA_addr, rS_addr, sh_imm);
assign( rA, binop(Iop_Sar64, getIReg(rS_addr), mkU8(sh_imm)) );
- set_XER_CA( ty, PPCG_FLAG_OP_SRADI,
- mkexpr(rA),
- getIReg(rS_addr),
- mkU64(sh_imm),
- mkWidenFrom32(ty, getXER_CA32(), /* Syned */False) );
+ set_XER_CA_CA32( ty, PPCG_FLAG_OP_SRADI,
+ mkexpr(rA),
+ getIReg(rS_addr),
+ mkU64(sh_imm),
+ mkWidenFrom32(ty, getXER_CA_32(), /* Syned */False) );
break;
case 0x21B: // srd (Shift Right DWord, PPC64 p574)
@@ -11482,6 +11643,13 @@
store( mkexpr(EA), unop( Iop_V128HIto64,
getVSReg( vRS+32 ) ) );
+ /* HW is clearing vector element 1. Don't see that in the ISA but
+ * matching the HW.
+ */
+ putVSReg( vRS+32, binop( Iop_64HLtoV128,
+ unop( Iop_V128HIto64,
+ getVSReg( vRS+32 ) ),
+ mkU64( 0 ) ) );
return True;
case 0x3:
@@ -11767,7 +11935,13 @@
case 0x247: { // mffs (Move from FPSCR, PPC32 p468)
UChar frD_addr = ifieldRegDS(theInstr);
- UInt b11to20 = IFIELD(theInstr, 11, 10);
+ UChar frB_addr = ifieldRegB(theInstr);
+ IRTemp frB = newTemp(Ity_F64);
+ UInt b11to12 = IFIELD(theInstr, 19, 2);
+ UInt b13to15 = IFIELD(theInstr, 16, 3);
+ UInt RN = IFIELD(theInstr, 11, 2);
+ UInt DRN = IFIELD(theInstr, 11, 3);
+
/* The FPSCR_DRN, FPSCR_RN and FPSCR_FPCC are all stored in
* their own 8-bit entries with distinct offsets. The FPSCR
* register is handled as two 32-bit values. We need to
@@ -11783,17 +11957,117 @@
binop( Iop_Shl32,
getFPCC(),
mkU8(63-51) ) ) );
- IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR,
- MASK_FPSCR_DRN );
+ IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR, MASK_FPSCR_DRN );
- if (b11to20 != 0) {
- vex_printf("dis_fp_scr(ppc)(instr,mffs)\n");
+ if ((b11to12 == 0) && (b13to15 == 0)) {
+ DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
+
+ } else if ((b11to12 == 0) && (b13to15 == 1)) {
+ DIP("mffsce fr%u\n", frD_addr);
+ /* Technically as of 4/5/2017 we are not tracking VE, OE, UE, ZE,
+ or XE but in case that changes in the future, do the masking. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64, fpscr_upper,
+ binop( Iop_And32, fpscr_lower,
+ mkU32( 0xFFFFFF07 ) ) ) ) );
+
+ } else if ((b11to12 == 2) && (b13to15 == 4)) {
+ IRTemp frB_int = newTemp(Ity_I64);
+
+ DIP("mffscdrn fr%u,fr%u\n", frD_addr, frB_addr);
+
+ assign( frB, getFReg(frB_addr));
+ assign( frB_int, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_DRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, mkexpr( frB_int ), MASK_FPSCR_DRN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 5)) {
+ DIP("mffscdrni fr%u,%d\n", frD_addr, DRN);
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_DRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, binop( Iop_32HLto64, mkU32( DRN ),
+ mkU32( 0 ) ), MASK_FPSCR_DRN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 6)) {
+ IRTemp frB_int = newTemp(Ity_I64);
+
+ DIP("mffscrn fr%u,fr%u\n", frD_addr,frB_addr);
+
+ assign( frB, getFReg(frB_addr));
+ assign( frB_int, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_CRN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, mkexpr( frB_int ), MASK_FPSCR_RN );
+
+ } else if ((b11to12 == 2) && (b13to15 == 7)) {
+ DIP("mffscrni fr%u,%u\n", frD_addr, RN);
+
+ /* Clear all of the FPSCR bits except for the DRN field, VE,
+ OE, UE, ZE and XE bits and write the result to the frD
+ register. Note, currently the exception bits are not tracked but
+ will mask anyway in case that changes in the future. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, mkU32(0x7), fpscr_upper ),
+ binop( Iop_And32, mkU32(0xFF), fpscr_lower ) ) ) );
+
+ /* Put new_RN bits into the FPSCR register */
+ putGST_masked( PPC_GST_FPSCR, binop( Iop_32HLto64, mkU32( 0 ),
+ mkU32( RN ) ), MASK_FPSCR_RN );
+
+ } else if ((b11to12 == 3) && (b13to15 == 0)) {
+ DIP("mffsl fr%u\n", frD_addr);
+ /* Technically as of 4/5/2017 we are not tracking VE, OE, UE, ZE,
+ XE, FR, FI, C, FL, FG, FE, FU. Also only track DRN in the upper
+ bits but in case that changes in the future we will do the
+ masking. */
+ putFReg( frD_addr,
+ unop( Iop_ReinterpI64asF64,
+ binop( Iop_32HLto64,
+ binop( Iop_And32, fpscr_upper,
+ mkU32( 0x7 ) ),
+ binop( Iop_And32, fpscr_lower,
+ mkU32( 0x7F0FF ) ) ) ) );
+ } else {
+ vex_printf("dis_fp_scr(ppc)(mff**) Unrecognized instruction.\n");
return False;
}
- DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
- putFReg( frD_addr,
- unop( Iop_ReinterpI64asF64,
- binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
break;
}
@@ -11822,11 +12096,11 @@
/* new 64 bit move variant for power 6. If L field (bit 25) is
* a one do a full 64 bit move. Note, the FPSCR is not really
* properly modeled. This instruciton only changes the value of
- * the rounding mode. The HW exception bits do not get set in
- * the simulator. 1/12/09
+ * the rounding mode bit fields RN and DRN. The HW exception bits
+ * do not get set in the simulator. 1/12/09
*/
DIP("mtfsf%s %d,fr%u (L=1)\n", flag_rC ? ".":"", FM, frB_addr);
- mask = 0xFF;
+ mask = 0x1F000000FF;
} else {
DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr);
@@ -23415,6 +23689,85 @@
break;
}
+ case 0x23: { // vmsumudm
+ DIP("vmsumudm v%d,v%d,v%d,v%d\n",
+ vD_addr, vA_addr, vB_addr, vC_addr);
+ /* This instruction takes input vectors VA, VB consisting of 2 usigned
+ 64-bit integer elements and a 128 bit unsigned input U128_C. The
+ instruction performs the following operation:
+
+ VA[0] * VB[0] -> U128_mul_result0;
+ VA[1] * VB[1] -> U128_mul_result1;
+ U128_C + U128_mul_result0 + U128_mul_result1 -> U128_partial_sum;
+ carry out and overflow is discarded.
+ */
+
+ /* The Iop_MulI128low assumes the upper 64-bits in the two input operands
+ are zero. */
+ IRTemp mul_result0 = newTemp( Ity_I128 );
+ IRTemp mul_result1 = newTemp( Ity_I128 );
+ IRTemp partial_sum_hi = newTemp( Ity_I64 );
+ IRTemp partial_sum_low = newTemp( Ity_I64 );
+ IRTemp result_hi = newTemp( Ity_I64 );
+ IRTemp result_low = newTemp( Ity_I64 );
+ IRExpr *ca_sum, *ca_result;
+
+
+ /* Do multiplications */
+ assign ( mul_result0, binop( Iop_MullU64,
+ unop( Iop_V128to64, mkexpr( vA ) ),
+ unop( Iop_V128to64, mkexpr( vB) ) ) );
+
+ assign ( mul_result1, binop( Iop_MullU64,
+ unop( Iop_V128HIto64, mkexpr( vA ) ),
+ unop( Iop_V128HIto64, mkexpr( vB) ) ) );
+
+ /* Add the two 128-bit results using 64-bit unsigned adds, calculate carry
+ from low 64-bits add into sum of upper 64-bits. Throw away carry out
+ of the upper 64-bit sum. */
+ assign ( partial_sum_low, binop( Iop_Add64,
+ unop( Iop_128to64, mkexpr( mul_result0 ) ),
+ unop( Iop_128to64, mkexpr( mul_result1 ) )
+ ) );
+
+ /* ca_sum is type U32 */
+ ca_sum = calculate_XER_CA_64 ( PPCG_FLAG_OP_ADD,
+ mkexpr(partial_sum_low ),
+ unop( Iop_128to64, mkexpr( mul_result0 ) ),
+ unop( Iop_128to64, mkexpr( mul_result1 ) ),
+ mkU64( 0 ) );
+
+ assign ( partial_sum_hi,
+ binop( Iop_Add64,
+ binop( Iop_Add64,
+ unop( Iop_128HIto64, mkexpr( mul_result0 ) ),
+ unop( Iop_128HIto64, mkexpr( mul_result1 ) ) ),
+ binop( Iop_32HLto64, mkU32( 0 ), ca_sum ) ) );
+
+ /* Now add in the value of C */
+ assign ( result_low, binop( Iop_Add64,
+ mkexpr( partial_sum_low ),
+ unop( Iop_V128to64, mkexpr( vC ) ) ) );
+
+ /* ca_result is type U32 */
+ ca_result = calculate_XER_CA_64( PPCG_FLAG_OP_ADD,
+ mkexpr( result_low ),
+ mkexpr( partial_sum_low ),
+ unop( Iop_V128to64,
+ mkexpr( vC ) ),
+ mkU64( 0 ) );
+
+ assign ( result_hi,
+ binop( Iop_Add64,
+ binop( Iop_Add64,
+ mkexpr( partial_sum_hi ),
+ unop( Iop_V128HIto64, mkexpr( vC ) ) ),
+ binop( Iop_32HLto64, mkU32( 0 ), ca_result ) ) );
+
+ putVReg( vD_addr, binop( Iop_64HLtoV128,
+ mkexpr( result_hi ), mkexpr ( result_low ) ) );
+ break;
+ }
/* Multiply-Sum */
case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
@@ -27366,6 +27719,8 @@
DisResult dres;
UInt theInstr;
IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ UInt hwcaps = archinfo->hwcaps;
+ Long delta;
Bool allow_F = False;
Bool allow_V = False;
Bool allow_FX = False;
@@ -27374,8 +27729,6 @@
Bool allow_DFP = False;
Bool allow_isa_2_07 = False;
Bool allow_isa_3_0 = False;
- UInt hwcaps = archinfo->hwcaps;
- Long delta;
/* What insn variants are we supporting today? */
if (mode64) {
@@ -27398,6 +27751,9 @@
allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0));
}
+ /* Enable writting the OV32 and CA32 bits added with ISA3.0 */
+ OV32_CA32_supported = allow_isa_3_0;
+
/* The running delta */
delta = (Long)mkSzAddr(ty, (ULong)delta64);
@@ -28116,7 +28472,8 @@
case 0x040: // mcrfs
case 0x046: // mtfsb0
case 0x086: // mtfsfi
- case 0x247: // mffs
+ case 0x247: // mffs, mmfs., mffsce, mffscdrn, mffscdrni,
+ // mffscrn, mffscrn, mffscri, mffsl
case 0x2C7: // mtfsf
// Some of the above instructions need to know more about the
// ISA level supported by the host.
@@ -28261,6 +28618,7 @@
switch (opc2) {
/* Integer Arithmetic Instructions */
case 0x10A: case 0x00A: case 0x08A: // add, addc, adde
+ case 0x0AA: // addex
case 0x0EA: case 0x0CA: case 0x1EB: // addme, addze, divw
case 0x1CB: case 0x04B: case 0x00B: // divwu, mulhw, mulhwu
case 0x0EB: case 0x068: case 0x028: // mullw, neg, subf
@@ -28643,6 +29001,7 @@
switch (opc2) {
/* AV Mult-Add, Mult-Sum */
case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladduhm
+ case 0x23: // vmsumudm
case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm
case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs
if (!allow_V) goto decode_noV;
Modified: trunk/pub/libvex_guest_ppc32.h
==============================================================================
--- trunk/pub/libvex_guest_ppc32.h (original)
+++ trunk/pub/libvex_guest_ppc32.h Wed May 3 18:24:55 2017
@@ -173,49 +173,53 @@
/* XER pieces */
/* 1164 */ UChar guest_XER_SO; /* in lsb */
/* 1165 */ UChar guest_XER_OV; /* in lsb */
- /* 1166 */ UChar guest_XER_CA; /* in lsb */
- /* 1167 */ UChar guest_XER_BC; /* all bits */
+ /* 1166 */ UChar guest_XER_OV32; /* in lsb */
+ /* 1167 */ UChar guest_XER_CA; /* in lsb */
+ /* 1168 */ UChar guest_XER_CA32; /* in lsb */
+ /* 1169 */ UChar guest_XER_BC; /* all bits */
/* CR pieces */
- /* 1168 */ UChar guest_CR0_321; /* in [3:1] */
- /* 1169 */ UChar guest_CR0_0; /* in lsb */
- /* 1170 */ UChar guest_CR1_321; /* in [3:1] */
- /* 1171 */ UChar guest_CR1_0; /* in lsb */
- /* 1172 */ UChar guest_CR2_321; /* in [3:1] */
- /* 1173 */ UChar guest_CR2_0; /* in lsb */
- /* 1174 */ UChar guest_CR3_321; /* in [3:1] */
- /* 1175 */ UChar guest_CR3_0; /* in lsb */
- /* 1176 */ UChar guest_CR4_321; /* in [3:1] */
- /* 1177 */ UChar guest_CR4_0; /* in lsb */
- /* 1178 */ UChar guest_CR5_321; /* in [3:1] */
- /* 1179 */ UChar guest_CR5_0; /* in lsb */
- /* 1180 */ UChar guest_CR6_321; /* in [3:1] */
- /* 1181 */ UChar guest_CR6_0; /* in lsb */
- /* 1182 */ UChar guest_CR7_321; /* in [3:1] */
- /* 1183 */ UChar guest_CR7_0; /* in lsb */
+ /* 1170 */ UChar guest_CR0_321; /* in [3:1] */
+ /* 1171 */ UChar guest_CR0_0; /* in lsb */
+ /* 1172 */ UChar guest_CR1_321; /* in [3:1] */
+ /* 1173 */ UChar guest_CR1_0; /* in lsb */
+ /* 1174 */ UChar guest_CR2_321; /* in [3:1] */
+ /* 1175 */ UChar guest_CR2_0; /* in lsb */
+ /* 1176 */ UChar guest_CR3_321; /* in [3:1] */
+ /* 1177 */ UChar guest_CR3_0; /* in lsb */
+ /* 1178 */ UChar guest_CR4_321; /* in [3:1] */
+ /* 1179 */ UChar guest_CR4_0; /* in lsb */
+ /* 1180 */ UChar guest_CR5_321; /* in [3:1] */
+ /* 1181 */ UChar guest_CR5_0; /* in lsb */
+ /* 1182 */ UChar guest_CR6_321; /* in [3:1] */
+ /* 1183 */ UChar guest_CR6_0; /* in lsb */
+ /* 1184 */ UChar guest_CR7_321; /* in [3:1] */
+ /* 1185 */ UChar guest_CR7_0; /* in lsb */
/* FP Status and Control Register fields. Only rounding mode fields
* and Floating-point Condition Code (FPCC) fields in the FPSCR are
* supported.
*/
- /* 1184 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
- /* 1185 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
- /* 1186 */ UChar guest_C_FPCC; // Floating-Point Result Class Descriptor
+ /* 1186 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
+ /* 1187 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
+ /* 1188 */ UChar guest_C_FPCC; // Floating-Point Result Class Descriptor
// and Floating-point Condition Code
- /* 1187 */ UChar pad2;
+ /* 1189 */ UChar pad0;
+ /* 1190 */ UChar pad1;
+ /* 1191 */ UChar pad2;
/* Vector Save/Restore Register */
- /* 1188 */ UInt guest_VRSAVE;
+ /* 1192 */ UInt guest_VRSAVE;
/* Vector Status and Control Register */
- /* 1192 */ UInt guest_VSCR;
+ /* 1196 */ UInt guest_VSCR;
/* Emulation notes */
- /* 1196 */ UInt guest_EMNOTE;
+ /* 1200 */ UInt guest_EMNOTE;
/* For icbi: record start and length of area to invalidate */
- /* 1200 */ UInt guest_CMSTART;
- /* 1204 */ UInt guest_CMLEN;
+ /* 1204 */ UInt guest_CMSTART;
+ /* 1208 */ UInt guest_CMLEN;
/* Used to record the unredirected guest address at the start of
a translation whose start has been redirected. By reading
@@ -223,34 +227,35 @@
find out what the corresponding no-redirection address was.
Note, this is only set for wrap-style redirects, not for
replace-style ones. */
- /* 1208 */ UInt guest_NRADDR;
- /* 1212 */ UInt guest_NRADDR_GPR2; /* needed by aix */
+ /* 1212 */ UInt guest_NRADDR;
+ /* 1216 */ UInt guest_NRADDR_GPR2; /* needed by aix */
/* A grows-upwards stack for hidden saves/restores of LR and R2
needed for function interception and wrapping on ppc32-aix5.
A horrible hack. REDIR_SP points to the highest live entry,
and so starts at -1. */
- /* 1216 */ UInt guest_REDIR_SP;
- /* 1220 */ UInt guest_REDIR_STACK[VEX_GUEST_PPC32_REDIR_STACK_SIZE];
+ /* 1220 */ UInt guest_REDIR_SP;
+ /* 1224 */ UInt guest_REDIR_STACK[VEX_GUEST_PPC32_REDIR_STACK_SIZE];
/* Needed for Darwin (but mandated for all guest architectures):
CIA at the last SC insn. Used when backing up to restart a
syscall that has been interrupted by a signal. */
- /* 1348 */ UInt guest_IP_AT_SYSCALL;
+ /* 134C */ UInt guest_IP_AT_SYSCALL;
/* SPRG3, which AIUI is readonly in user space. Needed for
threading on AIX. */
- /* 1352 */ UInt guest_SPRG3_RO;
- /* 1356 */ UInt padding1;
- /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
- /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
- /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
- /* 1384 */ ULong guest_PPR; // Program Priority register
- /* 1392 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
- /* 1396 */ UInt guest_PSPB; // Problem State Priority Boost register
+ /* 1356 */ UInt guest_SPRG3_RO;
+ /* 1360 */ UInt padding1;
+ /* 1364 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
+ /* 1372 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
+ /* 1380 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+ /* 1388 */ ULong guest_PPR; // Program Priority register
+ /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register
...
[truncated message content] |
|
From: Carl E. L. <ce...@us...> - 2017-05-03 16:38:07
|
On Mon, 2017-05-01 at 12:58 -0700, Carl E. Love wrote:
> On Thu, 2017-04-27 at 17:02 +0200, Julian Seward wrote:
> > The important IR bits are these:
> >
> > 100004bc: 28 4c 20 7d ldbrx r9,0,r9
> > 100004c0: 28 54 40 7d ldbrx r10,0,r10
> > // t143 is r9 after the load
> > // t166 is r10 after the load
> >
> > 100004c4: 51 48 6a 7c subf. r3,r10,r9
> > t69 = Sub64(t143,t166) // r3
> > t167 = 64to8(CmpORD64S(t69,0x0:I64))
> >
> > 100004c8: 1c 00 82 40 bne 100004e4 <main+0x84>
> > if (CmpNE32(Xor32(And32(8Uto32(t167),0x2:I32),0x2:I32),0x0:I32))
> > { PUT(1296) = 0x100004E4:I64; exit-Boring }
> >
> > My best guess is, this is a problem with the instrumentation of the
> > CmpORD64S. What that does is to compare t69 against zero, and produce
> > a 3 bit value like this:
> >
> > 8 if t69 < 0, 4 if t69 > 0, 2 if t69 == 0
> >
> > A bit strange but that's how the Power integer condition codes work.
> > And you can see that the branch condition in the IR tests for 2, meaning
> > equal.
> >
> > This is handled by doCmpORD in mc_translate.c. It special cases the case
> > where the second arg is zero, but only for the < (8) case: that bit is a
> > copy of the most significant bit of t69, so it doesn't matter if all the
> > other bits are undefined. But it doesn't special case the == (2) case, and
> > so that bit is regarded as undefined if any bit in t69 is undefined. But
> > that's too pessimistic. In fact the "is t69 == 0" question is a defined
> > "no" if we can find any bit in t69 which is nonzero and defined. The
> > general logic is explained a bit more in the comment further up, "Accurate
> > interpretation of CmpEQ/CmpNE."
> >
> > Applying that to this problem would fix it, I suspect.
>
Here is my patch with two attempts to fix the issue. I think attempt 1
is actually flawed as I think I was returning the value of the condition
code bits not if they were define. I think fix 2 is the right one, but
I still get the same error plus an additional error about a syscall with
uninitialized data.
Carl Love
>From e7ee8ff9ac7efded61e2288698e09781d37e5520 Mon Sep 17 00:00:00 2001
From: Carl Love <ce...@us...>
Date: Wed, 3 May 2017 11:33:22 -0500
Subject: [PATCH] Attempted fix for compare of uninitialized data.
---
memcheck/mc_translate.c | 148 +++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 128 insertions(+), 20 deletions(-)
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 0b91840..5f08acd 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -1108,8 +1108,13 @@ static IRAtom* doCmpORD ( MCEnv* mce,
{
Bool m64 = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD64U;
Bool syned = cmp_op == Iop_CmpORD64S || cmp_op == Iop_CmpORD32S;
+ IROp opNOT = m64 ? Iop_Not64 : Iop_Not32;
IROp opOR = m64 ? Iop_Or64 : Iop_Or32;
+ IROp opXOR = m64 ? Iop_Xor64 : Iop_Xor32;
IROp opAND = m64 ? Iop_And64 : Iop_And32;
+ IROp opEQ = m64 ? Iop_CmpEQ64 : Iop_CmpEQ32;
+ IROp opNE = m64 ? Iop_CmpNE64 : Iop_CmpNE32;
+ IROp opWIDEN = m64 ? Iop_1Uto64 : Iop_1Uto32;
IROp opSHL = m64 ? Iop_Shl64 : Iop_Shl32;
IROp opSHR = m64 ? Iop_Shr64 : Iop_Shr32;
IRType ty = m64 ? Ity_I64 : Ity_I32;
@@ -1119,6 +1124,10 @@ static IRAtom* doCmpORD ( MCEnv* mce,
IRAtom* threeLeft1 = NULL;
IRAtom* sevenLeft1 = NULL;
+ IRAtom* lt_bit = NULL;
+ IRAtom* gt_bit = NULL;
+ IRAtom* eq_bit = NULL;
+ IRAtom* tmp_bit = NULL;
tl_assert(isShadowAtom(mce,xxhash));
tl_assert(isShadowAtom(mce,yyhash));
@@ -1139,26 +1148,125 @@ static IRAtom* doCmpORD ( MCEnv* mce,
/* if yy is zero, then it must be fully defined (zero#). */
tl_assert(isZero(yyhash));
threeLeft1 = m64 ? mkU64(3<<1) : mkU32(3<<1);
- return
- binop(
- opOR,
- assignNew(
- 'V', mce,ty,
- binop(
- opAND,
- mkPCastTo(mce,ty, xxhash),
- threeLeft1
- )),
- assignNew(
- 'V', mce,ty,
- binop(
- opSHL,
- assignNew(
- 'V', mce,ty,
- binop(opSHR, xxhash, mkU8(width-1))),
- mkU8(3)
- ))
- );
+#if 0
+ /* Approach 1. What I did here was calculate the value of the eq and gt
+ bits for the comparison versus zero, i.e. set the condition code
+ result bit. We use the xxhash bits as a mask to get the valid xx bits
+ and then compare that with zero. The returned value for EQ is
+ NOT(NOT(xxhash) AND (xx)) EQ 0) return value should be 0 if the bits
+ are defined and equal to zero. The value for GT is
+ NOT(NOT(xxhash) AND (xx)) NE 0). When comparing to zero NE implies GT.
+
+ THIS APPROACH IS REALLY CALCULATING THE ACTUAL CONDITION CODE VALUES
+ NOT IF BITS ARE VALID
+
+ This approach results in 384 condigional jump/move on uninitialized
+ values instead of just 1 for the test case.
+ */
+ tmp_bit = assignNew('V', mce,ty,
+ binop(opAND,
+ assignNew('V', mce,ty,
+ unop( opNOT,
+ assignNew('V', mce,ty,
+ mkPCastTo(mce,ty, xxhash)))),
+ assignNew('V', mce,ty, xx )));
+
+ /* The comparison gives 1 for EQ which implies value is defined. But "defined" says the shadow bit must be zero so we have
+ to NOT the result.
+ */
+ eq_bit = assignNew('V', mce,ty,
+ unop(opNOT,
+ assignNew('V', mce,ty,
+ unop(opWIDEN,
+ assignNew('V', mce,Ity_I1,
+ binop(opEQ, tmp_bit,
+ (m64 ? mkU64(0) : mkU32(0))))))));
+
+ /* since we are comparing with zero, NE implies xx must be GT zero */
+ gt_bit = assignNew('V', mce,ty,
+ unop(opNOT,
+ assignNew('V', mce,ty,
+ unop(opWIDEN,
+ assignNew('V', mce,Ity_I1,
+ binop(opNE, tmp_bit,
+ (m64 ? mkU64(0) : mkU32(0))))))));
+
+ // old gt calc assignNew('V', mce,ty, binop(opXOR, lt_bit, assignNew('V', mce,ty, unop(opNOT, eq_bit))));
+ lt_bit = assignNew('V', mce,ty, binop(opSHR, xxhash, mkU8(width-1)));
+
+ return binop( opOR,
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opAND,
+ mkPCastTo(mce,ty, xxhash),
+ threeLeft1
+ )),
+ assignNew(
+ 'V', mce,ty,
+ binop( opOR,
+ assignNew(
+ 'V', mce,ty,
+ binop( opOR,
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opSHL, lt_bit,
+ mkU8(3))),
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opSHL, eq_bit,
+ mkU8(2))))),
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opSHL, gt_bit,
+ mkU8(1))))));
+#else
+ /* Approach 2 is to return 0 for EQ AND GT if there are some xx bits that
+ are defined for use in the comparison. Or in other words if everything
+ is undefined, there are no valid bits that can be compared. EQ and GT
+ shadow bits are set to 1, i.e. undefined */
+ lt_bit = assignNew('V', mce,ty, binop(opSHR, xxhash, mkU8(width-1)));
+
+ /* Comparison is 1 if TRUE (i.e. bits are all undefined).
+
+ * THIS APPROACH STILL RESULTS IN 1 CONDITIONAL JUMP/MOVE DEPENDS ON
+ * UNINITIALIZED VALUE INSTEAD PLUS "Syscall param exit_group
+ * (status) contains uninitialized byte" WHICH DID NOT OCCUR
+ * BEFORE
+ */
+ tmp_bit = assignNew('V', mce,ty,
+ unop(opWIDEN,
+ assignNew('V', mce,Ity_I1,
+ binop( opEQ, (m64 ? mkU64(0xFFFFFFFFFFFFFFFF) : mkU32(0xFFFFFFFF)),
+ assignNew('V', mce,ty,
+ mkPCastTo(mce,ty,
+ xxhash))))));
+ return binop( opOR,
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opAND,
+ mkPCastTo(mce,ty, xxhash),
+ threeLeft1
+ )),
+ assignNew(
+ 'V', mce,ty,
+ binop( opOR,
+ assignNew(
+ 'V', mce,ty,
+ binop( opAND,
+ tmp_bit,
+ (m64 ? mkU64(0x6) : mkU32(0x6)))),
+ assignNew(
+ 'V', mce,ty,
+ binop(
+ opSHL, lt_bit,
+ mkU8(3))))));
+#endif
+
} else {
/* standard interpretation */
sevenLeft1 = m64 ? mkU64(7<<1) : mkU32(7<<1);
--
2.11.0
|
|
From: <sv...@va...> - 2017-05-03 14:34:10
|
Author: petarj
Date: Wed May 3 15:34:02 2017
New Revision: 3358
Log:
mips: remove unnecessary code
After r16309, abiinfo->guest__use_fallback_LLSC is already set for Cavium,
and hence it is not necessary to check archinfo->hwcaps in VEX.
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Wed May 3 15:34:02 2017
@@ -16988,8 +16988,7 @@
case 0x30: /* LL */
DIP("ll r%u, %u(r%u)", rt, imm, rs);
LOAD_STORE_PATTERN;
- if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM
- || abiinfo->guest__use_fallback_LLSC) {
+ if (abiinfo->guest__use_fallback_LLSC) {
t2 = newTemp(ty);
assign(t2, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), True));
putLLaddr(mkexpr(t1));
@@ -17007,8 +17006,7 @@
if (mode64) {
LOAD_STORE_PATTERN;
t2 = newTemp(Ity_I64);
- if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM
- || abiinfo->guest__use_fallback_LLSC) {
+ if (abiinfo->guest__use_fallback_LLSC) {
assign(t2, load(Ity_I64, mkexpr(t1)));
putLLaddr(mkexpr(t1));
putLLdata(mkexpr(t2));
@@ -17025,8 +17023,7 @@
DIP("sc r%u, %u(r%u)", rt, imm, rs);
t2 = newTemp(Ity_I1);
LOAD_STORE_PATTERN;
- if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM
- || abiinfo->guest__use_fallback_LLSC) {
+ if (abiinfo->guest__use_fallback_LLSC) {
t3 = newTemp(Ity_I32);
assign(t2, binop(mode64 ? Iop_CmpNE64 : Iop_CmpNE32,
mkexpr(t1), getLLaddr()));
@@ -17060,8 +17057,7 @@
if (mode64) {
t2 = newTemp(Ity_I1);
LOAD_STORE_PATTERN;
- if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM
- || abiinfo->guest__use_fallback_LLSC) {
+ if (abiinfo->guest__use_fallback_LLSC) {
t3 = newTemp(Ity_I64);
assign(t2, binop(Iop_CmpNE64, mkexpr(t1), getLLaddr()));
assign(t3, getIReg(rt));
|