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Author: carll
Date: Tue May 16 21:38:35 2017
New Revision: 16391
Log:
Power PC ISA 3.0 fixes:
Fix for stxvx instruction.
Add LE support for stxv instruction
Fix for the xscmpexpdp instruction
Bugzilla: 379703
VEX commit: 3374
Modified:
trunk/NEWS
trunk/none/tests/ppc64/test_isa_3_0.c
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue May 16 21:38:35 2017
@@ -196,7 +196,8 @@
379473 MIPS: add support for rdhwr cycle counter register
379504 remove TileGX/Linux port
379838 disAMode(x86): not an addr!
-
+379703 PC ISA 3.0 fixes: stxvx, stxv, xscmpexpdp instructions, expected output
+ update.
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modified: trunk/none/tests/ppc64/test_isa_3_0.c
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0.c (original)
+++ trunk/none/tests/ppc64/test_isa_3_0.c Tue May 16 21:38:35 2017
@@ -1153,7 +1153,7 @@
SET_FPSCR_ZERO \
SET_CR_ZERO \
__asm__ __volatile__ \
- ("xscmpexpdp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb));\
+ ("xscmpexpdp %0, %1, %2"::"i"(x), "wa"(vec_xa), "wa"(vec_xb));\
GET_CR(local_cr); \
GET_FPSCR(local_fpscr);
Modified: trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE (original)
+++ trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE Tue May 16 21:38:35 2017
@@ -44906,7 +44906,58 @@
vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021f001f0000001f (00000000)
vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
-All done. Tested 90 different instructions
+vmsumudm 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => f7b24e356e824069 58f0bdcfa67462d9 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => ecb537376270175e 56efabcba56768e1 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => e4d4d336a2f52ff5 100d2393f8ab5189 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => d9d7bc3896e306ea 0e0c118ff79e5791 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 4e7190050af6b7f5 100d29fbfa468cc0 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 43747906fee48eea 0e0c17f7f93992c8 (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => e8d8bf38a4f719f5 100d2b95faad5b8d (00000000)
+vmsumudm 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => dddba83a98e4f0ea 0e0c1991f9a06195 (00000000)
+vmsumudm 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => e4d4d336a2f52ff5 100d2393f8ab5189 (00000000)
+vmsumudm 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => d9d7bc3896e306ea 0e0c118ff79e5791 (00000000)
+vmsumudm 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 16055b081916541b 100d1b0509100245 (00000000)
+vmsumudm 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0b08440a0d042b10 0e0c09010803084d (00000000)
+vmsumudm 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 190693081a972c1b 100d1b050a906245 (00000000)
+vmsumudm 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0e097c0a0e850310 0e0c09010983684d (00000000)
+vmsumudm 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 19c6e1081af7621b 100d1b050af07a45 (00000000)
+vmsumudm 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0ec9ca0a0ee53910 0e0c090109e3804d (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 4e7190050af6b7f5 100d29fbfa468cc0 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 43747906fee48eea 0e0c17f7f93992c8 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 190693081a972c1b 100d1b050a906245 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0e097c0a0e850310 0e0c09010983684d (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 1e47cb081d38041b 100d1b050d30c245 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 134ab40a1125db10 0e0c09010c23c84d (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 1f9819081de03a1b 100d1b050dd8da45 (00000000)
+vmsumudm 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 149b020a11ce1110 0e0c09010ccbe04d (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 12021a0817141317 100d1b05070f0205 (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0705030a0b01ea0c 0e0c09010602080d (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => e8d8bf38a4f719f5 100d2b95faad5b8d (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => dddba83a98e4f0ea 0e0c1991f9a06195 (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 19c6e1081af7621b 100d1b050af07a45 (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0ec9ca0a0ee53910 0e0c090109e3804d (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 1f9819081de03a1b 100d1b050dd8da45 (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 149b020a11ce1110 0e0c09010ccbe04d (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 210c67081e9a701b 100d1b050e92f245 (00000000)
+vmsumudm 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 160f500a12884710 0e0c09010d85f84d (00000000)
+
+All done. Tested 91 different instructions
ppc vector inserts:
Test instruction group [ppc vector inserts]
vinsertb 0102010201020102 0102030405060708 [0] (into zeros) => 0200000000000000 0000000000000000
@@ -45443,7 +45494,7 @@
xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 00000000b0a09080 0000000000000000
xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => 00000000b0a09080 0000000000000000
-All done. Tested 100 different instructions
+All done. Tested 101 different instructions
ppc vector extract from vector to reg:
Test instruction group [ppc vector extract from vector to reg]
vextublx 0000000000000000 0000000000000000 0 => 0
@@ -46412,7 +46463,7 @@
vextuwrx 00101f0800101f10 00101f0000101f02 14 => 0
vextuwrx 00101f0800101f10 00101f0000101f02 15 => 0
-All done. Tested 106 different instructions
+All done. Tested 107 different instructions
ppc vector count leading/trailing bytes:
Test instruction group [ppc vector count leading/trailing bytes]
vclzlsbb 0000000000000000 0000000000000000 0 => 16
@@ -46437,7 +46488,7 @@
vctzlsbb 00001f0800001f10 00001f0000001f02 0 => 1
vctzlsbb 00101f0800101f10 00101f0000101f02 0 => 1
-All done. Tested 108 different instructions
+All done. Tested 109 different instructions
ppc vector load/store:
Test instruction group [ppc vector load/store]
lxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
@@ -52460,129 +52511,129 @@
stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
-All done. Tested 128 different instructions
+All done. Tested 129 different instructions
ppc vector load/store:
Test instruction group [ppc vector load/store]
lxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
-lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
-lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
-lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
-lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
@@ -52960,113 +53011,113 @@
stxvx 0000000000000000 0000000000000000 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
0000000000000000 0000000000000000 [ 0000000000000000 0000000000000000 0000000000000000 ffffffffffffffff ]
stxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0102030405060708 0102010201020102 [ 0102010201020102 0102030405060708 5555555555555555 0000000000000000 ]
+ 0102030405060708 0102010201020102 [ 0102030405060708 0102010201020102 5555555555555555 0000000000000000 ]
stxvx 0102030405060708 0102010201020102 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0000000000000000 ffffffffffffffff ]
+ 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0000000000000000 ffffffffffffffff ]
stxvx 0102010201020102 0102030405060708 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0102030405060708 0102010201020102 [ 0102010201020102 0102030405060708 ffffffffffffffff 0001020304050607 ]
+ 0102030405060708 0102010201020102 [ 0102030405060708 0102010201020102 ffffffffffffffff 0001020304050607 ]
stxvx 0102030405060708 0102010201020102 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0001020304050607 5555555555555555 ]
+ 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0001020304050607 5555555555555555 ]
stxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0102030405060708 0102010201020102 [ 0102010201020102 0102030405060708 5555555555555555 0000000000000000 ]
+ 0102030405060708 0102010201020102 [ 0102030405060708 0102010201020102 5555555555555555 0000000000000000 ]
stxvx 0102030405060708 0102010201020102 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0102010201020102 0102030405060708 [ 0102030405060708 0102010201020102 0000000000000000 ffffffffffffffff ]
+ 0102010201020102 0102030405060708 [ 0102010201020102 0102030405060708 0000000000000000 ffffffffffffffff ]
stxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0011223344556677 8899aabbccddeeff [ 8899aabbccddeeff 0011223344556677 5555555555555555 0000000000000000 ]
+ 0011223344556677 8899aabbccddeeff [ 0011223344556677 8899aabbccddeeff 5555555555555555 0000000000000000 ]
stxvx 0011223344556677 8899aabbccddeeff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0000000000000000 ffffffffffffffff ]
+ 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0000000000000000 ffffffffffffffff ]
stxvx 8899aabbccddeeff 0011223344556677 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0011223344556677 8899aabbccddeeff [ 8899aabbccddeeff 0011223344556677 ffffffffffffffff 0001020304050607 ]
+ 0011223344556677 8899aabbccddeeff [ 0011223344556677 8899aabbccddeeff ffffffffffffffff 0001020304050607 ]
stxvx 0011223344556677 8899aabbccddeeff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0001020304050607 5555555555555555 ]
+ 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0001020304050607 5555555555555555 ]
stxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0011223344556677 8899aabbccddeeff [ 8899aabbccddeeff 0011223344556677 5555555555555555 0000000000000000 ]
+ 0011223344556677 8899aabbccddeeff [ 0011223344556677 8899aabbccddeeff 5555555555555555 0000000000000000 ]
stxvx 0011223344556677 8899aabbccddeeff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 8899aabbccddeeff 0011223344556677 [ 0011223344556677 8899aabbccddeeff 0000000000000000 ffffffffffffffff ]
+ 8899aabbccddeeff 0011223344556677 [ 8899aabbccddeeff 0011223344556677 0000000000000000 ffffffffffffffff ]
stxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- f0e0d0c0b0a09080 7060504030201000 [ 7060504030201000 f0e0d0c0b0a09080 5555555555555555 0000000000000000 ]
+ f0e0d0c0b0a09080 7060504030201000 [ f0e0d0c0b0a09080 7060504030201000 5555555555555555 0000000000000000 ]
stxvx f0e0d0c0b0a09080 7060504030201000 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0000000000000000 ffffffffffffffff ]
+ 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0000000000000000 ffffffffffffffff ]
stxvx 7060504030201000 f0e0d0c0b0a09080 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- f0e0d0c0b0a09080 7060504030201000 [ 7060504030201000 f0e0d0c0b0a09080 ffffffffffffffff 0001020304050607 ]
+ f0e0d0c0b0a09080 7060504030201000 [ f0e0d0c0b0a09080 7060504030201000 ffffffffffffffff 0001020304050607 ]
stxvx f0e0d0c0b0a09080 7060504030201000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0001020304050607 5555555555555555 ]
+ 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0001020304050607 5555555555555555 ]
stxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- f0e0d0c0b0a09080 7060504030201000 [ 7060504030201000 f0e0d0c0b0a09080 5555555555555555 0000000000000000 ]
+ f0e0d0c0b0a09080 7060504030201000 [ f0e0d0c0b0a09080 7060504030201000 5555555555555555 0000000000000000 ]
stxvx f0e0d0c0b0a09080 7060504030201000 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 7060504030201000 f0e0d0c0b0a09080 [ f0e0d0c0b0a09080 7060504030201000 0000000000000000 ffffffffffffffff ]
+ 7060504030201000 f0e0d0c0b0a09080 [ 7060504030201000 f0e0d0c0b0a09080 0000000000000000 ffffffffffffffff ]
stxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0000100000001002 0000100800001010 [ 0000100800001010 0000100000001002 5555555555555555 0000000000000000 ]
+ 0000100000001002 0000100800001010 [ 0000100000001002 0000100800001010 5555555555555555 0000000000000000 ]
stxvx 0000100000001002 0000100800001010 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0000000000000000 ffffffffffffffff ]
+ 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0000000000000000 ffffffffffffffff ]
stxvx 0000100800001010 0000100000001002 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0000100000001002 0000100800001010 [ 0000100800001010 0000100000001002 ffffffffffffffff 0001020304050607 ]
+ 0000100000001002 0000100800001010 [ 0000100000001002 0000100800001010 ffffffffffffffff 0001020304050607 ]
stxvx 0000100000001002 0000100800001010 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0001020304050607 5555555555555555 ]
+ 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0001020304050607 5555555555555555 ]
stxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0000100000001002 0000100800001010 [ 0000100800001010 0000100000001002 5555555555555555 0000000000000000 ]
+ 0000100000001002 0000100800001010 [ 0000100000001002 0000100800001010 5555555555555555 0000000000000000 ]
stxvx 0000100000001002 0000100800001010 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0000100800001010 0000100000001002 [ 0000100000001002 0000100800001010 0000000000000000 ffffffffffffffff ]
+ 0000100800001010 0000100000001002 [ 0000100800001010 0000100000001002 0000000000000000 ffffffffffffffff ]
stxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0010100000101002 0010100800101010 [ 0010100800101010 0010100000101002 5555555555555555 0000000000000000 ]
+ 0010100000101002 0010100800101010 [ 0010100000101002 0010100800101010 5555555555555555 0000000000000000 ]
stxvx 0010100000101002 0010100800101010 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0000000000000000 ffffffffffffffff ]
+ 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0000000000000000 ffffffffffffffff ]
stxvx 0010100800101010 0010100000101002 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 0010100000101002 0010100800101010 [ 0010100800101010 0010100000101002 ffffffffffffffff 0001020304050607 ]
+ 0010100000101002 0010100800101010 [ 0010100000101002 0010100800101010 ffffffffffffffff 0001020304050607 ]
stxvx 0010100000101002 0010100800101010 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0001020304050607 5555555555555555 ]
+ 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0001020304050607 5555555555555555 ]
stxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 0010100000101002 0010100800101010 [ 0010100800101010 0010100000101002 5555555555555555 0000000000000000 ]
+ 0010100000101002 0010100800101010 [ 0010100000101002 0010100800101010 5555555555555555 0000000000000000 ]
stxvx 0010100000101002 0010100800101010 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 0010100800101010 0010100000101002 [ 0010100000101002 0010100800101010 0000000000000000 ffffffffffffffff ]
+ 0010100800101010 0010100000101002 [ 0010100800101010 0010100000101002 0000000000000000 ffffffffffffffff ]
stxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00001c0000001c02 00001c0800001c10 [ 00001c0800001c10 00001c0000001c02 5555555555555555 0000000000000000 ]
+ 00001c0000001c02 00001c0800001c10 [ 00001c0000001c02 00001c0800001c10 5555555555555555 0000000000000000 ]
stxvx 00001c0000001c02 00001c0800001c10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0000000000000000 ffffffffffffffff ]
+ 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0000000000000000 ffffffffffffffff ]
stxvx 00001c0800001c10 00001c0000001c02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 00001c0000001c02 00001c0800001c10 [ 00001c0800001c10 00001c0000001c02 ffffffffffffffff 0001020304050607 ]
+ 00001c0000001c02 00001c0800001c10 [ 00001c0000001c02 00001c0800001c10 ffffffffffffffff 0001020304050607 ]
stxvx 00001c0000001c02 00001c0800001c10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0001020304050607 5555555555555555 ]
+ 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0001020304050607 5555555555555555 ]
stxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00001c0000001c02 00001c0800001c10 [ 00001c0800001c10 00001c0000001c02 5555555555555555 0000000000000000 ]
+ 00001c0000001c02 00001c0800001c10 [ 00001c0000001c02 00001c0800001c10 5555555555555555 0000000000000000 ]
stxvx 00001c0000001c02 00001c0800001c10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00001c0800001c10 00001c0000001c02 [ 00001c0000001c02 00001c0800001c10 0000000000000000 ffffffffffffffff ]
+ 00001c0800001c10 00001c0000001c02 [ 00001c0800001c10 00001c0000001c02 0000000000000000 ffffffffffffffff ]
stxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00101c0000101c02 00101c0800101c10 [ 00101c0800101c10 00101c0000101c02 5555555555555555 0000000000000000 ]
+ 00101c0000101c02 00101c0800101c10 [ 00101c0000101c02 00101c0800101c10 5555555555555555 0000000000000000 ]
stxvx 00101c0000101c02 00101c0800101c10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0000000000000000 ffffffffffffffff ]
+ 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0000000000000000 ffffffffffffffff ]
stxvx 00101c0800101c10 00101c0000101c02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 00101c0000101c02 00101c0800101c10 [ 00101c0800101c10 00101c0000101c02 ffffffffffffffff 0001020304050607 ]
+ 00101c0000101c02 00101c0800101c10 [ 00101c0000101c02 00101c0800101c10 ffffffffffffffff 0001020304050607 ]
stxvx 00101c0000101c02 00101c0800101c10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0001020304050607 5555555555555555 ]
+ 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0001020304050607 5555555555555555 ]
stxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00101c0000101c02 00101c0800101c10 [ 00101c0800101c10 00101c0000101c02 5555555555555555 0000000000000000 ]
+ 00101c0000101c02 00101c0800101c10 [ 00101c0000101c02 00101c0800101c10 5555555555555555 0000000000000000 ]
stxvx 00101c0000101c02 00101c0800101c10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00101c0800101c10 00101c0000101c02 [ 00101c0000101c02 00101c0800101c10 0000000000000000 ffffffffffffffff ]
+ 00101c0800101c10 00101c0000101c02 [ 00101c0800101c10 00101c0000101c02 0000000000000000 ffffffffffffffff ]
stxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00001f0000001f02 00001f0800001f10 [ 00001f0800001f10 00001f0000001f02 5555555555555555 0000000000000000 ]
+ 00001f0000001f02 00001f0800001f10 [ 00001f0000001f02 00001f0800001f10 5555555555555555 0000000000000000 ]
stxvx 00001f0000001f02 00001f0800001f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ]
+ 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0000000000000000 ffffffffffffffff ]
stxvx 00001f0800001f10 00001f0000001f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 00001f0000001f02 00001f0800001f10 [ 00001f0800001f10 00001f0000001f02 ffffffffffffffff 0001020304050607 ]
+ 00001f0000001f02 00001f0800001f10 [ 00001f0000001f02 00001f0800001f10 ffffffffffffffff 0001020304050607 ]
stxvx 00001f0000001f02 00001f0800001f10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0001020304050607 5555555555555555 ]
+ 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0001020304050607 5555555555555555 ]
stxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00001f0000001f02 00001f0800001f10 [ 00001f0800001f10 00001f0000001f02 5555555555555555 0000000000000000 ]
+ 00001f0000001f02 00001f0800001f10 [ 00001f0000001f02 00001f0800001f10 5555555555555555 0000000000000000 ]
stxvx 00001f0000001f02 00001f0800001f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ]
+ 00001f0800001f10 00001f0000001f02 [ 00001f0800001f10 00001f0000001f02 0000000000000000 ffffffffffffffff ]
stxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00101f0000101f02 00101f0800101f10 [ 00101f0800101f10 00101f0000101f02 5555555555555555 0000000000000000 ]
+ 00101f0000101f02 00101f0800101f10 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ]
stxvx 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ]
+ 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0000000000000000 ffffffffffffffff ]
stxvx 00101f0800101f10 00101f0000101f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
- 00101f0000101f02 00101f0800101f10 [ 00101f0800101f10 00101f0000101f02 ffffffffffffffff 0001020304050607 ]
+ 00101f0000101f02 00101f0800101f10 [ 00101f0000101f02 00101f0800101f10 ffffffffffffffff 0001020304050607 ]
stxvx 00101f0000101f02 00101f0800101f10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
- 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0001020304050607 5555555555555555 ]
+ 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0001020304050607 5555555555555555 ]
stxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
- 00101f0000101f02 00101f0800101f10 [ 00101f0800101f10 00101f0000101f02 5555555555555555 0000000000000000 ]
+ 00101f0000101f02 00101f0800101f10 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ]
stxvx 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
- 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ]
+ 00101f0800101f10 00101f0000101f02 [ 00101f0800101f10 00101f0000101f02 0000000000000000 ffffffffffffffff ]
stxvh8x 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
0000000000000000 0000000000000000 [ 0000000000000000 0000000000000000 5555555555555555 0000000000000000 ]
@@ -53310,977 +53361,978 @@
stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ]
-All done. Tested 135 different instructions
+All done. Tested 136 different instructions
ppc vector scalar compare exponents doubles:
Test instruction group [ppc vector scalar compare exponents doubles]
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
-xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FU(SO)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FL-Normalized (LT)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000...
[truncated message content] |
|
From: <sv...@va...> - 2017-05-16 20:35:38
|
Author: carll
Date: Tue May 16 21:35:28 2017
New Revision: 3374
Log:
Power PC ISA 3.0 fixes:
Fix for stxvx instruction.
Add LE support for stxv instruction
Fix for the xscmpexpdp instruction
Bugzilla: 379703
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue May 16 21:35:28 2017
@@ -11584,7 +11584,7 @@
word[0] = newTemp(Ity_I64);
word[1] = newTemp(Ity_I64);
- DS = IFIELD( theInstr, 4, 11); // DQ in the instruction definition
+ DS = IFIELD( theInstr, 4, 12); // DQ in the instruction definition
assign( EA, ea_rAor0_simm( rA_addr, DS<<4 ) );
if ( IFIELD( theInstr, 0, 3) == 1) {
@@ -18560,16 +18560,19 @@
switch ( opc2 ) {
case 0x0ec: // xscmpexpdp (VSX Scalar Compare Exponents Double-Precision)
{
+ /* Compare 64-bit data, 128-bit layout:
+ src1[0:63] is double word, src1[64:127] is unused
+ src2[0:63] is double word, src2[64:127] is unused
+ */
IRExpr *bit4, *bit5, *bit6, *bit7;
UInt BF = IFIELD( theInstr, 23, 3 );
IRTemp eq_lt_gt = newTemp( Ity_I32 );
IRTemp CC = newTemp( Ity_I32 );
IRTemp vA_hi = newTemp( Ity_I64 );
IRTemp vB_hi = newTemp( Ity_I64 );
- UChar rA_addr = ifieldRegA(theInstr);
- UChar rB_addr = ifieldRegB(theInstr);
+ IRExpr *mask = mkU64( 0x7FF0000000000000 );
- DIP("xscmpexpdp %d,v%d,v%d\n", BF, rA_addr, rB_addr);
+ DIP("xscmpexpdp %d,v%d,v%d\n", BF, XA, XB);
assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) );
assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) );
@@ -18577,31 +18580,31 @@
/* A exp < B exp */
bit4 = binop( Iop_CmpLT64U,
binop( Iop_And64,
- mkexpr( vA_hi ),
- mkU64( 0x7FFF0000000000 ) ),
+ mkexpr( vA_hi ),
+ mask ),
binop( Iop_And64,
mkexpr( vB_hi ),
- mkU64( 0x7FFF0000000000 ) ) );
+ mask ) );
/* A exp > B exp */
bit5 = binop( Iop_CmpLT64U,
binop( Iop_And64,
mkexpr( vB_hi ),
- mkU64( 0x7FFF00000000000 ) ),
+ mask ),
binop( Iop_And64,
mkexpr( vA_hi ),
- mkU64( 0x7FFF00000000000 ) ) );
+ mask ) );
/* test equal */
bit6 = binop( Iop_CmpEQ64,
binop( Iop_And64,
mkexpr( vA_hi ),
- mkU64( 0x7FFF00000000000 ) ),
+ mask ),
binop( Iop_And64,
- mkexpr( vB_hi ),
- mkU64( 0x7FFF00000000000 ) ) );
+ mkexpr( vB_hi ),
+ mask ) );
/* exp A or exp B is NaN */
- bit7 = mkOR1( is_NaN( Ity_V128, vA ),
- is_NaN( Ity_V128, vB ) );
+ bit7 = mkOR1( is_NaN( Ity_I64, vA_hi ),
+ is_NaN( Ity_I64, vB_hi ) );
assign( eq_lt_gt, binop( Iop_Or32,
binop( Iop_Shl32,
@@ -18616,7 +18619,7 @@
mkU8( 1 ) ) ) ) );
assign(CC, binop( Iop_Or32,
mkexpr( eq_lt_gt ) ,
- unop( Iop_1Uto32, bit7 ) ) );
+ unop( Iop_1Sto32, bit7 ) ) );
putGST_field( PPC_GST_CR, mkexpr( CC ), BF );
putFPCC( mkexpr( CC ) );
@@ -20634,24 +20637,45 @@
unop( Iop_V128to64, mkexpr( vS ) ),
mkU64( 0xFFFFFFFF ) ) );
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
+ if (host_endness == VexEndnessBE) {
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
+ } else {
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word3 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word0 ) ) );
+ }
break;
}
|
|
From: <sv...@va...> - 2017-05-16 16:31:23
|
Author: petarj
Date: Tue May 16 17:31:16 2017
New Revision: 16390
Log:
mips64: add a workaround for Cavium CPUs to support mips32r1-r2-mips64r1
Linux kernel incorrectly shows that MIPS Cavium CPUs do not support mips32r1,
mips32r2 and mips64r1. This is due to incorrect defines in
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
that affect show_cpuinfo() function.
Until that is changed in Linux kernel, we need a workaround in Valgrind, so
all supported ISAs can be executed correctly.
Modified:
trunk/coregrind/m_machine.c
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Tue May 16 17:31:16 2017
@@ -726,6 +726,18 @@
vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R2;
if (VG_(strstr) (isa, "mips64r6") != NULL)
vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R6;
+
+ /*
+ * TODO(petarj): Remove this Cavium workaround once Linux kernel folks
+ * decide to change incorrect settings in
+ * mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h.
+ * The current settings show mips32r1, mips32r2 and mips64r1 as
+ * unsupported ISAs by Cavium MIPS CPUs.
+ */
+ if (VEX_MIPS_COMP_ID(vai.hwcaps) == VEX_PRID_COMP_CAVIUM) {
+ vai.hwcaps |= VEX_MIPS_CPU_ISA_M32R1 | VEX_MIPS_CPU_ISA_M32R2 |
+ VEX_MIPS_CPU_ISA_M64R1;
+ }
} else {
/*
* Kernel does not provide information about supported ISAs.
|
|
From: <sv...@va...> - 2017-05-16 15:21:42
|
Author: petarj
Date: Tue May 16 16:21:35 2017
New Revision: 3373
Log:
mips: rewrite parts of mips_dirtyhelper_rdhwr
The idea behind this change is to be less dependent on build-flags, and
more dependent on runtime environment.
So, if the code is compiled for mips32r1, it should be able to execute
mips32r2 code if the platforms supports it.
Modified:
trunk/priv/guest_mips_defs.h
trunk/priv/guest_mips_helpers.c
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_defs.h
==============================================================================
--- trunk/priv/guest_mips_defs.h (original)
+++ trunk/priv/guest_mips_defs.h Tue May 16 16:21:35 2017
@@ -100,9 +100,7 @@
#define MIPS_IEND Iend_BE
#endif
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
-extern HWord mips_dirtyhelper_rdhwr ( UInt rt, UInt rd );
-#endif
+extern HWord mips_dirtyhelper_rdhwr ( UInt rd );
/* Calculate FCSR in fp32 mode. */
extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs,
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Tue May 16 16:21:35 2017
@@ -424,29 +424,35 @@
}
};
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
-HWord mips_dirtyhelper_rdhwr ( UInt rt, UInt rd )
+#define ASM_VOLATILE_RDHWR(opcode) \
+ __asm__ __volatile__(".word 0x7C02003B | "#opcode" << 11 \n\t" \
+ : "+r" (x) : : \
+ )
+
+HWord mips_dirtyhelper_rdhwr ( UInt rd )
{
- HWord x = 0;
+#if defined(__mips__)
+ register HWord x __asm__("v0") = 0;
+
switch (rd) {
case 0: /* x = CPUNum() */
- __asm__ __volatile__("rdhwr %0, $0\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(0); /* rdhwr v0, $0 */
break;
case 1: /* x = SYNCI_Step() */
- __asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(1); /* rdhwr v0, $1 */
break;
case 2: /* x = CC() */
- __asm__ __volatile__("rdhwr %0, $2\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(2); /* rdhwr v0, $2 */
break;
case 3: /* x = CCRes() */
- __asm__ __volatile__("rdhwr %0, $3\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(3); /* rdhwr v0, $3 */
break;
case 31: /* x = CVMX_get_cycles() */
- __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+ ASM_VOLATILE_RDHWR(31); /* rdhwr v0, $31 */
break;
default:
@@ -454,8 +460,10 @@
break;
}
return x;
-}
+#else
+ return 0;
#endif
+}
#define ASM_VOLATILE_UNARY32(inst) \
__asm__ volatile(".set push" "\n\t" \
@@ -648,7 +656,8 @@
flt_op inst )
{
UInt ret = 0;
-#if defined(__mips__)
+#if defined(__mips__) && ((__mips == 64) || \
+ (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
#if defined(VGA_mips32)
VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
#else
@@ -699,8 +708,6 @@
case ROUNDWS:
ASM_VOLATILE_UNARY64(round.w.s)
break;
-#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \
- || (__mips == 64)
case CEILLS:
ASM_VOLATILE_UNARY64(ceil.l.s)
break;
@@ -737,7 +744,6 @@
case TRUNCLD:
ASM_VOLATILE_UNARY64(trunc.l.d)
break;
-#endif
case ADDS:
ASM_VOLATILE_BINARY64(add.s)
break;
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Tue May 16 16:21:35 2017
@@ -15091,29 +15091,31 @@
goto decode_failure;;
}
break;
- case 0x3B: { /* RDHWR */
+ case 0x3B: /* RDHWR */
DIP("rdhwr r%u, r%u", rt, rd);
+ if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps) ||
+ (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_BROADCOM)) {
if (rd == 29) {
putIReg(rt, getULR());
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
} else if (rd <= 3
|| (rd == 31
&& VEX_MIPS_COMP_ID(archinfo->hwcaps)
== VEX_PRID_COMP_CAVIUM)) {
- IRExpr** args = mkIRExprVec_2 (mkU32(rt), mkU32(rd));
+ IRExpr** arg = mkIRExprVec_1(mkU32(rd));
IRTemp val = newTemp(ty);
IRDirty *d = unsafeIRDirty_1_N(val,
0,
"mips_dirtyhelper_rdhwr",
&mips_dirtyhelper_rdhwr,
- args);
+ arg);
stmt(IRStmt_Dirty(d));
putIReg(rt, mkexpr(val));
-#endif
} else
goto decode_failure;
- break;
+ } else {
+ ILLEGAL_INSTRUCTON;
}
+ break;
case 0x04: /* INS */
msb = get_msb(cins);
lsb = get_lsb(cins);
@@ -17299,6 +17301,8 @@
mode64 = guest_arch != VexArchMIPS32;
fp_mode64 = abiinfo->guest_mips_fp_mode64;
+ vassert(VEX_MIPS_HOST_FP_MODE(archinfo->hwcaps) >= fp_mode64);
+
guest_code = guest_code_IN;
irsb = irsb_IN;
host_endness = host_endness_IN;
|
|
From: <sv...@va...> - 2017-05-16 15:17:19
|
Author: mjw
Date: Tue May 16 16:17:13 2017
New Revision: 16389
Log:
Add include/vgversion.h to clean-local.
It is a generated file that needs to be cleaned up.
Modified:
trunk/Makefile.am
Modified: trunk/Makefile.am
==============================================================================
--- trunk/Makefile.am (original)
+++ trunk/Makefile.am Tue May 16 16:17:13 2017
@@ -128,7 +128,7 @@
ln -s ../default.supp $(inplacedir)
clean-local:
- rm -rf $(inplacedir)
+ rm -rf $(inplacedir) include/vgversion.h
# Need config.h in the installed tree, since some files depend on it
pkginclude_HEADERS = config.h
|
|
From: <sv...@va...> - 2017-05-16 15:17:18
|
Author: mjw
Date: Tue May 16 16:17:12 2017
New Revision: 16388
Log:
Add dlopen_lib.h to drd/tests/Makefile.am noinst_HEADERS.
It is used in drd/tests/dlopen_lib.c and drd/tests/dlopen_main.c.
Modified:
trunk/drd/tests/Makefile.am
Modified: trunk/drd/tests/Makefile.am
==============================================================================
--- trunk/drd/tests/Makefile.am (original)
+++ trunk/drd/tests/Makefile.am Tue May 16 16:17:12 2017
@@ -19,7 +19,8 @@
noinst_HEADERS = \
tsan_thread_wrappers_pthread.h \
- unified_annotations.h
+ unified_annotations.h \
+ dlopen_lib.h
EXTRA_DIST = \
annotate_barrier.stderr.exp \
|
|
From: <sv...@va...> - 2017-05-16 15:17:18
|
Author: mjw
Date: Tue May 16 16:17:10 2017
New Revision: 16387
Log:
Call $(top_srcdir)/auxprogs/make_or_upd_vgversion_h.
Fixes srcdir != builddir builds.
Modified:
trunk/Makefile.am
Modified: trunk/Makefile.am
==============================================================================
--- trunk/Makefile.am (original)
+++ trunk/Makefile.am Tue May 16 16:17:10 2017
@@ -135,4 +135,4 @@
# vgversion.h defines accurate versions to report with -v --version
vgversion.h:
- auxprogs/make_or_upd_vgversion_h
+ $(top_srcdir)/auxprogs/make_or_upd_vgversion_h
|
|
From: <sv...@va...> - 2017-05-16 09:31:00
|
Author: sewardj
Date: Tue May 16 10:30:50 2017
New Revision: 16386
Log:
Redo rev 16384 to use the "house" conditionalisation scheme. Pertains to
BZ#368529.
Modified:
trunk/coregrind/m_main.c
Modified: trunk/coregrind/m_main.c
==============================================================================
--- trunk/coregrind/m_main.c (original)
+++ trunk/coregrind/m_main.c Tue May 16 10:30:50 2017
@@ -2422,6 +2422,7 @@
libgcc which boil down to an abort or raise, that's usually defined
in libc. Instead, define them here. */
#if defined(VGP_arm_linux)
+
void raise(void);
void raise(void){
VG_(printf)("Something called raise().\n");
@@ -2440,7 +2441,15 @@
vg_assert(0);
}
-#if defined(__ANDROID__)
+#endif /* defined(VGP_arm_linux) */
+
+/* Some Android helpers. See bug 368529. */
+#if defined(__clang__) \
+ && (defined(VGPV_arm_linux_android) \
+ || defined(VGPV_x86_linux_android) \
+ || defined(VGPV_mips32_linux_android) \
+ || defined(VGPV_arm64_linux_android))
+
/* Replace __aeabi_memcpy* functions with vgPlain_memcpy. */
void *__aeabi_memcpy(void *dest, const void *src, SizeT n);
void *__aeabi_memcpy(void *dest, const void *src, SizeT n)
@@ -2478,8 +2487,7 @@
{
return VG_(memset)(dest, 0, n);
}
-#endif /* defined(__ANDROID__) */
-#endif /* defined(VGP_arm_linux) */
+#endif /* clang and android, basically */
/* ---------------- Requirement 2 ---------------- */
|
|
From: <sv...@va...> - 2017-05-16 08:54:38
|
Author: iraisr
Date: Tue May 16 09:54:31 2017
New Revision: 16385
Log:
More bug squashing! Yay!
Modified:
trunk/docs/internals/3_12_BUGSTATUS.txt
Modified: trunk/docs/internals/3_12_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_12_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_12_BUGSTATUS.txt Tue May 16 09:54:31 2017
@@ -300,10 +300,6 @@
364533 Process terminating with default action of signal 4 (SIGILL): dumping
core, : at 0x4000E7C: ??? (in /lib/ld-uClibc.so.0)
-(carried over)
-368529 Android arm target link error, missing atexit and pthread_atfork
- (should take patch)
-
374814 VALGRIND INTERNAL ERROR: signal 11 (SIGSEGV) - exiting
possibly TLS related
@@ -516,10 +512,6 @@
364279 False "Uninitialized" on atomic_compare_exchange
*
-368529 Android arm target link error, missing atexit and pthread_atfork
- [has patch, should take]
-
-*
368791 unhandled syscall: 167 (swapon, amd64-linux)
[hoist mips64-linux specific wrapper as a linux specific one]
|
|
From: <sv...@va...> - 2017-05-16 08:50:55
|
Author: iraisr
Date: Tue May 16 09:50:48 2017
New Revision: 16384
Log:
Implement required stubs for Android on arm when built with clang/llvm.
Fixes BZ#368529
Slightly modified patch by: Elliott Hughes <en...@go...>
Modified:
trunk/NEWS
trunk/coregrind/m_main.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue May 16 09:50:48 2017
@@ -117,6 +117,7 @@
362223 assertion failed when .valgrindrc is a directory instead of a file
367543 bt/btc/btr/bts x86/x86_64 instructions are poorly-handled wrt flags
367942 Segfault vgPlain_do_sys_sigaction (m_signals.c:1138)
+368529 Android arm target link error, missing atexit and pthread_atfork
368863 WARNING: unhandled arm64-linux syscall: 100 (get_robust_list)
368865 WARNING: unhandled arm64-linux syscall: 272 (kcmp)
368868 disInstr(arm64): unhandled instruction 0xD53BE000 = cntfrq_el0 (ARMv8)
Modified: trunk/coregrind/m_main.c
==============================================================================
--- trunk/coregrind/m_main.c (original)
+++ trunk/coregrind/m_main.c Tue May 16 09:50:48 2017
@@ -2439,7 +2439,47 @@
VG_(printf)("Something called __aeabi_unwind_cpp_pr1()\n");
vg_assert(0);
}
-#endif
+
+#if defined(__ANDROID__)
+/* Replace __aeabi_memcpy* functions with vgPlain_memcpy. */
+void *__aeabi_memcpy(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy(void *dest, const void *src, SizeT n)
+{
+ return VG_(memcpy)(dest, src, n);
+}
+
+void *__aeabi_memcpy4(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy4(void *dest, const void *src, SizeT n)
+{
+ return VG_(memcpy)(dest, src, n);
+}
+
+void *__aeabi_memcpy8(void *dest, const void *src, SizeT n);
+void *__aeabi_memcpy8(void *dest, const void *src, SizeT n)
+{
+ return VG_(memcpy)(dest, src, n);
+}
+
+/* Replace __aeabi_memclr* functions with vgPlain_memset. */
+void *__aeabi_memclr(void *dest, SizeT n);
+void *__aeabi_memclr(void *dest, SizeT n)
+{
+ return VG_(memset)(dest, 0, n);
+}
+
+void *__aeabi_memclr4(void *dest, SizeT n);
+void *__aeabi_memclr4(void *dest, SizeT n)
+{
+ return VG_(memset)(dest, 0, n);
+}
+
+void *__aeabi_memclr8(void *dest, SizeT n);
+void *__aeabi_memclr8(void *dest, SizeT n)
+{
+ return VG_(memset)(dest, 0, n);
+}
+#endif /* defined(__ANDROID__) */
+#endif /* defined(VGP_arm_linux) */
/* ---------------- Requirement 2 ---------------- */
|
Author: iraisr
Date: Tue May 16 09:22:51 2017
New Revision: 16383
Log:
Increase Valgrind's load address to prevent mmap failure.
Fixes BZ#374963.
Previously Valgrind failed to start when the executable contained
large text, data or bss segments. The load address was increased
for almost all platforms to 0x58000000 (from 0x38000000),
giving another 512 MB for the executable.
Modified:
trunk/NEWS
trunk/configure.ac
trunk/coregrind/link_tool_exe_darwin.in
trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
trunk/coregrind/m_gdbserver/server.c
trunk/docs/xml/manual-core-adv.xml
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue May 16 09:22:51 2017
@@ -152,6 +152,7 @@
373555 Rename BBPTR to GSPTR as it denotes guest state pointer only
373938 const IRExpr arguments for matchIRExpr()
374719 some spelling fixes
+374963 increase valgrind's load address to prevent mmap failure
375514 valgrind_get_tls_addr() does not work in case of static TLS
375772 +1 error in get_elf_symbol_info() when computing value of 'hi' address
for ML_(find_rx_mapping)()
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Tue May 16 09:22:51 2017
@@ -522,8 +522,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -536,24 +536,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -562,8 +562,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -576,24 +576,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="ppc32"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="ppc64be"
VGCONF_ARCH_SEC="ppc32"
VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -605,8 +605,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
# Darwin gets identified as 32-bit even when it supports 64-bit.
@@ -623,25 +623,25 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
VGCONF_PLATFORM_SEC_CAPS=""
VGCONF_ARCH_PRI_CAPS="x86"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"
- valt_load_address_pri_norml="0x138000000"
- valt_load_address_pri_inner="0x128000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x158000000"
+ valt_load_address_pri_inner="0x138000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -649,8 +649,8 @@
VGCONF_ARCH_PRI="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${host_cpu}-${host_os})])
@@ -663,24 +663,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="arm"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="arm64"
VGCONF_ARCH_SEC="arm"
VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX"
VGCONF_PLATFORM_SEC_CAPS="ARM_LINUX"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
@@ -701,8 +701,8 @@
VGCONF_ARCH_PRI="mips32"
VGCONF_PLATFORM_PRI_CAPS="MIPS32_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -711,8 +711,8 @@
VGCONF_ARCH_PRI="mips64"
VGCONF_PLATFORM_PRI_CAPS="MIPS64_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -722,8 +722,8 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
@@ -736,24 +736,24 @@
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
elif test x$vg_cv_only32bit = xyes; then
VGCONF_ARCH_PRI="x86"
VGCONF_ARCH_SEC=""
VGCONF_PLATFORM_PRI_CAPS="X86_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS=""
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
else
VGCONF_ARCH_PRI="amd64"
VGCONF_ARCH_SEC="x86"
VGCONF_PLATFORM_PRI_CAPS="AMD64_SOLARIS"
VGCONF_PLATFORM_SEC_CAPS="X86_SOLARIS"
- valt_load_address_pri_norml="0x38000000"
- valt_load_address_pri_inner="0x28000000"
- valt_load_address_sec_norml="0x38000000"
- valt_load_address_sec_inner="0x28000000"
+ valt_load_address_pri_norml="0x58000000"
+ valt_load_address_pri_inner="0x38000000"
+ valt_load_address_sec_norml="0x58000000"
+ valt_load_address_sec_inner="0x38000000"
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
Modified: trunk/coregrind/link_tool_exe_darwin.in
==============================================================================
--- trunk/coregrind/link_tool_exe_darwin.in (original)
+++ trunk/coregrind/link_tool_exe_darwin.in Tue May 16 09:22:51 2017
@@ -38,7 +38,7 @@
#
# /usr/bin/ld -static -arch x86_64 -macosx_version_min 10.6 \
# -o memcheck-amd64-darwin -u __start -e __start \
-# -image_base 0x138000000 -stack_addr 0x13c000000 \
+# -image_base 0x158000000 -stack_addr 0x13c000000 \
# -stack_size 0x800000 \
# memcheck_amd*.o \
# ../coregrind/libcoregrind-amd64-darwin.a \
@@ -48,7 +48,7 @@
#
# /usr/bin/ld -static -arch i386 -macosx_version_min 10.6 \
# -o memcheck-x86-darwin -u __start -e __start \
-# -image_base 0x38000000 -stack_addr 0x3c000000 \
+# -image_base 0x58000000 -stack_addr 0x3c000000 \
# -stack_size 0x800000 \
# memcheck_x86*.o \
# ../coregrind/libcoregrind-x86-darwin.a \
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-linux.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-linux.c Tue May 16 09:22:51 2017
@@ -1655,7 +1655,7 @@
| |
|--------------------------------|
| client stack |
- |--------------------------------| 0x38000000
+ |--------------------------------| 0x58000000
| V's text |
|--------------------------------|
| |
@@ -1688,7 +1688,7 @@
| |
|--------------------------------|
| client stack |
- |--------------------------------| 0x00000000_38000000
+ |--------------------------------| 0x00000000_58000000
| V's text |
|--------------------------------|
| |
@@ -1723,9 +1723,9 @@
aspacem_cStart = aspacem_minAddr;
# ifdef ENABLE_INNER
- suggested_clstack_end = (Addr) 0x27ff0000 - 1; // 64kB below V's text
-# else
suggested_clstack_end = (Addr) 0x37ff0000 - 1; // 64kB below V's text
+# else
+ suggested_clstack_end = (Addr) 0x57ff0000 - 1; // 64kB below V's text
# endif
// --- Linux --------------------------------------------
Modified: trunk/coregrind/m_gdbserver/server.c
==============================================================================
--- trunk/coregrind/m_gdbserver/server.c (original)
+++ trunk/coregrind/m_gdbserver/server.c Tue May 16 09:22:51 2017
@@ -339,7 +339,7 @@
do not, suggest a 'likely somewhat working' address: */
const Addr tool_text_start
= tooldi ?
- VG_(DebugInfo_get_text_avma) (tooldi) : 0x38000000;
+ VG_(DebugInfo_get_text_avma) (tooldi) : 0x58000000;
const NSegment *toolseg
= tooldi ?
VG_(am_find_nsegment) (VG_(DebugInfo_get_text_avma) (tooldi))
Modified: trunk/docs/xml/manual-core-adv.xml
==============================================================================
--- trunk/docs/xml/manual-core-adv.xml (original)
+++ trunk/docs/xml/manual-core-adv.xml Tue May 16 09:22:51 2017
@@ -1516,9 +1516,9 @@
<screen><![CDATA[
(gdb) monitor v.set hostvisibility yes
-(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x38000000
+(gdb) add-symbol-file /path/to/tool/executable/file/memcheck-x86-linux 0x58000000
add symbol table from file "/path/to/tool/executable/file/memcheck-x86-linux" at
- .text_addr = 0x38000000
+ .text_addr = 0x58000000
(y or n) y
Reading symbols from /path/to/tool/executable/file/memcheck-x86-linux...done.
(gdb)
|
|
From: <sv...@va...> - 2017-05-16 08:03:17
|
Author: iraisr
Date: Tue May 16 09:03:10 2017
New Revision: 16382
Log:
Fixes for BZ#370028 are now finished.
Modified:
trunk/NEWS
trunk/docs/internals/3_12_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue May 16 09:03:10 2017
@@ -126,7 +126,7 @@
368924 WARNING: unhandled arm64-linux syscall: 84 (sync_file_range)
368925 WARNING: unhandled arm64-linux syscall: 130 (tkill)
368926 WARNING: unhandled arm64-linux syscall: 97 (unshare)
-370028 Reduce the number of compiler warnings on MIPS platforms (partial fix)
+370028 Reduce the number of compiler warnings on MIPS platforms
370635 arm64 missing syscall getcpu
371225 Fix order of timer_{gettime,getoverrun,settime} syscalls on arm64
371227 Clean AArch64 syscall table
Modified: trunk/docs/internals/3_12_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_12_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_12_BUGSTATUS.txt Tue May 16 09:03:10 2017
@@ -317,9 +317,6 @@
=== other/mips =========================================================
-370028 Reduce the number of compiler warnings on MIPS platforms
- [several patches landed, some still in works]
-
=== other/s390 =========================================================
=== other/Android ======================================================
@@ -489,10 +486,6 @@
(is mostly fixed)
**
-370028 Reduce the number of compiler warnings on MIPS platforms
- (2017-05-15: all ready patches are in)
-
-**
374963 increase valgrind's load address to prevent mmap failure
(has a patch with a change to 0x5800'0000)
|
|
From: <sv...@va...> - 2017-05-16 07:59:39
|
Author: iraisr
Date: Tue May 16 08:59:31 2017
New Revision: 3372
Log:
Reduce the number of compiler warnings on MIPS platforms
Partial fix for BZ#370028
Slightly modified patch by: Tamara Vlahovic <tam...@im...>
Modified:
trunk/priv/guest_amd64_helpers.c
trunk/priv/guest_x86_helpers.c
Modified: trunk/priv/guest_amd64_helpers.c
==============================================================================
--- trunk/priv/guest_amd64_helpers.c (original)
+++ trunk/priv/guest_amd64_helpers.c Tue May 16 08:59:31 2017
@@ -1939,18 +1939,17 @@
themselves are not transferred into the guest state. */
static
VexEmNote do_put_x87 ( Bool moveRegs,
- /*IN*/UChar* x87_state,
+ /*IN*/Fpu_State* x87_state,
/*OUT*/VexGuestAMD64State* vex_state )
{
Int stno, preg;
UInt tag;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
- UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
- UInt tagw = x87->env[FP_ENV_TAG];
- UInt fpucw = x87->env[FP_ENV_CTRL];
- UInt c3210 = x87->env[FP_ENV_STAT] & 0x4700;
+ UInt ftop = (x87_state->env[FP_ENV_STAT] >> 11) & 7;
+ UInt tagw = x87_state->env[FP_ENV_TAG];
+ UInt fpucw = x87_state->env[FP_ENV_CTRL];
+ UInt c3210 = x87_state->env[FP_ENV_STAT] & 0x4700;
VexEmNote ew;
UInt fpround;
ULong pair;
@@ -1971,7 +1970,7 @@
} else {
/* register is non-empty */
if (moveRegs)
- convert_f80le_to_f64le( &x87->reg[10*stno],
+ convert_f80le_to_f64le( &x87_state->reg[10*stno],
(UChar*)&vexRegs[preg] );
vexTags[preg] = 1;
}
@@ -2000,23 +1999,23 @@
we can approximate it. */
static
void do_get_x87 ( /*IN*/VexGuestAMD64State* vex_state,
- /*OUT*/UChar* x87_state )
+ /*OUT*/Fpu_State* x87_state )
{
Int i, stno, preg;
UInt tagw;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
UInt ftop = vex_state->guest_FTOP;
UInt c3210 = vex_state->guest_FC3210;
for (i = 0; i < 14; i++)
- x87->env[i] = 0;
+ x87_state->env[i] = 0;
- x87->env[1] = x87->env[3] = x87->env[5] = x87->env[13] = 0xFFFF;
- x87->env[FP_ENV_STAT]
+ x87_state->env[1] = x87_state->env[3] = x87_state->env[5]
+ = x87_state->env[13] = 0xFFFF;
+ x87_state->env[FP_ENV_STAT]
= toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
- x87->env[FP_ENV_CTRL]
+ x87_state->env[FP_ENV_CTRL]
= toUShort(amd64g_create_fpucw( vex_state->guest_FPROUND ));
/* Dump the register stack in ST order. */
@@ -2027,15 +2026,15 @@
/* register is empty */
tagw |= (3 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
} else {
/* register is full. */
tagw |= (0 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
}
}
- x87->env[FP_ENV_TAG] = toUShort(tagw);
+ x87_state->env[FP_ENV_TAG] = toUShort(tagw);
}
@@ -2067,7 +2066,7 @@
Int r, stno;
UShort *srcS, *dstS;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
/* Now build the proper fxsave x87 image from the fsave x87 image
we just made. */
@@ -2236,7 +2235,7 @@
tmp.env[FP_ENV_TAG] = fp_tags;
/* Now write 'tmp' into the guest state. */
- VexEmNote warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
+ VexEmNote warnX87 = do_put_x87( True/*moveRegs*/, &tmp, gst );
return warnX87;
}
@@ -2440,7 +2439,7 @@
VexEmNote amd64g_dirtyhelper_FLDENV ( /*OUT*/VexGuestAMD64State* vex_state,
/*IN*/HWord x87_state)
{
- return do_put_x87( False, (UChar*)x87_state, vex_state );
+ return do_put_x87( False, (Fpu_State*)x87_state, vex_state );
}
@@ -2492,7 +2491,7 @@
void amd64g_dirtyhelper_FNSAVE ( /*IN*/VexGuestAMD64State* vex_state,
/*OUT*/HWord x87_state)
{
- do_get_x87( vex_state, (UChar*)x87_state );
+ do_get_x87( vex_state, (Fpu_State*)x87_state );
}
@@ -2546,7 +2545,7 @@
VexEmNote amd64g_dirtyhelper_FRSTOR ( /*OUT*/VexGuestAMD64State* vex_state,
/*IN*/HWord x87_state)
{
- return do_put_x87( True, (UChar*)x87_state, vex_state );
+ return do_put_x87( True, (Fpu_State*)x87_state, vex_state );
}
Modified: trunk/priv/guest_x86_helpers.c
==============================================================================
--- trunk/priv/guest_x86_helpers.c (original)
+++ trunk/priv/guest_x86_helpers.c Tue May 16 08:59:31 2017
@@ -1599,18 +1599,17 @@
themselves are not transferred into the guest state. */
static
VexEmNote do_put_x87 ( Bool moveRegs,
- /*IN*/UChar* x87_state,
+ /*IN*/Fpu_State* x87_state,
/*OUT*/VexGuestX86State* vex_state )
{
Int stno, preg;
UInt tag;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
- UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
- UInt tagw = x87->env[FP_ENV_TAG];
- UInt fpucw = x87->env[FP_ENV_CTRL];
- UInt c3210 = x87->env[FP_ENV_STAT] & 0x4700;
+ UInt ftop = (x87_state->env[FP_ENV_STAT] >> 11) & 7;
+ UInt tagw = x87_state->env[FP_ENV_TAG];
+ UInt fpucw = x87_state->env[FP_ENV_CTRL];
+ UInt c3210 = x87_state->env[FP_ENV_STAT] & 0x4700;
VexEmNote ew;
UInt fpround;
ULong pair;
@@ -1631,7 +1630,7 @@
} else {
/* register is non-empty */
if (moveRegs)
- convert_f80le_to_f64le( &x87->reg[10*stno],
+ convert_f80le_to_f64le( &x87_state->reg[10*stno],
(UChar*)&vexRegs[preg] );
vexTags[preg] = 1;
}
@@ -1660,23 +1659,23 @@
we can approximate it. */
static
void do_get_x87 ( /*IN*/VexGuestX86State* vex_state,
- /*OUT*/UChar* x87_state )
+ /*OUT*/Fpu_State* x87_state )
{
Int i, stno, preg;
UInt tagw;
ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
UInt ftop = vex_state->guest_FTOP;
UInt c3210 = vex_state->guest_FC3210;
for (i = 0; i < 14; i++)
- x87->env[i] = 0;
+ x87_state->env[i] = 0;
- x87->env[1] = x87->env[3] = x87->env[5] = x87->env[13] = 0xFFFF;
- x87->env[FP_ENV_STAT]
+ x87_state->env[1] = x87_state->env[3] = x87_state->env[5]
+ = x87_state->env[13] = 0xFFFF;
+ x87_state->env[FP_ENV_STAT]
= toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
- x87->env[FP_ENV_CTRL]
+ x87_state->env[FP_ENV_CTRL]
= toUShort(x86g_create_fpucw( vex_state->guest_FPROUND ));
/* Dump the register stack in ST order. */
@@ -1687,15 +1686,15 @@
/* register is empty */
tagw |= (3 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
} else {
/* register is full. */
tagw |= (0 << (2*preg));
convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
- &x87->reg[10*stno] );
+ &x87_state->reg[10*stno] );
}
}
- x87->env[FP_ENV_TAG] = toUShort(tagw);
+ x87_state->env[FP_ENV_TAG] = toUShort(tagw);
}
@@ -1714,7 +1713,7 @@
Int r, stno;
UShort *srcS, *dstS;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
mxcsr = x86g_create_mxcsr( gst->guest_SSEROUND );
/* Now build the proper fxsave image from the x87 image we just
@@ -1865,7 +1864,7 @@
tmp.env[FP_ENV_TAG] = fp_tags;
/* Now write 'tmp' into the guest state. */
- warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
+ warnX87 = do_put_x87( True/*moveRegs*/, &tmp, gst );
{ UInt w32 = (((UInt)addrS[12]) & 0xFFFF)
| ((((UInt)addrS[13]) & 0xFFFF) << 16);
@@ -1888,14 +1887,14 @@
/* DIRTY HELPER (reads guest state, writes guest mem) */
void x86g_dirtyhelper_FSAVE ( VexGuestX86State* gst, HWord addr )
{
- do_get_x87( gst, (UChar*)addr );
+ do_get_x87( gst, (Fpu_State*)addr );
}
/* CALLED FROM GENERATED CODE */
/* DIRTY HELPER (writes guest state, reads guest mem) */
VexEmNote x86g_dirtyhelper_FRSTOR ( VexGuestX86State* gst, HWord addr )
{
- return do_put_x87( True/*regs too*/, (UChar*)addr, gst );
+ return do_put_x87( True/*regs too*/, (Fpu_State*)addr, gst );
}
/* CALLED FROM GENERATED CODE */
@@ -1906,7 +1905,7 @@
Int i;
UShort* addrP = (UShort*)addr;
Fpu_State tmp;
- do_get_x87( gst, (UChar*)&tmp );
+ do_get_x87( gst, &tmp );
for (i = 0; i < 14; i++)
addrP[i] = tmp.env[i];
}
@@ -1915,7 +1914,7 @@
/* DIRTY HELPER (writes guest state, reads guest mem) */
VexEmNote x86g_dirtyhelper_FLDENV ( VexGuestX86State* gst, HWord addr )
{
- return do_put_x87( False/*don't move regs*/, (UChar*)addr, gst);
+ return do_put_x87( False/*don't move regs*/, (Fpu_State*)addr, gst);
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -1925,7 +1924,7 @@
void LibVEX_GuestX86_get_x87 ( /*IN*/VexGuestX86State* vex_state,
/*OUT*/UChar* x87_state )
{
- do_get_x87 ( vex_state, x87_state );
+ do_get_x87 ( vex_state, (Fpu_State*)x87_state );
}
/* VISIBLE TO LIBVEX CLIENT */
@@ -1934,7 +1933,7 @@
VexEmNote LibVEX_GuestX86_put_x87 ( /*IN*/UChar* x87_state,
/*MOD*/VexGuestX86State* vex_state )
{
- return do_put_x87 ( True/*moveRegs*/, x87_state, vex_state );
+ return do_put_x87 ( True/*moveRegs*/, (Fpu_State*)x87_state, vex_state );
}
/* VISIBLE TO LIBVEX CLIENT */
|
|
From: <sv...@va...> - 2017-05-16 06:26:55
|
Author: sewardj
Date: Tue May 16 07:26:48 2017
New Revision: 3371
Log:
arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the
fallback LLSC implementation in that case. Pertains to bug #369459.
(VEX side changes)
Modified:
trunk/priv/main_main.c
trunk/pub/libvex.h
Modified: trunk/priv/main_main.c
==============================================================================
--- trunk/priv/main_main.c (original)
+++ trunk/priv/main_main.c Tue May 16 07:26:48 2017
@@ -1468,6 +1468,7 @@
vai->ppc_dcbzl_szB = 0;
vai->arm64_dMinLine_lg2_szB = 0;
vai->arm64_iMinLine_lg2_szB = 0;
+ vai->arm64_requires_fallback_LLSC = False;
vai->hwcache_info.num_levels = 0;
vai->hwcache_info.num_caches = 0;
vai->hwcache_info.caches = NULL;
Modified: trunk/pub/libvex.h
==============================================================================
--- trunk/pub/libvex.h (original)
+++ trunk/pub/libvex.h Tue May 16 07:26:48 2017
@@ -323,6 +323,9 @@
line size of 64 bytes would be encoded here as 6. */
UInt arm64_dMinLine_lg2_szB;
UInt arm64_iMinLine_lg2_szB;
+ /* ARM64: does the host require us to use the fallback LLSC
+ implementation? */
+ Bool arm64_requires_fallback_LLSC;
}
VexArchInfo;
|
|
From: <sv...@va...> - 2017-05-16 06:20:33
|
Author: sewardj
Date: Tue May 16 07:20:26 2017
New Revision: 16381
Log:
Bug 368507 - valgrind throws std::bad_alloc on memory allocations larger than 34255421416 bytes.
Increase the amount of usable memory from 64GB to 128GB on Linux and Solaris.
(Solaris bits from Ivo Raisr.) OSX is so far unchanged.
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
trunk/memcheck/mc_main.c
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-linux.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-linux.c Tue May 16 07:20:26 2017
@@ -1620,6 +1620,7 @@
aspacem_minAddr = VG_(clo_aspacem_minAddr);
+ // --- Darwin -------------------------------------------
#if defined(VGO_darwin)
# if VG_WORDSIZE == 4
@@ -1637,6 +1638,7 @@
suggested_clstack_end = -1; // ignored; Mach-O specifies its stack
+ // --- Solaris ------------------------------------------
#elif defined(VGO_solaris)
# if VG_WORDSIZE == 4
/*
@@ -1692,7 +1694,7 @@
| |
|--------------------------------|
| dynamic shared objects |
- |--------------------------------| 0x0000000f_ffffffff
+ |--------------------------------| 0x0000001f_ffffffff
| |
| |
|--------------------------------|
@@ -1702,18 +1704,18 @@
*/
/* Kernel likes to place objects at the end of the address space.
- However accessing memory beyond 64GB makes memcheck slow
+ However accessing memory beyond 128GB makes memcheck slow
(see memcheck/mc_main.c, internal representation). Therefore:
- mmapobj() syscall is emulated so that libraries are subject to
Valgrind's aspacemgr control
- Kernel shared pages (such as schedctl and hrt) are left as they are
because kernel cannot be told where they should be put */
# ifdef ENABLE_INNER
- aspacem_maxAddr = (Addr) 0x00000007ffffffff; // 32GB
- aspacem_vStart = (Addr) 0x0000000400000000; // 16GB
-# else
aspacem_maxAddr = (Addr) 0x0000000fffffffff; // 64GB
aspacem_vStart = (Addr) 0x0000000800000000; // 32GB
+# else
+ aspacem_maxAddr = (Addr) 0x0000001fffffffff; // 128GB
+ aspacem_vStart = (Addr) 0x0000001000000000; // 64GB
# endif
# else
# error "Unknown word size"
@@ -1726,6 +1728,7 @@
suggested_clstack_end = (Addr) 0x37ff0000 - 1; // 64kB below V's text
# endif
+ // --- Linux --------------------------------------------
#else
/* Establish address limits and block out unusable parts
@@ -1736,7 +1739,7 @@
sp_at_startup );
# if VG_WORDSIZE == 8
- aspacem_maxAddr = (Addr)0x1000000000ULL - 1; // 64G
+ aspacem_maxAddr = (Addr)0x2000000000ULL - 1; // 128G
# ifdef ENABLE_INNER
{ Addr cse = VG_PGROUNDDN( sp_at_startup ) - 1;
if (aspacem_maxAddr > cse)
@@ -1751,13 +1754,14 @@
aspacem_vStart = VG_PGROUNDUP(aspacem_minAddr
+ (aspacem_maxAddr - aspacem_minAddr + 1) / 2);
# ifdef ENABLE_INNER
- aspacem_vStart -= 0x10000000; // 256M
+ aspacem_vStart -= 0x20000000; // 512M
# endif
suggested_clstack_end = aspacem_maxAddr - 16*1024*1024ULL
+ VKI_PAGE_SIZE;
#endif
+ // --- (end) --------------------------------------------
aspacem_assert(VG_IS_PAGE_ALIGNED(aspacem_minAddr));
aspacem_assert(VG_IS_PAGE_ALIGNED(aspacem_maxAddr + 1));
Modified: trunk/memcheck/mc_main.c
==============================================================================
--- trunk/memcheck/mc_main.c (original)
+++ trunk/memcheck/mc_main.c Tue May 16 07:20:26 2017
@@ -176,10 +176,10 @@
#else
-/* Just handle the first 64G fast and the rest via auxiliary
+/* Just handle the first 128G fast and the rest via auxiliary
primaries. If you change this, Memcheck will assert at startup.
See the definition of UNALIGNED_OR_HIGH for extensive comments. */
-# define N_PRIMARY_BITS 20
+# define N_PRIMARY_BITS 21
#endif
@@ -8300,11 +8300,11 @@
tl_assert(sizeof(Addr) == 8);
tl_assert(sizeof(UWord) == 8);
tl_assert(sizeof(Word) == 8);
- tl_assert(MAX_PRIMARY_ADDRESS == 0xFFFFFFFFFULL);
- tl_assert(MASK(1) == 0xFFFFFFF000000000ULL);
- tl_assert(MASK(2) == 0xFFFFFFF000000001ULL);
- tl_assert(MASK(4) == 0xFFFFFFF000000003ULL);
- tl_assert(MASK(8) == 0xFFFFFFF000000007ULL);
+ tl_assert(MAX_PRIMARY_ADDRESS == 0x1FFFFFFFFFULL);
+ tl_assert(MASK(1) == 0xFFFFFFE000000000ULL);
+ tl_assert(MASK(2) == 0xFFFFFFE000000001ULL);
+ tl_assert(MASK(4) == 0xFFFFFFE000000003ULL);
+ tl_assert(MASK(8) == 0xFFFFFFE000000007ULL);
# endif
/* Check some assertions to do with the instrumentation machinery. */
|
|
From: <sv...@va...> - 2017-05-16 05:35:39
|
Author: sewardj
Date: Tue May 16 06:35:23 2017
New Revision: 16380
Log:
arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the
fallback LLSC implementation in that case. Pertains to bug #369459.
Modified:
trunk/coregrind/m_machine.c
trunk/coregrind/m_translate.c
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Tue May 16 06:35:23 2017
@@ -634,7 +634,7 @@
return model;
}
-#endif /* VGA_s390x */
+#endif /* defined(VGA_s390x) */
#if defined(VGA_mips32) || defined(VGA_mips64)
@@ -755,12 +755,65 @@
return True;
}
-#endif
+#endif /* defined(VGA_mips32) || defined(VGA_mips64) */
+
+#if defined(VGP_arm64_linux)
+
+/* Check to see whether we are running on a Cavium core, and if so auto-enable
+ the fallback LLSC implementation. See #369459. */
+
+static Bool VG_(parse_cpuinfo)(void)
+{
+ const char *search_Cavium_str = "CPU implementer\t: 0x43";
+
+ Int n, fh;
+ SysRes fd;
+ SizeT num_bytes, file_buf_size;
+ HChar *file_buf;
+
+ /* Slurp contents of /proc/cpuinfo into FILE_BUF */
+ fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR );
+ if ( sr_isError(fd) ) return False;
+
+ fh = sr_Res(fd);
+
+ /* Determine the size of /proc/cpuinfo.
+ Work around broken-ness in /proc file system implementation.
+ fstat returns a zero size for /proc/cpuinfo although it is
+ claimed to be a regular file. */
+ num_bytes = 0;
+ file_buf_size = 1000;
+ file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1);
+ while (42) {
+ n = VG_(read)(fh, file_buf, file_buf_size);
+ if (n < 0) break;
+
+ num_bytes += n;
+ if (n < file_buf_size) break; /* reached EOF */
+ }
+
+ if (n < 0) num_bytes = 0; /* read error; ignore contents */
+
+ if (num_bytes > file_buf_size) {
+ VG_(free)( file_buf );
+ VG_(lseek)( fh, 0, VKI_SEEK_SET );
+ file_buf = VG_(malloc)( "cpuinfo", num_bytes + 1 );
+ n = VG_(read)( fh, file_buf, num_bytes );
+ if (n < 0) num_bytes = 0;
+ }
-/* Determine what insn set and insn set variant the host has, and
- record it. To be called once at system startup. Returns False if
- this a CPU incapable of running Valgrind.
- Also determine information about the caches on this host. */
+ file_buf[num_bytes] = '\0';
+ VG_(close)(fh);
+
+ /* Parse file */
+ if (VG_(strstr)(file_buf, search_Cavium_str) != NULL)
+ vai.arm64_requires_fallback_LLSC = True;
+
+ VG_(free)(file_buf);
+ return True;
+}
+
+#endif /* defined(VGP_arm64_linux) */
Bool VG_(machine_get_hwcaps)( void )
{
@@ -1588,6 +1641,11 @@
VG_(machine_get_cache_info)(&vai);
+ /* Check whether we need to use the fallback LLSC implementation.
+ If the check fails, give up. */
+ if (! VG_(parse_cpuinfo)())
+ return False;
+
/* 0 denotes 'not set'. The range of legitimate values here,
after being set that is, is 2 though 17 inclusive. */
vg_assert(vai.arm64_dMinLine_lg2_szB == 0);
@@ -1600,6 +1658,8 @@
"ctr_el0.iMinLine_szB = %d\n",
1 << vai.arm64_dMinLine_lg2_szB,
1 << vai.arm64_iMinLine_lg2_szB);
+ VG_(debugLog)(1, "machine", "ARM64: requires_fallback_LLSC: %s\n",
+ vai.arm64_requires_fallback_LLSC ? "yes" : "no");
return True;
}
Modified: trunk/coregrind/m_translate.c
==============================================================================
--- trunk/coregrind/m_translate.c (original)
+++ trunk/coregrind/m_translate.c Tue May 16 06:35:23 2017
@@ -1707,7 +1707,10 @@
# if defined(VGP_arm64_linux)
vex_abiinfo.guest__use_fallback_LLSC
- = SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints));
+ = /* The user asked explicitly */
+ SimHintiS(SimHint_fallback_llsc, VG_(clo_sim_hints))
+ || /* we autodetected that it is necessary */
+ vex_archinfo.arm64_requires_fallback_LLSC;
# endif
/* Set up closure args. */
|