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From: Rhys K. <rhy...@gm...> - 2017-05-12 22:19:18
|
On 11 May 2017 at 21:37, <sv...@va...> wrote:
> Author: iraisr
> Date: Fri May 12 02:37:33 2017
> New Revision: 16366
>
> Log:
> Fix build problems on Solaris and OS X.
> Follow up to SVN r16364.
>
Confirming this fixes the build for macOS.
>
> Modified:
> trunk/coregrind/m_commandline.c
>
> Modified: trunk/coregrind/m_commandline.c
> ============================================================
> ==================
> --- trunk/coregrind/m_commandline.c (original)
> +++ trunk/coregrind/m_commandline.c Fri May 12 02:37:33 2017
> @@ -71,7 +71,7 @@
> or is world writeable (CVE-2008-4865). */
> if (res == 0
> && stat_buf.uid == VG_(geteuid)()
> - && (stat_buf.mode & VKI_S_IFREG)
> + && VKI_S_ISREG(stat_buf.mode)
> && !(stat_buf.mode & VKI_S_IWOTH)) {
> if ( stat_buf.size > 0 ) {
> f_clo = VG_(malloc)("commandline.rdv.1", stat_buf.size+1);
>
>
> ------------------------------------------------------------
> ------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers
>
|
|
From: <sv...@va...> - 2017-05-12 17:18:13
|
Author: iraisr
Date: Fri May 12 18:18:05 2017
New Revision: 16368
Log:
Reduce the number of compiler warnings on MIPS platforms in coregrind/m_mallocfree.c
Fixes BZ#370028
Patch by: Tamara Vlahovic <tam...@im...>
Modified:
trunk/coregrind/m_mallocfree.c
Modified: trunk/coregrind/m_mallocfree.c
==============================================================================
--- trunk/coregrind/m_mallocfree.c (original)
+++ trunk/coregrind/m_mallocfree.c Fri May 12 18:18:05 2017
@@ -148,6 +148,9 @@
}
Block;
+/* Ensure that Block payloads can be safely cast to various pointers below. */
+STATIC_ASSERT(VG_MIN_MALLOC_SZB % sizeof(void *) == 0);
+
// A superblock. 'padding' is never used, it just ensures that if the
// entire Superblock is aligned to VG_MIN_MALLOC_SZB, then payload_bytes[]
// will be too. It can add small amounts of padding unnecessarily -- eg.
@@ -296,8 +299,9 @@
SizeT get_bszB_as_is ( Block* b )
{
UByte* b2 = (UByte*)b;
- SizeT bszB_lo = *(SizeT*)&b2[0 + hp_overhead_szB()];
- SizeT bszB_hi = *(SizeT*)&b2[mk_plain_bszB(bszB_lo) - sizeof(SizeT)];
+ SizeT bszB_lo = *ASSUME_ALIGNED(SizeT*, &b2[0 + hp_overhead_szB()]);
+ SizeT bszB_hi = *ASSUME_ALIGNED(SizeT*,
+ &b2[mk_plain_bszB(bszB_lo) - sizeof(SizeT)]);
vg_assert2(bszB_lo == bszB_hi,
"Heap block lo/hi size mismatch: lo = %llu, hi = %llu.\n%s",
(ULong)bszB_lo, (ULong)bszB_hi, probably_your_fault);
@@ -316,8 +320,8 @@
void set_bszB ( Block* b, SizeT bszB )
{
UByte* b2 = (UByte*)b;
- *(SizeT*)&b2[0 + hp_overhead_szB()] = bszB;
- *(SizeT*)&b2[mk_plain_bszB(bszB) - sizeof(SizeT)] = bszB;
+ *ASSUME_ALIGNED(SizeT*, &b2[0 + hp_overhead_szB()]) = bszB;
+ *ASSUME_ALIGNED(SizeT*, &b2[mk_plain_bszB(bszB) - sizeof(SizeT)]) = bszB;
}
//---------------------------------------------------------------------------
@@ -408,25 +412,27 @@
void set_prev_b ( Block* b, Block* prev_p )
{
UByte* b2 = (UByte*)b;
- *(Block**)&b2[hp_overhead_szB() + sizeof(SizeT)] = prev_p;
+ *ASSUME_ALIGNED(Block**, &b2[hp_overhead_szB() + sizeof(SizeT)]) = prev_p;
}
static __inline__
void set_next_b ( Block* b, Block* next_p )
{
UByte* b2 = (UByte*)b;
- *(Block**)&b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)] = next_p;
+ *ASSUME_ALIGNED(Block**,
+ &b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)]) = next_p;
}
static __inline__
Block* get_prev_b ( Block* b )
{
UByte* b2 = (UByte*)b;
- return *(Block**)&b2[hp_overhead_szB() + sizeof(SizeT)];
+ return *ASSUME_ALIGNED(Block**, &b2[hp_overhead_szB() + sizeof(SizeT)]);
}
static __inline__
Block* get_next_b ( Block* b )
{
UByte* b2 = (UByte*)b;
- return *(Block**)&b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)];
+ return *ASSUME_ALIGNED(Block**,
+ &b2[get_bszB(b) - sizeof(SizeT) - sizeof(void*)]);
}
//---------------------------------------------------------------------------
@@ -437,14 +443,14 @@
{
UByte* b2 = (UByte*)b;
vg_assert( VG_(clo_profile_heap) );
- *(const HChar**)&b2[0] = cc;
+ *ASSUME_ALIGNED(const HChar**, &b2[0]) = cc;
}
static __inline__
const HChar* get_cc ( Block* b )
{
UByte* b2 = (UByte*)b;
vg_assert( VG_(clo_profile_heap) );
- return *(const HChar**)&b2[0];
+ return *ASSUME_ALIGNED(const HChar**, &b2[0]);
}
//---------------------------------------------------------------------------
@@ -454,7 +460,7 @@
Block* get_predecessor_block ( Block* b )
{
UByte* b2 = (UByte*)b;
- SizeT bszB = mk_plain_bszB( (*(SizeT*)&b2[-sizeof(SizeT)]) );
+ SizeT bszB = mk_plain_bszB(*ASSUME_ALIGNED(SizeT*, &b2[-sizeof(SizeT)]));
return (Block*)&b2[-bszB];
}
|
|
From: Aaron S. <acs...@li...> - 2017-05-12 15:03:58
|
On Fri, 2017-05-12 at 10:55 +0200, Julian Seward wrote:
> Yeah, to echo Ivo's point -- what you're looking at is a list of the
> blocks
> the first time they are executed -- because at that point they have
> to be
> instrumented. It's not an execution trace. All this really tells
> you is
> that the block at 0x6D04798 (the call target) has already been
> instrumented.
> You should be able to find evidence of that earlier in the debug
> output.
>
> So to return to the original question -- do you have some other
> reason to
> believe that bits of code that should be executed, are being missed?
>
> J
Julian & Ivo,
You are right, it was executed earlier:
==== SB 8296 (evchecks 3470788) [tid 1] 0x6d04798 _IO_no_init+8 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x94798
I was originally led to the conclusion that it wasn't being executed
when I single-stepped it (stepi) by running with --vgdb=yes --vgdb-
error=0 and attaching gdb and setting a breakpoint at 0x6cf1b84 (see
below). The presenting symptom is that the program segfaults shortly
after this when run in valgrind (any tool) and runs correctly native.
So either the gdbserver is behaving oddly and the problem is elsewhere,
or it is not executing this call, which results in segfault later in
glibc code because of stuff it was supposed to have initialized.
Breakpoint 1, 0x0000000006cf1b84 in _IO_vsscanf (
string=0xfff00e37f " R 12626 18764 12626 34818 18764 4194304 2816 0 0 0 7546 117 0 0 20 0 1 0 265857706 160563200 1672 18446744073709551615 939524096 942755688 70368633113024 0 0 0 0 0 2008612607 0 0 0 17 28
0 0 0 0 0 94"..., format=0x6b02170 "%*s%d", args=0xfff00e2a0 <incomplete sequence \343>) at iovsscanf.c:38
38 iovsscanf.c: No such file or directory.
(gdb) disass $pc-64,$pc+32
Dump of assembler code from 0x6cf1b44 to 0x6cf1ba4:
0x0000000006cf1b44 <_IO_vsscanf+20>: std r30,-16(r1)
0x0000000006cf1b48 <_IO_vsscanf+24>: std r31,-8(r1)
0x0000000006cf1b4c <_IO_vsscanf+28>: mr r30,r4
0x0000000006cf1b50 <_IO_vsscanf+32>: li r4,-1
0x0000000006cf1b54 <_IO_vsscanf+36>: li r7,0
0x0000000006cf1b58 <_IO_vsscanf+40>: mr r28,r3
0x0000000006cf1b5c <_IO_vsscanf+44>: mr r29,r5
0x0000000006cf1b60 <_IO_vsscanf+48>: li r9,0
0x0000000006cf1b64 <_IO_vsscanf+52>: li r6,0
0x0000000006cf1b68 <_IO_vsscanf+56>: li r5,-1
0x0000000006cf1b6c <_IO_vsscanf+60>: rlwinm r4,r4,0,16,16
0x0000000006cf1b70 <_IO_vsscanf+64>: std r0,16(r1)
0x0000000006cf1b74 <_IO_vsscanf+68>: stdu r1,-304(r1)
0x0000000006cf1b78 <_IO_vsscanf+72>: addi r31,r1,32
0x0000000006cf1b7c <_IO_vsscanf+76>: std r9,168(r1)
0x0000000006cf1b80 <_IO_vsscanf+80>: mr r3,r31
=> 0x0000000006cf1b84 <_IO_vsscanf+84>: bl 0x6d04798 <_IO_no_init+8>
0x0000000006cf1b88 <_IO_vsscanf+88>: nop
0x0000000006cf1b8c <_IO_vsscanf+92>: addis r9,r2,-1
0x0000000006cf1b90 <_IO_vsscanf+96>: mr r4,r28
0x0000000006cf1b94 <_IO_vsscanf+100>: mr r3,r31
0x0000000006cf1b98 <_IO_vsscanf+104>: li r6,0
0x0000000006cf1b9c <_IO_vsscanf+108>: li r5,0
0x0000000006cf1ba0 <_IO_vsscanf+112>: addi r9,r9,23208
End of assembler dump.
(gdb) stepi
0x0000000006cf1b88 38 in iovsscanf.c
(gdb) stepi
39 in iovsscanf.c
(gdb) p/x $pc
$1 = 0x6cf1b8c
(gdb) stepi
40 in iovsscanf.c
(gdb) stepi
0x0000000006cf1b94 40 in iovsscanf.c
(gdb) stepi
0x0000000006cf1b98 40 in iovsscanf.c
(gdb) stepi
0x0000000006cf1b9c 40 in iovsscanf.c
Here's my attempt to instrument the chaining and get more of a picture
of what's going on:
First call to _IO_no_init:
handle_chain_me place_to_chain 0x80477E920 ip 0x6cfbdc8 to_sNo 0x0 to_tteNo 0x85f5
--26007:0:transtab tt_tc_do_chaining host code 0x80477E95C from__patch_addr 0x80477E920
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B9B30 tcptr 0x80477E940 entry 0x6cfbdc8
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B9BA0 tcptr 0x80477E3A8 entry 0x6cfbd88
sched: CHAIN_TO_FAST_EP: 0x80477EBF0
==== SB 8295 (evchecks 3470785) [tid 1] 0x6d04798 _IO_no_init+8 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x94798
handle_chain_me place_to_chain 0x80477EBF0 ip 0x6d04798 to_sNo 0x0 to_tteNo 0x85f4
--26007:0:transtab tt_tc_do_chaining host code 0x80477EC2C from__patch_addr 0x80477EBF0
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B9AC0 tcptr 0x80477EC10 entry 0x6d04798
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B9B30 tcptr 0x80477E940 entry 0x6cfbdc8
sched: CHAIN_TO_SLOW_EP: 0x80477EFC8
==== SB 8296 (evchecks 3470786) [tid 1] 0x6d04710 _IO_old_init /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x94710
handle_chain_me place_to_chain 0x80477EFC8 ip 0x6d04710 to_sNo 0x0 to_tteNo 0x85f3
--26007:0:transtab tt_tc_do_chaining host code 0x80477EFE8 from__patch_addr 0x80477EFC8
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B9A50 tcptr 0x80477EFE8 entry 0x6d04710
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B9AC0 tcptr 0x80477EC10 entry 0x6d04798
==== SB 8297 (evchecks 3470787) [tid 1] 0x6d047c8 _IO_no_init+56 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x947c8
I don't see chaining (through this function anyway) from 6d04710 to anywhere which seems surprising.
Later, when the call that's skipped in gdb occurs (the block that ends with the call at 0x6cf1b84):
==== SB 8417 (evchecks 3471231) [tid 1] 0x6cf1b38 vsscanf@@GLIBC_2.17+8 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x81b38
====== AbiHint(Sub64(t88,0x120:I64), 288, 0x6D04798:I64) ======
-- PUT(1296) = 0x6D04798:I64; exit-Call
(xDirect) if (always) { imm64 r30,0x6D04798; std r30,1296(%r31); imm64-fixed5 r30,$disp_cp_chain_me_to_fastEP; mtctr r30; bctrl }
handle_chain_me place_to_chain 0x80478FB18 ip 0x6cf1b38 to_sNo 0x0 to_tteNo 0x857a
--26007:0:transtab tt_tc_do_chaining host code 0x80478FB54 from__patch_addr 0x80478FB18
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B6560 tcptr 0x80478FB38 entry 0x6cf1b38
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B65D0 tcptr 0x80478F6D0 entry 0x6ce89d0
sched: CHAIN_TO_FAST_EP: 0x804790094
This suggests that we do go to 6d04798, so why didn't the gdbserver step into there?
handle_chain_me place_to_chain 0x804790094 ip 0x6d04798 to_sNo 0x0 to_tteNo 0x85f4
--26007:0:transtab tt_tc_do_chaining host code 0x80477EC2C from__patch_addr 0x804790094
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B9AC0 tcptr 0x80477EC10 entry 0x6d04798
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B6560 tcptr 0x80478FB38 entry 0x6cf1b38
If 6cf1b38 is a new block at this point, shouldn't we have seen chaining from a successor to 6d04798 back to
6cf1b88?
==== SB 8418 (evchecks 3471235) [tid 1] 0x6cf1b88 vsscanf@@GLIBC_2.17+88 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x81b88
This is chaining of the block after 6cf1b38 to another call:
sched: CHAIN_TO_FAST_EP: 0x804790304
handle_chain_me place_to_chain 0x804790304 ip 0x6d06b28 to_sNo 0x0 to_tteNo 0x85ef
--26007:0:transtab tt_tc_do_chaining host code 0x80478005C from__patch_addr 0x804790304
--26007:0:transtab tt_tc_do_chaining to_tteC 0x8050B9890 tcptr 0x804780040 entry 0x6d06b28
--26007:0:transtab tt_tc_do_chaining from_tteC 0x8050B64F0 tcptr 0x8047900B0 entry 0x6cf1b88
sched: CHAIN_TO_FAST_EP: 0x80478044C
==== SB 8419 (evchecks 3471237) [tid 1] 0x6d06b58 _IO_str_init_static_internal+56 /opt/at10.0-4-beta1/lib64/power9/libc-2.24.so+0x96b58
Thanks,
Aaron
--
Aaron Sawdey, Ph.D. acs...@li...
050-2/C113 (507) 253-7520 home: 507/263-0782
IBM Linux Technology Center - PPC Toolchain
|
|
From: <sv...@va...> - 2017-05-12 14:11:13
|
Author: sewardj
Date: Fri May 12 15:11:03 2017
New Revision: 16367
Log:
Add test cases for PCMPxSTRx variant $0x10. Pertains to #371288.
Modified:
trunk/none/tests/amd64/pcmpstr64.c
trunk/none/tests/amd64/pcmpstr64.stdout.exp
Modified: trunk/none/tests/amd64/pcmpstr64.c
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64.c (original)
+++ trunk/none/tests/amd64/pcmpstr64.c Fri May 12 15:11:03 2017
@@ -205,7 +205,7 @@
switch (imm8) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
@@ -2217,6 +2217,88 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_10 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_10 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x10, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x10, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_10 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x10, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_10 ( void )
+{
+ char* wot = "10";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_10;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_10;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -2244,5 +2326,6 @@
istri_70();
istri_62();
istri_72();
+ istri_10();
return 0;
}
Modified: trunk/none/tests/amd64/pcmpstr64.stdout.exp
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64.stdout.exp (original)
+++ trunk/none/tests/amd64/pcmpstr64.stdout.exp Fri May 12 15:11:03 2017
@@ -524,3 +524,25 @@
istri 72 0000abcdabcdabcd 00000000000baba0 -> 08c1000b 08c1000b
istri 72 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
istri 72 0ddc0ffeebadfeed 00000000cafebabe -> 08c10004 08c10004
+istri 10 abcdacbdabcdabcd 000000000000000a -> 08810000 08810000
+istri 10 abcdabcdabcdabcd 000000000000000b -> 08810000 08810000
+istri 10 abcdabcdabcdabcd 00000000000000ab -> 08810000 08810000
+istri 10 abcdabc0abcdabcd 000000000000abcd -> 00c10008 00c10008
+istri 10 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 10 0bcdabcdabcdabcd 000000000000abcd -> 00c1000f 00c1000f
+istri 10 abcdabcdabcda0cd 000000000000abcd -> 00c10002 00c10002
+istri 10 abcdabcdabcdab0d 000000000000abcd -> 00c10001 00c10001
+istri 10 abcdabcdabcdabc0 000000000000abcd -> 08c10000 08c10000
+istri 10 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 10 abcdabcdabcdabcd 000000000000a0cd -> 00810002 00810002
+istri 10 abcdabcdabcdabcd 000000000000ab0d -> 00810001 00810001
+istri 10 abcdabcdabcdabcd 000000000000abc0 -> 08810000 08810000
+istri 10 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 10 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000010 00000010
+istri 10 0000abcdabcdabcd 000000000000abcd -> 00c1000c 00c1000c
+istri 10 0000abcdabcdabcd 000000000000dcba -> 00c1000c 00c1000c
+istri 10 0000abcdabcdabcd 000000000000bbbb -> 08c10000 08c10000
+istri 10 0000abcdabcdabcd 000000000000baba -> 08c10000 08c10000
+istri 10 0000abcdabcdabcd 00000000000baba0 -> 08c10000 08c10000
+istri 10 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
+istri 10 0ddc0ffeebadfeed 00000000cafebabe -> 08c10000 08c10000
|
|
From: <sv...@va...> - 2017-05-12 14:09:43
|
Author: sewardj
Date: Fri May 12 15:09:36 2017
New Revision: 3366
Log:
Enable the PCMPxSTRx variant $0x10. Fixes #372188.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_generic_x87.c
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Fri May 12 15:09:36 2017
@@ -18783,7 +18783,7 @@
switch (imm) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
Modified: trunk/priv/guest_generic_x87.c
==============================================================================
--- trunk/priv/guest_generic_x87.c (original)
+++ trunk/priv/guest_generic_x87.c Fri May 12 15:09:36 2017
@@ -797,7 +797,7 @@
switch (imm8) {
case 0x00: case 0x02:
case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14:
+ case 0x10: case 0x12: case 0x14:
case 0x18: case 0x1A:
case 0x30: case 0x34:
case 0x38: case 0x3A:
|
|
From: <sv...@va...> - 2017-05-12 13:32:12
|
Author: sewardj
Date: Fri May 12 14:32:02 2017
New Revision: 3365
Log:
Implement ADCX and ADOX instructions. Modified version of a patch from
jac...@gm.... Bug 360415.
Modified:
trunk/priv/guest_amd64_defs.h
trunk/priv/guest_amd64_helpers.c
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_defs.h
==============================================================================
--- trunk/priv/guest_amd64_defs.h (original)
+++ trunk/priv/guest_amd64_defs.h Fri May 12 14:32:02 2017
@@ -541,6 +541,12 @@
AMD64G_CC_OP_BLSR32, /* 59 */
AMD64G_CC_OP_BLSR64, /* 60 DEP1 = res, DEP2 = arg, NDEP = unused */
+ AMD64G_CC_OP_ADCX32, /* 61 DEP1 = argL, DEP2 = argR ^ oldCarry, .. */
+ AMD64G_CC_OP_ADCX64, /* 62 .. NDEP = old flags */
+
+ AMD64G_CC_OP_ADOX32, /* 63 DEP1 = argL, DEP2 = argR ^ oldOverflow, .. */
+ AMD64G_CC_OP_ADOX64, /* 64 .. NDEP = old flags */
+
AMD64G_CC_OP_NUMBER
};
Modified: trunk/priv/guest_amd64_helpers.c
==============================================================================
--- trunk/priv/guest_amd64_helpers.c (original)
+++ trunk/priv/guest_amd64_helpers.c Fri May 12 14:32:02 2017
@@ -560,6 +560,26 @@
/*-------------------------------------------------------------*/
+#define ACTIONS_ADX(DATA_BITS,DATA_UTYPE,FLAGNAME) \
+{ \
+ PREAMBLE(DATA_BITS); \
+ { ULong ocf; /* o or c */ \
+ ULong argL, argR, oldOC, res; \
+ oldOC = (CC_NDEP >> AMD64G_CC_SHIFT_##FLAGNAME) & 1; \
+ argL = CC_DEP1; \
+ argR = CC_DEP2 ^ oldOC; \
+ res = (argL + argR) + oldOC; \
+ if (oldOC) \
+ ocf = (DATA_UTYPE)res <= (DATA_UTYPE)argL; \
+ else \
+ ocf = (DATA_UTYPE)res < (DATA_UTYPE)argL; \
+ return (CC_NDEP & ~AMD64G_CC_MASK_##FLAGNAME) \
+ | (ocf << AMD64G_CC_SHIFT_##FLAGNAME); \
+ } \
+}
+
+/*-------------------------------------------------------------*/
+
#if PROFILE_RFLAGS
@@ -735,6 +755,12 @@
case AMD64G_CC_OP_BLSR32: ACTIONS_BLSR( 32, UInt );
case AMD64G_CC_OP_BLSR64: ACTIONS_BLSR( 64, ULong );
+ case AMD64G_CC_OP_ADCX32: ACTIONS_ADX( 32, UInt, C );
+ case AMD64G_CC_OP_ADCX64: ACTIONS_ADX( 64, ULong, C );
+
+ case AMD64G_CC_OP_ADOX32: ACTIONS_ADX( 32, UInt, O );
+ case AMD64G_CC_OP_ADOX64: ACTIONS_ADX( 64, ULong, O );
+
default:
/* shouldn't really make these calls from generated code */
vex_printf("amd64g_calculate_rflags_all_WRK(AMD64)"
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Fri May 12 14:32:02 2017
@@ -2121,6 +2121,54 @@
}
+/* Given ta1, ta2 and tres, compute tres = ADCX(ta1,ta2) or tres = ADOX(ta1,ta2)
+ and set flags appropriately.
+*/
+static void helper_ADCX_ADOX ( Bool isADCX, Int sz,
+ IRTemp tres, IRTemp ta1, IRTemp ta2 )
+{
+ UInt thunkOp;
+ IRType ty = szToITy(sz);
+ IRTemp oldflags = newTemp(Ity_I64);
+ IRTemp oldOC = newTemp(Ity_I64); // old O or C flag
+ IRTemp oldOCn = newTemp(ty); // old O or C flag, narrowed
+ IROp plus = mkSizedOp(ty, Iop_Add8);
+ IROp xor = mkSizedOp(ty, Iop_Xor8);
+
+ vassert(typeOfIRTemp(irsb->tyenv, tres) == ty);
+
+ switch (sz) {
+ case 8: thunkOp = isADCX ? AMD64G_CC_OP_ADCX64
+ : AMD64G_CC_OP_ADOX64; break;
+ case 4: thunkOp = isADCX ? AMD64G_CC_OP_ADCX32
+ : AMD64G_CC_OP_ADOX32; break;
+ default: vassert(0);
+ }
+
+ assign( oldflags, mk_amd64g_calculate_rflags_all() );
+
+ /* oldOC = old overflow/carry flag, 0 or 1 */
+ assign( oldOC, binop(Iop_And64,
+ binop(Iop_Shr64,
+ mkexpr(oldflags),
+ mkU8(isADCX ? AMD64G_CC_SHIFT_C
+ : AMD64G_CC_SHIFT_O)),
+ mkU64(1)) );
+
+ assign( oldOCn, narrowTo(ty, mkexpr(oldOC)) );
+
+ assign( tres, binop(plus,
+ binop(plus,mkexpr(ta1),mkexpr(ta2)),
+ mkexpr(oldOCn)) );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(thunkOp) ) );
+ stmt( IRStmt_Put( OFFB_CC_DEP1, widenUto64(mkexpr(ta1)) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, widenUto64(binop(xor, mkexpr(ta2),
+ mkexpr(oldOCn)) )) );
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(oldflags) ) );
+}
+
+
/* -------------- Helpers for disassembly printing. -------------- */
static const HChar* nameGrp1 ( Int opc_aux )
@@ -2894,6 +2942,10 @@
/*--- Disassembling common idioms ---*/
/*------------------------------------------------------------*/
+typedef
+ enum { WithFlagNone=2, WithFlagCarry, WithFlagCarryX, WithFlagOverX }
+ WithFlag;
+
/* Handle binary integer instructions of the form
op E, G meaning
op reg-or-mem, reg
@@ -2924,8 +2976,8 @@
static
ULong dis_op2_E_G ( const VexAbiInfo* vbi,
Prefix pfx,
- Bool addSubCarry,
- IROp op8,
+ IROp op8,
+ WithFlag flag,
Bool keep,
Int size,
Long delta0,
@@ -2940,37 +2992,63 @@
UChar rm = getUChar(delta0);
IRTemp addr = IRTemp_INVALID;
- /* addSubCarry == True indicates the intended operation is
- add-with-carry or subtract-with-borrow. */
- if (addSubCarry) {
- vassert(op8 == Iop_Add8 || op8 == Iop_Sub8);
- vassert(keep);
+ /* Stay sane -- check for valid (op8, flag, keep) combinations. */
+ switch (op8) {
+ case Iop_Add8:
+ switch (flag) {
+ case WithFlagNone: case WithFlagCarry:
+ case WithFlagCarryX: case WithFlagOverX:
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
+ }
+ break;
+ case Iop_Sub8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ if (flag == WithFlagCarry) vassert(keep);
+ break;
+ case Iop_And8:
+ vassert(flag == WithFlagNone);
+ break;
+ case Iop_Or8: case Iop_Xor8:
+ vassert(flag == WithFlagNone);
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
}
if (epartIsReg(rm)) {
/* Specially handle XOR reg,reg, because that doesn't really
depend on reg, and doing the obvious thing potentially
generates a spurious value check failure due to the bogus
- dependency. */
- if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry))
+ dependency. Ditto SUB/SBB reg,reg. */
+ if ((op8 == Iop_Xor8 || ((op8 == Iop_Sub8) && keep))
&& offsetIRegG(size,pfx,rm) == offsetIRegE(size,pfx,rm)) {
- if (False && op8 == Iop_Sub8)
- vex_printf("vex amd64->IR: sbb %%r,%%r optimisation(1)\n");
putIRegG(size,pfx,rm, mkU(ty,0));
}
assign( dst0, getIRegG(size,pfx,rm) );
assign( src, getIRegE(size,pfx,rm) );
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagCarryX) {
+ helper_ADCX_ADOX( True/*isADCX*/, size, dst1, dst0, src );
+ putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagOverX) {
+ helper_ADCX_ADOX( False/*!isADCX*/, size, dst1, dst0, src );
+ putIRegG(size, pfx, rm, mkexpr(dst1));
} else {
assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) );
if (isAddSub(op8))
@@ -2991,15 +3069,23 @@
assign( dst0, getIRegG(size,pfx,rm) );
assign( src, loadLE(szToITy(size), mkexpr(addr)) );
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegG(size, pfx, rm, mkexpr(dst1));
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagCarryX) {
+ /* normal store */
+ helper_ADCX_ADOX( True/*isADCX*/, size, dst1, dst0, src );
+ } else
+ if (op8 == Iop_Add8 && flag == WithFlagOverX) {
+ /* normal store */
+ helper_ADCX_ADOX( False/*!isADCX*/, size, dst1, dst0, src );
} else {
assign( dst1, binop(mkSizedOp(ty,op8), mkexpr(dst0), mkexpr(src)) );
if (isAddSub(op8))
@@ -3040,10 +3126,10 @@
static
ULong dis_op2_G_E ( const VexAbiInfo* vbi,
Prefix pfx,
- Bool addSubCarry,
- IROp op8,
+ IROp op8,
+ WithFlag flag,
Bool keep,
- Int size,
+ Int size,
Long delta0,
const HChar* t_amd64opc )
{
@@ -3056,19 +3142,33 @@
UChar rm = getUChar(delta0);
IRTemp addr = IRTemp_INVALID;
- /* addSubCarry == True indicates the intended operation is
- add-with-carry or subtract-with-borrow. */
- if (addSubCarry) {
- vassert(op8 == Iop_Add8 || op8 == Iop_Sub8);
- vassert(keep);
+ /* Stay sane -- check for valid (op8, flag, keep) combinations. */
+ switch (op8) {
+ case Iop_Add8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ vassert(keep);
+ break;
+ case Iop_Sub8:
+ vassert(flag == WithFlagNone || flag == WithFlagCarry);
+ if (flag == WithFlagCarry) vassert(keep);
+ break;
+ case Iop_And8: case Iop_Or8: case Iop_Xor8:
+ vassert(flag == WithFlagNone);
+ vassert(keep);
+ break;
+ default:
+ vassert(0);
}
+ /* flag != WithFlagNone is only allowed for Add and Sub and indicates the
+ intended operation is add-with-carry or subtract-with-borrow. */
+
if (epartIsReg(rm)) {
/* Specially handle XOR reg,reg, because that doesn't really
depend on reg, and doing the obvious thing potentially
generates a spurious value check failure due to the bogus
- dependency. Ditto SBB reg,reg. */
- if ((op8 == Iop_Xor8 || (op8 == Iop_Sub8 && addSubCarry))
+ dependency. Ditto SUB/SBB reg,reg. */
+ if ((op8 == Iop_Xor8 || ((op8 == Iop_Sub8) && keep))
&& offsetIRegG(size,pfx,rm) == offsetIRegE(size,pfx,rm)) {
putIRegE(size,pfx,rm, mkU(ty,0));
}
@@ -3076,12 +3176,12 @@
assign(dst0, getIRegE(size,pfx,rm));
assign(src, getIRegG(size,pfx,rm));
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
helper_ADC( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegE(size, pfx, rm, mkexpr(dst1));
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
helper_SBB( size, dst1, dst0, src,
/*no store*/IRTemp_INVALID, IRTemp_INVALID, 0 );
putIRegE(size, pfx, rm, mkexpr(dst1));
@@ -3107,7 +3207,7 @@
assign(dst0, loadLE(ty,mkexpr(addr)));
assign(src, getIRegG(size,pfx,rm));
- if (addSubCarry && op8 == Iop_Add8) {
+ if (op8 == Iop_Add8 && flag == WithFlagCarry) {
if (haveLOCK(pfx)) {
/* cas-style store */
helper_ADC( size, dst1, dst0, src,
@@ -3118,7 +3218,7 @@
/*store*/addr, IRTemp_INVALID, 0 );
}
} else
- if (addSubCarry && op8 == Iop_Sub8) {
+ if (op8 == Iop_Sub8 && flag == WithFlagCarry) {
if (haveLOCK(pfx)) {
/* cas-style store */
helper_SBB( size, dst1, dst0, src,
@@ -19876,20 +19976,20 @@
case 0x00: /* ADD Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagNone, True, 1, delta, "add" );
return delta;
case 0x01: /* ADD Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagNone, True, sz, delta, "add" );
return delta;
case 0x02: /* ADD Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagNone, True, 1, delta, "add" );
return delta;
case 0x03: /* ADD Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagNone, True, sz, delta, "add" );
return delta;
case 0x04: /* ADD Ib, AL */
@@ -19903,20 +20003,20 @@
case 0x08: /* OR Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Or8, WithFlagNone, True, 1, delta, "or" );
return delta;
case 0x09: /* OR Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Or8, WithFlagNone, True, sz, delta, "or" );
return delta;
case 0x0A: /* OR Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Or8, WithFlagNone, True, 1, delta, "or" );
return delta;
case 0x0B: /* OR Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Or8, WithFlagNone, True, sz, delta, "or" );
return delta;
case 0x0C: /* OR Ib, AL */
@@ -19930,20 +20030,20 @@
case 0x10: /* ADC Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagCarry, True, 1, delta, "adc" );
return delta;
case 0x11: /* ADC Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Add8, WithFlagCarry, True, sz, delta, "adc" );
return delta;
case 0x12: /* ADC Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarry, True, 1, delta, "adc" );
return delta;
case 0x13: /* ADC Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarry, True, sz, delta, "adc" );
return delta;
case 0x14: /* ADC Ib, AL */
@@ -19957,20 +20057,20 @@
case 0x18: /* SBB Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, 1, delta, "sbb" );
return delta;
case 0x19: /* SBB Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, sz, delta, "sbb" );
return delta;
case 0x1A: /* SBB Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, 1, delta, "sbb" );
return delta;
case 0x1B: /* SBB Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagCarry, True, sz, delta, "sbb" );
return delta;
case 0x1C: /* SBB Ib, AL */
@@ -19984,20 +20084,20 @@
case 0x20: /* AND Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_And8, WithFlagNone, True, 1, delta, "and" );
return delta;
case 0x21: /* AND Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_And8, WithFlagNone, True, sz, delta, "and" );
return delta;
case 0x22: /* AND Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, True, 1, delta, "and" );
return delta;
case 0x23: /* AND Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, True, sz, delta, "and" );
return delta;
case 0x24: /* AND Ib, AL */
@@ -20011,20 +20111,20 @@
case 0x28: /* SUB Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, True, 1, delta, "sub" );
return delta;
case 0x29: /* SUB Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, True, sz, delta, "sub" );
return delta;
case 0x2A: /* SUB Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, True, 1, delta, "sub" );
return delta;
case 0x2B: /* SUB Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, True, sz, delta, "sub" );
return delta;
case 0x2C: /* SUB Ib, AL */
@@ -20038,20 +20138,20 @@
case 0x30: /* XOR Gb,Eb */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Xor8, WithFlagNone, True, 1, delta, "xor" );
return delta;
case 0x31: /* XOR Gv,Ev */
if (!validF2orF3) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Xor8, WithFlagNone, True, sz, delta, "xor" );
return delta;
case 0x32: /* XOR Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Xor8, WithFlagNone, True, 1, delta, "xor" );
return delta;
case 0x33: /* XOR Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Xor8, WithFlagNone, True, sz, delta, "xor" );
return delta;
case 0x34: /* XOR Ib, AL */
@@ -20065,20 +20165,20 @@
case 0x38: /* CMP Gb,Eb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, False, 1, delta, "cmp" );
return delta;
case 0x39: /* CMP Gv,Ev */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ delta = dis_op2_G_E ( vbi, pfx, Iop_Sub8, WithFlagNone, False, sz, delta, "cmp" );
return delta;
case 0x3A: /* CMP Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, False, 1, delta, "cmp" );
return delta;
case 0x3B: /* CMP Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Sub8, WithFlagNone, False, sz, delta, "cmp" );
return delta;
case 0x3C: /* CMP Ib, AL */
@@ -20323,12 +20423,14 @@
case 0x84: /* TEST Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, 1, delta, "test" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, False,
+ 1, delta, "test" );
return delta;
case 0x85: /* TEST Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, sz, delta, "test" );
+ delta = dis_op2_E_G ( vbi, pfx, Iop_And8, WithFlagNone, False,
+ sz, delta, "test" );
return delta;
/* XCHG reg,mem automatically asserts LOCK# even without a LOCK
@@ -22547,7 +22649,6 @@
default:
break;
-
}
/* =-=-=-=-=-=-=-=-= SSSE3ery =-=-=-=-=-=-=-=-= */
@@ -22570,6 +22671,40 @@
return delta;
}
+ /* Ignore previous decode attempts and restart from the beginning of
+ the instruction. */
+ delta = deltaIN;
+ opc = getUChar(delta);
+ delta++;
+
+ switch (opc) {
+
+ case 0xF6: {
+ /* 66 0F 38 F6 = ADCX r32/64(G), m32/64(E) */
+ /* F3 0F 38 F6 = ADOX r32/64(G), m32/64(E) */
+ /* These were introduced in Broadwell. Gate them on AVX2 so as to at
+ least reject them on earlier guests. Has no host requirements. */
+ if (have66noF2noF3(pfx) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
+ if (sz == 2) {
+ sz = 4; /* 66 prefix but operand size is 4/8 */
+ }
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagCarryX, True,
+ sz, delta, "adcx" );
+ return delta;
+ }
+ if (haveF3no66noF2(pfx) && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
+ delta = dis_op2_E_G ( vbi, pfx, Iop_Add8, WithFlagOverX, True,
+ sz, delta, "adox" );
+ return delta;
+ }
+ /* else fall through */
+ break;
+ }
+
+ default:
+ break;
+ }
+
/*decode_failure:*/
return deltaIN; /* fail */
}
|
|
From: Julian S. <js...@ac...> - 2017-05-12 08:55:42
|
Yeah, to echo Ivo's point -- what you're looking at is a list of the blocks the first time they are executed -- because at that point they have to be instrumented. It's not an execution trace. All this really tells you is that the block at 0x6D04798 (the call target) has already been instrumented. You should be able to find evidence of that earlier in the debug output. So to return to the original question -- do you have some other reason to believe that bits of code that should be executed, are being missed? J |
|
From: <sv...@va...> - 2017-05-12 01:37:39
|
Author: iraisr
Date: Fri May 12 02:37:33 2017
New Revision: 16366
Log:
Fix build problems on Solaris and OS X.
Follow up to SVN r16364.
Modified:
trunk/coregrind/m_commandline.c
Modified: trunk/coregrind/m_commandline.c
==============================================================================
--- trunk/coregrind/m_commandline.c (original)
+++ trunk/coregrind/m_commandline.c Fri May 12 02:37:33 2017
@@ -71,7 +71,7 @@
or is world writeable (CVE-2008-4865). */
if (res == 0
&& stat_buf.uid == VG_(geteuid)()
- && (stat_buf.mode & VKI_S_IFREG)
+ && VKI_S_ISREG(stat_buf.mode)
&& !(stat_buf.mode & VKI_S_IWOTH)) {
if ( stat_buf.size > 0 ) {
f_clo = VG_(malloc)("commandline.rdv.1", stat_buf.size+1);
|
|
From: <sv...@va...> - 2017-05-12 01:16:10
|
Author: iraisr
Date: Fri May 12 02:16:01 2017
New Revision: 16365
Log:
Reduce the number of compiler warnings on MIPS platforms in coregrind/launcher-linux.c
Fixes BZ#370028
Patch by: Tamara Vlahovic <tam...@im...>
Modified:
trunk/coregrind/launcher-linux.c
Modified: trunk/coregrind/launcher-linux.c
==============================================================================
--- trunk/coregrind/launcher-linux.c (original)
+++ trunk/coregrind/launcher-linux.c Fri May 12 02:16:01 2017
@@ -129,7 +129,11 @@
static const char *select_platform(const char *clientname)
{
int fd;
- char header[4096];
+ union {
+ char c[4096];
+ Elf32_Ehdr ehdr32;
+ Elf64_Ehdr ehdr64;
+ } header;
ssize_t n_bytes;
const char *platform = NULL;
@@ -146,7 +150,7 @@
VG_(debugLog)(2, "launcher", "opened '%s'\n", clientname);
- n_bytes = read(fd, header, sizeof(header));
+ n_bytes = read(fd, header.c, sizeof(header));
close(fd);
if (n_bytes < 2) {
return NULL;
@@ -155,25 +159,25 @@
VG_(debugLog)(2, "launcher", "read %ld bytes from '%s'\n",
(long int)n_bytes, clientname);
- if (header[0] == '#' && header[1] == '!') {
+ if (header.c[0] == '#' && header.c[1] == '!') {
int i = 2;
STATIC_ASSERT(VKI_BINPRM_BUF_SIZE < sizeof header);
if (n_bytes > VKI_BINPRM_BUF_SIZE)
n_bytes = VKI_BINPRM_BUF_SIZE - 1;
- header[n_bytes] = '\0';
- char *eol = strchr(header, '\n');
+ header.c[n_bytes] = '\0';
+ char *eol = strchr(header.c, '\n');
if (eol != NULL)
*eol = '\0';
// Skip whitespace.
- while (header[i] == ' '|| header[i] == '\t')
+ while (header.c[i] == ' '|| header.c[i] == '\t')
i++;
// Get the interpreter name.
- const char *interp = header + i;
+ const char *interp = header.c + i;
- if (header[i] == '\0') {
+ if (header.c[i] == '\0') {
// No interpreter was found; fall back to default shell
# if defined(VGPV_arm_linux_android) \
|| defined(VGPV_x86_linux_android) \
@@ -184,108 +188,106 @@
interp = "/bin/sh";
# endif
} else {
- while (header[i]) {
- if (header[i] == ' ' || header[i] == '\t') break;
+ while (header.c[i]) {
+ if (header.c[i] == ' ' || header.c[i] == '\t') break;
i++;
}
- header[i] = '\0';
+ header.c[i] = '\0';
}
platform = select_platform(interp);
- } else if (n_bytes >= SELFMAG && memcmp(header, ELFMAG, SELFMAG) == 0) {
+ } else if (n_bytes >= SELFMAG && memcmp(header.c, ELFMAG, SELFMAG) == 0) {
- if (n_bytes >= sizeof(Elf32_Ehdr) && header[EI_CLASS] == ELFCLASS32) {
- const Elf32_Ehdr *ehdr = (Elf32_Ehdr *)header;
+ if (n_bytes >= sizeof(Elf32_Ehdr) && header.c[EI_CLASS] == ELFCLASS32) {
- if (header[EI_DATA] == ELFDATA2LSB) {
+ if (header.c[EI_DATA] == ELFDATA2LSB) {
# if defined(VGO_solaris)
- if (ehdr->e_machine == EM_386 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
+ if (header.ehdr32.e_machine == EM_386 &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
platform = "x86-solaris";
}
else
# endif
- if (ehdr->e_machine == EM_386 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_386 &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "x86-linux";
}
else
- if (ehdr->e_machine == EM_ARM &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_ARM &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm-linux";
}
else
- if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_MIPS &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips32-linux";
}
}
- else if (header[EI_DATA] == ELFDATA2MSB) {
- if (ehdr->e_machine == EM_PPC &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ else if (header.c[EI_DATA] == ELFDATA2MSB) {
+ if (header.ehdr32.e_machine == EM_PPC &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc32-linux";
}
else
- if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr32.e_machine == EM_MIPS &&
+ (header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr32.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips32-linux";
}
}
- } else if (n_bytes >= sizeof(Elf64_Ehdr) && header[EI_CLASS] == ELFCLASS64) {
- const Elf64_Ehdr *ehdr = (Elf64_Ehdr *)header;
+ } else if (n_bytes >= sizeof(Elf64_Ehdr) && header.c[EI_CLASS] == ELFCLASS64) {
- if (header[EI_DATA] == ELFDATA2LSB) {
+ if (header.c[EI_DATA] == ELFDATA2LSB) {
# if defined(VGO_solaris)
- if (ehdr->e_machine == EM_X86_64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
+ if (header.ehdr64.e_machine == EM_X86_64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SOLARIS)) {
platform = "amd64-solaris";
}
else
# endif
- if (ehdr->e_machine == EM_X86_64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_X86_64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "amd64-linux";
- } else if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_MIPS &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips64-linux";
- } else if (ehdr->e_machine == EM_AARCH64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_TILEGX &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm64-linux";
- } else if (ehdr->e_machine == EM_PPC64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_PPC64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc64le-linux";
}
- } else if (header[EI_DATA] == ELFDATA2MSB) {
+ } else if (header.c[EI_DATA] == ELFDATA2MSB) {
# if !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGPV_mips32_linux_android) \
&& !defined(VGPV_arm64_linux_android)
- if (ehdr->e_machine == EM_PPC64 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_PPC64 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc64be-linux";
}
else
- if (ehdr->e_machine == EM_S390 &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ if (header.ehdr64.e_machine == EM_S390 &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "s390x-linux";
- } else if (ehdr->e_machine == EM_MIPS &&
- (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
- ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ } else if (header.ehdr64.e_machine == EM_MIPS &&
+ (header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ header.ehdr64.e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips64-linux";
}
# endif
|
|
From: Ivo R. <iv...@iv...> - 2017-05-12 00:54:58
|
> But the very next block is the code following the bl at 0x6CF1B88, not > the code at 0x6D04798: > > ==== SB 8420 (evchecks 3471236) [tid 1] 0x6cf1b88 > vsscanf@@GLIBC_2.17+88 /opt/at10.0-4-beta1/lib64/power9/libc- > 2.24.so+0x81b88 An obvious question - are you sure that the next block executed is really SB 8420? It is not possible to deduce it from the VEX logs alone - they show only translations. I tracked a similar problem in past and had to add a debug statement in the scheduler and disable block chaining to get a clear picture what gets scheduled. Maybe there is a better way... I. |