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From: <sv...@va...> - 2016-10-17 19:24:27
|
Author: sewardj
Date: Mon Oct 17 20:24:20 2016
New Revision: 16063
Log:
Merge from trunk:
16045 Follow up for r16044. Fix compilation problem on Solaris.
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c Mon Oct 17 20:24:20 2016
@@ -955,8 +955,8 @@
}
}
- VG_(free)(info.interp_name); VG_(free)(info->interp_name);
- VG_(free)(info.interp_args); VG_(free)(info->interp_args);
+ VG_(free)(info.interp_name);
+ VG_(free)(info.interp_args);
return iifii;
}
|
|
From: <sv...@va...> - 2016-10-17 19:23:26
|
Author: sewardj
Date: Mon Oct 17 20:23:19 2016
New Revision: 16062
Log:
Merge from trunk:
16044 Further fixes following fix of leak in 16033
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_mallocfree.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/main.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/script.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c Mon Oct 17 20:23:19 2016
@@ -428,14 +428,10 @@
*ptr++ = (Addr)(argc + 1);
/* --- client argv --- */
- if (info->interp_name) {
+ if (info->interp_name)
*ptr++ = (Addr)copy_str(&strtab, info->interp_name);
- VG_(free)(info->interp_name);
- }
- if (info->interp_args) {
+ if (info->interp_args)
*ptr++ = (Addr)copy_str(&strtab, info->interp_args);
- VG_(free)(info->interp_args);
- }
*ptr++ = (Addr)copy_str(&strtab, VG_(args_the_exename));
@@ -566,8 +562,8 @@
// Tell aspacem about commpage, etc
record_system_memory();
- VG_(free)(info.interp_name);
- VG_(free)(info.interp_args);
+ VG_(free)(info.interp_name); info.interp_name = NULL;
+ VG_(free)(info.interp_args); info.interp_args = NULL;
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c Mon Oct 17 20:23:19 2016
@@ -584,14 +584,10 @@
*ptr++ = argc + 1;
/* --- client argv --- */
- if (info->interp_name) {
+ if (info->interp_name)
*ptr++ = (Addr)copy_str(&strtab, info->interp_name);
- VG_(free)(info->interp_name);
- }
- if (info->interp_args) {
+ if (info->interp_args)
*ptr++ = (Addr)copy_str(&strtab, info->interp_args);
- VG_(free)(info->interp_args);
- }
*ptr++ = (Addr)copy_str(&strtab, VG_(args_the_exename));
@@ -1017,8 +1013,8 @@
setup_client_dataseg( dseg_max_size );
}
- VG_(free)(info.interp_name);
- VG_(free)(info.interp_args);
+ VG_(free)(info.interp_name); info.interp_name = NULL;
+ VG_(free)(info.interp_args); info.interp_args = NULL;
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c Mon Oct 17 20:23:19 2016
@@ -581,14 +581,10 @@
*ptr++ = argc;
/* Copy-out client argv. */
- if (info->interp_name) {
+ if (info->interp_name)
*ptr++ = (Addr)copy_str(&strtab, info->interp_name);
- VG_(free)(info->interp_name);
- }
- if (info->interp_args) {
+ if (info->interp_args)
*ptr++ = (Addr)copy_str(&strtab, info->interp_args);
- VG_(free)(info->interp_args);
- }
*ptr++ = (Addr)copy_str(&strtab, VG_(args_the_exename));
for (i = 0; i < VG_(sizeXA)(VG_(args_for_client)); i++)
@@ -959,8 +955,8 @@
}
}
- VG_(free)(info.interp_name);
- VG_(free)(info.interp_args);
+ VG_(free)(info.interp_name); VG_(free)(info->interp_name);
+ VG_(free)(info.interp_args); VG_(free)(info->interp_args);
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_mallocfree.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_mallocfree.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_mallocfree.c Mon Oct 17 20:23:19 2016
@@ -2098,7 +2098,7 @@
/* If this is one of V's areas, check carefully the block we're
getting back. This picks up simple block-end overruns. */
if (aid != VG_AR_CLIENT)
- vg_assert(blockSane(a, b));
+ vg_assert(is_inuse_block(b) && blockSane(a, b));
b_bszB = get_bszB(b);
b_pszB = bszB_to_pszB(a, b_bszB);
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/main.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/main.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/main.c Mon Oct 17 20:23:19 2016
@@ -223,9 +223,9 @@
// Looks like a script. Run it with /bin/sh. This includes
// zero-length files.
-
+ VG_(free)(info->interp_name);
info->interp_name = VG_(strdup)("ume.desf.1", default_interp_name);
- info->interp_args = NULL;
+ VG_(free)(info->interp_args); info->interp_args = NULL;
if (info->argv && info->argv[0] != NULL)
info->argv[0] = exe_name;
@@ -281,9 +281,9 @@
Int VG_(do_exec)(const HChar* exe_name, ExeInfo* info)
{
Int ret;
-
- info->interp_name = NULL;
- info->interp_args = NULL;
+
+ VG_(free)(info->interp_name); info->interp_name = NULL;
+ VG_(free)(info->interp_args); info->interp_args = NULL;
ret = VG_(do_exec_inner)(exe_name, info);
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/script.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/script.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_ume/script.c Mon Oct 17 20:23:19 2016
@@ -115,7 +115,7 @@
cp++;
*cp = '\0';
}
-
+ VG_(free)(info->interp_name);
info->interp_name = VG_(strdup)("ume.ls.1", interp);
vg_assert(NULL != info->interp_name);
if (arg != NULL && *arg != '\0') {
|
|
From: <sv...@va...> - 2016-10-17 19:21:59
|
Author: sewardj
Date: Mon Oct 17 20:21:53 2016
New Revision: 16061
Log:
Merge from trunk:
16036 Fix corruption introduced by revision 16033
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c Mon Oct 17 20:21:53 2016
@@ -1821,7 +1821,7 @@
/* All required specs were found. Just free memory and return. */
for (i = 0; i < VG_(sizeXA)(fnpatts); i++)
- VG_(free)(VG_(indexXA)(fnpatts, i));
+ VG_(free)(*(HChar**) VG_(indexXA)(fnpatts, i));
VG_(deleteXA)(fnpatts);
}
|
Author: sewardj
Date: Mon Oct 17 20:20:46 2016
New Revision: 16060
Log:
Merge from trunk:
16033 Fix some (small) leaks found by self-hosting valgrind
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-darwin.c Mon Oct 17 20:20:46 2016
@@ -566,6 +566,8 @@
// Tell aspacem about commpage, etc
record_system_memory();
+ VG_(free)(info.interp_name);
+ VG_(free)(info.interp_args);
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-linux.c Mon Oct 17 20:20:46 2016
@@ -1017,6 +1017,8 @@
setup_client_dataseg( dseg_max_size );
}
+ VG_(free)(info.interp_name);
+ VG_(free)(info.interp_args);
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_initimg/initimg-solaris.c Mon Oct 17 20:20:46 2016
@@ -959,6 +959,8 @@
}
}
+ VG_(free)(info.interp_name);
+ VG_(free)(info.interp_args);
return iifii;
}
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_redir.c Mon Oct 17 20:20:46 2016
@@ -1820,6 +1820,8 @@
}
/* All required specs were found. Just free memory and return. */
+ for (i = 0; i < VG_(sizeXA)(fnpatts); i++)
+ VG_(free)(VG_(indexXA)(fnpatts, i));
VG_(deleteXA)(fnpatts);
}
|
|
From: <sv...@va...> - 2016-10-17 19:19:33
|
Author: sewardj
Date: Mon Oct 17 20:19:26 2016
New Revision: 16059
Log:
Merge from trunk:
16037 Fix for missing ISA changes in HW cap stuff needs updating patch
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/memcheck/tests/vbit-test/irops.c
branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c
Modified: branches/VALGRIND_3_12_BRANCH/memcheck/tests/vbit-test/irops.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/memcheck/tests/vbit-test/irops.c (original)
+++ branches/VALGRIND_3_12_BRANCH/memcheck/tests/vbit-test/irops.c Mon Oct 17 20:19:26 2016
@@ -1287,8 +1287,8 @@
case Iop_MulI128by10Carry:
case Iop_MulI128by10E:
case Iop_MulI128by10ECarry: {
- /* IROps require a processor that supports ISA 2.07 (Power 8) or newer */
- rc = system(MIN_POWER_ISA " 3.0 ");
+ /* IROps require a processor that supports ISA 3.00 (Power 9) or newer */
+ rc = system(MIN_POWER_ISA " 3.00 ");
rc /= 256;
/* MIN_POWER_ISA returns 0 if underlying HW supports the
* specified ISA or newer. Returns 1 if the HW does not support
Modified: branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c (original)
+++ branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c Mon Oct 17 20:19:26 2016
@@ -64,7 +64,7 @@
return !(isa_level >= 8);
} else {
- fprintf(stderr, "ERROR: invalid ISA version. Valid versions numbers are:\n" );
+ fprintf(stderr, "ERROR: invalid ISA version '%s'. Valid versions numbers are:\n", min_isa);
fprintf(stderr, " 2.05, 2.06, 2.07, 3.00\n" );
exit(2);
}
|
|
From: <sv...@va...> - 2016-10-17 19:11:58
|
Author: sewardj
Date: Mon Oct 17 20:11:51 2016
New Revision: 16058
Log:
Merge from trunk:
16035 Update NEWS file for bugzillas 369175 and 370265
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/NEWS (contents, props changed)
Modified: branches/VALGRIND_3_12_BRANCH/NEWS
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/NEWS (original)
+++ branches/VALGRIND_3_12_BRANCH/NEWS Mon Oct 17 20:11:51 2016
@@ -189,6 +189,8 @@
369441 bad lvec argument crashes process_vm_readv/writev syscall wrappers
369446 valgrind crashes on unknown fcntl command
369439 S390x: Unhandled insns RISBLG/RISBHG and LDE/LDER
+369175 jm_vec_isa_2_07 test crashes on ppc64
+370265 ISA 3.0 HW cap stuff needs updating
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
|
|
From: <sv...@va...> - 2016-10-17 19:11:04
|
Author: sewardj
Date: Mon Oct 17 20:10:57 2016
New Revision: 16057
Log:
Merge from trunk:
16034 Power configure fixes.
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/configure.ac
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0.c
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.vgtest
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.vgtest
branches/VALGRIND_3_12_BRANCH/tests/check_ppc64_auxv_cap
branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c
Modified: branches/VALGRIND_3_12_BRANCH/configure.ac
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/configure.ac (original)
+++ branches/VALGRIND_3_12_BRANCH/configure.ac Mon Oct 17 20:10:57 2016
@@ -1346,6 +1346,7 @@
AC_HWCAP_CONTAINS_FLAG([arch_2_05],[HWCAP_HAS_ISA_2_05])
AC_HWCAP_CONTAINS_FLAG([arch_2_06],[HWCAP_HAS_ISA_2_06])
AC_HWCAP_CONTAINS_FLAG([arch_2_07],[HWCAP_HAS_ISA_2_07])
+AC_HWCAP_CONTAINS_FLAG([arch_3_00],[HWCAP_HAS_ISA_3_00])
AC_HWCAP_CONTAINS_FLAG([htm],[HWCAP_HAS_HTM])
# ISA Levels
@@ -1516,20 +1517,21 @@
-a x$HWCAP_HAS_HTM = xyes )
# isa 3.0 checking
-AC_MSG_CHECKING([that assembler knows ISA 3.0 ])
+AC_MSG_CHECKING([that assembler knows ISA 3.00 ])
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
]], [[
__asm__ __volatile__("cnttzw 1,2 ");
]])], [
-ac_asm_have_isa_3_0=yes
+ac_asm_have_isa_3_00=yes
AC_MSG_RESULT([yes])
], [
-ac_asm_have_isa_3_0=no
+ac_asm_have_isa_3_00=no
AC_MSG_RESULT([no])
])
-AM_CONDITIONAL(HAS_ISA_3_0, test x$ac_asm_have_isa_3_0 = xyes)
+AM_CONDITIONAL(HAS_ISA_3_00, test x$ac_asm_have_isa_3_00 = xyes \
+ -a x$HWCAP_HAS_ISA_3_00 = xyes])
# Check for pthread_create@GLIBC2.0
AC_MSG_CHECKING([for pthread_create@GLIBC2.0()])
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am Mon Oct 17 20:10:57 2016
@@ -102,12 +102,12 @@
jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC)
-if HAS_ISA_3_0
-BUILD_FLAGS_ISA_3_0 = -mcpu=power8
-ISA_3_0_FLAG = -DHAS_ISA_3_0
+if HAS_ISA_3_00
+BUILD_FLAGS_ISA_3_00 = -mcpu=power8
+ISA_3_00_FLAG = -DHAS_ISA_3_00
else
-BUILD_FLAGS_ISA_3_0 =
-ISA_3_0_FLAG =
+BUILD_FLAGS_ISA_3_00 =
+ISA_3_00_FLAG =
endif
test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
@@ -139,8 +139,9 @@
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
-test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_0_FLAG) \
- @FLAG_M64@ $(BUILD_FLAGS_ISA_3_0)
+
+test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00)
test_isa_2_06_part3_LDADD = -lm
test_dfp1_LDADD = -lm
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0.c (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0.c Mon Oct 17 20:10:57 2016
@@ -94,7 +94,7 @@
#include <stdint.h>
/* This test is only valid on machines that support IBM POWER ISA 3.0. */
-#ifdef HAS_ISA_3_0
+#ifdef HAS_ISA_3_00
#include <assert.h>
#include <ctype.h> // isspace
@@ -3957,12 +3957,12 @@
);
}
-#endif // HAS_ISA_3_0
+#endif // HAS_ISA_3_00
int main (int argc, char **argv)
{
-#ifndef HAS_ISA_3_0
- printf("NO ISA 3.0 SUPPORT\n");
+#ifndef HAS_ISA_3_00
+ printf("NO ISA 3.00 SUPPORT\n");
return 0;
#else
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.vgtest
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.vgtest (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.vgtest Mon Oct 17 20:10:57 2016
@@ -1,2 +1,2 @@
-prereq: ../../../tests/check_ppc64_auxv_cap arch_3_0
+prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00
prog: test_isa_3_0 -a -d -q
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.vgtest
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.vgtest (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.vgtest Mon Oct 17 20:10:57 2016
@@ -1,2 +1,2 @@
-prereq: ../../../tests/check_ppc64_auxv_cap arch_3_0
+prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00
prog: test_isa_3_0 -i -m -D -B -N -P
Modified: branches/VALGRIND_3_12_BRANCH/tests/check_ppc64_auxv_cap
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/tests/check_ppc64_auxv_cap (original)
+++ branches/VALGRIND_3_12_BRANCH/tests/check_ppc64_auxv_cap Mon Oct 17 20:10:57 2016
@@ -14,7 +14,7 @@
P_HWCAP_1=" vsx arch_2_06 power6x dfp pa6t arch_2_05 ic_snoop smt booke"
P_HWCAP_2=" cellbe power5+ power5 power4 notb efpdouble efpsingle spe"
P_HWCAP_3=" ucache 4xxmac mmu fpu altivec ppc601 ppc64 ppc32 "
-P_HWCAP2_1=" tar isel ebb dscr htm arch_2_07 "
+P_HWCAP2_1=" tar isel ebb dscr htm arch_2_07 arch_3_00 "
CAPABILITY_FOUND="no"
for POTENTIAL_CAP in $P_HWCAP_1 $P_HWCAP_2 $P_HWCAP_3 $P_HWCAP2_1 ; do
if [ "x$CAPABILITY_WORD" = "x$POTENTIAL_CAP" ]; then
Modified: branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c (original)
+++ branches/VALGRIND_3_12_BRANCH/tests/min_power_isa.c Mon Oct 17 20:10:57 2016
@@ -5,7 +5,7 @@
/* main() */
int main(int argc, char **argv)
{
- /* This program is passed in a minimum ISA that the underlying hardwre
+ /* This program is passed in a minimum ISA that the underlying hardware
* needs to support. If the HW supports this ISA or newer, return 0
* for supported. Otherwise, return 1 for not supported. Return 2 for
* usage error.
@@ -45,8 +45,8 @@
isa_level = 7;
#endif
-#ifdef HAS_ISA_3_0
- if (debug) printf("HAS_ISA_3_0 is set\n");
+#ifdef HAS_ISA_3_00
+ if (debug) printf("HAS_ISA_3_00 is set\n");
isa_level = 8;
#endif
@@ -60,12 +60,12 @@
} else if (strcmp (min_isa, "2.07") == 0) {
return !(isa_level >= 7);
- } else if (strcmp (min_isa, "3.0") == 0) {
+ } else if (strcmp (min_isa, "3.00") == 0) {
return !(isa_level >= 8);
} else {
fprintf(stderr, "ERROR: invalid ISA version. Valid versions numbers are:\n" );
- fprintf(stderr, " 2.05, 2.06, 2.07\n" );
+ fprintf(stderr, " 2.05, 2.06, 2.07, 3.00\n" );
exit(2);
}
|
|
From: <sv...@va...> - 2016-10-17 19:09:11
|
Author: sewardj
Date: Mon Oct 17 20:08:58 2016
New Revision: 16056
Log:
Merge from trunk:
16032 ISA 3.0 BE testsuite fixes
Added:
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
- copied unchanged from r16032, trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
- copied unchanged from r16032, trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/ppc64_helpers.h
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_other.stdout.exp
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/Makefile.am Mon Oct 17 20:08:58 2016
@@ -38,8 +38,10 @@
test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest \
- test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp test_isa_3_0_altivec.vgtest \
- test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp test_isa_3_0_other.vgtest
+ test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp \
+ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \
+ test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp \
+ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest
check_PROGRAMS = \
allexec \
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/ppc64_helpers.h
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/ppc64_helpers.h (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/ppc64_helpers.h Mon Oct 17 20:08:58 2016
@@ -566,12 +566,16 @@
int x;
for (x = 0; x < BUFFER_SIZE; x++)
- switch(t) {
+ /* Don't want each of the 32-bit chunks to be identical. Loads of a
+ * byte from the wrong 32-bit chuck are not detectable if the chunks
+ * are identical.
+ */
+ switch((t+x)%BUFFER_SIZE) {
case 0:
buffer[x] = 0xffffffffffffffff;
break;
case 1:
- buffer[x] = 0xaaaaaaaaaaaaaaaa;
+ buffer[x] = 0x0001020304050607;
break;
case 2:
buffer[x] = 0x5555555555555555;
@@ -595,7 +599,7 @@
unsigned long pattern[PATTERN_SIZE] = {
0xffffffffffffffff,
0xaaaaaaaaaaaaaaaa,
- 0x5555555555555555,
+ 0x5152535455565758,
0x0000000000000000,
0xffaa5599113377cc,
};
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp Mon Oct 17 20:08:58 2016
@@ -635,1922 +635,1922 @@
xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000008000000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000008000000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
-xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7ffffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7ffffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 8000fffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 8000fffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => ffff80000000000180007ffffffffffe FPRF-C FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => ffff80000000000180007ffffffffffe FPRF-C FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87fffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => fffffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => fffffffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007ffffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007ffffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00000000000000008000000000000000 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007ffffffffffeffff800000000001 FPRF-C FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007ffffffffffeffff800000000001 FPRF-C FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00000000000000008000fffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000008000fffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000fffffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000fffffffffffffffe FPRF-C FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 01000000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 01000000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 01003fffffffffff8000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 01003fffffffffff8000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80fdfffffffffffc0000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80fdfffffffffffc0000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG...
[truncated message content] |
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From: <sv...@va...> - 2016-10-17 19:04:37
|
Author: sewardj
Date: Mon Oct 17 20:04:28 2016
New Revision: 3267
Log:
Merge from trunk:
3260 ISA 3.0 BE fixes for various new instructions
Modified:
branches/VEX_3_12_BRANCH/ (props changed)
branches/VEX_3_12_BRANCH/priv/guest_ppc_toIR.c
branches/VEX_3_12_BRANCH/priv/host_ppc_isel.c
Modified: branches/VEX_3_12_BRANCH/priv/guest_ppc_toIR.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_ppc_toIR.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_ppc_toIR.c Mon Oct 17 20:04:28 2016
@@ -19166,10 +19166,6 @@
/* only supported on ISA 3.0 and newer */
IRTemp result = newTemp( Ity_V128 );
IRTemp tmp64 = newTemp( Ity_I64 );
- IRTemp f0 = newTemp( Ity_I64 );
- IRTemp f1 = newTemp( Ity_I64 );
- IRTemp f2 = newTemp( Ity_I64 );
- IRTemp f3 = newTemp( Ity_I64 );
if (!allow_isa_3_0) return False;
DIP("xvcvsphp v%d,v%d\n", XT,XB);
@@ -19178,26 +19174,32 @@
* I64 result to the V128 register to store.
*/
assign( tmp64, unop( Iop_F32toF16x4, mkexpr( vB ) ) );
- assign( f0,binop( Iop_And64,
- mkU64( 0xFFFF ), mkexpr( tmp64 ) ) );
- assign( f1, binop( Iop_And64,
- mkU64( 0xFFFF0000 ), mkexpr( tmp64 ) ) );
- assign( f2, binop( Iop_And64,
- mkU64( 0xFFFF00000000 ), mkexpr( tmp64 ) ) );
- assign( f3, binop( Iop_And64,
- mkU64( 0xFFFF000000000000 ), mkexpr( tmp64 ) ) );
- /* Scater 16-bit float values from returned 64-bit value
+ /* Scatter 16-bit float values from returned 64-bit value
* of V128 result.
*/
- assign( result,
- binop( Iop_Perm8x16,
- binop( Iop_64HLtoV128,
- mkU64( 0 ),
- mkexpr( tmp64 ) ),
- binop ( Iop_64HLtoV128,
- mkU64( 0x0000080900000A0B ),
- mkU64( 0x00000C0D00000E0F ) ) ) );
+ if (host_endness == VexEndnessLE)
+ /* Note location 0 may have a valid number in it. Location
+ * 15 should always be zero. Use 0xF to put zeros in the
+ * desired bytes.
+ */
+ assign( result,
+ binop( Iop_Perm8x16,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp64 ),
+ mkU64( 0 ) ),
+ binop ( Iop_64HLtoV128,
+ mkU64( 0x0F0F00010F0F0203 ),
+ mkU64( 0x0F0F04050F0F0607 ) ) ) );
+ else
+ assign( result,
+ binop( Iop_Perm8x16,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp64 ),
+ mkU64( 0 ) ),
+ binop ( Iop_64HLtoV128,
+ mkU64( 0x0F0F06070F0F0405 ),
+ mkU64( 0x0F0F02030F0F0001 ) ) ) );
putVSReg( XT, mkexpr( result ) );
} else if ( inst_select == 31 ) {
@@ -19526,31 +19528,43 @@
DIP("lxvx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- for ( i = 0; i< 4; i++ ) {
- word[i] = newTemp( Ity_I64 );
-
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 3; i>= 0; i-- ) {
+ word[i] = newTemp( Ity_I64 );
- assign( word[i], unop( Iop_32Uto64,
- load( Ity_I32, irx_addr ) ) );
- ea_off += 4;
- }
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( word[i], unop( Iop_32Uto64,
+ load( Ity_I32, irx_addr ) ) );
+ ea_off += 4;
+ }
- if ( host_endness == VexEndnessBE )
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_Or64,
- mkexpr( word[0] ),
+ mkexpr( word[2] ),
binop( Iop_Shl64,
- mkexpr( word[1] ),
+ mkexpr( word[3] ),
mkU8( 32 ) ) ),
binop( Iop_Or64,
- mkexpr( word[3] ),
+ mkexpr( word[0] ),
binop( Iop_Shl64,
- mkexpr( word[2] ),
+ mkexpr( word[1] ),
mkU8( 32 ) ) ) ) );
+ } else {
+ for ( i = 0; i< 4; i++ ) {
+ word[i] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( word[i], unop( Iop_32Uto64,
+ load( Ity_I32, irx_addr ) ) );
+ ea_off += 4;
+ }
- else
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_Or64,
mkexpr( word[2] ),
@@ -19562,6 +19576,7 @@
binop( Iop_Shl64,
mkexpr( word[1] ),
mkU8( 32 ) ) ) ) );
+ }
break;
}
@@ -19619,78 +19634,104 @@
mkU64( 8 ) ) ),
mkexpr( nb_gt16 ) ) );
-
/* fetch all 16 bytes, we will remove what we don't want later */
- for ( i = 0; i < 8; i++ ) {
- byte[i] = newTemp( Ity_I64 );
- tmp_low[i+1] = newTemp( Ity_I64 );
-
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- ea_off += 1;
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 0; i < 8; i++ ) {
+ byte[i] = newTemp( Ity_I64 );
+ tmp_hi[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
- if ( host_endness == VexEndnessBE )
assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
+
+ assign( tmp_hi[i+1], binop( Iop_Or64,
+ mkexpr( byte[i] ),
+ mkexpr( tmp_hi[i] ) ) );
+ }
+
+ for ( i = 0; i < 8; i++ ) {
+ byte[i+8] = newTemp( Ity_I64 );
+ tmp_low[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
+ assign( byte[i+8], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * ( 7 - i ) ) ) );
- else
- /* Reverse byte order */
+ assign( tmp_low[i+1], binop( Iop_Or64,
+ mkexpr( byte[i+8] ),
+ mkexpr( tmp_low[i] ) ) );
+ }
+ assign( ld_result, binop( Iop_ShlV128,
+ binop( Iop_ShrV128,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
+ mkexpr( shift ) ),
+ mkexpr( shift ) ) );
+ } else {
+ for ( i = 0; i < 8; i++ ) {
+ byte[i] = newTemp( Ity_I64 );
+ tmp_low[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
assign( byte[i], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * i ) ) );
- assign( tmp_low[i+1],
- binop( Iop_Or64,
- mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
- }
-
- for ( i = 0; i < 8; i++ ) {
- byte[i + 8] = newTemp( Ity_I64 );
- tmp_hi[i+1] = newTemp( Ity_I64 );
+ assign( tmp_low[i+1],
+ binop( Iop_Or64,
+ mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
+ }
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- ea_off += 1;
+ for ( i = 0; i < 8; i++ ) {
+ byte[i + 8] = newTemp( Ity_I64 );
+ tmp_hi[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
- if ( host_endness == VexEndnessBE )
- assign( byte[i+8], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * ( 7 - i ) ) ) );
-
- else
- /* Reverse byte order */
assign( byte[i+8], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * i ) ) );
- assign( tmp_hi[i+1], binop( Iop_Or64,
- mkexpr( byte[i+8] ),
- mkexpr( tmp_hi[i] ) ) );
- }
-
- if ( host_endness == VexEndnessBE )
- assign( ld_result, binop( Iop_ShrV128,
- binop( Iop_64HLtoV128,
- mkexpr( tmp_hi[8] ),
- mkexpr( tmp_low[8] ) ),
- mkexpr( shift ) ) );
- else
+ assign( tmp_hi[i+1], binop( Iop_Or64,
+ mkexpr( byte[i+8] ),
+ mkexpr( tmp_hi[i] ) ) );
+ }
assign( ld_result, binop( Iop_ShrV128,
binop( Iop_ShlV128,
binop( Iop_64HLtoV128,
- mkexpr( tmp_low[8] ),
- mkexpr( tmp_hi[8] ) ),
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
mkexpr( shift ) ),
mkexpr( shift ) ) );
+ }
- /* If nb = 0, make out the calculated load result so the stored
+
+ /* If nb = 0, mask out the calculated load result so the stored
* value is zero.
*/
+
putVSReg( XT, binop( Iop_AndV128,
mkexpr( ld_result ),
binop( Iop_64HLtoV128,
@@ -19808,9 +19849,23 @@
/* The load is a 64-bit fetch that is Endian aware, just want
* the lower 32 bits. */
- assign( data, binop( Iop_And64,
- load( Ity_I64, mkexpr( EA ) ),
- mkU64( 0xFFFFFFFF ) ) );
+ if ( host_endness == VexEndnessBE ) {
+ UInt ea_off = 4;
+ IRExpr* irx_addr;
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Sub8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( data, binop( Iop_And64,
+ load( Ity_I64, irx_addr ),
+ mkU64( 0xFFFFFFFF ) ) );
+
+ } else {
+ assign( data, binop( Iop_And64,
+ load( Ity_I64, mkexpr( EA ) ),
+ mkU64( 0xFFFFFFFF ) ) );
+ }
/* Take lower 32-bits and spat across the four word positions */
putVSReg( XT,
@@ -19825,7 +19880,6 @@
binop( Iop_Shl64,
mkexpr( data ),
mkU8( 32 ) ) ) ) );
-
break;
}
@@ -19860,10 +19914,17 @@
case 0x30D: // lxsibzx
{
IRExpr *byte;
+ IRExpr* irx_addr;
DIP("lxsibzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- byte = load( Ity_I64, mkexpr( EA ) );
+ if ( host_endness == VexEndnessBE )
+ irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 7 ) );
+
+ else
+ irx_addr = mkexpr( EA );
+
+ byte = load( Ity_I64, irx_addr );
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_And64,
byte,
@@ -19875,10 +19936,17 @@
case 0x32D: // lxsihzx
{
IRExpr *byte;
+ IRExpr* irx_addr;
DIP("lxsihzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- byte = load( Ity_I64, mkexpr( EA ) );
+ if ( host_endness == VexEndnessBE )
+ irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 6 ) );
+
+ else
+ irx_addr = mkexpr( EA );
+
+ byte = load( Ity_I64, irx_addr );
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_And64,
byte,
@@ -19958,21 +20026,14 @@
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
ea_off += 2;
- if ( host_endness == VexEndnessBE )
assign( h_word[i], binop( Iop_Shl64,
unop( Iop_16Uto64,
load( Ity_I16, irx_addr ) ),
- mkU8( 16 * i ) ) );
+ mkU8( 16 * ( 3 - i ) ) ) );
- else
- assign( h_word[i], binop( Iop_Shl64,
- unop( Iop_16Uto64,
- load( Ity_I16, irx_addr ) ),
- mkU8( 16 * (3 - i) ) ) );
-
- assign( tmp_low[i+1],
- binop( Iop_Or64,
- mkexpr( h_word[i] ), mkexpr( tmp_low[i] ) ) );
+ assign( tmp_low[i+1],
+ binop( Iop_Or64,
+ mkexpr( h_word[i] ), mkexpr( tmp_low[i] ) ) );
}
for ( i = 0; i < 4; i++ ) {
@@ -19986,7 +20047,8 @@
assign( h_word[i+4], binop( Iop_Shl64,
unop( Iop_16Uto64,
load( Ity_I16, irx_addr ) ),
- mkU8( 16 * (3 - i) ) ) );
+ mkU8( 16 * ( 3 - i ) ) ) );
+
assign( tmp_hi[i+1], binop( Iop_Or64,
mkexpr( h_word[i+4] ),
mkexpr( tmp_hi[i] ) ) );
@@ -20020,17 +20082,10 @@
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
ea_off += 1;
- if ( host_endness == VexEndnessBE )
- assign( byte[i], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * i ) ) );
-
- else
- assign( byte[i], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * ( 7 - i ) ) ) );
+ assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
assign( tmp_low[i+1],
binop( Iop_Or64,
@@ -20203,47 +20258,24 @@
unop( Iop_V128to64, mkexpr( vS ) ),
mkU64( 0xFFFFFFFF ) ) );
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
- if ( host_endness == VexEndnessBE ) {
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word3 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word0 ) ) );
-
- } else {
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
- }
+ store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
break;
}
@@ -20849,43 +20881,86 @@
mkU64( 0xFFFF ) ) );
/* Do the 32-bit stores. The store() does an Endian aware store. */
- store( mkexpr( EA ), unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word0 ),
- binop( Iop_Shl64,
- mkexpr( half_word1 ),
- mkU8( 16 ) ) ) ) );
+ if ( host_endness == VexEndnessBE ) {
+ store( mkexpr( EA ), unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word1 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word0 ),
+ mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word2 ),
- binop( Iop_Shl64,
- mkexpr( half_word3 ),
- mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word4 ),
- binop( Iop_Shl64,
- mkexpr( half_word5 ),
- mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word3 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word2 ),
+ mkU8( 16 ) ) ) ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word6 ),
- binop( Iop_Shl64,
- mkexpr( half_word7 ),
- mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word5 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word4 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word7 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word6 ),
+ mkU8( 16 ) ) ) ) );
+
+ } else {
+ store( mkexpr( EA ), unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word0 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word1 ),
+ mkU8( 16 ) ) ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word2 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word3 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word4 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word5 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word6 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word7 ),
+ mkU8( 16 ) ) ) ) );
+ }
break;
}
@@ -20915,27 +20990,54 @@
mkU64( 0xFF ) ) );
}
- for ( i = 0; i < 16; i = i + 4) {
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 0; i < 16; i = i + 4) {
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr,
- unop( Iop_64to32,
- binop( Iop_Or64,
- binop( Iop_Or64,
- mkexpr( byte[i] ),
- binop( Iop_Shl64,
- mkexpr( byte[i+1] ),
- mkU8( 8 ) ) ),
- binop( Iop_Or64,
- binop( Iop_Shl64,
- mkexpr( byte[i+2] ),
- mkU8( 16 ) ),
- binop( Iop_Shl64,
- mkexpr( byte[i+3] ),
- mkU8( 24 ) ) ) ) ) );
+ store( irx_addr,
+ unop( Iop_64to32,
+ binop( Iop_Or64,
+ binop( Iop_Or64,
+ mkexpr( byte[i+3] ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+2] ),
+ mkU8( 8 ) ) ),
+ binop( Iop_Or64,
+ binop( Iop_Shl64,
+ mkexpr( byte[i+1] ),
+ mkU8( 16 ) ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i] ),
+ mkU8( 24 ) ) ) ) ) );
+ ea_off += 4;
+ }
- ea_off += 4;
+ } else {
+ for ( i = 0; i < 16; i = i + 4) {
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr,
+ unop( Iop_64to32,
+ binop( Iop_Or64,
+ binop( Iop_Or64,
+ mkexpr( byte[i] ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+1] ),
+ mkU8( 8 ) ) ),
+ binop( Iop_Or64,
+ binop( Iop_Shl64,
+ mkexpr( byte[i+2] ),
+ mkU8( 16 ) ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+3] ),
+ mkU8( 24 ) ) ) ) ) );
+
+ ea_off += 4;
+ }
}
break;
}
@@ -21314,13 +21416,20 @@
/* store 64-bit float in upper 64-bits of 128-bit register,
* lower 64-bits are zero.
*/
- assign( vT,
- binop( Iop_F64HLtoF128,
- mkexpr( ftmp ),
- unop( Iop_ReinterpI64asF64, mkU64( 0 ) ) ) );
+ if (host_endness == VexEndnessLE)
+ assign( vT,
+ binop( Iop_F64HLtoF128,
+ mkexpr( ftmp ),
+ unop( Iop_ReinterpI64asF64, mkU64( 0 ) ) ) );
+ else
+ assign( vT,
+ binop( Iop_F64HLtoF128,
+ unop( Iop_ReinterpI64asF64, mkU64( 0 ) ),
+ mkexpr( ftmp ) ) );
assign( tmp, unop( Iop_ReinterpF64asI64,
unop( Iop_F128HItoF64, mkexpr( vT ) ) ) );
+
generate_store_FPRF( Ity_I64, tmp );
break;
}
Modified: branches/VEX_3_12_BRANCH/priv/host_ppc_isel.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/host_ppc_isel.c (original)
+++ branches/VEX_3_12_BRANCH/priv/host_ppc_isel.c Mon Oct 17 20:04:28 2016
@@ -2349,7 +2349,8 @@
HReg r2 = newVRegI(env); /* I16*/
HReg r3 = newVRegI(env); /* I16*/
HReg vsrc = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
- PPCAMode *am_off0, *am_off2, *am_off4, *am_off6, *am_off8, *am_off12;
+ PPCAMode *am_off0, *am_off2, *am_off4, *am_off6, *am_off8;
+ PPCAMode *am_off10, *am_off12, *am_off14;
HReg r_aligned16;
sub_from_sp( env, 32 ); // Move SP down
@@ -2364,23 +2365,26 @@
am_off4 = PPCAMode_IR( 4, r_aligned16 );
am_off6 = PPCAMode_IR( 6, r_aligned16 );
am_off8 = PPCAMode_IR( 8, r_aligned16 );
+ am_off10 = PPCAMode_IR( 10, r_aligned16 );
am_off12 = PPCAMode_IR( 12, r_aligned16 );
+ am_off14 = PPCAMode_IR( 14, r_aligned16 );
/* Store v128 result to stack. */
+ addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off0));
+
+ /* fetch four I16 from V128, store into contiguous I64 via stack, */
if (IEndianess == Iend_LE) {
- addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off0));
+ addInstr(env, PPCInstr_Load( 2, r3, am_off12, mode64));
+ addInstr(env, PPCInstr_Load( 2, r2, am_off8, mode64));
+ addInstr(env, PPCInstr_Load( 2, r1, am_off4, mode64));
+ addInstr(env, PPCInstr_Load( 2, r0, am_off0, mode64));
} else {
- addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off8));
+ addInstr(env, PPCInstr_Load( 2, r0, am_off14, mode64));
+ addInstr(env, PPCInstr_Load( 2, r1, am_off10, mode64));
+ addInstr(env, PPCInstr_Load( 2, r2, am_off6, mode64));
+ addInstr(env, PPCInstr_Load( 2, r3, am_off2, mode64));
}
- /* fetch four I16 from V128, store into contiguous I64 via stack, */
-
- /* get 16-bit values */
- addInstr(env, PPCInstr_Load( 2, r3, am_off12, mode64));
- addInstr(env, PPCInstr_Load( 2, r2, am_off8, mode64));
- addInstr(env, PPCInstr_Load( 2, r1, am_off4, mode64));
- addInstr(env, PPCInstr_Load( 2, r0, am_off0, mode64));
-
/* store in contiguous 64-bit values */
addInstr(env, PPCInstr_Store( 2, am_off6, r3, mode64));
addInstr(env, PPCInstr_Store( 2, am_off4, r2, mode64));
@@ -2388,11 +2392,8 @@
addInstr(env, PPCInstr_Store( 2, am_off0, r0, mode64));
/* Fetch I64 */
- if (IEndianess == Iend_LE) {
- addInstr(env, PPCInstr_Load(8, dst, am_off0, mode64));
- } else {
- addInstr(env, PPCInstr_Load(8, dst, am_off8, mode64));
- }
+ addInstr(env, PPCInstr_Load(8, dst, am_off0, mode64));
+
add_to_sp( env, 32 ); // Reset SP
return dst;
}
@@ -4197,7 +4198,12 @@
*/
sub_from_sp( env, 16 );
addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, tmp, zero_r1));
- addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, eight_r1));
+ if (IEndianess == Iend_LE)
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, eight_r1));
+ else
+ /* High 64-bits stored at lower address */
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, zero_r1));
+
add_to_sp( env, 16 );
return fr_dst;
|
|
From: <sv...@va...> - 2016-10-17 17:11:09
|
Author: sewardj
Date: Mon Oct 17 18:11:02 2016
New Revision: 16055
Log:
Merge, from trunk:
16031 mips32: add pselect6 to the list of supported syscalls
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c Mon Oct 17 18:11:02 2016
@@ -1138,7 +1138,7 @@
LINX_ (__NR_readlinkat, sys_readlinkat), // 298
LINX_ (__NR_fchmodat, sys_fchmodat), // 299
LINX_ (__NR_faccessat, sys_faccessat), // 300
- //..
+ LINXY (__NR_pselect6, sys_pselect6), // 301
LINXY (__NR_ppoll, sys_ppoll), // 302
//..
LINX_ (__NR_set_robust_list, sys_set_robust_list), // 309
|
|
From: <sv...@va...> - 2016-10-17 17:02:41
|
Author: sewardj
Date: Mon Oct 17 18:02:32 2016
New Revision: 16054
Log:
Merge, from trunk:
16030 fix building the dfp testcase
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/configure.ac
Modified: branches/VALGRIND_3_12_BRANCH/configure.ac
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/configure.ac (original)
+++ branches/VALGRIND_3_12_BRANCH/configure.ac Mon Oct 17 18:02:32 2016
@@ -1428,8 +1428,12 @@
AC_MSG_CHECKING([that assembler knows DFP])
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
]], [[
+ #ifdef __s390__
+ __asm__ __volatile__("adtr 1, 2, 3")
+ #else
__asm__ __volatile__("dadd 1, 2, 3");
__asm__ __volatile__("dcffix 1, 2");
+ #endif
]])], [
ac_asm_have_dfp=yes
AC_MSG_RESULT([yes])
@@ -1442,8 +1446,12 @@
CFLAGS="-mhard-dfp -Werror"
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
]], [[
+ #ifdef __s390__
+ __asm__ __volatile__("adtr 1, 2, 3")
+ #else
__asm__ __volatile__("dadd 1, 2, 3");
__asm__ __volatile__("dcffix 1, 2");
+ #endif
]])], [
ac_compiler_have_dfp=yes
AC_MSG_RESULT([yes])
@@ -1468,7 +1476,7 @@
AC_MSG_RESULT([no])
])
AM_CONDITIONAL(BUILD_DFP_TESTS, test x$ac_compiler_have_dfp_type = xyes \
- -a xHWCAP_$HAS_DFP = xyes )
+ -a x$HWCAP_HAS_DFP = xyes )
# HTM (Hardware Transactional Memory)
|
Author: sewardj
Date: Mon Oct 17 18:01:34 2016
New Revision: 16053
Log:
Merge, from trunk:
16029 actually test high-word by providing the plumbing...
Added:
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.stderr.exp
- copied unchanged from r16029, trunk/none/tests/s390x/high-word.stderr.exp
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.stdout.exp
- copied unchanged from r16029, trunk/none/tests/s390x/high-word.stdout.exp
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.vgtest
- copied unchanged from r16029, trunk/none/tests/s390x/high-word.vgtest
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
|
|
From: <sv...@va...> - 2016-10-17 17:00:50
|
Author: sewardj
Date: Mon Oct 17 18:00:44 2016
New Revision: 16052
Log:
Merge, from trunk:
16028 s390/highword fix compile warning with some compilers
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.c
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.c (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.c Mon Oct 17 18:00:44 2016
@@ -5,8 +5,8 @@
#define BRASLCLOBBER "0","1","2","3","4","5","14", \
"f0","f1","f2","f3","f4","f5","f6","f7","memory","cc"
-static void inner_iter() { putchar('.'); }
-static void outer_iter() { putchar('+'); }
+void inner_iter() { putchar('.'); }
+void outer_iter() { putchar('+'); }
static void
check_brcth(int m, int n)
|
|
From: <sv...@va...> - 2016-10-17 17:00:10
|
Author: sewardj
Date: Mon Oct 17 17:59:59 2016
New Revision: 16051
Log:
Merge, from trunk:
16027 s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
Added:
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/high-word.c
- copied unchanged from r16027, trunk/none/tests/s390x/high-word.c
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/NEWS (contents, props changed)
branches/VALGRIND_3_12_BRANCH/docs/internals/s390-opcodes.csv
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/Makefile.am
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.c
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.stdout.exp
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.c
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.stdout.exp
branches/VALGRIND_3_12_BRANCH/none/tests/s390x/opcodes.h
Modified: branches/VALGRIND_3_12_BRANCH/NEWS
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/NEWS (original)
+++ branches/VALGRIND_3_12_BRANCH/NEWS Mon Oct 17 17:59:59 2016
@@ -188,6 +188,7 @@
369402 Bad set/get_thread_area pointer crashes valgrind
369441 bad lvec argument crashes process_vm_readv/writev syscall wrappers
369446 valgrind crashes on unknown fcntl command
+369439 S390x: Unhandled insns RISBLG/RISBHG and LDE/LDER
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
Modified: branches/VALGRIND_3_12_BRANCH/docs/internals/s390-opcodes.csv
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/docs/internals/s390-opcodes.csv (original)
+++ branches/VALGRIND_3_12_BRANCH/docs/internals/s390-opcodes.csv Mon Oct 17 17:59:59 2016
@@ -68,7 +68,7 @@
epair,"extract primary ASN and instance",N/A,"privileged instruction"
ereg,"extract stacked registers","not implemented",
esar,"extract secondary ASN",N/A,"privileged instruction",
-esair,"extract secondary ASN and instance,N/A,"privileged instruction",
+esair,"extract secondary ASN and instance",N/A,"privileged instruction",
esta,"extract stacked state","not implemented",
ex,execute,implemented,
hdr,"halve (long)","won't do","hfp instruction"
@@ -125,7 +125,7 @@
msta,"modify stacked state","not implemented",
mvc,move,implemented,
mvcdk,"move with destination key",N/A,"privileged instruction"
-mvcin,"move inverse","not implemented",
+mvcin,"move inverse",implemented,
mvck,"move with key",N/A,"privileged instruction"
mvcl,"move long",implemented,
mvcp,"move to primary",N/A,"privileged instruction"
@@ -548,8 +548,8 @@
lxd,"load lengthened long to extended hfp","won't do","hfp instruction"
lxer,"load lengthened short to extended hfp","won't do","hfp instruction"
lxe,"load lengthened short to extended hfp","won't do","hfp instruction"
-lder,"load lengthened short to long hfp","won't do","hfp instruction"
-lde,"load lengthened short to long hfp","won't do","hfp instruction"
+lder,"load lengthened short to long hfp",implemented,"hfp instruction"
+lde,"load lengthened short to long hfp",implemented,"hfp instruction"
lnxr,"load negative extended hfp","won't do","hfp instruction"
lpxr,"load positive extended hfp","won't do","hfp instruction"
lexr,"load rounded extended to short hfp","won't do","hfp instruction"
@@ -840,7 +840,7 @@
alhhlr,"add logical high low",implemented,
alsih,"add logical with signed immediate high with cc",implemented,
alsihn,"add logical with signed immediate high no cc",implemented,
-brcth,"branch relative on count high","not implemented",
+brcth,"branch relative on count high",implemented,
chhr,"compare high high",implemented,
chlr,"compare high low",implemented,
chf,"compare high",implemented,
@@ -854,8 +854,8 @@
lfh,"load high",implemented,
llch,"load logical character high",implemented,
llhh,"load logical halfword high",implemented,
-risbhg,"rotate then insert selected bits high","not implemented",
-risblg,"rotate then insert selected bits low","not implemented",
+risbhg,"rotate then insert selected bits high",implemented,
+risblg,"rotate then insert selected bits low",implemented,
stch,"store character high",implemented,
sthh,"store halfword high",implemented,
stfh,"store high",implemented,
@@ -980,3 +980,520 @@
cxzt,"convert from zoned extended","not implemented",zEC12,
czdt,"convert to zoned long","not implemented",zEC12,
czxt,"convert to zoned extended","not implemented",zEC12,
+vfsdb,"vector fp subtract","not implemented",z13
+vlpf,"vector load positive word","not implemented",z13
+verllh,"vector element rotate left logical mem halfword","not implemented",z13
+vzero,"vector set to zero","not implemented",z13
+vmalof,"vector multiply and add logical odd word","not implemented",z13
+vleif,"vector load word element immediate","not implemented",z13
+vlpb,"vector load positive byte","not implemented",z13
+vmxlh,"vector maximum logical halfword","not implemented",z13
+vpksfs,"vector pack saturate word","not implemented",z13
+vfenezh,"vector find element not equal halfword","not implemented",z13
+vecl,"vector element compare logical","not implemented",z13
+verimb,"vector element rotate and insert under mask byte","not implemented",z13
+vaccq,"vector add compute carry quadword","not implemented",z13
+vleh,"vector load halfword element","not implemented",z13
+vst,"vector store","not implemented",z13
+vsteg,"vector store double word element","not implemented",z13
+vmnf,"vector minimum word","not implemented",z13
+vavgl,"vector average logical","not implemented",z13
+vfpsodb,"vector fp perform sign operation","not implemented",z13
+llzrgf,"load logical and zero rightmost bytes 32->64","not implemented",z13
+vledb,"vector fp load rounded","not implemented",z13
+vldeb,"vector fp load lengthened","not implemented",z13
+vclzg,"vector count leading zeros doubleword","not implemented",z13
+vecg,"vector element compare double word","not implemented",z13
+vpksgs,"vector pack saturate double word","not implemented",z13
+vsel,"vector select","not implemented",z13
+vllezb,"vector load logical byte element and zero","not implemented",z13
+vfaezh,"vector find any element equal","not implemented",z13
+vftci,"vector fp test data class immediate","not implemented",z13
+veclb,"vector element compare logical byte","not implemented",z13
+vuplhw,"vector unpack low halfword","not implemented",z13
+veslvb,"vector element shift left reg byte","not implemented",z13
+vuplh,"vector unpack logical high","not implemented",z13
+vlde,"vector fp load lengthened","not implemented",z13
+vmoh,"vector multiply odd halfword","not implemented",z13
+vfaehs,"vector find any element equal","not implemented",z13
+vftcidb,"vector fp test data class immediate","not implemented",z13
+vaq,"vector add quad word","not implemented",z13
+vlgvh,"vector load gr from vr halfword element","not implemented",z13
+vchlg,"vector compare high logical double word","not implemented",z13
+vlvgp,"vector load VR from GRs disjoint","not implemented",z13
+vceqg,"vector compare equal double word","not implemented",z13
+vfeezh,"vector find element equal halfword","not implemented",z13
+vlvgf,"vector load VR word element from GR","not implemented",z13
+vsteb,"vector store byte element","not implemented",z13
+vgmb,"vector generate mask byte","not implemented",z13
+vpklsf,"vector pack logical saturate word","not implemented",z13
+vmao,"vector multiply and add odd","not implemented",z13
+vchf,"vector compare high word","not implemented",z13
+vesraf,"vector element shift right arithmetic mem word","not implemented",z13
+vsbiq,"vector subtract with borrow indication quadword","not implemented",z13
+vuphb,"vector unpack high byte","not implemented",z13
+vgfmb,"vector galois field multiply sum byte","not implemented",z13
+vrepih,"vector replicate immediate halfword","not implemented",z13
+vcdlg,"vector fp convert from logical 64 bit","not implemented",z13
+cxpt,"convert from packed to extended dfp","not implemented",z13
+vceqb,"vector compare equal byte","not implemented",z13
+vstrczfs,"vector string range compare word","not implemented",z13
+vpklshs,"vector pack logical saturate halfword","not implemented",z13
+vlvgb,"vector load VR byte element from GR","not implemented",z13
+lcbb,"load count to block boundary","not implemented",z13
+vlcf,"vector load complement word","not implemented",z13
+vlvg,"vector load VR element from GR","not implemented",z13
+vmalef,"vector multiply and add logical even word","not implemented",z13
+vn,"vector and","not implemented",z13
+vmae,"vector multiply and add even","not implemented",z13
+vstrc,"vector string range compare","not implemented",z13
+vfcedb,"vector fp compare equal","not implemented",z13
+vgfm,"vector galois field multiply sum","not implemented",z13
+vlrepb,"vector load and replicate byte elements","not implemented",z13
+vgfmag,"vector galois field multiply sum and accumulate doubleword","not implemented",z13
+vflndb,"vector fp perform sign operation","not implemented",z13
+vmaeb,"vector multiply and add even byte","not implemented",z13
+vpkg,"vector pack double word","not implemented",z13
+vsb,"vector subtract byte","not implemented",z13
+vchl,"vector compare high logical","not implemented",z13
+vlvgh,"vector load VR halfword element from GR","not implemented",z13
+locghi,"load halfword immediate on condition into 64 bit gpr","not implemented",z13
+vmalb,"vector multiply and add low byte","not implemented",z13
+vchlgs,"vector compare high logical double word","not implemented",z13
+vstef,"vector store word element","not implemented",z13
+lzrf,"load and zero rightmost byte 32->32","not implemented",z13
+vmrlh,"vector merge low halfword","not implemented",z13
+vchbs,"vector compare high byte","not implemented",z13
+vesrlf,"vector element shift right logical mem word","not implemented",z13
+vmxf,"vector maximum word","not implemented",z13
+vgmh,"vector generate mask halfword","not implemented",z13
+vfenezb,"vector find element not equal byte","not implemented",z13
+vpklsgs,"vector pack logical saturate double word","not implemented",z13
+vpksg,"vector pack saturate double word","not implemented",z13
+vfaeh,"vector find any element equal halfword","not implemented",z13
+vmlof,"vector multiply logical odd word","not implemented",z13
+vmahh,"vector multiply and add high halfword","not implemented",z13
+vx,"vector exclusive or","not implemented",z13
+vchlfs,"vector compare high logical word","not implemented",z13
+vacccq,"vector add with carry compute carry quadword","not implemented",z13
+vchb,"vector compare high byte","not implemented",z13
+vmaloh,"vector multiply and add logical odd halfword","not implemented",z13
+vmleh,"vector multiply logical even halfword","not implemented",z13
+verimh,"vector element rotate and insert under mask halfword","not implemented",z13
+vlrepf,"vector load and replicate word elements","not implemented",z13
+vgfmg,"vector galois field multiply sum doubleword","not implemented",z13
+vpklsg,"vector pack logical saturate double word","not implemented",z13
+vesrlvf,"vector element shift right logical reg word","not implemented",z13
+vrepg,"vector replicate double word","not implemented",z13
+vmalob,"vector multiply and add logical odd byte","not implemented",z13
+vmxb,"vector maximum byte","not implemented",z13
+vmnl,"vector minimum logical","not implemented",z13
+vmng,"vector minimum doubleword","not implemented",z13
+vchlb,"vector compare high logical byte","not implemented",z13
+wfadb,"vector fp add","not implemented",z13
+vmrl,"vector merge low","not implemented",z13
+wfk,"vector fp compare and signal scalar","not implemented",z13
+vno,"vector nor","not implemented",z13
+vstrcf,"vector string range compare word","not implemented",z13
+vfmsdb,"vector fp multiply and subtract","not implemented",z13
+vavgh,"vector average half word","not implemented",z13
+vchlhs,"vector compare high logical half word","not implemented",z13
+vah,"vector add halfword","not implemented",z13
+vmalhh,"vector multiply and add logical high halfword","not implemented",z13
+wldeb,"vector fp load lengthened","not implemented",z13
+vmrh,"vector merge high","not implemented",z13
+vclgdb,"vector fp convert to logical 64 bit","not implemented",z13
+wfsqdb,"vector fp square root","not implemented",z13
+vpopct,"vector population count","not implemented",z13
+vfenef,"vector find element not equal word","not implemented",z13
+vgfmf,"vector galois field multiply sum word","not implemented",z13
+vgmf,"vector generate mask word","not implemented",z13
+vleg,"vector load double word element","not implemented",z13
+vmn,"vector minimum","not implemented",z13
+vrepi,"vector replicate immediate","not implemented",z13
+vsegb,"vector sign extend byte to double word","not implemented",z13
+cpxt,"convert from extended dfp to packed","not implemented",z13
+wftcidb,"vector fp test data class immediate","not implemented",z13
+wfchedbs,"vector fp compare high or equal","not implemented",z13
+vpks,"vector pack saturate","not implemented",z13
+veslg,"vector element shift left mem doubleword","not implemented",z13
+vupllb,"vector unpack logical low byte","not implemented",z13
+vscbig,"vector subtract compute borrow indication doubleword","not implemented",z13
+vsegh,"vector sign extend halfword to double word","not implemented",z13
+vsumb,"vector sum across word - byte elements","not implemented",z13
+vgeg,"vector gather element 8 byte elements","not implemented",z13
+vcgd,"vector fp convert to fixed 64 bit","not implemented",z13
+vuplhb,"vector unpack logical high byte","not implemented",z13
+verllv,"vector element rotate left logical reg","not implemented",z13
+vavgb,"vector average byte","not implemented",z13
+veclh,"vector element compare logical half word","not implemented",z13
+vfmadb,"vector fp multiply and add","not implemented",z13
+vesravb,"vector element shift right arithmetic reg byte","not implemented",z13
+vmaleb,"vector multiply and add logical even byte","not implemented",z13
+vuplf,"vector unpack low word","not implemented",z13
+vsbi,"vector subtract with borrow indication","not implemented",z13
+vupll,"vector unpack logical low","not implemented",z13
+vmrhh,"vector merge high halfword","not implemented",z13
+vfenezbs,"vector find element not equal byte","not implemented",z13
+vmhb,"vector multiply high byte","not implemented",z13
+vfmdb,"vector fp multiply","not implemented",z13
+vesrlg,"vector element shift right logical mem doubleword","not implemented",z13
+vmahb,"vector multiply and add high byte","not implemented",z13
+vstrczf,"vector string range compare word","not implemented",z13
+wfcedb,"vector fp compare equal","not implemented",z13
+vscbih,"vector subtract compute borrow indication halfword","not implemented",z13
+vlch,"vector load complement halfword","not implemented",z13
+vfenebs,"vector find element not equal byte","not implemented",z13
+vpklsh,"vector pack logical saturate halfword","not implemented",z13
+vlgv,"vector load gr from vr element","not implemented",z13
+vchfs,"vector compare high word","not implemented",z13
+vctzb,"vector count trailing zeros byte","not implemented",z13
+vfaef,"vector find any element equal word","not implemented",z13
+vstrch,"vector string range compare halfword","not implemented",z13
+wfidb,"vector load fp integer","not implemented",z13
+vmrhb,"vector merge high byte","not implemented",z13
+vuph,"vector unpack high","not implemented",z13
+vperm,"vector permute","not implemented",z13
+vrep,"vector replicate","not implemented",z13
+vmalhb,"vector multiply and add logical high byte","not implemented",z13
+vleib,"vector load byte element immediate","not implemented",z13
+vavg,"vector average","not implemented",z13
+vfenefs,"vector find element not equal word","not implemented",z13
+vsumh,"vector sum across word - halfword elements","not implemented",z13
+vchh,"vector compare high half word","not implemented",z13
+wcdgb,"vector fp convert from fixed 64 bit","not implemented",z13
+verllvb,"vector element rotate left logical reg byte","not implemented",z13
+vec,"vector element compare","not implemented",z13
+vpdi,"vector permute double word immediate","not implemented",z13
+vfchedb,"vector fp compare high or equal","not implemented",z13
+vchlh,"vector compare high logical half word","not implemented",z13
+vmaleh,"vector multiply and add logical even halfword","not implemented",z13
+vstrcb,"vector string range compare byte","not implemented",z13
+vsumqg,"vector sum across quadword - doubleword elements","not implemented",z13
+vlc,"vector load complement","not implemented",z13
+vlreph,"vector load and replicate halfword elements","not implemented",z13
+vistrb,"vector isolate string byte","not implemented",z13
+vmo,"vector multiply odd","not implemented",z13
+vmxg,"vector maximum doubleword","not implemented",z13
+vsrab,"vector shift right arithmetic by byte","not implemented",z13
+vsbcbiq,"vector subtract with borrow compute borrow indication quadword","not implemented",z13
+wfchdb,"vector fp compare high","not implemented",z13
+vmlhf,"vector multiply logical high word","not implemented",z13
+vesra,"vector element shift right arithmetic mem","not implemented",z13
+vmnh,"vector minimum halfword","not implemented",z13
+vled,"vector fp load rounded","not implemented",z13
+vstrczbs,"vector string range compare byte","not implemented",z13
+vaccb,"vector add compute carry byte","not implemented",z13
+vmahf,"vector multiply and add high word","not implemented",z13
+wfcedbs,"vector fp compare equal","not implemented",z13
+vmeh,"vector multiply even halfword","not implemented",z13
+vclzb,"vector count leading zeros byte","not implemented",z13
+vmh,"vector multiply high","not implemented",z13
+vllez,"vector load logical element and zero","not implemented",z13
+vnc,"vector and with complement","not implemented",z13
+vesrlvg,"vector element shift right logical reg doubleword","not implemented",z13
+vrepif,"vector replicate immediate word","not implemented",z13
+vfd,"vector fp divide","not implemented",z13
+vesrlb,"vector element shift right logical mem byte","not implemented",z13
+vavglg,"vector average logical double word","not implemented",z13
+vpksh,"vector pack saturate halfword","not implemented",z13
+veslv,"vector element shift left reg","not implemented",z13
+vone,"vector set to ones","not implemented",z13
+vsrl,"vector shift right logical","not implemented",z13
+vcdg,"vector fp convert from fixed 64 bit","not implemented",z13
+vmlhw,"vector multiply low halfword","not implemented",z13
+vscbib,"vector subtract compute borrow indication byte","not implemented",z13
+vrepib,"vector replicate immediate byte","not implemented",z13
+vpk,"vector pack","not implemented",z13
+vmhh,"vector multiply high halfword","not implemented",z13
+vfaezhs,"vector find any element equal","not implemented",z13
+vaf,"vector add word","not implemented",z13
+vmalh,"vector multiply and add logical high","not implemented",z13
+vgmg,"vector generate mask double word","not implemented",z13
+vstrczh,"vector string range compare halfword","not implemented",z13
+vag,"vector add double word","not implemented",z13
+vllezf,"vector load logical word element and zero","not implemented",z13
+vistrbs,"vector isolate string byte","not implemented",z13
+vstm,"vector store multiple","not implemented",z13
+vgfmh,"vector galois field multiply sum halfword","not implemented",z13
+verllvf,"vector element rotate left logical reg word","not implemented",z13
+vsra,"vector shift right arithmetic","not implemented",z13
+vslb,"vector shift left by byte","not implemented",z13
+vesravf,"vector element shift right arithmetic reg word","not implemented",z13
+vfcedbs,"vector fp compare equal","not implemented",z13
+vceqbs,"vector compare equal byte","not implemented",z13
+vsbcbi,"vector subtract with borrow compute borrow indication","not implemented",z13
+vmle,"vector multiply logical even","not implemented",z13
+vfaezfs,"vector find any element equal","not implemented",z13
+vsumg,"vector sum across doubleword","not implemented",z13
+vfaeb,"vector find any element equal byte","not implemented",z13
+vleih,"vector load halfword element immediate","not implemented",z13
+vmlob,"vector multiply logical odd byte","not implemented",z13
+vllezh,"vector load logical halfword element and zero","not implemented",z13
+vmalo,"vector multiply and add logical odd","not implemented",z13
+vclzh,"vector count leading zeros halfword","not implemented",z13
+vesravh,"vector element shift right arithmetic reg halfword","not implemented",z13
+vceqfs,"vector compare equal word","not implemented",z13
+vlp,"vector load positive","not implemented",z13
+wfmsdb,"vector fp multiply and subtract","not implemented",z13
+vstrcbs,"vector string range compare byte","not implemented",z13
+vaccg,"vector add compute carry doubleword","not implemented",z13
+wfsdb,"vector fp subtract","not implemented",z13
+vfee,"vector find element equal","not implemented",z13
+vmxh,"vector maximum halfword","not implemented",z13
+vtm,"vector test under mask","not implemented",z13
+vctzf,"vector count trailing zeros word","not implemented",z13
+vfms,"vector fp multiply and subtract","not implemented",z13
+vavgg,"vector average double word","not implemented",z13
+vistr,"vector isolate string","not implemented",z13
+vesrlvb,"vector element shift right logical reg byte","not implemented",z13
+vesrl,"vector element shift right logical mem","not implemented",z13
+vmah,"vector multiply and add high","not implemented",z13
+vesrlvh,"vector element shift right logical reg halfword","not implemented",z13
+vesrah,"vector element shift right arithmetic mem halfword","not implemented",z13
+vrepig,"vector replicate immediate double word","not implemented",z13
+wfddb,"vector fp divide","not implemented",z13
+vmhf,"vector multiply high word","not implemented",z13
+vupllf,"vector unpack logical low word","not implemented",z13
+veslf,"vector element shift left mem word","not implemented",z13
+wflpdb,"vector fp perform sign operation","not implemented",z13
+vscbi,"vector subtract compute borrow indication","not implemented",z13
+vmnlb,"vector minimum logical byte","not implemented",z13
+veslh,"vector element shift left mem halfword","not implemented",z13
+vfaebs,"vector find any element equal","not implemented",z13
+vleb,"vector load byte element","not implemented",z13
+vfaezb,"vector find any element equal","not implemented",z13
+vlbb,"vector load to block boundary","not implemented",z13
+vflcdb,"vector fp perform sign operation","not implemented",z13
+vmlo,"vector multiply logical odd","not implemented",z13
+vlgvf,"vector load gr from vr word element","not implemented",z13
+vavgf,"vector average word","not implemented",z13
+veslvh,"vector element shift left reg halfword","not implemented",z13
+vacch,"vector add compute carry halfword","not implemented",z13
+vsumgh,"vector sum across doubleword - halfword","not implemented",z13
+vmaeh,"vector multiply and add even halfword","not implemented",z13
+vmnlh,"vector minimum logical halfword","not implemented",z13
+vstl,"vector store with length","not implemented",z13
+wfmadb,"vector fp multiply and add","not implemented",z13
+vme,"vector multiply even","not implemented",z13
+wfmdb,"vector fp multiply","not implemented",z13
+wflcdb,"vector fp perform sign operation","not implemented",z13
+vreph,"vector replicate halfword","not implemented",z13
+vclgd,"vector fp convert to logical 64 bit","not implemented",z13
+vpkls,"vector pack logical saturate","not implemented",z13
+vsf,"vector subtract word","not implemented",z13
+vflpdb,"vector fp perform sign operation","not implemented",z13
+vesrlv,"vector element shift right logical reg","not implemented",z13
+vpklsfs,"vector pack logical saturate word","not implemented",z13
+vcdgb,"vector fp convert from fixed 64 bit","not implemented",z13
+verll,"vector element rotate left logical mem","not implemented",z13
+vfeezf,"vector find element equal word","not implemented",z13
+wclgdb,"vector fp convert to logical 64 bit","not implemented",z13
+vgfma,"vector galois field multiply sum and accumulate","not implemented",z13
+vmob,"vector multiply odd byte","not implemented",z13
+vfeneb,"vector find element not equal byte","not implemented",z13
+vfene,"vector find element not equal","not implemented",z13
+vfenezfs,"vector find element not equal word","not implemented",z13
+vmal,"vector multiply and add low","not implemented",z13
+vfchdb,"vector fp compare high","not implemented",z13
+vfeezb,"vector find element equal byte","not implemented",z13
+vfae,"vector find any element equal","not implemented",z13
+vfchdbs,"vector fp compare high","not implemented",z13
+vsceg,"vector scatter element 8 byte","not implemented",z13
+vfeezfs,"vector find element equal word","not implemented",z13
+vsumgf,"vector sum across doubleword - word","not implemented",z13
+vmnb,"vector minimum byte","not implemented",z13
+vlef,"vector load word element","not implemented",z13
+vceqgs,"vector compare equal double word","not implemented",z13
+vech,"vector element compare half word","not implemented",z13
+vctz,"vector count trailing zeros","not implemented",z13
+vmloh,"vector multiply logical odd halfword","not implemented",z13
+vaccc,"vector add with carry compute carry","not implemented",z13
+vmale,"vector multiply and add logical even","not implemented",z13
+vsteh,"vector store halfword element","not implemented",z13
+vceq,"vector compare equal","not implemented",z13
+vfchedbs,"vector fp compare high or equal","not implemented",z13
+vesl,"vector element shift left mem","not implemented",z13
+vesrav,"vector element shift right arithmetic reg","not implemented",z13
+vfma,"vector fp multiply and add","not implemented",z13
+vmnlg,"vector minimum logical doubleword","not implemented",z13
+vclz,"vector count leading zeros","not implemented",z13
+vmrlf,"vector merge low word","not implemented",z13
+vistrh,"vector isolate string halfword","not implemented",z13
+vmxlb,"vector maximum logical byte","not implemented",z13
+vfs,"vector fp subtract","not implemented",z13
+vfm,"vector fp multiply","not implemented",z13
+vll,"vector load with length","not implemented",z13
+vleig,"vector load double word element immediate","not implemented",z13
+vfaezbs,"vector find any element equal","not implemented",z13
+veslvg,"vector element shift left reg doubleword","not implemented",z13
+locfh,"load high on condition from memory","not implemented",z13
+vfeeb,"vector find element equal byte","not implemented",z13
+vsumq,"vector sum across quadword","not implemented",z13
+vmleb,"vector multiply logical even byte","not implemented",z13
+vesrag,"vector element shift right arithmetic mem doubleword","not implemented",z13
+vceqh,"vector compare equal half word","not implemented",z13
+vmalf,"vector multiply and add low word","not implemented",z13
+vstrchs,"vector string range compare halfword","not implemented",z13
+vcgdb,"vector fp convert to fixed 64 bit","not implemented",z13
+vsq,"vector subtract quadword","not implemented",z13
+vnot,"vector not","not implemented",z13
+vfch,"vector fp compare high","not implemented",z13
+lochi,"load halfword immediate on condition into 32 bit gpr","not implemented",z13
+verllvh,"vector element rotate left logical reg halfword","not implemented",z13
+cpdt,"convert from long dfp to packed","not implemented",z13
+vrepb,"vector replicate byte","not implemented",z13
+ppno,"perform pseudorandom number operation","not implemented",z13
+vfeef,"vector find element equal word","not implemented",z13
+vac,"vector add with carry","not implemented",z13
+verimf,"vector element rotate and insert under mask word","not implemented",z13
+vfi,"vector load fp integer","not implemented",z13
+vistrfs,"vector isolate string word","not implemented",z13
+vecf,"vector element compare word","not implemented",z13
+vfeezbs,"vector find element equal byte","not implemented",z13
+wflndb,"vector fp perform sign operation","not implemented",z13
+vscbif,"vector subtract compute borrow indication word","not implemented",z13
+vchhs,"vector compare high half word","not implemented",z13
+vmlb,"vector multiply low byte","not implemented",z13
+veslvf,"vector element shift left reg word","not implemented",z13
+vfaefs,"vector find any element equal","not implemented",z13
+vlrep,"vector load and replicate","not implemented",z13
+vaccf,"vector add compute carry word","not implemented",z13
+vpksf,"vector pack saturate word","not implemented",z13
+vavglf,"vector average logical word","not implemented",z13
+vmef,"vector multiply even word","not implemented",z13
+vuplhh,"vector unpack logical high halfword","not implemented",z13
+vmxl,"vector maximum logical","not implemented",z13
+vgfmah,"vector galois field multiply sum and accumulate halfword","not implemented",z13
+vmalhf,"vector multiply and add logical high word","not implemented",z13
+vsh,"vector subtract halfword","not implemented",z13
+vuplb,"vector unpack low byte","not implemented",z13
+vsegf,"vector sign extend word to double word","not implemented",z13
+vmxlf,"vector maximum logical word","not implemented",z13
+wcdlgb,"vector fp convert from logical 64 bit","not implemented",z13
+vstrczb,"vector string range compare byte","not implemented",z13
+vsldb,"vector shift left double by byte","not implemented",z13
+vesrlh,"vector element shift right logical mem halfword","not implemented",z13
+cdpt,"convert from packed to long dfp","not implemented",z13
+vlcb,"vector load complement byte","not implemented",z13
+wfpsodb,"vector fp perform sign operation","not implemented",z13
+vsum,"vector sum across word","not implemented",z13
+vfeehs,"vector find element equal halfword","not implemented",z13
+vml,"vector multiply low","not implemented",z13
+vuphh,"vector unpack high halfword","not implemented",z13
+vavglb,"vector average logical byte","not implemented",z13
+vmlf,"vector multiply low word","not implemented",z13
+wledb,"vector fp load rounded","not implemented",z13
+vstrcfs,"vector string range compare word","not implemented",z13
+wcgdb,"vector fp convert to fixed 64 bit","not implemented",z13
+vlph,"vector load positive halfword","not implemented",z13
+vfenezf,"vector find element not equal word","not implemented",z13
+vseg,"vector sign extend to double word","not implemented",z13
+vcksm,"vector checksum","not implemented",z13
+vsrlb,"vector shift right logical by byte","not implemented",z13
+verimg,"vector element rotate and insert under mask doubleword","not implemented",z13
+vesravg,"vector element shift right arithmetic reg doubleword","not implemented",z13
+vmlhh,"vector multiply logical high halfword","not implemented",z13
+vfaezf,"vector find any element equal","not implemented",z13
+vfenehs,"vector find element not equal halfword","not implemented",z13
+vlr,"vector register load","not implemented",z13
+vgbm,"vector generate byte mask","not implemented",z13
+vmnlf,"vector minimum logical word","not implemented",z13
+vlm,"vector load multiple","not implemented",z13
+vmrlb,"vector merge low byte","not implemented",z13
+vavglh,"vector average logical half word","not implemented",z13
+wfkdb,"vector fp compare and signal scalar","not implemented",z13
+veslb,"vector element shift left mem byte","not implemented",z13
+wfchedb,"vector fp compare high or equal","not implemented",z13
+vllezg,"vector load logical double word element and zero","not implemented",z13
+vmaob,"vector multiply and add odd byte","not implemented",z13
+vmrhf,"vector merge high word","not implemented",z13
+vchg,"vector compare high double word","not implemented",z13
+locfhr,"load high on condition from gpr","not implemented",z13
+vlpg,"vector load positive doubleword","not implemented",z13
+vcdlgb,"vector fp convert from logical 64 bit","not implemented",z13
+vstrczhs,"vector string range compare halfword","not implemented",z13
+vecb,"vector element compare byte","not implemented",z13
+vmxlg,"vector maximum logical doubleword","not implemented",z13
+vfpso,"vector fp perform sign operation","not implemented",z13
+verim,"vector element rotate and insert under mask","not implemented",z13
+vsumqf,"vector sum across quadword - word elements","not implemented",z13
+vfeefs,"vector find element equal word","not implemented",z13
+vfche,"vector fp compare high or equal","not implemented",z13
+vistrhs,"vector isolate string halfword","not implemented",z13
+vsl,"vector shift left","not implemented",z13
+vfenezhs,"vector find element not equal halfword","not implemented",z13
+vsg,"vector subtract doubleword","not implemented",z13
+vclzf,"vector count leading zeros word","not implemented",z13
+wfcdb,"vector fp compare scalar","not implemented",z13
+vmaoh,"vector multiply and add odd halfword","not implemented",z13
+vchgs,"vector compare high double word","not implemented",z13
+vchlf,"vector compare high logical word","not implemented",z13
+va,"vector add","not implemented",z13
+vmrlg,"vector merge low double word","not implemented",z13
+vlcg,"vector load complement doubleword","not implemented",z13
+vceqf,"vector compare equal word","not implemented",z13
+vacq,"vector add with carry quadword","not implemented",z13
+vmaof,"vector multiply and add odd word","not implemented",z13
+vfadb,"vector fp add","not implemented",z13
+vmlef,"vector multiply logical even word","not implemented",z13
+wfc,"vector fp compare scalar","not implemented",z13
+vmx,"vector maximum","not implemented",z13
+vmlh,"vector multiply logical high","not implemented",z13
+vmeb,"vector multiply even byte","not implemented",z13
+vfddb,"vector fp divide","not implemented",z13
+vpkshs,"vector pack saturate halfword","not implemented",z13
+vpkf,"vector pack word","not implemented",z13
+vlrepg,"vector load and replicate double word elements","not implemented",z13
+vmaef,"vector multiply and add even word","not implemented",z13
+vfeneh,"vector find element not equal halfword","not implemented",z13
+vgfmaf,"vector galois field multiply sum and accumulate word","not implemented",z13
+vctzg,"vector count trailing zeros doubleword","not implemented",z13
+lzrg,"load and zero rightmost byte 64->64","not implemented",z13
+vmof,"vector multiply odd word","not implemented",z13
+vfsqdb,"vector fp square root","not implemented",z13
+vlgvg,"vector load gr from vr double word element","not implemented",z13
+verllf,"vector element rotate left logical mem word","not implemented",z13
+verllg,"vector element rotate left logical mem doubleword","not implemented",z13
+vrepf,"vector replicate word","not implemented",z13
+vfeezhs,"vector find element equal halfword","not implemented",z13
+wfchdbs,"vector fp compare high","not implemented",z13
+lochhi,"load halfword high immediate on condition","not implemented",z13
+vmalhw,"vector multiply and add low halfword","not implemented",z13
+vmlhb,"vector multiply logical high byte","not implemented",z13
+vfeeh,"vector find element equal halfword","not implemented",z13
+vgm,"vector generate mask","not implemented",z13
+vgfmab,"vector galois field multiply sum and accumulate byte","not implemented",z13
+vmrhg,"vector merge high double word","not implemented",z13
+veclg,"vector element compare logical double word","not implemented",z13
+vl,"vector memory load","not implemented",z13
+vctzh,"vector count trailing zeros halfword","not implemented",z13
+vuplhf,"vector unpack logical high word","not implemented",z13
+verllvg,"vector element rotate left logical reg doubleword","not implemented",z13
+vupl,"vector unpack low","not implemented",z13
+vlgvb,"vector load gr from vr byte element","not implemented",z13
+vab,"vector add byte","not implemented",z13
+vch,"vector compare high","not implemented",z13
+veclf,"vector element compare logical word","not implemented",z13
+vgef,"vector gather element 4 byte elements","not implemented",z13
+vscbiq,"vector subtract compute borrow indication quadword","not implemented",z13
+cdgtr,"convert from fixed long dfp","not implemented",z13
+vesrab,"vector element shift right arithmetic mem byte","not implemented",z13
+vfsq,"vector fp square root","not implemented",z13
+vscef,"vector scatter element 4 byte","not implemented",z13
+vpkh,"vector pack halfword","not implemented",z13
+vfa,"vector fp add","not implemented",z13
+vo,"vector or","not implemented",z13
+verllb,"vector element rotate left logical mem byte","not implemented",z13
+stocfh,"store high on condition","not implemented",z13
+vchlbs,"vector compare high logical byte","not implemented",z13
+vuphf,"vector unpack high word","not implemented",z13
+vacc,"vector add compute carry","not implemented",z13
+vistrf,"vector isolate string word","not implemented",z13
+vceqhs,"vector compare equal half word","not implemented",z13
+vfidb,"vector load fp integer","not implemented",z13
+vupllh,"vector unpack logical low halfword","not implemented",z13
+vfce,"vector fp compare equal","not implemented",z13
+vs,"vector subtract","not implemented",z13
+vfeebs,"vector find element equal byte","not implemented",z13
+vlvgg,"vector load VR double word element from GR","not implemented",z13
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/Makefile.am
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/Makefile.am (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/Makefile.am Mon Oct 17 17:59:59 2016
@@ -12,6 +12,7 @@
rounding-1 rounding-2 rounding-3 rounding-4 rounding-5 bfp-1 \
bfp-2 bfp-3 bfp-4 srnm srnmb comp-1 comp-2 exrl tmll tm stmg \
ex clst mvc test_fork test_sig rounding-6 rxsbg popcnt \
+ high-word \
spechelper-alr spechelper-algr \
spechelper-slr spechelper-slgr \
spechelper-cr spechelper-clr \
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.c (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.c Mon Oct 17 17:59:59 2016
@@ -71,6 +71,26 @@
printf("lcdbr %f -> %f\n", in, out);
}
+void lder(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lder %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"f"(in));
+ printf("lder %f -> %lx\n", in, out);
+}
+
+void lde(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lde %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"R"(in));
+ printf("lde %f -> %lx\n", in, out);
+}
+
int main(void)
{
// square root
@@ -98,5 +118,11 @@
lcdbr(-17.5); // 8 byte values
lcdbr(234.5); // 8 byte values
+ // load lengthened
+ lder(0.2, 321.5f);
+ lder(0.9, -8388607.f);
+ lde(0.2, -321.5f);
+ lde(0.9, 8388607.f);
+
return 0;
}
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.stdout.exp
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.stdout.exp (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/bfp-2.stdout.exp Mon Oct 17 17:59:59 2016
@@ -12,3 +12,7 @@
lcebr 123.500000 -> -123.500000
lcdbr -17.500000 -> 17.500000
lcdbr 234.500000 -> -234.500000
+lder 321.500000 -> 43a0c00000000000
+lder -8388607.000000 -> cafffffe00000000
+lde -321.500000 -> c3a0c00000000000
+lde 8388607.000000 -> 4afffffe00000000
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.c (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.c Mon Oct 17 17:59:59 2016
@@ -57,6 +57,13 @@
asm volatile( "mvc 0(5,%0),10(%1)\n"
::"a" (buf),"a" (buf): "memory");
printf("after: buf = |%s|\n", buf);
-
+ printf("\n");
+
+ /* Move inverse (mvcin) */
+ printf("------- Move inverse 17 bytes from BUFFER to TARGET\n");
+ printf("before: target = |%s|\n", target);
+ asm volatile( "mvcin 0(17,%0),0(%1)\n"
+ ::"a" (target),"a" (buffer + 16): "memory");
+ printf("after: target = |%s|\n", target);
return 0;
}
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.stdout.exp
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.stdout.exp (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/mvc.stdout.exp Mon Oct 17 17:59:59 2016
@@ -15,3 +15,7 @@
------- Non-destructive overlap buf[0:4] = buf[10:14]
before: buf = |0123456789abcde|
after: buf = |abcde56789abcde|
+
+------- Move inverse 17 bytes from BUFFER to TARGET
+before: target = |-xxx-----------------|
+after: target = |Xfedcba9876543210----|
Modified: branches/VALGRIND_3_12_BRANCH/none/tests/s390x/opcodes.h
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/none/tests/s390x/opcodes.h (original)
+++ branches/VALGRIND_3_12_BRANCH/none/tests/s390x/opcodes.h Mon Oct 17 17:59:59 2016
@@ -330,6 +330,8 @@
#define ROSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,56)
#define RXSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,57)
#define RISBGN(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,59)
+#define RISBHG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,5d)
+#define RISBLG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,51)
#define SFPC(r1) RRE_R0(b384,r1)
#define SGRK(r3,r1,r2) RRF_R0RR2(b9e9,r3,0,r1,r2)
#define SHHHR(r3,r1,r2) RRF_R0RR2(b9c9,r3,0,r1,r2)
|
|
From: <sv...@va...> - 2016-10-17 16:34:49
|
Author: sewardj
Date: Mon Oct 17 17:34:42 2016
New Revision: 3266
Log:
Merge, from trunk:
3259 s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
Modified:
branches/VEX_3_12_BRANCH/ (props changed)
branches/VEX_3_12_BRANCH/priv/guest_s390_toIR.c
Modified: branches/VEX_3_12_BRANCH/priv/guest_s390_toIR.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_s390_toIR.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_s390_toIR.c Mon Oct 17 17:34:42 2016
@@ -3831,6 +3831,16 @@
}
static const HChar *
+s390_irgen_BRCTH(UChar r1, UInt i2)
+{
+ put_gpr_w0(r1, binop(Iop_Sub32, get_gpr_w0(r1), mkU32(1)));
+ if_condition_goto(binop(Iop_CmpNE32, get_gpr_w0(r1), mkU32(0)),
+ guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1));
+
+ return "brcth";
+}
+
+static const HChar *
s390_irgen_BRCTG(UChar r1, UShort i2)
{
put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1)));
@@ -7633,6 +7643,65 @@
return s390_irgen_RISBGx(r1, r2, i3, i4, i5, False);
}
+static IRExpr *
+s390_irgen_RISBxG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5,
+ Bool high)
+{
+ UChar from;
+ UChar to;
+ UChar rot;
+ UChar z_bit;
+ UInt mask;
+ UInt maskc;
+ IRTemp op2 = newTemp(Ity_I32);
+
+ from = i3 & 31;
+ to = i4 & 31;
+ rot = i5 & 63;
+ z_bit = i4 & 128;
+ if (rot == 0) {
+ assign(op2, high ? get_gpr_w0(r2) : get_gpr_w1(r2));
+ } else if (rot == 32) {
+ assign(op2, high ? get_gpr_w1(r2) : get_gpr_w0(r2));
+ } else {
+ assign(op2,
+ unop(high ? Iop_64HIto32 : Iop_64to32,
+ binop(Iop_Or64,
+ binop(Iop_Shl64, get_gpr_dw0(r2), mkU8(rot)),
+ binop(Iop_Shr64, get_gpr_dw0(r2), mkU8(64 - rot)))));
+ }
+ if (from <= to) {
+ mask = ~0U;
+ mask = (mask >> from) & (mask << (31 - to));
+ maskc = ~mask;
+ } else {
+ maskc = ~0U;
+ maskc = (maskc >> (to + 1)) & (maskc << (32 - from));
+ mask = ~maskc;
+ }
+ if (z_bit) {
+ return binop(Iop_And32, mkexpr(op2), mkU32(mask));
+ }
+ return binop(Iop_Or32,
+ binop(Iop_And32, high ? get_gpr_w0(r1) : get_gpr_w1(r1),
+ mkU32(maskc)),
+ binop(Iop_And32, mkexpr(op2), mkU32(mask)));
+}
+
+static const HChar *
+s390_irgen_RISBHG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5)
+{
+ put_gpr_w0(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, True));
+ return "risbhg";
+}
+
+static const HChar *
+s390_irgen_RISBLG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5)
+{
+ put_gpr_w1(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, False));
+ return "risblg";
+}
+
static const HChar *
s390_irgen_SAR(UChar r1, UChar r2)
{
@@ -8770,6 +8839,15 @@
}
static const HChar *
+s390_irgen_LDER(UChar r1, UChar r2)
+{
+ put_fpr_dw0(r1, mkF64i(0x0));
+ put_fpr_w0(r1, get_fpr_w0(r2));
+
+ return "lder";
+}
+
+static const HChar *
s390_irgen_LXR(UChar r1, UChar r2)
{
put_fpr_dw0(r1, get_fpr_dw0(r2));
@@ -8795,6 +8873,15 @@
}
static const HChar *
+s390_irgen_LDE(UChar r1, IRTemp op2addr)
+{
+ put_fpr_dw0(r1, mkF64i(0x0));
+ put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr)));
+
+ return "lde";
+}
+
+static const HChar *
s390_irgen_LEY(UChar r1, IRTemp op2addr)
{
put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr)));
@@ -10911,6 +10998,22 @@
}
static void
+s390_irgen_MVCIN_EX(IRTemp length, IRTemp start1, IRTemp start2)
+{
+ IRTemp counter = newTemp(Ity_I64);
+
+ assign(counter, get_counter_dw0());
+
+ store(binop(Iop_Add64, mkexpr(start1), mkexpr(counter)),
+ load(Ity_I8, binop(Iop_Sub64, mkexpr(start2), mkexpr(counter))));
+
+ /* Check for end of field */
+ put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
+ iterate_if(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)));
+ put_counter_dw0(mkU64(0));
+}
+
+static void
s390_irgen_TR_EX(IRTemp length, IRTemp start1, IRTemp start2)
{
IRTemp op = newTemp(Ity_I8);
@@ -11043,6 +11146,11 @@
s390_irgen_EX_SS(r1, addr2, s390_irgen_TR_EX, 64);
return "ex@tr";
+ case 0xe800000000000000ULL:
+ /* special case MVCIN */
+ s390_irgen_EX_SS(r1, addr2, s390_irgen_MVCIN_EX, 64);
+ return "ex@mvcin";
+
default:
{
/* everything else will get a self checking prefix that also checks the
@@ -11487,6 +11595,17 @@
}
static const HChar *
+s390_irgen_MVCIN(UChar length, IRTemp start1, IRTemp start2)
+{
+ IRTemp len = newTemp(Ity_I64);
+
+ assign(len, mkU64(length));
+ s390_irgen_MVCIN_EX(len, start1, start2);
+
+ return "mvcin";
+}
+
+static const HChar *
s390_irgen_MVCL(UChar r1, UChar r2)
{
IRTemp addr1 = newTemp(Ity_I64);
@@ -14560,7 +14679,8 @@
ovl.fmt.RRF.r3, ovl.fmt.RRF.r2); goto ok;
case 0xb31f: s390_format_RRF_F0FF(s390_irgen_MSDBR, ovl.fmt.RRF.r1,
ovl.fmt.RRF.r3, ovl.fmt.RRF.r2); goto ok;
- case 0xb324: /* LDER */ goto unimplemented;
+ case 0xb324: s390_format_RRE_FF(s390_irgen_LDER, ovl.fmt.RRE.r1,
+ ovl.fmt.RRE.r2); goto ok;
case 0xb325: /* LXDR */ goto unimplemented;
case 0xb326: /* LXER */ goto unimplemented;
case 0xb32e: /* MAER */ goto unimplemented;
@@ -16046,7 +16166,13 @@
case 0xec0000000045ULL: s390_format_RIE_RRP(s390_irgen_BRXLG, ovl.fmt.RIE.r1,
ovl.fmt.RIE.r3, ovl.fmt.RIE.i2);
goto ok;
- case 0xec0000000051ULL: /* RISBLG */ goto unimplemented;
+ case 0xec0000000051ULL: s390_format_RIE_RRUUU(s390_irgen_RISBLG,
+ ovl.fmt.RIE_RRUUU.r1,
+ ovl.fmt.RIE_RRUUU.r2,
+ ovl.fmt.RIE_RRUUU.i3,
+ ovl.fmt.RIE_RRUUU.i4,
+ ovl.fmt.RIE_RRUUU.i5);
+ goto ok;
case 0xec0000000054ULL: s390_format_RIE_RRUUU(s390_irgen_RNSBG,
ovl.fmt.RIE_RRUUU.r1,
ovl.fmt.RIE_RRUUU.r2,
@@ -16082,7 +16208,13 @@
ovl.fmt.RIE_RRUUU.i4,
ovl.fmt.RIE_RRUUU.i5);
goto ok;
- case 0xec000000005dULL: /* RISBHG */ goto unimplemented;
+ case 0xec000000005dULL: s390_format_RIE_RRUUU(s390_irgen_RISBHG,
+ ovl.fmt.RIE_RRUUU.r1,
+ ovl.fmt.RIE_RRUUU.r2,
+ ovl.fmt.RIE_RRUUU.i3,
+ ovl.fmt.RIE_RRUUU.i4,
+ ovl.fmt.RIE_RRUUU.i5);
+ goto ok;
case 0xec0000000064ULL: s390_format_RIE_RRPU(s390_irgen_CGRJ,
ovl.fmt.RIE_RRPU.r1,
ovl.fmt.RIE_RRPU.r2,
@@ -16245,7 +16377,10 @@
ovl.fmt.RXF.r3, ovl.fmt.RXF.x2,
ovl.fmt.RXF.b2, ovl.fmt.RXF.d2,
ovl.fmt.RXF.r1); goto ok;
- case 0xed0000000024ULL: /* LDE */ goto unimplemented;
+ case 0xed0000000024ULL: s390_format_RXE_FRRD(s390_irgen_LDE,
+ ovl.fmt.RXE.r1, ovl.fmt.RXE.x2,
+ ovl.fmt.RXE.b2,
+ ovl.fmt.RXE.d2); goto ok;
case 0xed0000000025ULL: /* LXD */ goto unimplemented;
case 0xed0000000026ULL: /* LXE */ goto unimplemented;
case 0xed000000002eULL: /* MAE */ goto unimplemented;
@@ -16421,7 +16556,8 @@
case 0xc802ULL: /* CSST */ goto unimplemented;
case 0xc804ULL: /* LPD */ goto unimplemented;
case 0xc805ULL: /* LPDG */ goto unimplemented;
- case 0xcc06ULL: /* BRCTH */ goto unimplemented;
+ case 0xcc06ULL: s390_format_RIL_RP(s390_irgen_BRCTH, ovl.fmt.RIL.r1,
+ ovl.fmt.RIL.i2); goto ok;
case 0xcc08ULL: s390_format_RIL_RI(s390_irgen_AIH, ovl.fmt.RIL.r1,
ovl.fmt.RIL.i2); goto ok;
case 0xcc0aULL: s390_format_RIL_RI(s390_irgen_ALSIH, ovl.fmt.RIL.r1,
@@ -16471,7 +16607,9 @@
case 0xdfULL: /* EDMK */ goto unimplemented;
case 0xe1ULL: /* PKU */ goto unimplemented;
case 0xe2ULL: /* UNPKU */ goto unimplemented;
- case 0xe8ULL: /* MVCIN */ goto unimplemented;
+ case 0xe8ULL: s390_format_SS_L0RDRD(s390_irgen_MVCIN, ovl.fmt.SS.l,
+ ovl.fmt.SS.b1, ovl.fmt.SS.d1,
+ ovl.fmt.SS.b2, ovl.fmt.SS.d2); goto ok;
case 0xe9ULL: /* PKA */ goto unimplemented;
case 0xeaULL: /* UNPKA */ goto unimplemented;
case 0xeeULL: /* PLO */ goto unimplemented;
|
|
From: <sv...@va...> - 2016-10-17 16:25:14
|
Author: sewardj
Date: Mon Oct 17 17:25:02 2016
New Revision: 3265
Log:
Merge, from trunk:
3258 mips: remove support for mfc0/dmfc0
Modified:
branches/VEX_3_12_BRANCH/ (props changed)
branches/VEX_3_12_BRANCH/priv/guest_mips_defs.h
branches/VEX_3_12_BRANCH/priv/guest_mips_helpers.c
branches/VEX_3_12_BRANCH/priv/guest_mips_toIR.c
Modified: branches/VEX_3_12_BRANCH/priv/guest_mips_defs.h
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_mips_defs.h (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_mips_defs.h Mon Oct 17 17:25:02 2016
@@ -93,11 +93,6 @@
SUBS, SUBD, DIVS
} flt_op;
-extern UInt mips32_dirtyhelper_mfc0 ( UInt rd, UInt sel );
-
-extern ULong mips64_dirtyhelper_dmfc0 ( UInt rd, UInt sel );
-
-
#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
extern UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd );
extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
Modified: branches/VEX_3_12_BRANCH/priv/guest_mips_helpers.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_mips_helpers.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_mips_helpers.c Mon Oct 17 17:25:02 2016
@@ -418,668 +418,6 @@
}
};
-#define ASM_VOLATILE_CASE(rd, sel) \
- case rd: \
- asm volatile ("mfc0 %0, $" #rd ", "#sel"\n\t" :"=r" (x) ); \
- break;
-
-UInt mips32_dirtyhelper_mfc0(UInt rd, UInt sel)
-{
- UInt x = 0;
-#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
- switch (sel) {
- case 0:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 0);
- ASM_VOLATILE_CASE(1, 0);
- ASM_VOLATILE_CASE(2, 0);
- ASM_VOLATILE_CASE(3, 0);
- ASM_VOLATILE_CASE(4, 0);
- ASM_VOLATILE_CASE(5, 0);
- ASM_VOLATILE_CASE(6, 0);
- ASM_VOLATILE_CASE(7, 0);
- ASM_VOLATILE_CASE(8, 0);
- ASM_VOLATILE_CASE(9, 0);
- ASM_VOLATILE_CASE(10, 0);
- ASM_VOLATILE_CASE(11, 0);
- ASM_VOLATILE_CASE(12, 0);
- ASM_VOLATILE_CASE(13, 0);
- ASM_VOLATILE_CASE(14, 0);
- ASM_VOLATILE_CASE(15, 0);
- ASM_VOLATILE_CASE(16, 0);
- ASM_VOLATILE_CASE(17, 0);
- ASM_VOLATILE_CASE(18, 0);
- ASM_VOLATILE_CASE(19, 0);
- ASM_VOLATILE_CASE(20, 0);
- ASM_VOLATILE_CASE(21, 0);
- ASM_VOLATILE_CASE(22, 0);
- ASM_VOLATILE_CASE(23, 0);
- ASM_VOLATILE_CASE(24, 0);
- ASM_VOLATILE_CASE(25, 0);
- ASM_VOLATILE_CASE(26, 0);
- ASM_VOLATILE_CASE(27, 0);
- ASM_VOLATILE_CASE(28, 0);
- ASM_VOLATILE_CASE(29, 0);
- ASM_VOLATILE_CASE(30, 0);
- ASM_VOLATILE_CASE(31, 0);
- default:
- break;
- }
- break;
- case 1:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 1);
- ASM_VOLATILE_CASE(1, 1);
- ASM_VOLATILE_CASE(2, 1);
- ASM_VOLATILE_CASE(3, 1);
- ASM_VOLATILE_CASE(4, 1);
- ASM_VOLATILE_CASE(5, 1);
- ASM_VOLATILE_CASE(6, 1);
- ASM_VOLATILE_CASE(7, 1);
- ASM_VOLATILE_CASE(8, 1);
- ASM_VOLATILE_CASE(9, 1);
- ASM_VOLATILE_CASE(10, 1);
- ASM_VOLATILE_CASE(11, 1);
- ASM_VOLATILE_CASE(12, 1);
- ASM_VOLATILE_CASE(13, 1);
- ASM_VOLATILE_CASE(14, 1);
- ASM_VOLATILE_CASE(15, 1);
- ASM_VOLATILE_CASE(16, 1);
- ASM_VOLATILE_CASE(17, 1);
- ASM_VOLATILE_CASE(18, 1);
- ASM_VOLATILE_CASE(19, 1);
- ASM_VOLATILE_CASE(20, 1);
- ASM_VOLATILE_CASE(21, 1);
- ASM_VOLATILE_CASE(22, 1);
- ASM_VOLATILE_CASE(23, 1);
- ASM_VOLATILE_CASE(24, 1);
- ASM_VOLATILE_CASE(25, 1);
- ASM_VOLATILE_CASE(26, 1);
- ASM_VOLATILE_CASE(27, 1);
- ASM_VOLATILE_CASE(28, 1);
- ASM_VOLATILE_CASE(29, 1);
- ASM_VOLATILE_CASE(30, 1);
- ASM_VOLATILE_CASE(31, 1);
- default:
- break;
- }
- break;
- case 2:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 2);
- ASM_VOLATILE_CASE(1, 2);
- ASM_VOLATILE_CASE(2, 2);
- ASM_VOLATILE_CASE(3, 1);
- ASM_VOLATILE_CASE(4, 2);
- ASM_VOLATILE_CASE(5, 2);
- ASM_VOLATILE_CASE(6, 2);
- ASM_VOLATILE_CASE(7, 2);
- ASM_VOLATILE_CASE(8, 2);
- ASM_VOLATILE_CASE(9, 2);
- ASM_VOLATILE_CASE(10, 2);
- ASM_VOLATILE_CASE(11, 2);
- ASM_VOLATILE_CASE(12, 2);
- ASM_VOLATILE_CASE(13, 2);
- ASM_VOLATILE_CASE(14, 2);
- ASM_VOLATILE_CASE(15, 2);
- ASM_VOLATILE_CASE(16, 2);
- ASM_VOLATILE_CASE(17, 2);
- ASM_VOLATILE_CASE(18, 2);
- ASM_VOLATILE_CASE(19, 2);
- ASM_VOLATILE_CASE(20, 2);
- ASM_VOLATILE_CASE(21, 2);
- ASM_VOLATILE_CASE(22, 2);
- ASM_VOLATILE_CASE(23, 2);
- ASM_VOLATILE_CASE(24, 2);
- ASM_VOLATILE_CASE(25, 2);
- ASM_VOLATILE_CASE(26, 2);
- ASM_VOLATILE_CASE(27, 2);
- ASM_VOLATILE_CASE(28, 2);
- ASM_VOLATILE_CASE(29, 2);
- ASM_VOLATILE_CASE(30, 2);
- ASM_VOLATILE_CASE(31, 2);
- default:
- break;
- }
- break;
- case 3:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 3);
- ASM_VOLATILE_CASE(1, 3);
- ASM_VOLATILE_CASE(2, 3);
- ASM_VOLATILE_CASE(3, 3);
- ASM_VOLATILE_CASE(4, 3);
- ASM_VOLATILE_CASE(5, 3);
- ASM_VOLATILE_CASE(6, 3);
- ASM_VOLATILE_CASE(7, 3);
- ASM_VOLATILE_CASE(8, 3);
- ASM_VOLATILE_CASE(9, 3);
- ASM_VOLATILE_CASE(10, 3);
- ASM_VOLATILE_CASE(11, 3);
- ASM_VOLATILE_CASE(12, 3);
- ASM_VOLATILE_CASE(13, 3);
- ASM_VOLATILE_CASE(14, 3);
- ASM_VOLATILE_CASE(15, 3);
- ASM_VOLATILE_CASE(16, 3);
- ASM_VOLATILE_CASE(17, 3);
- ASM_VOLATILE_CASE(18, 3);
- ASM_VOLATILE_CASE(19, 3);
- ASM_VOLATILE_CASE(20, 3);
- ASM_VOLATILE_CASE(21, 3);
- ASM_VOLATILE_CASE(22, 3);
- ASM_VOLATILE_CASE(23, 3);
- ASM_VOLATILE_CASE(24, 3);
- ASM_VOLATILE_CASE(25, 3);
- ASM_VOLATILE_CASE(26, 3);
- ASM_VOLATILE_CASE(27, 3);
- ASM_VOLATILE_CASE(28, 3);
- ASM_VOLATILE_CASE(29, 3);
- ASM_VOLATILE_CASE(30, 3);
- ASM_VOLATILE_CASE(31, 3);
- default:
- break;
- }
- break;
- case 4:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 4);
- ASM_VOLATILE_CASE(1, 4);
- ASM_VOLATILE_CASE(2, 4);
- ASM_VOLATILE_CASE(3, 4);
- ASM_VOLATILE_CASE(4, 4);
- ASM_VOLATILE_CASE(5, 4);
- ASM_VOLATILE_CASE(6, 4);
- ASM_VOLATILE_CASE(7, 4);
- ASM_VOLATILE_CASE(8, 4);
- ASM_VOLATILE_CASE(9, 4);
- ASM_VOLATILE_CASE(10, 4);
- ASM_VOLATILE_CASE(11, 4);
- ASM_VOLATILE_CASE(12, 4);
- ASM_VOLATILE_CASE(13, 4);
- ASM_VOLATILE_CASE(14, 4);
- ASM_VOLATILE_CASE(15, 4);
- ASM_VOLATILE_CASE(16, 4);
- ASM_VOLATILE_CASE(17, 4);
- ASM_VOLATILE_CASE(18, 4);
- ASM_VOLATILE_CASE(19, 4);
- ASM_VOLATILE_CASE(20, 4);
- ASM_VOLATILE_CASE(21, 4);
- ASM_VOLATILE_CASE(22, 4);
- ASM_VOLATILE_CASE(23, 4);
- ASM_VOLATILE_CASE(24, 4);
- ASM_VOLATILE_CASE(25, 4);
- ASM_VOLATILE_CASE(26, 4);
- ASM_VOLATILE_CASE(27, 4);
- ASM_VOLATILE_CASE(28, 4);
- ASM_VOLATILE_CASE(29, 4);
- ASM_VOLATILE_CASE(30, 4);
- ASM_VOLATILE_CASE(31, 4);
- default:
- break;
- }
- break;
- case 5:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 5);
- ASM_VOLATILE_CASE(1, 5);
- ASM_VOLATILE_CASE(2, 5);
- ASM_VOLATILE_CASE(3, 5);
- ASM_VOLATILE_CASE(4, 5);
- ASM_VOLATILE_CASE(5, 5);
- ASM_VOLATILE_CASE(6, 5);
- ASM_VOLATILE_CASE(7, 5);
- ASM_VOLATILE_CASE(8, 5);
- ASM_VOLATILE_CASE(9, 5);
- ASM_VOLATILE_CASE(10, 5);
- ASM_VOLATILE_CASE(11, 5);
- ASM_VOLATILE_CASE(12, 5);
- ASM_VOLATILE_CASE(13, 5);
- ASM_VOLATILE_CASE(14, 5);
- ASM_VOLATILE_CASE(15, 5);
- ASM_VOLATILE_CASE(16, 5);
- ASM_VOLATILE_CASE(17, 5);
- ASM_VOLATILE_CASE(18, 5);
- ASM_VOLATILE_CASE(19, 5);
- ASM_VOLATILE_CASE(20, 5);
- ASM_VOLATILE_CASE(21, 5);
- ASM_VOLATILE_CASE(22, 5);
- ASM_VOLATILE_CASE(23, 5);
- ASM_VOLATILE_CASE(24, 5);
- ASM_VOLATILE_CASE(25, 5);
- ASM_VOLATILE_CASE(26, 5);
- ASM_VOLATILE_CASE(27, 5);
- ASM_VOLATILE_CASE(28, 5);
- ASM_VOLATILE_CASE(29, 5);
- ASM_VOLATILE_CASE(30, 5);
- ASM_VOLATILE_CASE(31, 5);
- default:
- break;
- }
- break;
- case 6:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 6);
- ASM_VOLATILE_CASE(1, 6);
- ASM_VOLATILE_CASE(2, 6);
- ASM_VOLATILE_CASE(3, 6);
- ASM_VOLATILE_CASE(4, 6);
- ASM_VOLATILE_CASE(5, 6);
- ASM_VOLATILE_CASE(6, 6);
- ASM_VOLATILE_CASE(7, 6);
- ASM_VOLATILE_CASE(8, 6);
- ASM_VOLATILE_CASE(9, 6);
- ASM_VOLATILE_CASE(10, 6);
- ASM_VOLATILE_CASE(11, 6);
- ASM_VOLATILE_CASE(12, 6);
- ASM_VOLATILE_CASE(13, 6);
- ASM_VOLATILE_CASE(14, 6);
- ASM_VOLATILE_CASE(15, 6);
- ASM_VOLATILE_CASE(16, 6);
- ASM_VOLATILE_CASE(17, 6);
- ASM_VOLATILE_CASE(18, 6);
- ASM_VOLATILE_CASE(19, 6);
- ASM_VOLATILE_CASE(20, 6);
- ASM_VOLATILE_CASE(21, 6);
- ASM_VOLATILE_CASE(22, 6);
- ASM_VOLATILE_CASE(23, 6);
- ASM_VOLATILE_CASE(24, 6);
- ASM_VOLATILE_CASE(25, 6);
- ASM_VOLATILE_CASE(26, 6);
- ASM_VOLATILE_CASE(27, 6);
- ASM_VOLATILE_CASE(28, 6);
- ASM_VOLATILE_CASE(29, 6);
- ASM_VOLATILE_CASE(30, 6);
- ASM_VOLATILE_CASE(31, 6);
- default:
- break;
- }
- break;
- case 7:
- /* __asm__("mfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE(0, 7);
- ASM_VOLATILE_CASE(1, 7);
- ASM_VOLATILE_CASE(2, 7);
- ASM_VOLATILE_CASE(3, 7);
- ASM_VOLATILE_CASE(4, 7);
- ASM_VOLATILE_CASE(5, 7);
- ASM_VOLATILE_CASE(6, 7);
- ASM_VOLATILE_CASE(7, 7);
- ASM_VOLATILE_CASE(8, 7);
- ASM_VOLATILE_CASE(9, 7);
- ASM_VOLATILE_CASE(10, 7);
- ASM_VOLATILE_CASE(11, 7);
- ASM_VOLATILE_CASE(12, 7);
- ASM_VOLATILE_CASE(13, 7);
- ASM_VOLATILE_CASE(14, 7);
- ASM_VOLATILE_CASE(15, 7);
- ASM_VOLATILE_CASE(16, 7);
- ASM_VOLATILE_CASE(17, 7);
- ASM_VOLATILE_CASE(18, 7);
- ASM_VOLATILE_CASE(19, 7);
- ASM_VOLATILE_CASE(20, 7);
- ASM_VOLATILE_CASE(21, 7);
- ASM_VOLATILE_CASE(22, 7);
- ASM_VOLATILE_CASE(23, 7);
- ASM_VOLATILE_CASE(24, 7);
- ASM_VOLATILE_CASE(25, 7);
- ASM_VOLATILE_CASE(26, 7);
- ASM_VOLATILE_CASE(27, 7);
- ASM_VOLATILE_CASE(28, 7);
- ASM_VOLATILE_CASE(29, 7);
- ASM_VOLATILE_CASE(30, 7);
- ASM_VOLATILE_CASE(31, 7);
- default:
- break;
- }
- break;
-
- default:
- break;
- }
-#endif
- return x;
-}
-
-#undef ASM_VOLATILE_CASE
-
-#define ASM_VOLATILE_CASE(rd, sel) \
- case rd: \
- asm volatile ("dmfc0 %0, $" #rd ", "#sel"\n\t" :"=r" (x) ); \
- break;
-
-ULong mips64_dirtyhelper_dmfc0 ( UInt rd, UInt sel )
-{
- ULong x = 0;
-#if defined(VGP_mips64_linux)
- switch (sel) {
- case 0:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 0);
- ASM_VOLATILE_CASE (1, 0);
- ASM_VOLATILE_CASE (2, 0);
- ASM_VOLATILE_CASE (3, 0);
- ASM_VOLATILE_CASE (4, 0);
- ASM_VOLATILE_CASE (5, 0);
- ASM_VOLATILE_CASE (6, 0);
- ASM_VOLATILE_CASE (7, 0);
- ASM_VOLATILE_CASE (8, 0);
- ASM_VOLATILE_CASE (9, 0);
- ASM_VOLATILE_CASE (10, 0);
- ASM_VOLATILE_CASE (11, 0);
- ASM_VOLATILE_CASE (12, 0);
- ASM_VOLATILE_CASE (13, 0);
- ASM_VOLATILE_CASE (14, 0);
- ASM_VOLATILE_CASE (15, 0);
- ASM_VOLATILE_CASE (16, 0);
- ASM_VOLATILE_CASE (17, 0);
- ASM_VOLATILE_CASE (18, 0);
- ASM_VOLATILE_CASE (19, 0);
- ASM_VOLATILE_CASE (20, 0);
- ASM_VOLATILE_CASE (21, 0);
- ASM_VOLATILE_CASE (22, 0);
- ASM_VOLATILE_CASE (23, 0);
- ASM_VOLATILE_CASE (24, 0);
- ASM_VOLATILE_CASE (25, 0);
- ASM_VOLATILE_CASE (26, 0);
- ASM_VOLATILE_CASE (27, 0);
- ASM_VOLATILE_CASE (28, 0);
- ASM_VOLATILE_CASE (29, 0);
- ASM_VOLATILE_CASE (30, 0);
- ASM_VOLATILE_CASE (31, 0);
- default:
- break;
- }
- break;
- case 1:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 1);
- ASM_VOLATILE_CASE (1, 1);
- ASM_VOLATILE_CASE (2, 1);
- ASM_VOLATILE_CASE (3, 1);
- ASM_VOLATILE_CASE (4, 1);
- ASM_VOLATILE_CASE (5, 1);
- ASM_VOLATILE_CASE (6, 1);
- ASM_VOLATILE_CASE (7, 1);
- ASM_VOLATILE_CASE (8, 1);
- ASM_VOLATILE_CASE (9, 1);
- ASM_VOLATILE_CASE (10, 1);
- ASM_VOLATILE_CASE (11, 1);
- ASM_VOLATILE_CASE (12, 1);
- ASM_VOLATILE_CASE (13, 1);
- ASM_VOLATILE_CASE (14, 1);
- ASM_VOLATILE_CASE (15, 1);
- ASM_VOLATILE_CASE (16, 1);
- ASM_VOLATILE_CASE (17, 1);
- ASM_VOLATILE_CASE (18, 1);
- ASM_VOLATILE_CASE (19, 1);
- ASM_VOLATILE_CASE (20, 1);
- ASM_VOLATILE_CASE (21, 1);
- ASM_VOLATILE_CASE (22, 1);
- ASM_VOLATILE_CASE (23, 1);
- ASM_VOLATILE_CASE (24, 1);
- ASM_VOLATILE_CASE (25, 1);
- ASM_VOLATILE_CASE (26, 1);
- ASM_VOLATILE_CASE (27, 1);
- ASM_VOLATILE_CASE (28, 1);
- ASM_VOLATILE_CASE (29, 1);
- ASM_VOLATILE_CASE (30, 1);
- ASM_VOLATILE_CASE (31, 1);
- default:
- break;
- }
- break;
- case 2:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 2);
- ASM_VOLATILE_CASE (1, 2);
- ASM_VOLATILE_CASE (2, 2);
- ASM_VOLATILE_CASE (3, 1);
- ASM_VOLATILE_CASE (4, 2);
- ASM_VOLATILE_CASE (5, 2);
- ASM_VOLATILE_CASE (6, 2);
- ASM_VOLATILE_CASE (7, 2);
- ASM_VOLATILE_CASE (8, 2);
- ASM_VOLATILE_CASE (9, 2);
- ASM_VOLATILE_CASE (10, 2);
- ASM_VOLATILE_CASE (11, 2);
- ASM_VOLATILE_CASE (12, 2);
- ASM_VOLATILE_CASE (13, 2);
- ASM_VOLATILE_CASE (14, 2);
- ASM_VOLATILE_CASE (15, 2);
- ASM_VOLATILE_CASE (16, 2);
- ASM_VOLATILE_CASE (17, 2);
- ASM_VOLATILE_CASE (18, 2);
- ASM_VOLATILE_CASE (19, 2);
- ASM_VOLATILE_CASE (20, 2);
- ASM_VOLATILE_CASE (21, 2);
- ASM_VOLATILE_CASE (22, 2);
- ASM_VOLATILE_CASE (23, 2);
- ASM_VOLATILE_CASE (24, 2);
- ASM_VOLATILE_CASE (25, 2);
- ASM_VOLATILE_CASE (26, 2);
- ASM_VOLATILE_CASE (27, 2);
- ASM_VOLATILE_CASE (28, 2);
- ASM_VOLATILE_CASE (29, 2);
- ASM_VOLATILE_CASE (30, 2);
- ASM_VOLATILE_CASE (31, 2);
- default:
- break;
- }
- break;
- case 3:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 3);
- ASM_VOLATILE_CASE (1, 3);
- ASM_VOLATILE_CASE (2, 3);
- ASM_VOLATILE_CASE (3, 3);
- ASM_VOLATILE_CASE (4, 3);
- ASM_VOLATILE_CASE (5, 3);
- ASM_VOLATILE_CASE (6, 3);
- ASM_VOLATILE_CASE (7, 3);
- ASM_VOLATILE_CASE (8, 3);
- ASM_VOLATILE_CASE (9, 3);
- ASM_VOLATILE_CASE (10, 3);
- ASM_VOLATILE_CASE (11, 3);
- ASM_VOLATILE_CASE (12, 3);
- ASM_VOLATILE_CASE (13, 3);
- ASM_VOLATILE_CASE (14, 3);
- ASM_VOLATILE_CASE (15, 3);
- ASM_VOLATILE_CASE (16, 3);
- ASM_VOLATILE_CASE (17, 3);
- ASM_VOLATILE_CASE (18, 3);
- ASM_VOLATILE_CASE (19, 3);
- ASM_VOLATILE_CASE (20, 3);
- ASM_VOLATILE_CASE (21, 3);
- ASM_VOLATILE_CASE (22, 3);
- ASM_VOLATILE_CASE (23, 3);
- ASM_VOLATILE_CASE (24, 3);
- ASM_VOLATILE_CASE (25, 3);
- ASM_VOLATILE_CASE (26, 3);
- ASM_VOLATILE_CASE (27, 3);
- ASM_VOLATILE_CASE (28, 3);
- ASM_VOLATILE_CASE (29, 3);
- ASM_VOLATILE_CASE (30, 3);
- ASM_VOLATILE_CASE (31, 3);
- default:
- break;
- }
- break;
- case 4:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 4);
- ASM_VOLATILE_CASE (1, 4);
- ASM_VOLATILE_CASE (2, 4);
- ASM_VOLATILE_CASE (3, 4);
- ASM_VOLATILE_CASE (4, 4);
- ASM_VOLATILE_CASE (5, 4);
- ASM_VOLATILE_CASE (6, 4);
- ASM_VOLATILE_CASE (7, 4);
- ASM_VOLATILE_CASE (8, 4);
- ASM_VOLATILE_CASE (9, 4);
- ASM_VOLATILE_CASE (10, 4);
- ASM_VOLATILE_CASE (11, 4);
- ASM_VOLATILE_CASE (12, 4);
- ASM_VOLATILE_CASE (13, 4);
- ASM_VOLATILE_CASE (14, 4);
- ASM_VOLATILE_CASE (15, 4);
- ASM_VOLATILE_CASE (16, 4);
- ASM_VOLATILE_CASE (17, 4);
- ASM_VOLATILE_CASE (18, 4);
- ASM_VOLATILE_CASE (19, 4);
- ASM_VOLATILE_CASE (20, 4);
- ASM_VOLATILE_CASE (21, 4);
- ASM_VOLATILE_CASE (22, 4);
- ASM_VOLATILE_CASE (23, 4);
- ASM_VOLATILE_CASE (24, 4);
- ASM_VOLATILE_CASE (25, 4);
- ASM_VOLATILE_CASE (26, 4);
- ASM_VOLATILE_CASE (27, 4);
- ASM_VOLATILE_CASE (28, 4);
- ASM_VOLATILE_CASE (29, 4);
- ASM_VOLATILE_CASE (30, 4);
- ASM_VOLATILE_CASE (31, 4);
- default:
- break;
- }
- break;
- case 5:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 5);
- ASM_VOLATILE_CASE (1, 5);
- ASM_VOLATILE_CASE (2, 5);
- ASM_VOLATILE_CASE (3, 5);
- ASM_VOLATILE_CASE (4, 5);
- ASM_VOLATILE_CASE (5, 5);
- ASM_VOLATILE_CASE (6, 5);
- ASM_VOLATILE_CASE (7, 5);
- ASM_VOLATILE_CASE (8, 5);
- ASM_VOLATILE_CASE (9, 5);
- ASM_VOLATILE_CASE (10, 5);
- ASM_VOLATILE_CASE (11, 5);
- ASM_VOLATILE_CASE (12, 5);
- ASM_VOLATILE_CASE (13, 5);
- ASM_VOLATILE_CASE (14, 5);
- ASM_VOLATILE_CASE (15, 5);
- ASM_VOLATILE_CASE (16, 5);
- ASM_VOLATILE_CASE (17, 5);
- ASM_VOLATILE_CASE (18, 5);
- ASM_VOLATILE_CASE (19, 5);
- ASM_VOLATILE_CASE (20, 5);
- ASM_VOLATILE_CASE (21, 5);
- ASM_VOLATILE_CASE (22, 5);
- ASM_VOLATILE_CASE (23, 5);
- ASM_VOLATILE_CASE (24, 5);
- ASM_VOLATILE_CASE (25, 5);
- ASM_VOLATILE_CASE (26, 5);
- ASM_VOLATILE_CASE (27, 5);
- ASM_VOLATILE_CASE (28, 5);
- ASM_VOLATILE_CASE (29, 5);
- ASM_VOLATILE_CASE (30, 5);
- ASM_VOLATILE_CASE (31, 5);
- default:
- break;
- }
- break;
- case 6:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 6);
- ASM_VOLATILE_CASE (1, 6);
- ASM_VOLATILE_CASE (2, 6);
- ASM_VOLATILE_CASE (3, 6);
- ASM_VOLATILE_CASE (4, 6);
- ASM_VOLATILE_CASE (5, 6);
- ASM_VOLATILE_CASE (6, 6);
- ASM_VOLATILE_CASE (7, 6);
- ASM_VOLATILE_CASE (8, 6);
- ASM_VOLATILE_CASE (9, 6);
- ASM_VOLATILE_CASE (10, 6);
- ASM_VOLATILE_CASE (11, 6);
- ASM_VOLATILE_CASE (12, 6);
- ASM_VOLATILE_CASE (13, 6);
- ASM_VOLATILE_CASE (14, 6);
- ASM_VOLATILE_CASE (15, 6);
- ASM_VOLATILE_CASE (16, 6);
- ASM_VOLATILE_CASE (17, 6);
- ASM_VOLATILE_CASE (18, 6);
- ASM_VOLATILE_CASE (19, 6);
- ASM_VOLATILE_CASE (20, 6);
- ASM_VOLATILE_CASE (21, 6);
- ASM_VOLATILE_CASE (22, 6);
- ASM_VOLATILE_CASE (23, 6);
- ASM_VOLATILE_CASE (24, 6);
- ASM_VOLATILE_CASE (25, 6);
- ASM_VOLATILE_CASE (26, 6);
- ASM_VOLATILE_CASE (27, 6);
- ASM_VOLATILE_CASE (28, 6);
- ASM_VOLATILE_CASE (29, 6);
- ASM_VOLATILE_CASE (30, 6);
- ASM_VOLATILE_CASE (31, 6);
- default:
- break;
- }
- break;
- case 7:
- /* __asm__("dmfc0 %0, $1, 0" :"=r" (x)); */
- switch (rd) {
- ASM_VOLATILE_CASE (0, 7);
- ASM_VOLATILE_CASE (1, 7);
- ASM_VOLATILE_CASE (2, 7);
- ASM_VOLATILE_CASE (3, 7);
- ASM_VOLATILE_CASE (4, 7);
- ASM_VOLATILE_CASE (5, 7);
- ASM_VOLATILE_CASE (6, 7);
- ASM_VOLATILE_CASE (7, 7);
- ASM_VOLATILE_CASE (8, 7);
- ASM_VOLATILE_CASE (9, 7);
- ASM_VOLATILE_CASE (10, 7);
- ASM_VOLATILE_CASE (11, 7);
- ASM_VOLATILE_CASE (12, 7);
- ASM_VOLATILE_CASE (13, 7);
- ASM_VOLATILE_CASE (14, 7);
- ASM_VOLATILE_CASE (15, 7);
- ASM_VOLATILE_CASE (16, 7);
- ASM_VOLATILE_CASE (17, 7);
- ASM_VOLATILE_CASE (18, 7);
- ASM_VOLATILE_CASE (19, 7);
- ASM_VOLATILE_CASE (20, 7);
- ASM_VOLATILE_CASE (21, 7);
- ASM_VOLATILE_CASE (22, 7);
- ASM_VOLATILE_CASE (23, 7);
- ASM_VOLATILE_CASE (24, 7);
- ASM_VOLATILE_CASE (25, 7);
- ASM_VOLATILE_CASE (26, 7);
- ASM_VOLATILE_CASE (27, 7);
- ASM_VOLATILE_CASE (28, 7);
- ASM_VOLATILE_CASE (29, 7);
- ASM_VOLATILE_CASE (30, 7);
- ASM_VOLATILE_CASE (31, 7);
- default:
- break;
- }
- break;
-
- default:
- break;
- }
-#endif
- return x;
-}
-
#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd )
{
Modified: branches/VEX_3_12_BRANCH/priv/guest_mips_toIR.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_mips_toIR.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_mips_toIR.c Mon Oct 17 17:25:02 2016
@@ -13392,33 +13392,6 @@
}
}
break; /* COP1 */
- case 0x10: /* COP0 */
- if (rs == 0) { /* MFC0 */
- DIP("mfc0 r%u, r%u, %u", rt, rd, sel);
- IRTemp val = newTemp(Ity_I32);
- IRExpr** args = mkIRExprVec_3 (IRExpr_BBPTR(), mkU32(rd), mkU32(sel));
- IRDirty *d = unsafeIRDirty_1_N(val,
- 0,
- "mips32_dirtyhelper_mfc0",
- &mips32_dirtyhelper_mfc0,
- args);
- stmt(IRStmt_Dirty(d));
- putIReg(rt, mkexpr(val));
- } else if (rs == 1) {
- /* Doubleword Move from Coprocessor 0 - DMFC0; MIPS64 */
- DIP("dmfc0 r%u, r%u, %u", rt, rd, sel);
- IRTemp val = newTemp(Ity_I64);
- IRExpr** args = mkIRExprVec_3 (IRExpr_BBPTR(), mkU64(rd), mkU64(sel));
- IRDirty *d = unsafeIRDirty_1_N(val,
- 0,
- "mips64_dirtyhelper_dmfc0",
- &mips64_dirtyhelper_dmfc0,
- args);
- stmt(IRStmt_Dirty(d));
- putDReg(rt, mkexpr(val));
- } else
- goto decode_failure;
- break;
case 0x31: /* LWC1 */
/* Load Word to Floating Point - LWC1 (MIPS32) */
|
|
From: <sv...@va...> - 2016-10-17 16:17:05
|
Author: sewardj
Date: Mon Oct 17 17:16:57 2016
New Revision: 3264
Log:
Merge, from trunk:
3257 Relax the overly-restrictive implementation of (T3) SUB{S}.W Rd,
SP, Rm, {shift}. #354274
Modified:
branches/VEX_3_12_BRANCH/ (props changed)
branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c
Modified: branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c Mon Oct 17 17:16:57 2016
@@ -20576,10 +20576,10 @@
&& rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
valid = True;
}
- /* also allow "sub.w reg, sp, reg w/ no shift
+ /* also allow "sub.w reg, sp, reg lsl #N for N=0,1,2 or 3
(T1) "SUB (SP minus register) */
if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
- && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+ && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
valid = True;
}
if (valid) {
|
|
From: <sv...@va...> - 2016-10-17 16:15:34
|
Author: sewardj
Date: Mon Oct 17 17:15:27 2016
New Revision: 16050
Log:
Merge, from trunk:
16026 mips32: fix the wrong offset for mmap2()
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips32-linux.c Mon Oct 17 17:15:27 2016
@@ -530,7 +530,7 @@
PRE(sys_mmap2)
{
- /* Exactly like sys_mmap() except the file offset is specified in pagesize
+ /* Exactly like sys_mmap() except the file offset is specified in 4096 byte
units rather than bytes, so that it can be used for files bigger than
2^32 bytes. */
SysRes r;
@@ -540,7 +540,7 @@
unsigned long, prot, unsigned long, flags,
unsigned long, fd, unsigned long, offset);
r = mips_PRE_sys_mmap(tid, ARG1, ARG2, ARG3, ARG4, ARG5,
- VKI_PAGE_SIZE * (Off64T) ARG6);
+ 4096 * (Off64T) ARG6);
SET_STATUS_from_SysRes(r);
}
|
|
From: <sv...@va...> - 2016-10-17 16:10:16
|
Author: sewardj
Date: Mon Oct 17 17:10:10 2016
New Revision: 16049
Log:
Merge from trunk:
16025 Add a warning to the get/set_thread_area wrapper for bad info pointers.
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c
branches/VALGRIND_3_12_BRANCH/memcheck/tests/x86-linux/scalar.stderr.exp
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-x86-linux.c Mon Oct 17 17:10:10 2016
@@ -596,7 +596,9 @@
static SysRes sys_modify_ldt ( ThreadId tid,
Int func, void* ptr, UInt bytecount )
{
- SysRes ret;
+ /* Set return value to something "safe". I think this will never
+ actually be returned, though. */
+ SysRes ret = VG_(mk_SysRes_Error)( VKI_ENOSYS );
if (func != 0 && func != 1 && func != 2 && func != 0x11) {
ret = VG_(mk_SysRes_Error)( VKI_ENOSYS );
@@ -634,8 +636,10 @@
vg_assert(8 == sizeof(VexGuestX86SegDescr));
vg_assert(sizeof(HWord) == sizeof(VexGuestX86SegDescr*));
- if (info == NULL || ! ML_(safe_to_deref)(info, sizeof(vki_modify_ldt_t)))
+ if (info == NULL || ! ML_(safe_to_deref)(info, sizeof(vki_modify_ldt_t))) {
+ VG_(umsg)("Warning: bad u_info address %p in set_thread_area\n", info);
return VG_(mk_SysRes_Error)( VKI_EFAULT );
+ }
gdt = (VexGuestX86SegDescr*)VG_(threads)[tid].arch.vex.guest_GDT;
@@ -686,8 +690,10 @@
vg_assert(sizeof(HWord) == sizeof(VexGuestX86SegDescr*));
vg_assert(8 == sizeof(VexGuestX86SegDescr));
- if (info == NULL || ! ML_(safe_to_deref)(info, sizeof(vki_modify_ldt_t)))
+ if (info == NULL || ! ML_(safe_to_deref)(info, sizeof(vki_modify_ldt_t))) {
+ VG_(umsg)("Warning: bad u_info address %p in get_thread_area\n", info);
return VG_(mk_SysRes_Error)( VKI_EFAULT );
+ }
idx = info->entry_number;
Modified: branches/VALGRIND_3_12_BRANCH/memcheck/tests/x86-linux/scalar.stderr.exp
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/memcheck/tests/x86-linux/scalar.stderr.exp (original)
+++ branches/VALGRIND_3_12_BRANCH/memcheck/tests/x86-linux/scalar.stderr.exp Mon Oct 17 17:10:10 2016
@@ -3380,6 +3380,7 @@
by 0x........: main (scalar.c:1084)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
+Warning: bad u_info address 0x........ in set_thread_area
-----------------------------------------------------
244:__NR_get_thread_area 1s 1m
-----------------------------------------------------
@@ -3392,6 +3393,7 @@
by 0x........: main (scalar.c:1088)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
+Warning: bad u_info address 0x........ in get_thread_area
-----------------------------------------------------
245: __NR_io_setup 2s 1m
-----------------------------------------------------
|
|
From: <sv...@va...> - 2016-10-17 16:08:23
|
Author: sewardj
Date: Mon Oct 17 17:08:17 2016
New Revision: 16048
Log:
Merge, from trunk:
16024 Fix n-i-bz bug in auto free pool: a block using the last byte
of the meta pool was not auto-freed.
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/memcheck/mc_malloc_wrappers.c
Modified: branches/VALGRIND_3_12_BRANCH/memcheck/mc_malloc_wrappers.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/memcheck/mc_malloc_wrappers.c (original)
+++ branches/VALGRIND_3_12_BRANCH/memcheck/mc_malloc_wrappers.c Mon Oct 17 17:08:17 2016
@@ -698,7 +698,7 @@
VG_(HT_ResetIter)(MC_(malloc_list));
while (!found && (mc = VG_(HT_Next)(MC_(malloc_list))) ) {
- if (mc->data >= StartAddr && mc->data + mc->szB < EndAddr) {
+ if (mc->data >= StartAddr && mc->data + mc->szB <= EndAddr) {
if (VG_(clo_verbosity) > 2) {
VG_(message)(Vg_UserMsg, "Auto-free of 0x%lx size=%lu\n",
mc->data, (mc->szB + 0UL));
|
|
From: <sv...@va...> - 2016-10-17 16:06:43
|
Author: sewardj
Date: Mon Oct 17 17:06:31 2016
New Revision: 16047
Log:
Merge, from trunk:
16018 mips: replace use of (d)addi with (d)addiu
Modified:
branches/VALGRIND_3_12_BRANCH/ (props changed)
branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips32-linux.S
branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips64-linux.S
branches/VALGRIND_3_12_BRANCH/coregrind/m_libcsetjmp.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips64-linux.c
branches/VALGRIND_3_12_BRANCH/coregrind/m_trampoline.S
branches/VALGRIND_3_12_BRANCH/helgrind/tests/tc08_hbl2.c
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips32-linux.S
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips32-linux.S (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips32-linux.S Mon Oct 17 17:06:31 2016
@@ -196,7 +196,7 @@
addu $13, $13, $14
lw $12, 0($13) /* t3 = VG_(tt_fast)[hash] :: ULong* */
- addi $13, $13, 4
+ addiu $13, $13, 4
lw $25, 0($13) /* little-endian, so comparing 1st 32bit word */
nop
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips64-linux.S
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips64-linux.S (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_dispatch/dispatch-mips64-linux.S Mon Oct 17 17:06:31 2016
@@ -196,7 +196,7 @@
daddu $13, $13, $14
ld $12, 0($13) /* t3 = VG_(tt_fast)[hash] :: ULong* */
- daddi $13, $13, 8
+ daddiu $13, $13, 8
ld $25, 0($13) /* little-endian, so comparing 1st 32bit word */
nop
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_libcsetjmp.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_libcsetjmp.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_libcsetjmp.c Mon Oct 17 17:06:31 2016
@@ -594,7 +594,7 @@
/* Checking whether second argument is zero. */
" bnez $a1, 1f \n\t"
" nop \n\t"
-" addi $a1, $a1, 1 \n\t" /* We must return 1 if val=0. */
+" addiu $a1, $a1, 1 \n\t" /* We must return 1 if val=0. */
"1: \n\t"
" move $v0, $a1 \n\t" /* Return value of second argument. */
" j $ra \n\t"
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips64-linux.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips64-linux.c (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_syswrap/syswrap-mips64-linux.c Mon Oct 17 17:06:31 2016
@@ -173,7 +173,7 @@
" ld $30, 8($29)\n"
" ld $28, 16($29)\n"
" jr $31\n"
-" daddi $29,$29, 32\n"
+" daddiu $29,$29, 32\n"
".previous\n"
);
Modified: branches/VALGRIND_3_12_BRANCH/coregrind/m_trampoline.S
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/coregrind/m_trampoline.S (original)
+++ branches/VALGRIND_3_12_BRANCH/coregrind/m_trampoline.S Mon Oct 17 17:06:31 2016
@@ -1278,8 +1278,8 @@
//la $a0, string
j strlen_cond
strlen_loop:
- addi $v0, $v0, 1
- addi $a0, $a0, 1
+ addiu $v0, $v0, 1
+ addiu $a0, $a0, 1
strlen_cond:
lbu $t0, ($a0)
bne $t0, $zero, strlen_loop
Modified: branches/VALGRIND_3_12_BRANCH/helgrind/tests/tc08_hbl2.c
==============================================================================
--- branches/VALGRIND_3_12_BRANCH/helgrind/tests/tc08_hbl2.c (original)
+++ branches/VALGRIND_3_12_BRANCH/helgrind/tests/tc08_hbl2.c Mon Oct 17 17:06:31 2016
@@ -125,11 +125,11 @@
# define INC(_lval,_lqual) \
__asm__ __volatile__ ( \
"L1xyzzy1" _lqual":\n" \
- " move $t0, %0\n" \
- " ll $t1, 0($t0)\n" \
- " addi $t1, $t1, 1\n" \
- " sc $t1, 0($t0)\n" \
- " beqz $t1, L1xyzzy1" _lqual \
+ " move $t0, %0\n" \
+ " ll $t1, 0($t0)\n" \
+ " addiu $t1, $t1, 1\n" \
+ " sc $t1, 0($t0)\n" \
+ " beqz $t1, L1xyzzy1" _lqual \
: /*out*/ : /*in*/ "r"(&(_lval)) \
: /*trash*/ "t0", "t1", "memory" \
)
|
|
From: <sv...@va...> - 2016-10-17 15:47:15
|
Author: sewardj
Date: Mon Oct 17 16:47:07 2016
New Revision: 16046
Log:
Update bug and merge status info.
Modified:
trunk/NEWS
trunk/docs/internals/3_11_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Mon Oct 17 16:47:07 2016
@@ -5,6 +5,7 @@
* ================== PLATFORM CHANGES =================
* Preliminary support for macOS 10.12 (Sierra) has been added.
+* mips: support for O32 FPXX ABI has been added.
* ==================== TOOL CHANGES ====================
@@ -93,6 +94,7 @@
353891 Assert 'bad_scanned_addr < VG_ROUNDDN(start+len, sizeof(Addr))' failed
353917 unhandled amd64-solaris syscall fchdir(120)
353920 unhandled amd64-solaris syscall: 170
+354274 arm: unhandled instruction: 0xEBAD 0x0AC1 (sub.w sl, sp, r1, lsl #3)
354392 unhandled amd64-solaris syscall: 171
354797 Vbit test does not include Iops for Power 8 instruction support
354883 tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
Modified: trunk/docs/internals/3_11_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_11_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_11_BUGSTATUS.txt Mon Oct 17 16:47:07 2016
@@ -33,9 +33,6 @@
352630 valgrind: Unrecognised instruction at address 0x4fc4d33.
[what insn is this?]
-354274 arm: unhandled instruction: 0xEBAD 0x0AC1 (sub.w sl, sp, r1, lsl #3)
- [harmless, has patch]
-
355526 disInstr(arm): unhandled instruction: 0x1823E91
[what insn is this?]
@@ -268,6 +265,9 @@
* mention that x86-linux is deprecated
+* the mempool changes (367995) are still under discussion
+ (PhilippeW, dev list, 6 Oct 2016) and may need further cleanup
+
========================================================================
========================================================================
========================================================================
@@ -275,9 +275,67 @@
Thu 15 Sep 12:55:21 CEST 2016
+368863 WARNING: unhandled arm64-linux syscall: 100
+368864 WARNING: unhandled arm64-linux syscall: 262
+368865 WARNING: unhandled arm64-linux syscall: 272
+368866 WARNING: unhandled arm64-linux syscall: 238
+368868 disInstr(arm64): unhandled instruction 0xD53BE000 = cntfrq_el0 (ARMv8)
+368873 Please add FreeBSD to supported OS list
+368913 WARNING: unhandled arm64-linux syscall: 117
+368914 WARNING: unhandled arm64-linux syscall: 142
+368916 WARNING: unhandled arm64-linux syscall: 234
+368917 WARNING: unhandled arm64-linux syscall: 218
+368918 WARNING: unhandled arm64-linux syscall: 127
+368919 WARNING: unhandled arm64-linux syscall: 274
+368920 WARNING: unhandled arm64-linux syscall: 275
+368921 WARNING: unhandled arm64-linux syscall: 162
+368922 WARNING: unhandled arm64-linux syscall: 161
+368923 WARNING: unhandled arm64-linux syscall: 268
+368924 WARNING: unhandled arm64-linux syscall: 84
+368925 WARNING: unhandled arm64-linux syscall: 130
+368926 WARNING: unhandled arm64-linux syscall: 97
+368960 WARNING: unhandled amd64-linux syscall: 163
+369026 WARNING: unhandled amd64-linux syscall: 169
+369027 WARNING: unhandled amd64-linux syscall: 216 (remap_file_pages)
+369028 WARNING: unhandled amd64-linux syscall: 314 (sched_setattr)
+369029 WARNING: unhandled amd64-linux syscall: 315 (sched_getattr)
+369030 WARNING: unhandled amd64-linux syscall: 171 (setdomainname)
+369031 WARNING: unhandled amd64-linux syscall: 308 (setns)
+369032 WARNING: unhandled amd64-linux syscall: 205 (set_thread_area)
+369033 WARNING: unhandled amd64-linux syscall: 139 (sysfs)
+369034 WARNING: unhandled amd64-linux syscall: 136 (ustat)
+369053 AMD64 fma4 instructions missing 256 bit support
+
+369264 Fedora 24 i686 and vex x86->IR:
+ unhandled instruction bytes: 0xC5 0xF8 0x10 0x3 (32 bit AVX) -> wontfix
+
+369409 null pointer dereference in vgPlain_do_syscall
+ possibly a dup of (fixed) 353370
+
+369456 callgrind_control failed to find an active callgrind run.
+ OSX specific
+
+369459 valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
+
+369509 ARMv8.1 LSE instructions are not supported
+369723 __builtin_longjmp not supported in clang/llvm on Android arm64 target
+ Has patch
+
+369854 Valgrind reports an Invalid Read in __intel_new_memcpy
+ Should be handled by --partial-loads-ok=yes
+
+370028 Reduce the number of compiler warnings on MIPS platforms
+370635 arm64 missing syscall getcpu
+370941 Investigate using new VG_(HT_remove_at_Iter)() at other places
+ in memcheck
+
+Mon 17 Oct 16:50:15 CEST 2016
+
========================================================================
========================================================================
+
+
3_12_BRANCH: vex 3250 is a copy of trunk 3249
val 15963 is a copy of trunk 15962
@@ -289,7 +347,9 @@
15970 -> 15972 fix for bugzilla 361253 [s390x]
15971 -> 15973 Add feature check for tests that use -march=armv8-a+crc.
15975 -> 16007 Avoid unused variable warning.
+
15976 Prelim support for macOS Sierra (10.12). Partial fix for #365327.
+
15977 -> 16008 ppcBE, fix the expected output file for
none/tests/ppc64/jm_int_isa_2_07.stdout.exp
15978 -> 16009 Use proper compiler flags on Solaris for fma4 test.
@@ -305,7 +365,6 @@
15987 -> 16012 mc-manual.xml: Fix some mismatched open/close tags.
15988 -> 16013 Use AM_LDFLAGS instead of LDFLAGS in exp-bbv/tests Makefiles.
15989 -> 16014 Don't require the current working directory to exist. #369209.
-
15990 -> 16015 Fix pre_mem_read_sockaddr crash on invalid syscall arguments.
Bug #369356.
15991 -> 16015 Fix crash in msghdr_foreachfield when iov_len isn't safe to
@@ -322,8 +381,6 @@
15997 -> 16015 Don't check bad iovec array in process_vm_readv/writev.
Bug #369441.
15998 -> 16015 Don't crash, but warn and return EINVAL on unknown fcntl command.
-(TODO: ask mjw about these)
-
15999 -> 16017 Replace --wait-for-gdb=yes memory loop by a call to VG_(poll)
(5000 milliseconds)
16000 -> 16017 Well, 5 seconds is too short for me to type a attach pid command
@@ -331,15 +388,53 @@
3251 -> 3254 Fix for clean helpers on BE
3252 -> 3255 Fix rounding mode check and instruction stxvl
16001 -> 16019 mips32: test for syscalls prctl(GET/SET_FP_MODE)
+
16002 Update svn:ignore list
+
3253 -> 3256 mips64: support for fp32 mode
16003 -> 16020 mips64: support for prctl(GET/SET_FP_MODE) syscalls
16004 -> 16021 mips64: support for prctl(GET/SET_FP_MODE) syscalls
+
16005 mips: update svn:ignore list
+
16006 -> 16022 dhat: add "tot-blocks-allocd" metric
-16018 mips: replace use of (d)addi with (d)addiu
-(tracked up to and including 16022)
+16018 M mips: replace use of (d)addi with (d)addiu
+3257 M Relax the overly-restrictive implementation of (T3) SUB{S}.W Rd,
+ SP, Rm, {shift}. #354274
+16023 Update 3_11_BUGSTATUS.txt
+16024 M Fix n-i-bz bug in auto free pool: a block using the last byte
+ of the meta pool was not auto-freed.
+16025 M Add a warning to the get/set_thread_area wrapper for bad info pointers.
+3258 M mips: remove support for mfc0/dmfc0
+16026 M mips32: fix the wrong offset for mmap2()
+3259 M s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
+16027 M s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
+16028 M s390/highword fix compile warning with some compilers
+16029 M actually test high-word by providing the plumbing...
+16030 M fix building the dfp testcase
+16031 M mips32: add pselect6 to the list of supported syscalls
+3260 M ISA 3.0 BE fixes for various new instructions
+16032 M ISA 3.0 BE testsuite fixes
+16033 M Fix some (small) leaks found by self-hosting valgrind
+16034 M Power configure fixes.
+16035 M Update NEWS file for bugzillas 369175 and 370265
+16036 M Fix corruption introduced by revision 16033
+16037 M Fix for missing ISA changes in HW cap stuff needs updating patch
+16038 M mips: clear fcc bits in fcsr after calling printf()
+3261 M mips: allow VEX to be compiled for soft-float
+16039 M mips: allow Valgrind to be compiled for soft-float
+3262 M mips: fix incorrect implementation of luxc1/suxc1 instructions
+16040 M mips32: add the test cases for luxc1/suxc1 instructions
+3263 M mips64: fix error introduced by r3262
+16041 M fix 369468 Remove quadratic metapool alg. using VG_(HT_remove_at_Iter)(VgHashTable *table)
+16042 M Clarify name and description/manual for meta mempool
+16043 M Introduce leak-pool-3.* back into EXTRA_DIST as they are not related
+to leak-autofreepool tests. This is a follow up fix for r16042.
+16044 M Further fixes following fix of leak in 16033
+16045 M Follow up for r16044. Fix compilation problem on Solaris.
+
+(tracked up to and including 16045/3263)
3.12.0.BETA1 is 3_12_BRANCHes at 15973/3250.
|