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From: Philippe W. <phi...@sk...> - 2016-09-10 09:48:38
|
> 2016-09-09 20:28 GMT+02:00 Jakub Beránek <ber...@gm...>:
> I'm playing with symbolic execution inside Valgrind and
> therefore when the program calls malloc(x);
>
>
> I need to know the address of x to get its symbolic
> constraints (I don't really care about the actual value of x).
I am not sure to fully understand what you are trying to do.
There is not necessarily any address for the argument.
So, what is the tool supposed to do when you have a call such as:
malloc (10)
or
malloc (any_var + any_other_var)
?
In the first case, there is no var address
In the second case, also no address (or rather you might imagine you
have 2 addresses to track ?)
That being said, what you are trying to do might somewhat looks
like origin tracking in memcheck, which tries to determine the origin
of undef values (e.g. an allocation stack trace, or a stack frame).
You might maybe get some ideas from this.
Philippe
|
|
From: Ivo R. <iv...@iv...> - 2016-09-10 00:51:21
|
2016-09-09 20:28 GMT+02:00 Jakub Beránek <ber...@gm...>: > I'm playing with symbolic execution inside Valgrind and therefore when the > program calls malloc(x); > > I need to know the address of x to get its symbolic constraints (I don't > really care about the actual value of x). > > I realize that getting this to work will probably differ significantly > amongst different platforms, I'm not even sure if it's universally possible > (for example on AMD64 I can track the last assignment into > parameter-passing registers, but on x86 it's much harder to track what's on > the stack before a function call). > I also realize that this is not a typical usage for a Valgrind tool :-) > Oh my, that's completely different story, then. I am thinking how would you do that in the client/guest program itself, if there is no Valgrind involved. This would rely significantly on function argument passing convention used on every particular platform. > Maybe with DWARF I could link the function call to the parameter passing. > Maybe another possibility would be to mess with the IR code, in the tool's instrument() callback. But I don't see an efficient way at this moment. I. |
|
From: Ivo R. <iv...@iv...> - 2016-09-09 17:35:49
|
2016-09-08 15:05 GMT+02:00 Jakub Beránek <ber...@gm...>: > I'm experimenting with writing a valgrind tool and I'd like to access > function parameters, specifically the size given to malloc. > I assume you are implementing VG_(needs_malloc_replacement)() and have a vgpreload_* module? > It is passed to the malloc callback, but I need to know the address of the > variable that was passed as the parameter (if it wasn't a constant). > Have a look at how existing tools implement VG_(needs_malloc_replacement)() and in particular, how do they implement pmalloc() callback. For example ms_malloc() in massif. Passing of the function parameters from the client (instrumented program) to the tool is performed as follows: - vgpreload_* library is loaded with the client program - vgpreload_* library defines malloc() replacements as per vg_replace_malloc.c [for example via ALLOC_or_NULL] - replacement function uses a client request: special sequence of instructions [for example VALGRIND_NON_SIMD_CALL1] - when Valgrind translates and instruments the client program and all the libraries, it recognizes the client request and acts accordingly - when the instrumented program is run, it calls into the tool's provided callback [for example ms_malloc()] Therefore there is no need to have any knowledge about function argument passing convention, which differs among architectures. This is all hidden behind client request definition (valgrind.h) and VEX frontend, specific to a particular architecture. The tool is architecture agnostic. Hope that helps, I. Btw, what is the main purpose of your tool? |
|
From: Carl E. L. <ce...@us...> - 2016-09-08 16:43:48
|
Valgrind Developers: The following patch was submitted to me by Will Schmidt to fix an issue with the massif/tests/mmapunmap test failure on ppc64. https://bugs.kde.org/show_bug.cgi?id=368461 I have tested the patch on PPC and it seems fine. Since this patch touches an arch independent file it needs to be reviewed and tested by the other platform developers. Please let us know if you find any issues with the patch. It is a small patch, I have attached it below for your convenience. Carl Love ----------------------------------------------------------------------- adapt massif mmapunmap test to handle ppc64 backtrace The reported backtrace on ppc64 platform reports "generic_start_main.isra.0" in the backtrace, where other platforms typically see "main". Adjust the vgtest file to handle this variation. This is similar to existing changes as seen in deep-D.post.exp --- massif/tests/Makefile.am | 3 ++- massif/tests/mmapunmap.post.exp-ppc64 | 1 + massif/tests/mmapunmap.vgtest | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 massif/tests/mmapunmap.post.exp-ppc64 diff --git a/massif/tests/Makefile.am b/massif/tests/Makefile.am index 4b69bfc..29cc9d3 100644 --- a/massif/tests/Makefile.am +++ b/massif/tests/Makefile.am @@ -24,7 +24,8 @@ EXTRA_DIST = \ long-names.post.exp long-names.stderr.exp long-names.vgtest \ long-time.post.exp long-time.stderr.exp long-time.vgtest \ malloc_usable.stderr.exp malloc_usable.vgtest \ - mmapunmap.post.exp mmapunmap.stderr.exp mmapunmap.vgtest \ + mmapunmap.post.exp mmapunmap.post.exp-ppc64 \ + mmapunmap.stderr.exp mmapunmap.vgtest \ new-cpp.post.exp new-cpp.stderr.exp new-cpp.vgtest \ no-stack-no-heap.post.exp no-stack-no-heap.stderr.exp no-stack-no-heap.vgtest \ null.post.exp null.stderr.exp null.vgtest \ diff --git a/massif/tests/mmapunmap.post.exp-ppc64 b/massif/tests/mmapunmap.post.exp-ppc64 new file mode 100644 index 0000000..59550a3 --- /dev/null +++ b/massif/tests/mmapunmap.post.exp-ppc64 @@ -0,0 +1 @@ + n1: 81920000 0x........: generic_start_main.isra.0 (in /...libc...) diff --git a/massif/tests/mmapunmap.vgtest b/massif/tests/mmapunmap.vgtest index 503b750..40e5664 100644 --- a/massif/tests/mmapunmap.vgtest +++ b/massif/tests/mmapunmap.vgtest @@ -2,5 +2,5 @@ prog: mmapunmap vgopts: --pages-as-heap=yes --threshold=30.0 -q vgopts: --stacks=no --time-unit=B --depth=8 --massif-out-file=massif.out vgopts: --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element -post: grep -A4 -e =peak massif.out | grep -e 'main (mmapunmap.c:16)' | tr -s ' ' | ../../tests/filter_addresses +post: grep -A4 -e =peak massif.out | grep -e 'main (mmapunmap.c:16)\|generic_start_main.isra.0' | tr -s ' ' | ../../tests/filter_addresses | ../../tests/filter_libc cleanup: rm massif.out |
|
From: Jakub B. <ber...@gm...> - 2016-09-08 13:06:11
|
Hello, I'm experimenting with writing a valgrind tool and I'd like to access function parameters, specifically the size given to malloc. It is passed to the malloc callback, but I need to know the address of the variable that was passed as the parameter (if it wasn't a constant). Is there a simple way to do this without searching through the stack frame? Thank you, Kuba Beranek |
|
From: Knapp, R. L <ras...@in...> - 2016-09-07 20:14:00
|
Hi all, I am working on this idea. I will let you know more when I have more information. Regards, -Rashawn -----Original Message----- From: Jeffrey Walton [mailto:nol...@gm...] Sent: Wednesday, September 07, 2016 1:09 PM To: Philippe Waroquiers <phi...@sk...> Cc: val...@li...; js...@ac...; Petar Jovanovic <mip...@gm...>; val...@li... Subject: Re: [Valgrind-users] [Valgrind-developers] AVX-512 support inquiry >> Can you make available, reliable, administrative-hassle-free remote >> access to a box that supports AVX-512? > Assuming there is an access to an AVX512 box, I can take in charge the > updates needed for valgrind gdbserver. > > Note that one admin hassle free way to provide such a box is for intel > to donate such a box to gcc compile farm (and maybe even better, to > host it). +1. I was thinking the same thing - host a farm or donate a couple of machines to the GCC compile farm. Jeff ------------------------------------------------------------------------------ _______________________________________________ Valgrind-users mailing list Val...@li... https://lists.sourceforge.net/lists/listinfo/valgrind-users |
|
From: <sv...@va...> - 2016-09-07 20:12:39
|
Author: philippe
Date: Wed Sep 7 21:12:30 2016
New Revision: 15945
Log:
Fix 199468 - Suppressions: stack size limited to 25 while --num-callers allows more frames
Nr of callers in a suppression entry had a smaller limit than the max
for --num-callers.
This means it was not possible to precisely suppress an error with a big
stack trace.
Also, --gen-suppressions was not providing the full stack trace of
the error in the generated suppressions.
Now, a suppression entry can have the same nr of callers as a backtrace.
Generated suppressions are generated with up to --num-callers callers.
This change has neglectible impact :
* memory: stack array of 500*2 words is declared, instead of 24*2 words
This array is declared on the interim stack (startup stack), which is
largely big enough.
* cpu : neglectible more cpu needed to read suppression entries
(to initialise the bigger stack array when reading a supp entry),
Apart of the above, no impact on performance (unless of course bigger
supp entries are really used).
Note that this does not impact the behaviour for existing suppression files.
Modified:
trunk/NEWS
trunk/coregrind/m_errormgr.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Sep 7 21:12:30 2016
@@ -26,6 +26,11 @@
"nouserintercepts" can be any non-existing library name).
This new functionality is not implemented for darwin/macosx.
+* The maximum number of callers in a suppression entry is now equal to
+ the maximum size for --num-callers (500).
+ Note that --gen-suppressions=yes|all similarly generate suppression
+ containing up to --num-callers frames.
+
* New and modified GDB server monitor features:
- Valgrind's gdbserver now accepts the command 'catch syscall'.
@@ -58,6 +63,7 @@
where XXXXXX is the bug number as listed below.
191069 Exiting due to signal not reported in XML output
+199468 Suppressions: stack size limited to 25 while --num-callers allows more frames
212352 vex amd64 unhandled opc_aux = 0x 2, first_opcode == 0xDC (FCOM)
278744 cvtps2pd with redundant RexW
303877 valgrind doesn't support compressed debuginfo sections.
Modified: trunk/coregrind/m_errormgr.c
==============================================================================
--- trunk/coregrind/m_errormgr.c (original)
+++ trunk/coregrind/m_errormgr.c Wed Sep 7 21:12:30 2016
@@ -195,8 +195,8 @@
}
CoreSuppKind;
-/* Max number of callers for context in a suppression. */
-#define VG_MAX_SUPP_CALLERS 24
+/* Max number of callers for context in a suppression is
+ VG_DEEPEST_BACKTRACE. */
/* For each caller specified for a suppression, record the nature of
the caller name. Not of interest to tools. */
@@ -410,8 +410,7 @@
// Print stack trace elements
UInt n_ips = VG_(get_ExeContext_n_ips)(ec);
vg_assert(n_ips > 0);
- if (n_ips > VG_MAX_SUPP_CALLERS)
- n_ips = VG_MAX_SUPP_CALLERS;
+ vg_assert(n_ips <= VG_DEEPEST_BACKTRACE);
VG_(apply_StackTrace)(printSuppForIp_nonXML,
text,
VG_(get_ExeContext_StackTrace)(ec),
@@ -1260,7 +1259,7 @@
HChar* tool_names;
HChar* supp_name;
const HChar* err_str = NULL;
- SuppLoc tmp_callers[VG_MAX_SUPP_CALLERS];
+ SuppLoc tmp_callers[VG_DEEPEST_BACKTRACE];
// Check it's not a directory.
if (VG_(is_dir)( filename )) {
@@ -1289,7 +1288,7 @@
supp->count = 0;
// Initialise temporary reading-in buffer.
- for (i = 0; i < VG_MAX_SUPP_CALLERS; i++) {
+ for (i = 0; i < VG_DEEPEST_BACKTRACE; i++) {
tmp_callers[i].ty = NoName;
tmp_callers[i].name_is_simple_str = False;
tmp_callers[i].name = NULL;
@@ -1391,7 +1390,7 @@
BOMB("missing stack trace");
}
}
- if (i == VG_MAX_SUPP_CALLERS)
+ if (i == VG_DEEPEST_BACKTRACE)
BOMB("too many callers in stack trace");
if (i > 0 && i >= VG_(clo_backtrace_size))
break;
|
|
From: Philippe W. <phi...@sk...> - 2016-09-07 19:33:21
|
On Wed, 2016-09-07 at 10:23 +0200, Julian Seward wrote: > Yes, I have seen AVX-512 looming on the horizon for a while. Yes, we > should support it. Dealing with AVX/AVX2 was a lot of work, and there is > not much AVX-512 available hardware out there, which may explain the > relative lack of activity so far. > > I would be willing to make the infrastructural changes in VEX and Valgrind > necessary to provide a framework in which we can incrementally add support > for individual instructions. That would be: addition of support for 512 > bit registers, changes in the front end instruction decoding framework, and > changes in the back end (if any required, possibly none). > > One problem is the lack of hardware. As I understand it, some but not > all Skylake CPUs support AVX-512. Having said that, if you are really > looking for a working implementation on Knights Landing then it would > be necessary to test any implementation both on Skylake+AVX512 and > Knights Landing. > > A good description of the instruction set is also necessary. Is that > publically available? > > Can you make available, reliable, administrative-hassle-free > remote access to a box that supports AVX-512? Assuming there is an access to an AVX512 box, I can take in charge the updates needed for valgrind gdbserver. Note that one admin hassle free way to provide such a box is for intel to donate such a box to gcc compile farm (and maybe even better, to host it). Philippe |
|
From: Carl E. L. <ce...@us...> - 2016-09-07 18:58:47
|
Valgrind Developers: The following patch was submitted to me by Will Schmidt. I have reviewed and tested the patch on PPC64 Power 7 and Power 8 platforms. The patch fixes the helgrind/tests/tc06_two_races_xml test failure on the Power 8 platforms. The test does not fail on Power 7. I created a bugzilla for the issue: https://bugs.kde.org/show_bug.cgi?id=368416 The patch touches architecture independent files the patch needs to be reviewed by the community. I have attached the patch below for your convenience. Please let me know if you see any issues with the patch. Thanks. Carl Love ------------------------------------------------------------------------------------------ Add a tc06_two_races_xml exp output for ppc64. This differs from the existing .exp in that does not contain the pthread_create_WRK entry frame. The non-xml version of this test passes because there is a filter that eliminates the pthread_create_WRK entry from that output. That was introduced in r13983, which added a filter to scrub out pthread_create_WRK from all of the outputs, and updated the .exp files to match. The additional exp file added here covers that same condition for the xml version of this test. I'll note that I did look at the code in and around pthread_create_WRK, in conjunction with the debug and comments from r13983. It looks like the _WRK stack frame is being reused rather than stacked upon. I suspect some part of branch-and-relink-to-noredir is not behaving quite as expected. That said, this rather simple update to the exp is sufficient and is not hiding anything I think is critical... --- helgrind/tests/Makefile.am | 2 helgrind/tests/tc06_two_races_xml.stderr.exp-ppc64 | 259 ++++++++++++++++++++ 2 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 helgrind/tests/tc06_two_races_xml.stderr.exp-ppc64 diff --git a/helgrind/tests/Makefile.am b/helgrind/tests/Makefile.am index 8a0d6e6..a666158 100644 --- a/helgrind/tests/Makefile.am +++ b/helgrind/tests/Makefile.am @@ -68,7 +68,7 @@ EXTRA_DIST = \ tc06_two_races.vgtest tc06_two_races.stdout.exp \ tc06_two_races.stderr.exp \ tc06_two_races_xml.vgtest tc06_two_races_xml.stdout.exp \ - tc06_two_races_xml.stderr.exp \ + tc06_two_races_xml.stderr.exp tc06_two_races_xml.stderr.exp-ppc64 \ tc07_hbl1.vgtest tc07_hbl1.stdout.exp tc07_hbl1.stderr.exp \ tc08_hbl2.vgtest tc08_hbl2.stdout.exp tc08_hbl2.stderr.exp \ tc09_bad_unlock.vgtest tc09_bad_unlock.stdout.exp \ diff --git a/helgrind/tests/tc06_two_races_xml.stderr.exp-ppc64 b/helgrind/tests/tc06_two_races_xml.stderr.exp-ppc64 new file mode 100644 index 0000000..a442a28 --- /dev/null +++ b/helgrind/tests/tc06_two_races_xml.stderr.exp-ppc64 @@ -0,0 +1,259 @@ +<?xml version="1.0"?> + +<valgrindoutput> + +<protocolversion>4</protocolversion> +<protocoltool>helgrind</protocoltool> + +<preamble> + <line>Helgrind, a thread error detector</line> + <line>Copyright (C) XXXX-YYYY, and GNU GPL'd, by OpenWorks LLP et al.</line> + <line>Using Valgrind-X.Y.X and LibVEX; rerun with -h for copyright info</line> + <line>Command: ./tc06_two_races</line> +</preamble> + +<pid>...</pid> +<ppid>...</ppid> +<tool>helgrind</tool> + +<args> + <vargv> + <exe>...</exe> + <arg>--command-line-only=yes</arg> + <arg>--memcheck:leak-check=no</arg> + <arg>--tool=helgrind</arg> + <arg>--read-var-info=yes</arg> + <arg>--xml=yes</arg> + <arg>--xml-fd=2</arg> + <arg>--log-file=/dev/null</arg> + </vargv> + <argv> + <exe>...</exe> + </argv> +</args> + +<status> + <state>RUNNING</state> + <time>...</time> +</status> + +<announcethread> + <hthreadid>1</hthreadid> + <isrootthread></isrootthread> +</announcethread> + +<announcethread> + <hthreadid>2</hthreadid> + <stack> + <frame>...</frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>pthread_create</fn> + <dir>...</dir> + <file>hg_intercepts.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>26</line> + </frame> + </stack> +</announcethread> + +<error> + <unique>...</unique> + <tid>...</tid> + <kind>Race</kind> + <xwhat> + <text>Possible data race during read of size 4 at 0x........ by thread #x</text> + <hthreadid>1</hthreadid> + </xwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>31</line> + </frame> + </stack> + <xauxwhat> + <text>This conflicts with a previous write of size 4 by thread #x</text> + <hthreadid>2</hthreadid> + </xauxwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>child_fn</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>14</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>mythread_wrapper</fn> + <dir>...</dir> + <file>hg_intercepts.c</file> + <line>...</line> + </frame> + <frame>...</frame> + </stack> + <auxwhat>Location 0x........ is 0 bytes inside global var "unprot1"</auxwhat> + <xauxwhat><text>declared at tc06_two_races.c:9</text> <file>tc06_two_races.c</file> <line>9</line> </xauxwhat> +</error> + +<error> + <unique>...</unique> + <tid>...</tid> + <kind>Race</kind> + <xwhat> + <text>Possible data race during write of size 4 at 0x........ by thread #x</text> + <hthreadid>1</hthreadid> + </xwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>31</line> + </frame> + </stack> + <xauxwhat> + <text>This conflicts with a previous write of size 4 by thread #x</text> + <hthreadid>2</hthreadid> + </xauxwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>child_fn</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>14</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>mythread_wrapper</fn> + <dir>...</dir> + <file>hg_intercepts.c</file> + <line>...</line> + </frame> + <frame>...</frame> + </stack> + <auxwhat>Location 0x........ is 0 bytes inside global var "unprot1"</auxwhat> + <xauxwhat><text>declared at tc06_two_races.c:9</text> <file>tc06_two_races.c</file> <line>9</line> </xauxwhat> +</error> + +<error> + <unique>...</unique> + <tid>...</tid> + <kind>Race</kind> + <xwhat> + <text>Possible data race during read of size 4 at 0x........ by thread #x</text> + <hthreadid>1</hthreadid> + </xwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>35</line> + </frame> + </stack> + <xauxwhat> + <text>This conflicts with a previous write of size 4 by thread #x</text> + <hthreadid>2</hthreadid> + </xauxwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>child_fn</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>18</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>mythread_wrapper</fn> + <dir>...</dir> + <file>hg_intercepts.c</file> + <line>...</line> + </frame> + <frame>...</frame> + </stack> + <auxwhat>Location 0x........ is 0 bytes inside global var "unprot2"</auxwhat> + <xauxwhat><text>declared at tc06_two_races.c:9</text> <file>tc06_two_races.c</file> <line>9</line> </xauxwhat> +</error> + +<error> + <unique>...</unique> + <tid>...</tid> + <kind>Race</kind> + <xwhat> + <text>Possible data race during write of size 4 at 0x........ by thread #x</text> + <hthreadid>1</hthreadid> + </xwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>35</line> + </frame> + </stack> + <xauxwhat> + <text>This conflicts with a previous write of size 4 by thread #x</text> + <hthreadid>2</hthreadid> + </xauxwhat> + <stack> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>child_fn</fn> + <dir>...</dir> + <file>tc06_two_races.c</file> + <line>18</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>mythread_wrapper</fn> + <dir>...</dir> + <file>hg_intercepts.c</file> + <line>...</line> + </frame> + <frame>...</frame> + </stack> + <auxwhat>Location 0x........ is 0 bytes inside global var "unprot2"</auxwhat> + <xauxwhat><text>declared at tc06_two_races.c:9</text> <file>tc06_two_races.c</file> <line>9</line> </xauxwhat> +</error> + + +<status> + <state>FINISHED</state> + <time>...</time> +</status> + +<errorcounts>...</errorcounts> + +<suppcounts>...</suppcounts> + +</valgrindoutput> + |
|
From: Carl E. L. <ce...@us...> - 2016-09-07 18:36:29
|
Valgrind Developers: The following patch was submitted to me by Will Schmidt to fix an issue with the Power Altivec configure test. I have created a bugzilla for it, https://bugs.kde.org/show_bug.cgi?id=368412 I have tested the patch on PPC and it seems fine. Since this patch touches an arch independent file it needs to be reviewed and tested by the other platform developers. Please let us know if you find any issues with the patch. It is a small patch, I have attached it below for your convenience. Carl Love ----------------------------------------------------------------------------------------- An earlier change introduced a think-o in the altivec capability check, allowing a false positive if the compiler supported altivec but the hardware did not. --- configure.ac | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index dd4fcb9..62faf4b 100644 --- a/configure.ac +++ b/configure.ac @@ -1379,12 +1379,13 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ ]])], [ ac_have_altivec=yes AC_MSG_RESULT([yes]) -AC_DEFINE([HAS_ALTIVEC], 1, +AC_DEFINE([COMPILER_SUPPORTS_ALTIVEC], 1, [Define to 1 if gcc/as can do Altivec.]) ], [ ac_have_altivec=no AC_MSG_RESULT([no]) ]) + CFLAGS=$safe_CFLAGS AM_CONDITIONAL([HAS_ALTIVEC], [test x$ac_have_altivec = xyes \ -a x$HWCAP_HAS_ALTIVEC = xyes]) |
|
From: John R. <jr...@bi...> - 2016-09-07 13:35:28
|
> A good description of the instruction set is also necessary. http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf |
|
From: Julian S. <js...@ac...> - 2016-09-07 08:23:40
|
Yes, I have seen AVX-512 looming on the horizon for a while. Yes, we should support it. Dealing with AVX/AVX2 was a lot of work, and there is not much AVX-512 available hardware out there, which may explain the relative lack of activity so far. I would be willing to make the infrastructural changes in VEX and Valgrind necessary to provide a framework in which we can incrementally add support for individual instructions. That would be: addition of support for 512 bit registers, changes in the front end instruction decoding framework, and changes in the back end (if any required, possibly none). One problem is the lack of hardware. As I understand it, some but not all Skylake CPUs support AVX-512. Having said that, if you are really looking for a working implementation on Knights Landing then it would be necessary to test any implementation both on Skylake+AVX512 and Knights Landing. A good description of the instruction set is also necessary. Is that publically available? Can you make available, reliable, administrative-hassle-free remote access to a box that supports AVX-512? J > -----Original Message----- > From: Petar Jovanovic [mailto:mip...@gm...] > Sent: Monday, September 05, 2016 11:48 AM > To: Jeff Hammond <jef...@gm...> > Cc: val...@li...; val...@li...; Mark Wielaard <mj...@re...> > Subject: Re: [Valgrind-developers] [Valgrind-users] AVX-512 support inquiry > > On Mon, Sep 5, 2016 at 6:31 PM, Jeff Hammond <jef...@gm...> wrote: >> >> It would be really valuable to a number of HPC programmers. Many DOE >> labs use it heavily. I wish I could help implement but I don't have >> the relevant skills. >> > > It may be worth to open a bug at kde and track future discussion there. |
|
From: Knapp, R. L <ras...@in...> - 2016-09-05 19:57:30
|
Petar and others on the Valgrind lists, I asked this question because of just what Jeff states that there are many HPC programmers and HPC laboratories which use Valgrind extensively. I do not mind opening a KDE bug discussion, but after not finding anything on this topic after searching through the KDE archive and the mailing lists archives, I thought first to ask via the mailing lists if anyone is currently working on contributing AVX-512 support to Valgrind. Intel's Knights Landing processor has shipped with AVX-512: https://software.intel.com/en-us/articles/intel-xeon-phi-x200-family-processor-performance-monitoring-reference-manual. From the KDE bug discussions for AVX2 (https://bugs.kde.org/show_bug.cgi?id=305728 ), I realize adding AVX-512 support is a large piece of development. Thank you all for your inputs. I will open up a KDE bug discussion on this topic. Regards, Rashawn Knapp, Intel Corporation -----Original Message----- From: Petar Jovanovic [mailto:mip...@gm...] Sent: Monday, September 05, 2016 11:48 AM To: Jeff Hammond <jef...@gm...> Cc: val...@li...; val...@li...; Mark Wielaard <mj...@re...> Subject: Re: [Valgrind-developers] [Valgrind-users] AVX-512 support inquiry On Mon, Sep 5, 2016 at 6:31 PM, Jeff Hammond <jef...@gm...> wrote: > > It would be really valuable to a number of HPC programmers. Many DOE > labs use it heavily. I wish I could help implement but I don't have > the relevant skills. > It may be worth to open a bug at kde and track future discussion there. Regards, Petar ------------------------------------------------------------------------------ _______________________________________________ Valgrind-developers mailing list Val...@li... https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
|
From: John R. <jr...@bi...> - 2016-09-05 19:22:37
|
> wikipedia claims there is not much hardware out there (yet?) that has > support for it: https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512 wikipedia seems to be a couple months behind the times. The current 6th generation Intel Core processors, code name "Skylake", have AVX-512. So a "new generation" laptop probably will have it, especially considering the current "back to school" and upcoming "holiday season" selling cycles. In the US the CPU chips themselves, and compatible motherboards, are shipping from stock at all leading retailers, and in the usual price ranges. processor : 3 vendor_id : GenuineIntel cpu family : 6 model : 94 model name : Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz stepping : 3 microcode : 0x9e cpu MHz : 800.000 cache size : 6144 KB physical id : 0 siblings : 4 core id : 3 cpu cores : 4 apicid : 6 initial apicid : 6 fpu : yes fpu_exception : yes cpuid level : 22 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch epb intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx rdseed adx smap clflushopt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp bugs : bogomips : 6388.01 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: |
|
From: Petar J. <mip...@gm...> - 2016-09-05 18:48:32
|
On Mon, Sep 5, 2016 at 6:31 PM, Jeff Hammond <jef...@gm...> wrote: > > It would be really valuable to a number of HPC programmers. Many DOE labs > use it heavily. I wish I could help implement but I don't have the relevant > skills. > It may be worth to open a bug at kde and track future discussion there. Regards, Petar |
|
From: Jeff H. <jef...@gm...> - 2016-09-05 16:31:50
|
On Monday, September 5, 2016, Mark Wielaard <mj...@re...> wrote: > On Fri, 2016-09-02 at 00:05 +0000, Knapp, Rashawn L wrote: > > With many new platforms hitting the market which include AVX-512 > > instruction extensions, and as a valgrind user, I want to inquire > > about Valgrind’s development underway to support these instructions. > > I will appreciate any information available regarding this. > > As far as I know nobody is currently working on AVX-512 instruction and > the new larger register support in valgrind. I don't even see a bug > report requesting it. If someone does have hardware that supports > AVX-512 it would be great if they could work on support for it. There is a good chance we can arrange remote access to hardware within Intel. Otherwise I can ask one of the DOE labs that has test hardware if they can help. (A lab that doesn't have onerous remote access limitations...). If all else fails, we loan out development boxes for certain purposes. > > But > wikipedia claims there is not much hardware out there (yet?) that has > support for it: https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512 > > Intel Xeon Phi 72xx aka Knights Landing is the only generally available product that supports it. Numerous unofficial sources and slides on GCC AVX-512 support by Intel describe another implementation. > Given your email address you might also want to ask people at Intel if > they think AVX-512 support for valgrind would be useful and whether they > could help with implementing support for it. > > It would be really valuable to a number of HPC programmers. Many DOE labs use it heavily. I wish I could help implement but I don't have the relevant skills. Jeff, who also works for Intel > Thanks, > > Mark > > ------------------------------------------------------------ > ------------------ > _______________________________________________ > Valgrind-developers mailing list > Val...@li... <javascript:;> > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > -- Jeff Hammond jef...@gm... http://jeffhammond.github.io/ |
|
From: Mark W. <mj...@re...> - 2016-09-05 14:16:34
|
On Fri, 2016-09-02 at 00:05 +0000, Knapp, Rashawn L wrote: > With many new platforms hitting the market which include AVX-512 > instruction extensions, and as a valgrind user, I want to inquire > about Valgrind’s development underway to support these instructions. > I will appreciate any information available regarding this. As far as I know nobody is currently working on AVX-512 instruction and the new larger register support in valgrind. I don't even see a bug report requesting it. If someone does have hardware that supports AVX-512 it would be great if they could work on support for it. But wikipedia claims there is not much hardware out there (yet?) that has support for it: https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512 Given your email address you might also want to ask people at Intel if they think AVX-512 support for valgrind would be useful and whether they could help with implementing support for it. Thanks, Mark |
|
From: <sv...@va...> - 2016-09-05 13:13:23
|
Author: mjw
Date: Mon Sep 5 14:13:12 2016
New Revision: 15944
Log:
Use -std=c++0x for big_debuginfo_symbol to appease older compilers.
gcc 4.4 doesn't know -std=c++11, but does recognize -std=c++0x.
Modified:
trunk/memcheck/tests/Makefile.am
Modified: trunk/memcheck/tests/Makefile.am
==============================================================================
--- trunk/memcheck/tests/Makefile.am (original)
+++ trunk/memcheck/tests/Makefile.am Mon Sep 5 14:13:12 2016
@@ -447,7 +447,7 @@
demangle_SOURCES = demangle.cpp
big_debuginfo_symbol_SOURCES = big_debuginfo_symbol.cpp
-big_debuginfo_symbol_CXXFLAGS = $(AM_CXXFLAGS) -std=c++11
+big_debuginfo_symbol_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x
bug340392_CFLAGS = $(AM_CFLAGS) -O3
dw4_CFLAGS = $(AM_CFLAGS) -gdwarf-4 -fdebug-types-section
|
|
From: Knapp, R. L <ras...@in...> - 2016-09-02 00:12:59
|
------------------------------------------------------------------------------ |
|
From: <sv...@va...> - 2016-09-01 15:19:20
|
Author: sewardj
Date: Thu Sep 1 16:19:07 2016
New Revision: 15943
Log:
Connect up the v8 memory insn tests to the build system, and arrange
for both ARM and Thumb encodings to be tested.
Modify the existing v8 crypto tests so that both ARM and Thumb encodings
are tested.
Added:
trunk/none/tests/arm/v8crypto_a.c
- copied unchanged from r15942, trunk/none/tests/arm/v8crypto.c
trunk/none/tests/arm/v8crypto_a.stderr.exp
- copied unchanged from r15942, trunk/none/tests/arm/v8crypto.stderr.exp
trunk/none/tests/arm/v8crypto_a.stdout.exp
- copied unchanged from r15942, trunk/none/tests/arm/v8crypto.stdout.exp
trunk/none/tests/arm/v8crypto_a.vgtest
- copied, changed from r15942, trunk/none/tests/arm/v8crypto.vgtest
trunk/none/tests/arm/v8crypto_t.c (with props)
trunk/none/tests/arm/v8crypto_t.stderr.exp (with props)
trunk/none/tests/arm/v8crypto_t.stdout.exp (with props)
trunk/none/tests/arm/v8crypto_t.vgtest
trunk/none/tests/arm/v8memory_a.c
- copied unchanged from r15942, trunk/none/tests/arm/v8memory.c
trunk/none/tests/arm/v8memory_a.stderr.exp
trunk/none/tests/arm/v8memory_a.stdout.exp
trunk/none/tests/arm/v8memory_a.vgtest
trunk/none/tests/arm/v8memory_t.c (with props)
trunk/none/tests/arm/v8memory_t.stderr.exp (with props)
trunk/none/tests/arm/v8memory_t.stdout.exp (with props)
trunk/none/tests/arm/v8memory_t.vgtest
Removed:
trunk/none/tests/arm/v8crypto.c
trunk/none/tests/arm/v8crypto.stderr.exp
trunk/none/tests/arm/v8crypto.stdout.exp
trunk/none/tests/arm/v8crypto.vgtest
trunk/none/tests/arm/v8memory.c
Modified:
trunk/none/tests/arm/Makefile.am
Modified: trunk/none/tests/arm/Makefile.am
==============================================================================
--- trunk/none/tests/arm/Makefile.am (original)
+++ trunk/none/tests/arm/Makefile.am Thu Sep 1 16:19:07 2016
@@ -12,7 +12,10 @@
v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
- v8crypto.stdout.exp v8crypto.stderr.exp v8crypto.vgtest \
+ v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
+ v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
+ v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
vcvt_fixed_float_VFP.vgtest \
vfp.stdout.exp vfp.stderr.exp vfp.vgtest \
@@ -28,7 +31,10 @@
v6intARM \
v6intThumb \
v6media \
- v8crypto \
+ v8crypto_a \
+ v8crypto_t \
+ v8memory_a \
+ v8memory_t \
vcvt_fixed_float_VFP \
vfp \
vfpv4_fma
@@ -51,7 +57,13 @@
v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
-v8crypto_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8
+v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+
+v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
+v8memory_t_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -mthumb
vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
-mfpu=neon \
Removed: trunk/none/tests/arm/v8crypto.c
==============================================================================
--- trunk/none/tests/arm/v8crypto.c (original)
+++ trunk/none/tests/arm/v8crypto.c (removed)
@@ -1,255 +0,0 @@
-
-/*
-gcc -o v8crypto v8crypto.c -march=armv8-a -mfpu=crypto-neon-fp-armv8
-gcc -o v8crypto v8crypto.c -mfpu=crypto-neon-fp-armv8
-*/
-
-#include <stdio.h>
-#include <assert.h>
-#include <malloc.h> // memalign
-#include <string.h> // memset
-#include "tests/malloc.h"
-#include <math.h> // isnormal
-
-typedef unsigned char UChar;
-typedef unsigned short int UShort;
-typedef unsigned int UInt;
-typedef signed int Int;
-typedef unsigned char UChar;
-typedef unsigned long long int ULong;
-typedef signed long long int Long;
-typedef double Double;
-typedef float Float;
-
-typedef unsigned char Bool;
-#define False ((Bool)0)
-#define True ((Bool)1)
-
-
-#define ITERS 1
-
-typedef
- enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
- LaneTy;
-
-union _V128 {
- UChar u8[16];
- UShort u16[8];
- UInt u32[4];
- ULong u64[2];
- Float f32[4];
- Double f64[2];
-};
-typedef union _V128 V128;
-
-static inline UChar randUChar ( void )
-{
- static UInt seed = 80021;
- seed = 1103515245 * seed + 12345;
- return (seed >> 17) & 0xFF;
-}
-
-//static ULong randULong ( LaneTy ty )
-//{
-// Int i;
-// ULong r = 0;
-// for (i = 0; i < 8; i++) {
-// r = (r << 8) | (ULong)(0xFF & randUChar());
-// }
-// return r;
-//}
-
-/* Generates a random V128. Ensures that that it contains normalised
- FP numbers when viewed as either F32x4 or F64x2, so that it is
- reasonable to use in FP test cases. */
-static void randV128 ( /*OUT*/V128* v, LaneTy ty )
-{
- static UInt nCalls = 0, nIters = 0;
- Int i;
- nCalls++;
- while (1) {
- nIters++;
- for (i = 0; i < 16; i++) {
- v->u8[i] = randUChar();
- }
- if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
- && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
- break;
- }
- if (0 == (nCalls & 0xFF))
- printf("randV128: %u calls, %u iters\n", nCalls, nIters);
-}
-
-static void showV128 ( V128* v )
-{
- Int i;
- for (i = 15; i >= 0; i--)
- printf("%02x", (Int)v->u8[i]);
-}
-
-//static void showBlock ( const char* msg, V128* block, Int nBlock )
-//{
-// Int i;
-// printf("%s\n", msg);
-// for (i = 0; i < nBlock; i++) {
-// printf(" ");
-// showV128(&block[i]);
-// printf("\n");
-// }
-//}
-
-
-/* ---------------------------------------------------------------- */
-/* -- Parameterisable test macros -- */
-/* ---------------------------------------------------------------- */
-
-#define DO50(_action) \
- do { \
- Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
- } while (0)
-
-
-/* Generate a test that involves two vector regs,
- with no bias as towards which is input or output.
- It's OK to use r8 as scratch.*/
-#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
- __attribute__((noinline)) \
- static void test_##TESTNAME ( LaneTy ty ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[4+1]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0], ty); \
- randV128(&block[1], ty); \
- randV128(&block[2], ty); \
- randV128(&block[3], ty); \
- __asm__ __volatile__( \
- "mov r9, #0 ; vmsr fpscr, r9 ; " \
- "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
- "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
- INSN " ; " \
- "add r9, %0, #32 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
- "add r9, %0, #48 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
- "vmrs r9, fpscr ; str r9, [%0, #64] " \
- : : "r"(&block[0]) \
- : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "r8", "r9" \
- ); \
- printf(INSN " "); \
- UInt fpscr = 0xFFFFFFFF & block[4].u32[0]; \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf(" "); \
- showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
- } \
- }
-
-
-/* Generate a test that involves three vector regs,
- with no bias as towards which is input or output. It's also OK
- to use r8 scratch. */
-#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
- __attribute__((noinline)) \
- static void test_##TESTNAME ( LaneTy ty ) { \
- Int i; \
- for (i = 0; i < ITERS; i++) { \
- V128 block[6+1]; \
- memset(block, 0x55, sizeof(block)); \
- randV128(&block[0], ty); \
- randV128(&block[1], ty); \
- randV128(&block[2], ty); \
- randV128(&block[3], ty); \
- randV128(&block[4], ty); \
- randV128(&block[5], ty); \
- __asm__ __volatile__( \
- "mov r9, #0 ; vmsr fpscr, r9 ; " \
- "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
- "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
- "add r9, %0, #32 ; vld1.8 { q"#VECREG3NO" }, [r9] ; " \
- INSN " ; " \
- "add r9, %0, #48 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
- "add r9, %0, #64 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
- "add r9, %0, #80 ; vst1.8 { q"#VECREG3NO" }, [r9] ; " \
- "vmrs r9, fpscr ; str r9, [%0, #96] " \
- : : "r"(&block[0]) \
- : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "q"#VECREG3NO, \
- "r8", "r9" \
- ); \
- printf(INSN " "); \
- UInt fpscr = 0xFFFFFFFF & block[6].u32[0]; \
- showV128(&block[0]); printf(" "); \
- showV128(&block[1]); printf(" "); \
- showV128(&block[2]); printf(" "); \
- showV128(&block[3]); printf(" "); \
- showV128(&block[4]); printf(" "); \
- showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
- } \
- }
-
-// ======================== CRYPTO ========================
-
-GEN_TWOVEC_TEST(aesd_q_q, "aesd.8 q3, q4", 3, 4)
-GEN_TWOVEC_TEST(aese_q_q, "aese.8 q12, q13", 12, 13)
-GEN_TWOVEC_TEST(aesimc_q_q, "aesimc.8 q15, q0", 15, 0)
-GEN_TWOVEC_TEST(aesmc_q_q, "aesmc.8 q1, q9", 1, 9)
-
-GEN_THREEVEC_TEST(sha1c_q_q_q, "sha1c.32 q11, q10, q2", 11, 10, 2)
-GEN_TWOVEC_TEST(sha1h_q_q, "sha1h.32 q6, q7", 6, 7)
-GEN_THREEVEC_TEST(sha1m_q_q_q, "sha1m.32 q2, q8, q13", 2, 8, 13)
-GEN_THREEVEC_TEST(sha1p_q_q_q, "sha1p.32 q3, q9, q14", 3, 9, 14)
-GEN_THREEVEC_TEST(sha1su0_q_q_q, "sha1su0.32 q4, q10, q15", 4, 10, 15)
-GEN_TWOVEC_TEST(sha1su1_q_q, "sha1su1.32 q11, q2", 11, 2)
-
-GEN_THREEVEC_TEST(sha256h2_q_q_q, "sha256h2.32 q9, q8, q7", 9, 8, 7)
-GEN_THREEVEC_TEST(sha256h_q_q_q, "sha256h.32 q10, q9, q8", 10, 9, 8)
-GEN_TWOVEC_TEST(sha256su0_q_q, "sha256su0.32 q11, q10", 11, 10)
-GEN_THREEVEC_TEST(sha256su1_q_q_q, "sha256su1.32 q12, q11, q10", 12, 11, 10)
-
-// This is a bit complex. This really mentions three registers, so it
-// should really be a THREEVEC variant. But the two source registers
-// are D registers. So we say it is just a TWOVEC insn, producing a Q
-// and taking a single Q (q7); q7 is the d14-d15 register pair, which
-// is why the insn itself is mentions d14 and d15 whereas the
-// numbers that follow mention q7. The result (q7) is 128 bits wide and
-// so is unaffected by these shenanigans.
-GEN_TWOVEC_TEST(pmull_q_d_d, "vmull.p64 q13, d14, d15", 13, 7)
-
-int main ( void )
-{
- // ======================== CRYPTO ========================
-
- // aesd.8 q_q (aes single round decryption)
- // aese.8 q_q (aes single round encryption)
- // aesimc.8 q_q (aes inverse mix columns)
- // aesmc.8 q_q (aes mix columns)
- if (1) DO50( test_aesd_q_q(TyNONE) );
- if (1) DO50( test_aese_q_q(TyNONE) );
- if (1) DO50( test_aesimc_q_q(TyNONE) );
- if (1) DO50( test_aesmc_q_q(TyNONE) );
-
- // sha1c.32 q_q_q
- // sha1h.32 q_q
- // sha1m.32 q_q_q
- // sha1p.32 q_q_q
- // sha1su0.32 q_q_q
- // sha1su1.32 q_q
- if (1) DO50( test_sha1c_q_q_q(TyNONE) );
- if (1) DO50( test_sha1h_q_q(TyNONE) );
- if (1) DO50( test_sha1m_q_q_q(TyNONE) );
- if (1) DO50( test_sha1p_q_q_q(TyNONE) );
- if (1) DO50( test_sha1su0_q_q_q(TyNONE) );
- if (1) DO50( test_sha1su1_q_q(TyNONE) );
-
- // sha256h2.32 q_q_q
- // sha256h.32 q_q_q
- // sha256su0.32 q_q
- // sha256su1.32 q_q_q
- if (1) DO50( test_sha256h2_q_q_q(TyNONE) );
- if (1) DO50( test_sha256h_q_q_q(TyNONE) );
- if (1) DO50( test_sha256su0_q_q(TyNONE) );
- if (1) DO50( test_sha256su1_q_q_q(TyNONE) );
-
- // vmull.64 q_d_d
- if (1) DO50( test_pmull_q_d_d(TyD) );
-
- return 0;
-}
Removed: trunk/none/tests/arm/v8crypto.stderr.exp
==============================================================================
(empty)
Removed: trunk/none/tests/arm/v8crypto.stdout.exp
==============================================================================
--- trunk/none/tests/arm/v8crypto.stdout.exp (original)
+++ trunk/none/tests/arm/v8crypto.stdout.exp (removed)
@@ -1,764 +0,0 @@
-aesd.8 q3, q4 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 0b2e475e420871824d7cdc612ba75949 7d6528c5fa956a0d69c3e9a6af27d13b fpscr=00000000
-aesd.8 q3, q4 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 cefe1576cbb79d35090c4bc5cd5e254e 065d77195d623e6b842adc6450659e17 fpscr=00000000
-aesd.8 q3, q4 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 8787cfa0c55f8b880ec24d33671ce39c 5ff85bc9535c191fd3a727d1a705f65d fpscr=00000000
-aesd.8 q3, q4 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 0fa1ba54db875e753f2fda19695e01c3 6897b536bbe4da8a369dab4f9465b86e fpscr=00000000
-aesd.8 q3, q4 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 1d4f03e13a592943100557914019c7d3 019963bf7459630b8d69483df7e8c6a9 fpscr=00000000
-aesd.8 q3, q4 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 708971e54d4a5bee2651524c4d73e17d 0a5f45c55f1c9202b76ddefcb0ebfe6e fpscr=00000000
-aesd.8 q3, q4 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 7ebee36ccf2be6e3b221fcaa201aec63 63483da65c8c49d096084deb9ed0411e fpscr=00000000
-aesd.8 q3, q4 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 03af402bb4e5954d1a01ee34dd79fb66 ecb42ac54b0966d4089b756aa3f77018 fpscr=00000000
-aesd.8 q3, q4 8404eb7f0cf4ca6fee8536da9dbf68bc ff6f850f2c57ea2a2c810e6dc1a1833d a73054d003e9766854053c20a8714591 ff6f850f2c57ea2a2c810e6dc1a1833d fpscr=00000000
-aesd.8 q3, q4 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 297777a9c72ee6de5f10eeecc2112f74 f078b65e01737fd22bfa8f668c8b14f4 fpscr=00000000
-aesd.8 q3, q4 c5e48064a393c8e947a34273c10a3c47 6ec34f98a2199d3c810bdacfab80ee3d 586fed550ecfe2b5093d7f78c7cf5fbd 6ec34f98a2199d3c810bdacfab80ee3d fpscr=00000000
-aesd.8 q3, q4 b984aed62671e865e6f21d40fc7bc013 5d0f926ce1157eaa95c45b338afcb3df 0f2435c0aeea985f31ce8f8f8f8c6d27 5d0f926ce1157eaa95c45b338afcb3df fpscr=00000000
-aesd.8 q3, q4 acb722146c6cbfa9ea4a022e1d3d7dbb 048612e51a468e36c51cdd8f87e12ab4 37b92e2b6f93ef6e0f2edaf14e9508fb 048612e51a468e36c51cdd8f87e12ab4 fpscr=00000000
-aesd.8 q3, q4 80ddba7e53e42d123208cf9b04b0569c 4288ae612c0dad40f0733f448390351b ea033acba85417486bed00efa8eb9bea 4288ae612c0dad40f0733f448390351b fpscr=00000000
-aesd.8 q3, q4 14575775bc3a12029d8e66ea90352a18 f9754842f9c9ba28f82a63b15c68b274 271d6fb2538d36956894e257bc7ecbb8 f9754842f9c9ba28f82a63b15c68b274 fpscr=00000000
-aesd.8 q3, q4 4784d95987cd4ed80c3ca578a32bd88e 08aebee85fda964fbba02737f3c98220 6c1c2d56923b11852d95469220870abe 08aebee85fda964fbba02737f3c98220 fpscr=00000000
-aesd.8 q3, q4 fbc4208894fdc0f55f706da71bf2425f 4e92f1b240a122141a366d352714867e 6d983ba2d2f552e019b9887468a7517b 4e92f1b240a122141a366d352714867e fpscr=00000000
-aesd.8 q3, q4 0e780c65c22b4ab8778d9ed6d9eb46ea ac82c1007a7d3cd8f54b130cdaa89cef d5c70fbc1a64b4909a147a7a11b98036 ac82c1007a7d3cd8f54b130cdaa89cef fpscr=00000000
-aesd.8 q3, q4 61ff7d4df3b6ca8131f01866bd76c58f 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 b95ffb6b00963b03de94d801deaf8f8d 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 fpscr=00000000
-aesd.8 q3, q4 d4ba52a206ff21b170fbbab6a7f19faf 3004b7a97cf69dda9f7301c1392d8087 df97789eae93fe05bd5acb0261402aee 3004b7a97cf69dda9f7301c1392d8087 fpscr=00000000
-aesd.8 q3, q4 47086cc3da642fa7130d662777beb4a9 16559ec50352a3d92d460a61a5dd0f6f 7fccf0a57000b88ae58dfe98d12404c7 16559ec50352a3d92d460a61a5dd0f6f fpscr=00000000
-aesd.8 q3, q4 9a49ac115048d4c4f987fa170d3ce4dd 9432a2e46543b956b819f459105730e9 dedfb377d705d774d90319b6f89ed728 9432a2e46543b956b819f459105730e9 fpscr=00000000
-aesd.8 q3, q4 adddf0eb4808f06704c857e949cc0fac 89fba268812abdb21e4a9e0958fac555 e3116541a62412b5122310a043944869 89fba268812abdb21e4a9e0958fac555 fpscr=00000000
-aesd.8 q3, q4 5f2619b1a20662f012305efa0acd1475 d70f7fb13667914c413cead25e27ac14 fd817e5297bbc678e74c9aee50d8d3d8 d70f7fb13667914c413cead25e27ac14 fpscr=00000000
-aesd.8 q3, q4 918107c43ea20cc00420edac31a0d599 5cce191e65591384ff4cb613013cc685 08b8cb7a801c5786579282f46363e9c4 5cce191e65591384ff4cb613013cc685 fpscr=00000000
-aesd.8 q3, q4 24509983fc3bcc36baf7e45e9fa43077 fa99500fef6024ba39dce32c239cf309 780bc8f09c7638f08212331e4157128a fa99500fef6024ba39dce32c239cf309 fpscr=00000000
-aesd.8 q3, q4 f6f2b14fbb3184b2141625713239066f 8fcf04e5b2dca44fcf4c517ea3a413ff ac465462af75ca21408b2ffb9f53d296 8fcf04e5b2dca44fcf4c517ea3a413ff fpscr=00000000
-aesd.8 q3, q4 e8c72e865de41295f2db8f44cbbf37e2 fcd015ff8f2e73a3a0fae06860b606c7 0e7bd8af9b4006247f872e42481049c2 fcd015ff8f2e73a3a0fae06860b606c7 fpscr=00000000
-aesd.8 q3, q4 da30ef8bc0b5573e34a901384a97a32f 20fd62bd65b571158e48704b3c31abc2 0fe0232414c52c0b2980bf8fc052b453 20fd62bd65b571158e48704b3c31abc2 fpscr=00000000
-aesd.8 q3, q4 ac8dd5bbc503330eb9dd5dab8e212ab7 ddb5cd8016d27d057796e0861576e44f e8ccb6492cdacd9ea976ecfaec5134e1 ddb5cd8016d27d057796e0861576e44f fpscr=00000000
-aesd.8 q3, q4 3d3cc0784c2f856363d9810079bbabd9 125934a781e479d33d431279cce48fce d23755ef4e8422fc80bca6af9d59ba87 125934a781e479d33d431279cce48fce fpscr=00000000
-aesd.8 q3, q4 6f9f902235982fa010fd4e94e9c808f5 9e477892854b43e0beafe48541dc8da0 6f48b8fc2b9b6272fc2d67e3bea9c8ed 9e477892854b43e0beafe48541dc8da0 fpscr=00000000
-aesd.8 q3, q4 20162517609f0f22a1a7a4c9c0a51f6b 63e279a20368bc8bdb3b370954bcbf24 e71c4bd2648e22b700ba471fbd26a792 63e279a20368bc8bdb3b370954bcbf24 fpscr=00000000
-aesd.8 q3, q4 31005fb9ada2074bf63a63fedcb4d29c 3f871736dc9ac5357446eb65e4e703bb 7601a873d750978a2cea51e81176d43d 3f871736dc9ac5357446eb65e4e703bb fpscr=00000000
-aesd.8 q3, q4 83bd1e68fb03f57bef136b941e54ffe8 139832afee423c3d6930e0fad3ba39c4 803212319699ce982fc2c745dcf84242 139832afee423c3d6930e0fad3ba39c4 fpscr=00000000
-aesd.8 q3, q4 f4ad41832c22ba116c949cea66e687ae 2ced5f927f2b383caf8484c5f3078d2a ad7c11e32de034fa5072a34e3340e94f 2ced5f927f2b383caf8484c5f3078d2a fpscr=00000000
-aesd.8 q3, q4 e309aef8a605af130821eb96e737777e b5a9377eb31749ef710cf757885d2728 06faf5dcb958c4552f476cddaf39f9b9 b5a9377eb31749ef710cf757885d2728 fpscr=00000000
-aesd.8 q3, q4 dbacfa35b7d2b75af8ad6b99bb3fa4c2 c673c91ec9aed3f8b9c3e32f2103009d 37458c0bde6d971a8aef1d79f8016684 c673c91ec9aed3f8b9c3e32f2103009d fpscr=00000000
-aesd.8 q3, q4 9f043af6a1aed58f1ee978efa4b054d2 76f140aa4182b4e706a17746411ab40c 2ad4d8a7eb62fbf7a077a0b73442bd9c 76f140aa4182b4e706a17746411ab40c fpscr=00000000
-aesd.8 q3, q4 2ad7482a960fb2b27014160ebbdb47e4 a7837c83faf3cb1d360794fec60222d6 1382afb7b4e5111bb8fdbc17985528a1 a7837c83faf3cb1d360794fec60222d6 fpscr=00000000
-aesd.8 q3, q4 5e86033374552e23ce8e2455e0205c58 37885d08d662faf92a541ab7911c2b5a 2c7a1949e46dd17a1ad7023baeb29d6a 37885d08d662faf92a541ab7911c2b5a fpscr=00000000
-aesd.8 q3, q4 19714a711ce1284318b88425f2de758f 0760c299b42e1fdcc2e9e9cf82c7aff8 d070b2c8e98eb36e6fe37abb7a5f9702 0760c299b42e1fdcc2e9e9cf82c7aff8 fpscr=00000000
-aesd.8 q3, q4 3cf6fe426e1281712ef114ddd37570e8 f76b8d9773b81b24de24e0a879648e11 62b537b559e3baedde750c3f17628f69 f76b8d9773b81b24de24e0a879648e11 fpscr=00000000
-aesd.8 q3, q4 a77700084a491a0ef099b6dd61462ec3 e70a9c61f55fce335d68e1a25652a804 b22b19e4729bda8bf413dc6b18ff1c31 e70a9c61f55fce335d68e1a25652a804 fpscr=00000000
-aesd.8 q3, q4 3a542e238fe5d1793d1148867eb08f81 b79cd058188318692112ca1cf9f1dd31 ead51203b4f8117c85b14837c4d30cfc b79cd058188318692112ca1cf9f1dd31 fpscr=00000000
-aesd.8 q3, q4 d4ec68f21f468712f7b8ab3708137382 478209dbbd84d92508847c7642a20df9 5c6d9d4c22560db21a458af87da8d803 478209dbbd84d92508847c7642a20df9 fpscr=00000000
-aesd.8 q3, q4 579f90d5d9cd1c3afceebf50e0d0ba24 761b274ac4c4f0c7f31ed81010c417bc 1717836e7b9b0a21de4f1872fb4020e2 761b274ac4c4f0c7f31ed81010c417bc fpscr=00000000
-aesd.8 q3, q4 a1cd852d9cd970502d146432e64644c9 25c80a060da03fb0c33ebc4b44b8ddd8 1a95920b4f0c2da0ac36f9af99af73e3 25c80a060da03fb0c33ebc4b44b8ddd8 fpscr=00000000
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-aese.8 q12, q13 f30110c432a534d0478d5d7e053a4e0c 2e467d8e98e7468c75a0cbeda561e618 acd8c2d623393c4ae0a040dcc12c90fa 2e467d8e98e7468c75a0cbeda561e618 fpscr=00000000
-aese.8 q12, q13 62bbc77143b71e92668b24fb9133bf52 9fedb2229a090d2c018b42f3d3ec8415 3563e2ed859e9dae2cb17d3054ae33a0 9fedb2229a090d2c018b42f3d3ec8415 fpscr=00000000
-aese.8 q12, q13 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 3090dba9c08cfe3d1596f04521389124 f2789356f1fb0d2b99885af4db13d1b7 fpscr=00000000
-aese.8 q12, q13 74876ac63afb7562c67d2c86fa7c09a3 07121ecd88441b7dd2cc3eca9347d80f 37c83e2bfae292c0f92a9f298f08c991 07121ecd88441b7dd2cc3eca9347d80f fpscr=00000000
-aese.8 q12, q13 077815d35567232e66c997070e860c39 109cfa471afbe686e2ede96f8809f947 8436e6225f73dfc24469a645f0def3f3 109cfa471afbe686e2ede96f8809f947 fpscr=00000000
-aese.8 q12, q13 89ad76dc21a1f8f15acd7ad9f991bada c201829797974fddfe5d063c8be33ce1 4e6044b34940bf714091a9d9b30510e2 c201829797974fddfe5d063c8be33ce1 fpscr=00000000
-aese.8 q12, q13 fba1981add7938e3067d74917c37833e f82db3448c8c9a654f1c8c8db3b639e1 d1eff4583b0cf1448a643a9c7be6419e f82db3448c8c9a654f1c8c8db3b639e1 fpscr=00000000
-aese.8 q12, q13 9cdd1a32cd007ff7daac12cf3a64acbd e76fcc086aeb0414a9cd126c0869c6a0 5cef02808fd7f6112337210a21e963a4 e76fcc086aeb0414a9cd126c0869c6a0 fpscr=00000000
-aese.8 q12, q13 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 2fbd47242724ba0dd9532680d1d9ef44 d4442998096825896787a06c436d8e39 fpscr=00000000
-aese.8 q12, q13 95a6e59e2a7fabcb65b86284a1cb27a3 a20cab554a62dd2468a718ec4422710c d0c0b11fd71e2fdfd9ac38459aa4da79 a20cab554a62dd2468a718ec4422710c fpscr=00000000
-aese.8 q12, q13 aef4eeb358364f4add55d3bb09c439c9 3028339e0d3a0c468e8f584ceae94e7a fc57f5d8edd8c1fe11861a680bfe3d6d 3028339e0d3a0c468e8f584ceae94e7a fpscr=00000000
-aese.8 q12, q13 af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 13a4d3abf00521f0c2ac1aa9894a8d8f 5df79fd3324f914fb79f41ec172107e2 fpscr=00000000
-aese.8 q12, q13 7742a77a117513548f9ea7c3a323665c 0bd9cf5599014e9dc435b32da92a7aa5 c4629c15b30145dd67144c281092fa99 0bd9cf5599014e9dc435b32da92a7aa5 fpscr=00000000
-randV128: 256 calls, 266 iters
-aese.8 q12, q13 e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 f37adda8c0716dfefad803eb16d76ec2 182fa58322b1219295b48e6f81658922 fpscr=00000000
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-aese.8 q12, q13 d2b5bf6419898df003e6fe7283eff6cb 7d772f10f5706b75304780122c8b69f0 ce32db92c343609779258ed07999f3e2 7d772f10f5706b75304780122c8b69f0 fpscr=00000000
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-aese.8 q12, q13 d4eaedef93c21b55bdb0c6ce36392d36 8cf3c5a6e236ba0ab0c81fb7053f6b55 a3bc5a3bd76f34cfc3d432b66abf35fb 8cf3c5a6e236ba0ab0c81fb7053f6b55 fpscr=00000000
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-aese.8 q12, q13 0beca39f21ddd399b28a073ef6656128 1eca927d6d5eee012a6fe8ae3cfe5e6a 29d975984614c74674f7276059ecdf2c 1eca927d6d5eee012a6fe8ae3cfe5e6a fpscr=00000000
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-aese.8 q12, q13 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 2d6efcb8b022dff3f25760a4cf7b0982 6eeb8d90d86668b60a08b6d0cfc59797 fpscr=00000000
-aese.8 q12, q13 1854ddf6d8b991ce01deaf4923243fc0 fe609a94181e600278e7d2d9d92a333d ba12feaab6aba04b2d18a1608e5cff54 fe609a94181e600278e7d2d9d92a333d fpscr=00000000
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-aese.8 q12, q13 9c423a145875f5144ccc5e105c99661d cdd47e0b8597b02c38527c577ae28aed c10bcec092211b07f7906ea0d198938c cdd47e0b8597b02c38527c577ae28aed fpscr=00000000
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-aese.8 q12, q13 2af3bd4b509e6608a513cfe482162be8 6f8ae74d5f7960b4a01933ef595f6af1 7667836f6b3bbe65b9b66f2b6e94b0d4 6f8ae74d5f7960b4a01933ef595f6af1 fpscr=00000000
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-aese.8 q12, q13 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 ac17003b2df651f59a5732bf7eea0256 fc95f5d55c34e70e2034036b2540d210 fpscr=00000000
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-aese.8 q12, q13 751dfa1352e40c98674442111330555e 76df5c23d344e7279f0d2317c41d637d 0c3b050441d824080e25e96f7be0ef26 76df5c23d344e7279f0d2317c41d637d fpscr=00000000
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-aese.8 q12, q13 6109ca6565cab2e77d69475df9b640b0 c34d90bb1a1256ba10a38a2b40833c5f d274101d3c96be4c561b69383a61bddf c34d90bb1a1256ba10a38a2b40833c5f fpscr=00000000
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-aesimc.8 q15, q0 23c025e6d5d2e99c2ac801d7a6e270f6 02471f026197d9cd943b5e67093fabba d86c759947a02025265fdb34ce7522be 02471f026197d9cd943b5e67093fabba fpscr=00000000
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-aesimc.8 q15, q0 bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 425c1b8ed32981f3fb66fbe250e310aa 4aeb1e341b4e429f4dc35e54b697e4cc fpscr=00000000
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-aesimc.8 q15, q0 ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 0cecae5f5153ff97a1d4381061782424 bb263bb7ac3dd62d8563a61df253853d fpscr=00000000
-aesimc.8 q15, q0 8ed3ed6fa5a46224d78477c55858ae69 60e0a4508b474b138ad25076fcb5b098 c4f4e8acd5d726b08f67a93f5bd7d538 60e0a4508b474b138ad25076fcb5b098 fpscr=00000000
-aesimc.8 q15, q0 f76b95fa6844fb06cbc7d36dc1d5402f 650eb2968b4fd6a0532863cf4c4877ad e88fa189e718c588855a00080d8d91cf 650eb2968b4fd6a0532863cf4c4877ad fpscr=00000000
-aesimc.8 q15, q0 e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc f1a30f55492f300105541c7ecd1d3822 aa0f44e98eb45934c0c5bf89c26cb8dc fpscr=00000000
-randV128: 512 calls, 530 iters
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-randV128: 768 calls, 793 iters
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-sha1c.32 q11, q10, q2 3439076a3e197cca193bd9259bec90f1 94e3abf26c26b7a66d1858edf6f399e9 c5dd39d1b0c43bc118fccda3094fb4e2 2e7bb2d2ec5b4e9b836f3a8ae10eb7bc 94e3abf26c26b7a66d1858edf6f399e9 c5dd39d1b0c43bc118fccda3094fb4e2 fpscr=00000000
-sha1c.32 q11, q10, q2 2497720343b5ec2ae5f8f1335752c15f 5f2d600012fbb3181054e0951279a0c3 4d260583d0bcc78de4fa82c3ce0e851d 03260cfbfba3e7acdc5cc678e5933de1 5f2d600012fbb3181054e0951279a0c3 4d260583d0bcc78de4fa82c3ce0e851d fpscr=00000000
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-sha1c.32 q11, q10, q2 153d92147f5309d64b43e1a21bee4078 00cccbbd5f8a40bcd0100e90e20d52c2 2631b48f178f1faa4759a8ab53ad8446 44c07e68cce9ee338eaad3ae93355b20 00cccbbd5f8a40bcd0100e90e20d52c2 2631b48f178f1faa4759a8ab53ad8446 fpscr=00000000
-sha1c.32 q11, q10, q2 de3613dbcdea9a46a0b7619465b43f63 6d233614316bfe51ff7d51608f00c029 3ddf478523227766b5984b4c78162e0a a7103b3bf116a55734ccda6d9cdd892b 6d233614316bfe51ff7d51608f00c029 3ddf478523227766b5984b4c78162e0a fpscr=00000000
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-randV128: 1024 calls, 1056 iters
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-sha1c.32 q11, q10, q2 86aa11887877a6d849b3512b5e2a8218 719d0091bedc6be2af5ad84456767099 c427c35c3abfacfd95205105b4d4b23d 67b5999a1a4535222c7c94e49dc5e4b9 719d0091bedc6be2af5ad84456767099 c427c35c3abfacfd95205105b4d4b23d fpscr=00000000
-sha1c.32 q11, q10, q2 f349fc88a17f04a72ababa3ade7ec0f6 50e072765b13b4cc78e1e3c8661d1a2a 9b877bb77e0fce842b7e1a6eea9715e2 4481e4e2c2ba83271780231bcbd04249 50e072765b13b4cc78e1e3c8661d1a2a 9b877bb77e0fce842b7e1a6eea9715e2 fpscr=00000000
-sha1c.32 q11, q10, q2 d9d62b65994cc8a7e6f3a0a57d8b0bb2 87a7575fc345b1ad3a70d90ed4f3609e 278154bc0d107047583cbe7f3c7e24ef 5705e1f02bb42a8dbe1d6a6b7c0e6b54 87a7575fc345b1ad3a70d90ed4f3609e 278154bc0d107047583cbe7f3c7e24ef fpscr=00000000
-sha1c.32 q11, q10, q2 c9f644af6c35b5a9298bd0f8923b179a 1d18e1cf5b84e96a50db4f1b9ccfb00a e575baa0e0ae972530ded746a0c24cf6 5b5aa14045931c173c7d4dae324d0a87 1d18e1cf5b84e96a50db4f1b9ccfb00a e575baa0e0ae972530ded746a0c24cf6 fpscr=00000000
-sha1c.32 q11, q10, q2 cbd0cbcccaa715e279b7db6a963b13c1 3151b853da308a1146e2e32500cd8fd7 4f455ede773e287b72d7d019b8471c89 12d78d9e224720743aa53d60a6f1c76f 3151b853da308a1146e2e32500cd8fd7 4f455ede773e287b72d7d019b8471c89 fpscr=00000000
-sha1c.32 q11, q10, q2 413a82184f5f247e5d780d4ad43726b8 162f6cae00d9a9616fd38c835bbc95f9 69510c18b200844005914da50633a077 0d8be4f96b0713a63a46fda966988a50 162f6cae00d9a9616fd38c835bbc95f9 69510c18b200844005914da50633a077 fpscr=00000000
-sha1c.32 q11, q10, q2 df37fbf8712136a00a527c7a3e712721 81b790423f419a7dff326017a1e19514 e69d59b105b800971d9062cd7ccaac64 f07db74f5fad078f90f149eef8978e6e 81b790423f419a7dff326017a1e19514 e69d59b105b800971d9062cd7ccaac64 fpscr=00000000
-sha1c.32 q11, q10, q2 59cccbd0a3b1a06db3c73ae0ca2ee8a2 26edba740e2eb08a2a8571c6c67e63cc 7c2dd90fe42aefa4ee582477105015f5 820d5be25e212a9dbd3388f8d19fe146 26edba740e2eb08a2a8571c6c67e63cc 7c2dd90fe42aefa4ee582477105015f5 fpscr=00000000
-sha1h.32 q6, q7 62fd870459d3b6088d5e5d5e6ab23ddf b9d47da8de6340ab234dd474bfd8d4c6 000000000000000000000000aff63531 b9d47da8de6340ab234dd474bfd8d4c6 fpscr=00000000
-sha1h.32 q6, q7 d8308a161f694382213cafb53a36aff3 86ff9089fca3cac10660484e4f7344dc 00000000000000000000000013dcd137 86ff9089fca3cac10660484e4f7344dc fpscr=00000000
-sha1h.32 q6, q7 be27c1a5174d78728950fadd603a4d91 7b86d0bd834973a67642acd16da757d4 0000000000000000000000001b69d5f5 7b86d0bd834973a67642acd16da757d4 fpscr=00000000
-sha1h.32 q6, q7 f3400e1021de3339a4fd1e35bc20f51a 77c81da655b51bba5253e15cf9d4ed0e 000000000000000000000000be753b43 77c81da655b51bba5253e15cf9d4ed0e fpscr=00000000
-sha1h.32 q6, q7 59de50b71e7c553654a0fa1d2d4888ed 5c2557a35145a25b79f3c74fd35be6ea 000000000000000000000000b4d6f9ba 5c2557a35145a25b79f3c74fd35be6ea fpscr=00000000
-sha1h.32 q6, q7 ce5f66faeb88beca779c70f69511e66a 08fe5d15565be8ebcc833e0bdb9b22c9 00000000000000000000000076e6c8b2 08fe5d15565be8ebcc833e0bdb9b22c9 fpscr=00000000
-sha1h.32 q6, q7 3423313a6b614e53ee4e5e1fd2dbeff2 5db2115b4557cdca2b6225eff1f5800b 000000000000000000000000fc7d6002 5db2115b4557cdca2b6225eff1f5800b fpscr=00000000
-sha1h.32 q6, q7 698a92d77d68e5349918a6f9c50683e4 39a151d5fe98305776f15e5cf5c8e20f 000000000000000000000000fd723883 39a151d5fe98305776f15e5cf5c8e20f fpscr=00000000
-sha1h.32 q6, q7 4ef5672f00fb63ca585926e34ef381a1 7d2cfee4617ef2f28d8fc7b1c6742635 000000000000000000000000719d098d 7d2cfee4617ef2f28d8fc7b1c6742635 fpscr=00000000
-sha1h.32 q6, q7 c3c391a4d67da7770a72bf3d4d01cb88 09b2f9e74e69f4fb509d414e46592ddd 00000000000000000000000051964b77 09b2f9e74e69f4fb509d414e46592ddd fpscr=00000000
-sha1h.32 q6, q7 a855ef96dd4b939b91c15167a2913ff9 bd93203fa5ba14d39e79ad9453d8d768 00000000000000000000000014f635da bd93203fa5ba14d39e79ad9453d8d768 fpscr=00000000
-sha1h.32 q6, q7 dc0a6363f6c70594cca9bcc22d02be55 7830544b46d033d95986e9e2ce510435 0000000000000000000000007394410d 7830544b46d033d95...
[truncated message content] |
|
From: Ivo R. <iv...@iv...> - 2016-09-01 14:54:28
|
Dear developers, Would the Valgrind community be interested in a Valgrind developer room at FOSDEM 2017 [1]? The deadline for developer room proposals is September 9th. I volunteer to help with help with the organization. We had a dev room at FOSDEM 2014 and 2015 and it seemed to be quite interesting experience for all participating... Kind regards, I. [1] https://fosdem.org/2017/news/2016-07-20-call-for-participation/ |
|
From: <sv...@va...> - 2016-09-01 13:11:02
|
Author: sewardj
Date: Thu Sep 1 14:10:55 2016
New Revision: 15942
Log:
Enable test cases for arm32 v8 insns: LDAEX{,B,H,D}, STLEX{,B,H,D}
(load-acquire exclusive, store-release exclusive)
Modified:
trunk/none/tests/arm/v8memory.c
Modified: trunk/none/tests/arm/v8memory.c
==============================================================================
--- trunk/none/tests/arm/v8memory.c (original)
+++ trunk/none/tests/arm/v8memory.c Thu Sep 1 14:10:55 2016
@@ -7,6 +7,11 @@
none/tests/arm/v8memory.c -I. -Wall -mthumb
*/
+/* These tests unfortunately are unable to check the relative
+ placement (or, even, presence) of the required memory fences
+ relative to the store/load required. They only verify the
+ data-movement component. */
+
#include <stdio.h>
#include <malloc.h> // memalign
#include <string.h> // memset
@@ -126,7 +131,7 @@
MEM_TEST("stl r6, [r10]")
MEM_TEST("stlb r9, [r10]")
MEM_TEST("stlh r3, [r10]")
-#if 0
+
////////////////////////////////////////////////////////////////
printf("LDAEX{,B,H,D} (reg)\n\n");
MEM_TEST("ldaex r6, [r10]")
@@ -135,6 +140,7 @@
MEM_TEST("ldaexd r2, r3, [r10]")
////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a cleared (missing) reservation.
printf("STLEX{,B,H,D} (reg) -- expected to fail\n\n");
MEM_TEST("clrex; stlex r9, r6, [r10]")
MEM_TEST("clrex; stlexb r9, r6, [r10]")
@@ -142,14 +148,17 @@
MEM_TEST("clrex; stlexd r9, r2, r3, [r10]")
////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a successful reservation.
+ // By using ldaex* to create the reservation in the first place,
+ // they also verify that ldaex* actually create a reservation.
printf("STLEX{,B,H,D} (reg) -- expected to succeed\n\n");
- MEM_TEST("ldrex r2, [r10] ; stlex r9, r6, [r10]")
- MEM_TEST("ldrexb r2, [r10] ; stlexb r9, r6, [r10]")
- MEM_TEST("ldrexh r2, [r10] ; stlexh r9, r3, [r10]")
+ MEM_TEST("ldaex r2, [r10] ; stlex r9, r6, [r10]")
+ MEM_TEST("ldaexb r2, [r10] ; stlexb r9, r6, [r10]")
+ MEM_TEST("ldaexh r2, [r10] ; stlexh r9, r3, [r10]")
MEM_TEST("mov r4, r2 ; mov r5, r3 ; " // preserve r2/r3 around the ldrexd
- "ldrexd r2, r3, [r10] ; "
+ "ldaexd r2, r3, [r10] ; "
"mov r2, r4 ; mov r3, r5 ; "
"stlexd r9, r2, r3, [r10]")
-#endif
+
return 0;
}
|
|
From: <sv...@va...> - 2016-09-01 13:08:19
|
Author: sewardj
Date: Thu Sep 1 14:08:10 2016
New Revision: 3248
Log:
Implement arm32 v8 insns: LDAEX{,B,H,D}, STLEX{,B,H,D}
(load-acquire exclusive, store-release exclusive)
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Thu Sep 1 14:08:10 2016
@@ -13140,7 +13140,7 @@
{
UInt nn = 16; // invalid
UInt tt = 16; // invalid
- UInt sz = 4; // invalid
+ UInt szBlg2 = 4; // invalid
Bool isLoad = False;
Bool gate = False;
if (isT) {
@@ -13150,8 +13150,8 @@
nn = INSN(19,16);
tt = INSN(15,12);
isLoad = INSN(20,20) == 1;
- sz = INSN(5,4); // 00:B 01:H 10:W 11:invalid
- gate = sz != BITS2(1,1) && tt != 15 && nn != 15;
+ szBlg2 = INSN(5,4); // 00:B 01:H 10:W 11:invalid
+ gate = szBlg2 != BITS2(1,1) && tt != 15 && nn != 15;
}
} else {
if (INSN(27,23) == BITS5(0,0,0,1,1) && INSN(20,20) == 1
@@ -13159,8 +13159,8 @@
nn = INSN(19,16);
tt = INSN(15,12);
isLoad = True;
- sz = INSN(22,21); // 10:B 11:H 00:W 01:invalid
- gate = sz != BITS2(0,1) && tt != 15 && nn != 15;
+ szBlg2 = INSN(22,21); // 10:B 11:H 00:W 01:invalid
+ gate = szBlg2 != BITS2(0,1) && tt != 15 && nn != 15;
}
else
if (INSN(27,23) == BITS5(0,0,0,1,1) && INSN(20,20) == 0
@@ -13168,15 +13168,15 @@
nn = INSN(19,16);
tt = INSN(3,0);
isLoad = False;
- sz = INSN(22,21); // 10:B 11:H 00:W 01:invalid
- gate = sz != BITS2(0,1) && tt != 15 && nn != 15;
+ szBlg2 = INSN(22,21); // 10:B 11:H 00:W 01:invalid
+ gate = szBlg2 != BITS2(0,1) && tt != 15 && nn != 15;
}
if (gate) {
- // Rearrange sz bits to be the same as the Thumb case
- switch (sz) {
- case 2: sz = 0; break;
- case 3: sz = 1; break;
- case 0: sz = 2; break;
+ // Rearrange szBlg2 bits to be the same as the Thumb case
+ switch (szBlg2) {
+ case 2: szBlg2 = 0; break;
+ case 3: szBlg2 = 1; break;
+ case 0: szBlg2 = 2; break;
default: /*NOTREACHED*/vassert(0);
}
}
@@ -13185,18 +13185,18 @@
// is passed in by the caller. Note that the the loads and stores
// are conditional, so we don't have to truncate the IRSB at this
// point, but the fence is unconditional. There's no way to
- // represent a conditional fence (without a side exit), but it
+ // represent a conditional fence without a side exit, but it
// doesn't matter from a correctness standpoint that it is
// unconditional -- it just loses a bit of performance in the
// case where the condition doesn't hold.
if (gate) {
- vassert(sz <= 2 && nn <= 14 && tt <= 14);
+ vassert(szBlg2 <= 2 && nn <= 14 && tt <= 14);
IRExpr* ea = llGetIReg(nn);
if (isLoad) {
static IRLoadGOp cvt[3]
= { ILGop_8Uto32, ILGop_16Uto32, ILGop_Ident32 };
IRTemp data = newTemp(Ity_I32);
- loadGuardedLE(data, cvt[sz], ea, mkU32(0)/*alt*/, condT);
+ loadGuardedLE(data, cvt[szBlg2], ea, mkU32(0)/*alt*/, condT);
if (isT) {
putIRegT(tt, mkexpr(data), condT);
} else {
@@ -13206,7 +13206,7 @@
} else {
stmt(IRStmt_MBE(Imbe_Fence));
IRExpr* data = llGetIReg(tt);
- switch (sz) {
+ switch (szBlg2) {
case 0: data = unop(Iop_32to8, data); break;
case 1: data = unop(Iop_32to16, data); break;
case 2: break;
@@ -13216,12 +13216,250 @@
}
const HChar* ldNames[3] = { "ldab", "ldah", "lda" };
const HChar* stNames[3] = { "stlb", "stlh", "stl" };
- DIP("%s r%u, [r%u]", (isLoad ? ldNames : stNames)[sz], tt, nn);
+ DIP("%s r%u, [r%u]", (isLoad ? ldNames : stNames)[szBlg2], tt, nn);
return True;
}
/* else fall through */
}
+ /* ----------- LDAEX{,B,H,D}, STLEX{,B,H,D} ----------- */
+ /* 31 27 23 19 15 11 7 3
+ A1: cond 0001 1101 n t 1110 1001 1111 LDAEXB Rt, [Rn]
+ A1: cond 0001 1111 n t 1110 1001 1111 LDAEXH Rt, [Rn]
+ A1: cond 0001 1001 n t 1110 1001 1111 LDAEX Rt, [Rn]
+ A1: cond 0001 1011 n t 1110 1001 1111 LDAEXD Rt, Rt+1, [Rn]
+
+ A1: cond 0001 1100 n d 1110 1001 t STLEXB Rd, Rt, [Rn]
+ A1: cond 0001 1110 n d 1110 1001 t STLEXH Rd, Rt, [Rn]
+ A1: cond 0001 1000 n d 1110 1001 t STLEX Rd, Rt, [Rn]
+ A1: cond 0001 1010 n d 1110 1001 t STLEXD Rd, Rt, Rt+1, [Rn]
+
+ 31 28 24 19 15 11 7 3
+ T1: 111 0100 01101 n t 1111 1100 1111 LDAEXB Rt, [Rn]
+ T1: 111 0100 01101 n t 1111 1101 1111 LDAEXH Rt, [Rn]
+ T1: 111 0100 01101 n t 1111 1110 1111 LDAEX Rt, [Rn]
+ T1: 111 0100 01101 n t t2 1111 1111 LDAEXD Rt, Rt2, [Rn]
+
+ T1: 111 0100 01100 n t 1111 1100 d STLEXB Rd, Rt, [Rn]
+ T1: 111 0100 01100 n t 1111 1101 d STLEXH Rd, Rt, [Rn]
+ T1: 111 0100 01100 n t 1111 1110 d STLEX Rd, Rt, [Rn]
+ T1: 111 0100 01100 n t t2 1111 d STLEXD Rd, Rt, Rt2, [Rn]
+ */
+ {
+ UInt nn = 16; // invalid
+ UInt tt = 16; // invalid
+ UInt tt2 = 16; // invalid
+ UInt dd = 16; // invalid
+ UInt szBlg2 = 4; // invalid
+ Bool isLoad = False;
+ Bool gate = False;
+ if (isT) {
+ if (INSN(31,21) == BITS11(1,1,1,0,1,0,0,0,1,1,0)
+ && INSN(7,6) == BITS2(1,1)) {
+ isLoad = INSN(20,20) == 1;
+ nn = INSN(19,16);
+ tt = INSN(15,12);
+ tt2 = INSN(11,8);
+ szBlg2 = INSN(5,4);
+ dd = INSN(3,0);
+ gate = True;
+ if (szBlg2 < BITS2(1,1) && tt2 != BITS4(1,1,1,1)) gate = False;
+ if (isLoad && dd != BITS4(1,1,1,1)) gate = False;
+ // re-set not-used register values to invalid
+ if (szBlg2 < BITS2(1,1)) tt2 = 16;
+ if (isLoad) dd = 16;
+ }
+ } else {
+ /* ARM encoding. Do the load and store cases separately as
+ the register numbers are in different places and a combined decode
+ is too confusing. */
+ if (INSN(27,23) == BITS5(0,0,0,1,1) && INSN(20,20) == 1
+ && INSN(11,0) == BITS12(1,1,1,0,1,0,0,1,1,1,1,1)) {
+ szBlg2 = INSN(22,21);
+ isLoad = True;
+ nn = INSN(19,16);
+ tt = INSN(15,12);
+ gate = True;
+ }
+ else
+ if (INSN(27,23) == BITS5(0,0,0,1,1) && INSN(20,20) == 0
+ && INSN(11,4) == BITS8(1,1,1,0,1,0,0,1)) {
+ szBlg2 = INSN(22,21);
+ isLoad = False;
+ nn = INSN(19,16);
+ dd = INSN(15,12);
+ tt = INSN(3,0);
+ gate = True;
+ }
+ if (gate) {
+ // Rearrange szBlg2 bits to be the same as the Thumb case
+ switch (szBlg2) {
+ case 2: szBlg2 = 0; break;
+ case 3: szBlg2 = 1; break;
+ case 0: szBlg2 = 2; break;
+ case 1: szBlg2 = 3; break;
+ default: /*NOTREACHED*/vassert(0);
+ }
+ }
+ }
+ // Perform further checks on register numbers
+ if (gate) {
+ /**/ if (isT && isLoad) {
+ // Thumb load
+ if (szBlg2 < 3) {
+ if (! (tt != 13 && tt != 15 && nn != 15)) gate = False;
+ } else {
+ if (! (tt != 13 && tt != 15 && tt2 != 13 && tt2 != 15
+ && tt != tt2 && nn != 15)) gate = False;
+ }
+ }
+ else if (isT && !isLoad) {
+ // Thumb store
+ if (szBlg2 < 3) {
+ if (! (dd != 13 && dd != 15 && tt != 13 && tt != 15
+ && nn != 15 && dd != nn && dd != tt)) gate = False;
+ } else {
+ if (! (dd != 13 && dd != 15 && tt != 13 && tt != 15
+ && tt2 != 13 && tt2 != 15 && nn != 15 && dd != nn
+ && dd != tt && dd != tt2)) gate = False;
+ }
+ }
+ else if (!isT && isLoad) {
+ // ARM Load
+ if (szBlg2 < 3) {
+ if (! (tt != 15 && nn != 15)) gate = False;
+ } else {
+ if (! (tt & 1) == 0 && tt != 14 && nn != 15) gate = False;
+ vassert(tt2 == 16/*invalid*/);
+ tt2 = tt + 1;
+ }
+ }
+ else if (!isT && !isLoad) {
+ // ARM Store
+ if (szBlg2 < 3) {
+ if (! (dd != 15 && tt != 15 && nn != 15
+ && dd != nn && dd != tt)) gate = False;
+ } else {
+ if (! (dd != 15 && (tt & 1) == 0 && tt != 14 && nn != 15
+ && dd != nn && dd != tt && dd != tt+1)) gate = False;
+ vassert(tt2 == 16/*invalid*/);
+ tt2 = tt + 1;
+ }
+ }
+ else /*NOTREACHED*/vassert(0);
+ }
+ // Paranoia ..
+ vassert(szBlg2 <= 3);
+ if (szBlg2 < 3) { vassert(tt2 == 16/*invalid*/); }
+ else { vassert(tt2 <= 14); }
+ if (isLoad) { vassert(dd == 16/*invalid*/); }
+ else { vassert(dd <= 14); }
+ // If we're still good even after all that, generate the IR.
+ if (gate) {
+ /* First, go unconditional. Staying in-line is too complex. */
+ if (isT) {
+ vassert(condT != IRTemp_INVALID);
+ mk_skip_over_T32_if_cond_is_false( condT );
+ } else {
+ if (condT != IRTemp_INVALID) {
+ mk_skip_over_A32_if_cond_is_false( condT );
+ condT = IRTemp_INVALID;
+ }
+ }
+ /* Now the load or store. */
+ IRType ty = Ity_INVALID; /* the type of the transferred data */
+ const HChar* nm = NULL;
+ switch (szBlg2) {
+ case 0: nm = "b"; ty = Ity_I8; break;
+ case 1: nm = "h"; ty = Ity_I16; break;
+ case 2: nm = ""; ty = Ity_I32; break;
+ case 3: nm = "d"; ty = Ity_I64; break;
+ default: vassert(0);
+ }
+ IRExpr* ea = isT ? getIRegT(nn) : getIRegA(nn);
+ if (isLoad) {
+ // LOAD. Transaction, then fence.
+ IROp widen = Iop_INVALID;
+ switch (szBlg2) {
+ case 0: widen = Iop_8Uto32; break;
+ case 1: widen = Iop_16Uto32; break;
+ case 2: case 3: break;
+ default: vassert(0);
+ }
+ IRTemp res = newTemp(ty);
+ // FIXME: assumes little-endian guest
+ stmt( IRStmt_LLSC(Iend_LE, res, ea, NULL/*this is a load*/) );
+
+# define PUT_IREG(_nnz, _eez) \
+ do { vassert((_nnz) <= 14); /* no writes to the PC */ \
+ if (isT) { putIRegT((_nnz), (_eez), IRTemp_INVALID); } \
+ else { putIRegA((_nnz), (_eez), \
+ IRTemp_INVALID, Ijk_Boring); } } while(0)
+ if (ty == Ity_I64) {
+ // FIXME: assumes little-endian guest
+ PUT_IREG(tt, unop(Iop_64to32, mkexpr(res)));
+ PUT_IREG(tt2, unop(Iop_64HIto32, mkexpr(res)));
+ } else {
+ PUT_IREG(tt, widen == Iop_INVALID
+ ? mkexpr(res) : unop(widen, mkexpr(res)));
+ }
+ stmt(IRStmt_MBE(Imbe_Fence));
+ if (ty == Ity_I64) {
+ DIP("ldrex%s%s r%u, r%u, [r%u]\n",
+ nm, isT ? "" : nCC(conq), tt, tt2, nn);
+ } else {
+ DIP("ldrex%s%s r%u, [r%u]\n", nm, isT ? "" : nCC(conq), tt, nn);
+ }
+# undef PUT_IREG
+ } else {
+ // STORE. Fence, then transaction.
+ IRTemp resSC1, resSC32, data;
+ IROp narrow = Iop_INVALID;
+ switch (szBlg2) {
+ case 0: narrow = Iop_32to8; break;
+ case 1: narrow = Iop_32to16; break;
+ case 2: case 3: break;
+ default: vassert(0);
+ }
+ stmt(IRStmt_MBE(Imbe_Fence));
+ data = newTemp(ty);
+# define GET_IREG(_nnz) (isT ? getIRegT(_nnz) : getIRegA(_nnz))
+ assign(data,
+ ty == Ity_I64
+ // FIXME: assumes little-endian guest
+ ? binop(Iop_32HLto64, GET_IREG(tt2), GET_IREG(tt))
+ : narrow == Iop_INVALID
+ ? GET_IREG(tt)
+ : unop(narrow, GET_IREG(tt)));
+# undef GET_IREG
+ resSC1 = newTemp(Ity_I1);
+ // FIXME: assumes little-endian guest
+ stmt( IRStmt_LLSC(Iend_LE, resSC1, ea, mkexpr(data)) );
+
+ /* Set rDD to 1 on failure, 0 on success. Currently we have
+ resSC1 == 0 on failure, 1 on success. */
+ resSC32 = newTemp(Ity_I32);
+ assign(resSC32,
+ unop(Iop_1Uto32, unop(Iop_Not1, mkexpr(resSC1))));
+ vassert(dd <= 14); /* no writes to the PC */
+ if (isT) {
+ putIRegT(dd, mkexpr(resSC32), IRTemp_INVALID);
+ } else {
+ putIRegA(dd, mkexpr(resSC32), IRTemp_INVALID, Ijk_Boring);
+ }
+ if (ty == Ity_I64) {
+ DIP("strex%s%s r%u, r%u, r%u, [r%u]\n",
+ nm, isT ? "" : nCC(conq), dd, tt, tt2, nn);
+ } else {
+ DIP("strex%s%s r%u, r%u, [r%u]\n",
+ nm, isT ? "" : nCC(conq), dd, tt, nn);
+ }
+ } /* if (isLoad) */
+ return True;
+ } /* if (gate) */
+ /* else fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
|