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From: <sv...@va...> - 2015-12-28 22:02:26
|
Author: philippe
Date: Mon Dec 28 22:02:18 2015
New Revision: 15753
Log:
Fix 353660 XML in auxwhat tag not escaping reserved symbols properly
Changed a few %s or %pS into %ps in m_addrinfo.c
(based on code reading matching the pattern given in the bug report,
as there was no reproducer).
Modified:
trunk/NEWS
trunk/coregrind/m_addrinfo.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Mon Dec 28 22:02:18 2015
@@ -45,6 +45,7 @@
353084 arm64 doesn't support sigpending system call
353370 don't advertise RDRAND in cpuid for Core-i7-4910-like avx2 machine
353398 WARNING: unhandled amd64-solaris syscall: 207
+353660 XML in auxwhat tag not escaping reserved symbols properly
353680 s390x: Crash with certain glibc versions due to non-implemented TBEGIN
353891 Assert 'bad_scanned_addr < VG_ROUNDDN(start+len, sizeof(Addr))' failed
353917 unhandled amd64-solaris syscall fchdir(120)
Modified: trunk/coregrind/m_addrinfo.c
==============================================================================
--- trunk/coregrind/m_addrinfo.c (original)
+++ trunk/coregrind/m_addrinfo.c Mon Dec 28 22:02:18 2015
@@ -463,7 +463,7 @@
hasfn = VG_(get_fnname)(ai->Addr.Stack.IP, &fn);
if (hasfn || hasfile)
- VG_(emit)( "%sin frame #%d, created by %s (%s:%s)%s\n",
+ VG_(emit)( "%sin frame #%d, created by %ps (%ps:%s)%s\n",
xpre,
ai->Addr.Stack.frameNo,
hasfn ? fn : "???",
@@ -573,7 +573,7 @@
case Addr_DataSym:
VG_(emit)( "%sAddress 0x%lx is %llu bytes "
- "inside data symbol \"%pS\"%s\n",
+ "inside data symbol \"%ps\"%s\n",
xpre, a,
(ULong)ai->Addr.DataSym.offset,
ai->Addr.DataSym.name,
@@ -595,7 +595,7 @@
break;
case Addr_SectKind:
- VG_(emit)( "%sAddress 0x%lx is in the %pS segment of %pS%s\n",
+ VG_(emit)( "%sAddress 0x%lx is in the %ps segment of %ps%s\n",
xpre, a,
VG_(pp_SectKind)(ai->Addr.SectKind.kind),
ai->Addr.SectKind.objname,
@@ -627,7 +627,7 @@
case Addr_SegmentKind:
VG_(emit)( "%sAddress 0x%lx is in "
- "a %s%s%s %s%s%pS segment%s\n",
+ "a %s%s%s %s%s%ps segment%s\n",
xpre,
a,
ai->Addr.SegmentKind.hasR ? "r" : "-",
|
|
From: Julian S. <js...@ac...> - 2015-12-28 16:44:17
|
[Arriving very late at the party] What this does is Reg1 = SP + (Reg2 << shift-amount) If you consider what that could possibly be used for .. it seems like it would compute the end address of a stack allocated array of Reg2 items, each of size (1 << shift-amount). I suspect that's why we've only ever seen shift amounts of 0,1,2,3 up till this point. Given that these array items are not likely to be very big in practice, and given that I have great difficulty in understanding the ARM ARM limitations on shift amounts for this particular instruction, I'd be more comfortable increasing the allowable shift amounts up to say 8 (allowing element sizes of up to 256) but not more than that. If it breaks again we could increase it, but given that it's taken years even for the case '4' to appear, I think that's fairly unlikely. In summary, I am inclined to change the <= 31 to <= 8. J On 24/11/15 23:15, Florian Krohm wrote: > OK, thanks for the explanation. Attached is the patch I'm proposing > which removes the ad-hoc limitation and allows shift amounts up to and > including 31. I looked at the downstream code and it has not problems > handling such shift amounts. > I'm copying Julian to he can chime in and offer an explanation as to why > that limitation existed at all. If there is no yelling I'm going to > commit this in the next couple of days. > > Florian > > On 24.11.2015 21:14, Michael Daniels wrote: >>> are there other values >4 possible, that we should handle as well? >> >> Shifts are 5 bits, so its possible this value could be as high as 31. >> Like the other patch, the check could/should probably just be >> removed altogether. It was just not clear why it was limited in the >> first place, so I only bumped it as needed. >> ________________________________________ >> From: Florian Krohm [fl...@ei...] >> Sent: Tuesday, November 24, 2015 2:48 PM >> To: Michael Daniels; val...@li... >> Subject: Re: [Valgrind-developers] [PATCH][VEX] Bump allowed shift value for "add.w reg, sp, reg, lsl #N" >> >> I'm not familiar with arm. But I'm wondering whether allowing teh value >> 4 here is the right thing to do. Or, phrased differently: are there >> other values >4 possible, that we should handle as well? >> >> Florian >> >> >> On 19.11.2015 17:51, Michael Daniels wrote: >>> Hello, >>> >>> When using GCC 5.2 I am seeing this assembly generated in some cases: >>> >>> add.w reg, sp, reg, lsl #4 >>> >>> The current limit is 3 though, so it was causing it to be caught as an unhandled instruction. >>> >>> Patch attached to bump the number from 3 to 4. >>> >>> Thanks, >>> >>> Mike >>> --------------------------------------------------------------------- >>> This transmission (including any attachments) may contain confidential information, privileged material (including material protected by the solicitor-client or other applicable privileges), or constitute non-public information. Any use of this information by anyone other than the intended recipient is prohibited. If you have received this transmission in error, please immediately reply to the sender and delete this information from your system. Use, dissemination, distribution, or reproduction of this transmission by unintended recipients is not authorized and may be unlawful. >>> >>> >>> >>> ------------------------------------------------------------------------------ >>> >>> >>> >>> _______________________________________________ >>> Valgrind-developers mailing list >>> Val...@li... >>> https://lists.sourceforge.net/lists/listinfo/valgrind-developers >>> >> >> > |