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From: Michael D. <mda...@qn...> - 2015-11-29 22:27:44
|
Any thoughts on this one? ________________________________________ From: Michael Daniels Sent: Thursday, November 19, 2015 12:07 PM To: val...@li... Subject: [PATCH][VEX] Remove limit on strd's negative immediates Hello, It seems newer versions of libgcc[0] have started using assembly like this: strd ip, lr, [sp, #-16]! Since VEX only checks for #-8, this is causing lots of complaints about invalid writes below the stack pointer. Attached is a patch to remove the check all together, allowing any negative immediates without generating a lot of noise. [0] https://github.com/gcc-mirror/gcc/blob/7aea4e7cdcd40d7bd47c64e76325a62191887d1b/libgcc/config/arm/bpabi.S#L151 Thanks, Mike |
|
From: Florian K. <fl...@ei...> - 2015-11-29 15:34:59
|
Patch applied as VEX r3206 Florian On 24.11.2015 23:15, Florian Krohm wrote: > OK, thanks for the explanation. Attached is the patch I'm proposing > which removes the ad-hoc limitation and allows shift amounts up to and > including 31. I looked at the downstream code and it has not problems > handling such shift amounts. > I'm copying Julian to he can chime in and offer an explanation as to why > that limitation existed at all. If there is no yelling I'm going to > commit this in the next couple of days. > > Florian > > On 24.11.2015 21:14, Michael Daniels wrote: >>> are there other values >4 possible, that we should handle as well? >> >> Shifts are 5 bits, so its possible this value could be as high as 31. >> Like the other patch, the check could/should probably just be >> removed altogether. It was just not clear why it was limited in the >> first place, so I only bumped it as needed. >> ________________________________________ >> From: Florian Krohm [fl...@ei...] >> Sent: Tuesday, November 24, 2015 2:48 PM >> To: Michael Daniels; val...@li... >> Subject: Re: [Valgrind-developers] [PATCH][VEX] Bump allowed shift value for "add.w reg, sp, reg, lsl #N" >> >> I'm not familiar with arm. But I'm wondering whether allowing teh value >> 4 here is the right thing to do. Or, phrased differently: are there >> other values >4 possible, that we should handle as well? >> >> Florian >> >> >> On 19.11.2015 17:51, Michael Daniels wrote: >>> Hello, >>> >>> When using GCC 5.2 I am seeing this assembly generated in some cases: >>> >>> add.w reg, sp, reg, lsl #4 >>> >>> The current limit is 3 though, so it was causing it to be caught as an unhandled instruction. >>> >>> Patch attached to bump the number from 3 to 4. >>> >>> Thanks, >>> >>> Mike |
|
From: <sv...@va...> - 2015-11-29 15:20:51
|
Author: florian
Date: Sun Nov 29 15:20:43 2015
New Revision: 3206
Log:
Handle shift amounts 0..31. It is unclear why the shift amounts
were initially restricted to 0..3.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sun Nov 29 15:20:43 2015
@@ -19665,10 +19665,10 @@
UInt how = INSN1(5,4);
Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
- /* but allow "add.w reg, sp, reg, lsl #N for N=0,1,2 or 3
+ /* but allow "add.w reg, sp, reg, lsl #N for N=0..31
(T3) "ADD (SP plus register) */
if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
- && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
+ && rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
valid = True;
}
/* also allow "sub.w reg, sp, reg w/ no shift
|