You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
|
|
1
(7) |
2
(5) |
3
(2) |
4
(8) |
5
(10) |
|
6
(3) |
7
(9) |
8
(7) |
9
(8) |
10
(7) |
11
(4) |
12
(11) |
|
13
(5) |
14
(17) |
15
(6) |
16
(15) |
17
|
18
(3) |
19
(1) |
|
20
(6) |
21
(18) |
22
(5) |
23
(9) |
24
(6) |
25
(3) |
26
(1) |
|
27
(1) |
28
|
29
(8) |
30
(5) |
|
|
|
|
From: Florian K. <fl...@ei...> - 2015-09-15 20:30:33
|
On 15.09.2015 21:55, Carl E. Love wrote:
> --- a/memcheck/tests/vbit-test/irops.c
> +++ b/memcheck/tests/vbit-test/irops.c
> @@ -1143,6 +1143,38 @@ get_irop(IROp op)
> return p->amd64 ? p : NULL;
> #endif
> #ifdef __powerpc__
> +#define MIN_POWER_ISA "../../../tests/min_power_isa"
> +
> + switch (op) {
> + case Iop_DivS64E:
> + case Iop_DivU64E:
> + case Iop_DivU32E:
> + case Iop_DivS32E:
> + case Iop_F64toI64U:
> + case Iop_F64toI32U:
> + case Iop_I64UtoF64:
> + case Iop_I64UtoF32:
> + case Iop_I64StoD64: {
> + int rc;
> + /* IROps require a processor that supports ISA 2.06 or newer */
> + rc = system(MIN_POWER_ISA " 2.06 ");
> + /* MIN_POWER_ISA returns 1 if underlying HW supports the
> + * specified ISA or newer.
> + */
> + if (rc == 0) return NULL;
> + if (rc > 2) {
> + fprintf(stderr,
> + " ERROR, min_power_isa() return code is invalid.\n");
> + exit(1);
util.c defines panic(const char *) which you could use here instead of
the fprintf for consistency.
> diff --git a/tests/Makefile.am b/tests/Makefile.am
> index 708c28e..e3c51ab 100644
> --- a/tests/Makefile.am
> +++ b/tests/Makefile.am
> @@ -1,6 +1,26 @@
>
> include $(top_srcdir)/Makefile.tool-tests.am
>
> +if HAS_ISA_2_05
> +ISA_2_05_FLAG = -DHAS_ISA_2_05
> +else
> +ISA_2_05_FLAG =
> +endif
> +
> +if HAS_ISA_2_06
> +ISA_2_06_FLAG = -DHAS_ISA_2_06
> +else
> +ISA_2_06_FLAG =
> +endif
> +
> +if HAS_ISA_2_07
> +ISA_2_07_FLAG = -DHAS_ISA_2_07
> +else
> +ISA_2_07_FLAG =
> +endif
> +
> +min_power_isa_FLAGS = $(HAS_ISA_2_05) $(HAS_ISA_2_06) $(HAS_ISA_2_07)
> +
> dist_noinst_SCRIPTS = \
> check_headers_and_includes \
> check_makefile_consistency \
> @@ -29,7 +49,8 @@ check_PROGRAMS = \
> s390x_features \
> mips_features \
> power_insn_available \
> - is_ppc64_BE
> + is_ppc64_BE \
> + min_power_isa
>
> AM_CFLAGS += $(AM_FLAG_M3264_PRI)
> AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
> @@ -40,3 +61,4 @@ else
> x86_amd64_features_CFLAGS = $(AM_CFLAGS)
> endif
>
> +min_power_isa_CFLAGS = $(min_power_isa_FLAGS)
> diff --git a/tests/min_power_isa.c b/tests/min_power_isa.c
> new file mode 100644
> index 0000000..6fed596
> --- /dev/null
> +++ b/tests/min_power_isa.c
> @@ -0,0 +1,67 @@
> +#include <stdio.h>
> +#include <stdbool.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <signal.h>
stdbool.h and signal.h are not needed.
> +
> +#define TRUE 1
> +#define FALSE 0
> +
> +/* main() */
> +int main(int argc, char **argv)
> +{
> + /* This program is passed in a minimum ISA that the underlying hardwre
> + * needs to support. If the HW supports this ISA or newer, return 1
> + * for true. Otherwise, return 0 for false. Return 2 for usage error.
> + */
> + int status;
> + char *min_isa;
> + int isa_level = 0;
> +
> + /* set the isa_level set by the Make */
> +#ifdef HWCAP_HAS_ISA_2_05
> + isa_level = 5;
> +#endif
> +
Hmm... The Makefile defines HAS_ISA_2_05 etc... not HWCAP_HAS_ISA_2_05
> + min_isa = argv[1];
> +
> + if (strcmp (min_isa, "2.05") == 0) {
> + if (isa_level >= 5) {
> + status = TRUE;
> + } else {
> + status = FALSE;
> + }
As a minor comment: you could simplify the control flow here:
if (strcmp (min_isa, "2.05") == 0)
return isa_level >= 5;
if (strcmp (min_isa, "2.06") == 0)
return isa_level >= 6;
and so on...
Florian
> +
> + } else if (strcmp (min_isa, "2.06") == 0) {
> + if (isa_level >= 6) {
> + status = TRUE;
> + } else {
> + status = FALSE;
> + }
> +
> + } else if (strcmp (min_isa, "2.07") == 0) {
> + if (isa_level >= 7) {
> + status = TRUE;
> + } else {
> + status = FALSE;
> + }
> +
> + } else {
> + status = FALSE;
> + }
> +
> + return status;
> +}
>
|
|
From: Philippe W. <phi...@sk...> - 2015-09-15 20:24:47
|
On Tue, 2015-09-15 at 04:19 -0400, Yue Chen wrote:
> Hi,
>
>
> Due to instrumentation, when doing memory tracing using tool lackey
> (``--tool=lackey --trace-mem=yes''), the recorded instruction
> addresses seem different from the original program's (e.g., ``I
> 04002166, 2''), and only have a 32-bit format output.
>
>
> Is there any way that I can translate this address to the original
> one?
>
>
> My environment is x86-64 FreeBSD 10.1.
FreeBSD port is not part of the valgrind (IMO, would be good
to merge the port).
Apart of that, checking on a 32 bits and 64 bits linux, lackey properly
shows the address of the instructions being executed.
This is the way I tested:
gdb ./memcheck/tests/trivialleak
(gdb) disass main
//// select one or 2 relevant instructions
Then run lackey, and see that these instructions were properly
reported, with their length.
The fact that they look only 32 bits (even on a 64 bits) is that lackey
is printing the addresses with code such as:
VG_(printf)("I %08lx,%lu\n", addr, size);
but that will properly print the correct values if addresses are > 4GB.
So, if really the addresses reported by lackey do not match your
executable, maybe there is something strange on FreeBSD port ?
Philippe
|
|
From: Carl E. L. <ce...@us...> - 2015-09-15 20:18:36
|
Posted to the wrong list the first time.
Carl Love
On Tue, 2015-09-15 at 13:15 -0700, Carl E. Love wrote:
> Julian:
>
> I would like to push the following patch into the 3.11 release. It adds
> support for the Program Priority register. I have created a bugzilla
> for this issue, bugzilla 352769.
>
> Please let me know if it is OK to push this patch to main line for inclusion
> in the 3.11 release or not. Thanks.
>
> Carl Love
>
> ---------------------------------------------------
>
> Add support for the Program Priority Register
>
> Added the Program Priority Register (PPR), support to read and write it
> via the mfspr and mtspr instructions as well as the special OR instruction
> No Op instructions. The setting of the PPR is dependent on the value in
> the Problem State Priority Boost register. Basic support for this register
> was added. Not all of the PSPB register functionality was added.
>
> Signed-off-by: Carl Love <ca...@us...>
> ---
> VEX/priv/guest_ppc_helpers.c | 4 ++
> VEX/priv/guest_ppc_toIR.c | 132 +++++++++++++++++++++++++++++++++++++++++++
> VEX/pub/libvex_guest_ppc32.h | 9 +--
> VEX/pub/libvex_guest_ppc64.h | 10 ++--
> 4 files changed, 147 insertions(+), 8 deletions(-)
>
> diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
> index 00137e4..08a0753 100644
> --- a/VEX/priv/guest_ppc_helpers.c
> +++ b/VEX/priv/guest_ppc_helpers.c
> @@ -521,6 +521,8 @@ void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
>
> vex_state->guest_IP_AT_SYSCALL = 0;
> vex_state->guest_SPRG3_RO = 0;
> + vex_state->guest_PPR = 0x4ULL << 50; // medium priority
> + vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
>
> vex_state->padding1 = 0;
> vex_state->padding2 = 0;
> @@ -691,6 +693,8 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
> vex_state->guest_TFHAR = 0;
> vex_state->guest_TFIAR = 0;
> vex_state->guest_TEXASR = 0;
> + vex_state->guest_PPR = 0x4ULL << 50; // medium priority
> + vex_state->guest_PSPB = 0x00; // an arbitrary non-zero value to start with
> }
>
>
> diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
> index 1f28da6..c6af3d0 100644
> --- a/VEX/priv/guest_ppc_toIR.c
> +++ b/VEX/priv/guest_ppc_toIR.c
> @@ -288,6 +288,8 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f )
> #define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR)
> #define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU)
> #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
> +#define OFFB_PPR offsetofPPCGuestState(guest_PPR)
> +#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB)
>
>
> /*------------------------------------------------------------*/
> @@ -438,6 +440,14 @@ typedef enum {
> PPC_GST_TFIAR, // Transactional Failure Instruction Address Register
> PPC_GST_TEXASR, // Transactional EXception And Summary Register
> PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper
> + PPC_GST_PPR, // Program Priority register
> + PPC_GST_PPR32, // Upper 32-bits of Program Priority register
> + PPC_GST_PSPB, /* Problem State Priority Boost register, Note, the
> + * register is initialized to a non-zero value. Currently
> + * Valgrind is not supporting the register value to
> + * automatically decrement. Could be added later if
> + * needed.
> + */
> PPC_GST_MAX
> } PPC_GST;
>
> @@ -2747,6 +2757,15 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
> case PPC_GST_TFIAR:
> return IRExpr_Get( OFFB_TFIAR, ty );
>
> + case PPC_GST_PPR:
> + return IRExpr_Get( OFFB_PPR, ty );
> +
> + case PPC_GST_PPR32:
> + return unop( Iop_64HIto32, IRExpr_Get( OFFB_PPR, ty ) );
> +
> + case PPC_GST_PSPB:
> + return IRExpr_Get( OFFB_PSPB, ty );
> +
> default:
> vex_printf("getGST(ppc): reg = %u", reg);
> vpanic("getGST(ppc)");
> @@ -2926,6 +2945,95 @@ static void putGST ( PPC_GST reg, IRExpr* src )
> vassert( ty_src == Ity_I64 );
> stmt( IRStmt_Put( OFFB_TFHAR, src ) );
> break;
> +
> + case PPC_GST_PPR32:
> + case PPC_GST_PPR:
> + {
> + /* The Program Priority Register (PPR) stores the priority in
> + * bits [52:50]. The user setable priorities are:
> + *
> + * 001 very low
> + * 010 low
> + * 011 medium low
> + * 100 medium
> + * 101 medium high
> + *
> + * If the argument is not between 0b001 and 0b100 the priority is set
> + * to 0b100. The priority can only be set to 0b101 if the the Problem
> + * State Boost Register is non-zero. The value of the PPR is not
> + * changed if the input is not valid.
> + */
> +
> + IRTemp not_valid = newTemp(Ity_I64);
> + IRTemp has_perm = newTemp(Ity_I64);
> + IRTemp new_src = newTemp(Ity_I64);
> + IRTemp PSPB_val = newTemp(Ity_I64);
> + IRTemp value = newTemp(Ity_I64);
> +
> + vassert(( ty_src == Ity_I64 ) || ( ty_src == Ity_I32 ));
> + assign( PSPB_val, binop( Iop_32HLto64,
> + mkU32( 0 ),
> + IRExpr_Get( OFFB_PSPB, Ity_I32 ) ) );
> + if( reg == PPC_GST_PPR32 ) {
> + vassert( ty_src == Ity_I32 );
> + assign( value, binop( Iop_32HLto64,
> + mkU32(0),
> + binop( Iop_And32,
> + binop( Iop_Shr32, src, mkU8( 18 ) ),
> + mkU32( 0x7 ) ) ) );
> + } else {
> + vassert( ty_src == Ity_I64 );
> + assign( value, binop( Iop_And64,
> + binop( Iop_Shr64, src, mkU8( 50 ) ),
> + mkU64( 0x7 ) ) );
> + }
> + assign( has_perm,
> + binop( Iop_And64,
> + unop( Iop_1Sto64,
> + binop( Iop_CmpEQ64,
> + mkexpr( PSPB_val ),
> + mkU64( 0 ) ) ),
> + unop( Iop_1Sto64,
> + binop( Iop_CmpEQ64,
> + mkU64( 0x5 ),
> + mkexpr( value ) ) ) ) );
> + assign( not_valid,
> + binop( Iop_Or64,
> + unop( Iop_1Sto64,
> + binop( Iop_CmpEQ64,
> + mkexpr( value ),
> + mkU64( 0 ) ) ),
> + unop( Iop_1Sto64,
> + binop( Iop_CmpLT64U,
> + mkU64( 0x5 ),
> + mkexpr( value ) ) ) ) );
> + assign( new_src,
> + binop( Iop_Or64,
> + binop( Iop_And64,
> + unop( Iop_Not64,
> + mkexpr( not_valid ) ),
> + src ),
> + binop( Iop_And64,
> + mkexpr( not_valid ),
> + binop( Iop_Or64,
> + binop( Iop_And64,
> + mkexpr( has_perm),
> + binop( Iop_Shl64,
> + mkexpr( value ),
> + mkU8( 50 ) ) ),
> + binop( Iop_And64,
> + IRExpr_Get( OFFB_PPR, ty ),
> + unop( Iop_Not64,
> + mkexpr( has_perm )
> + ) ) ) ) ) );
> +
> + /* make sure we only set the valid bit field [52:50] */
> + stmt( IRStmt_Put( OFFB_PPR,
> + binop( Iop_And64,
> + mkexpr( new_src ),
> + mkU64( 0x1C000000000000) ) ) );
> + break;
> + }
> default:
> vex_printf("putGST(ppc): reg = %u", reg);
> vpanic("putGST(ppc)");
> @@ -7131,6 +7239,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
> DIP("mfspr r%u (TEXASRU)\n", rD_addr);
> putIReg( rD_addr, getGST( PPC_GST_TEXASRU) );
> break;
> + case 0x9F: // 159
> + DIP("mfspr r%u (PSPB)\n", rD_addr);
> + putIReg( rD_addr, getGST( PPC_GST_PSPB) );
> + break;
> + case 0x380: // 896
> + DIP("mfspr r%u (PPR)\n", rD_addr);
> + putIReg( rD_addr, getGST( PPC_GST_PPR) );
> + break;
> + case 0x382: // 898
> + DIP("mfspr r%u (PPR)32\n", rD_addr);
> + putIReg( rD_addr, getGST( PPC_GST_PPR32) );
> + break;
> case 0x100:
> DIP("mfvrsave r%u\n", rD_addr);
> putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),
> @@ -7287,6 +7407,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
> DIP("mtspr r%u (TEXASR)\n", rS_addr);
> putGST( PPC_GST_TEXASR, mkexpr(rS) );
> break;
> + case 0x9F: // 159
> + DIP("mtspr r%u (PSPB)\n", rS_addr);
> + putGST( PPC_GST_PSPB, mkexpr(rS) );
> + break;
> + case 0x380: // 896
> + DIP("mtspr r%u (PPR)\n", rS_addr);
> + putGST( PPC_GST_PPR, mkexpr(rS) );
> + break;
> + case 0x382: // 898
> + DIP("mtspr r%u (PPR32)\n", rS_addr);
> + putGST( PPC_GST_PPR32, mkexpr(rS) );
> + break;
> default:
> vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR);
> return False;
> diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
> index 2489d55..5bebef8 100644
> --- a/VEX/pub/libvex_guest_ppc32.h
> +++ b/VEX/pub/libvex_guest_ppc32.h
> @@ -241,11 +241,12 @@ typedef
> /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
> /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
> /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
> - /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
> -
> + /* 1384 */ ULong guest_PPR; // Program Priority register
> + /* 1392 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
> + /* 1396 */ UInt guest_PSPB; // Problem State Priority Boost register
> /* Padding to make it have an 16-aligned size */
> - /* 1388 */ UInt padding2;
> -
> + /* 1400 */ UInt padding2;
> + /* 1404 */ UInt padding3;
> }
> VexGuestPPC32State;
>
> diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
> index dea2bba..f3310cb 100644
> --- a/VEX/pub/libvex_guest_ppc64.h
> +++ b/VEX/pub/libvex_guest_ppc64.h
> @@ -282,12 +282,14 @@ typedef
> /* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
> /* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
> /* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
> - /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
> + /* 1680 */ ULong guest_PPR; // Program Priority register
> + /* 1688 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
> + /* 1692 */ UInt guest_PSPB; // Problem State Priority Boost register
>
> /* Padding to make it have an 16-aligned size */
> - /* 1684 */ UInt padding1;
> - /* 1688 */ UInt padding2;
> - /* 1692 */ UInt padding3;
> + /* 1696 UInt padding1; currently not needed */
> + /* 1700 UInt padding2; currently not needed */
> + /* 1708 UInt padding3; currently not needed */
>
> }
> VexGuestPPC64State;
|
|
From: Carl E. L. <ce...@us...> - 2015-09-15 20:06:43
|
Julian:
I would like to push this fix into the Valgrind 3.11 release. Just wanted to check with
you first before I pushed it to main line as you are trying to freeze the code. Please
let me know if it is OK to push it.
I have created a bugzilla for this issue, bugzilla 352768.
Thanks.
Carl Love
------------------------------------------------------------------------------
Add support for the Power PC mbar instruction
Signed-off-by: Carl Love <ca...@us...>
---
VEX/priv/guest_ppc_toIR.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index c6af3d0..4fb45b4 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -6369,6 +6369,7 @@ static Bool dis_memsync ( UInt theInstr )
UInt b11to25 = IFIELD(theInstr, 11, 15);
UChar flag_L = ifieldRegDS(theInstr);
UInt b11to20 = IFIELD(theInstr, 11, 10);
+ UInt M0 = IFIELD(theInstr, 11, 5);
UChar rD_addr = ifieldRegDS(theInstr);
UChar rS_addr = rD_addr;
UChar rA_addr = ifieldRegA(theInstr);
@@ -6399,12 +6400,20 @@ static Bool dis_memsync ( UInt theInstr )
/* X-Form */
case 0x1F:
switch (opc2) {
- case 0x356: // eieio (Enforce In-Order Exec of I/O, PPC32 p394)
- if (b11to25 != 0 || b0 != 0) {
- vex_printf("dis_memsync(ppc)(eiei0,b11to25|b0)\n");
- return False;
+ case 0x356: // eieio or mbar (Enforce In-Order Exec of I/O, PPC32 p394)
+ if (M0 == 0) {
+ if (b11to20 != 0 || b0 != 0) {
+ vex_printf("dis_memsync(ppc)(eieio,b11to20|b0)\n");
+ return False;
+ }
+ DIP("eieio\n");
+ } else {
+ if (b11to20 != 0 || b0 != 0) {
+ vex_printf("dis_memsync(ppc)(mbar,b11to20|b0)\n");
+ return False;
+ }
+ DIP("mbar %d\n", M0);
}
- DIP("eieio\n");
/* Insert a memory fence, just to be on the safe side. */
stmt( IRStmt_MBE(Imbe_Fence) );
break;
--
2.1.0
|
|
From: Carl E. L. <ce...@us...> - 2015-09-15 19:55:53
|
Julian, Florian, Mark:
Mark recently found an issue with the proposed 3.11 release where the vbit test was failing on Power 6. I
have created a bugzilla for the issue, bugzilla 352765. I have created the following patch to address the
issue. If you can all review the patch, I would appreciate it.
We would like to include this in the 3.11 release. Julian, assuming the patch is OK, please let me know if
you would like me to push this into mainline so you can include it in 3.11 release or if you would like me
to wait. Thanks.
Carl Love
---------------------------------------------------------------------------------
>From b04421ef091cde6899bf158c42f1d9aa0dc0a60d Mon Sep 17 00:00:00 2001
From: Carl Love <ca...@us...>
Date: Tue, 15 Sep 2015 15:28:26 -0400
Subject: [PATCH 3/3] Add Power PC ISA check to the vbit-test
The support for the Valgrind Iops is dependent on the Power processor
support for various instructions. The instructions supported by a
given Power processor is based on the version of the ISA. The patch
add a check to the vbit-test to ensure it does not try to test an Iop
that generates an instruction on the host that is not supported.
Signed-off-by: Carl Love <ca...@us...>
---
memcheck/tests/vbit-test/irops.c | 32 +++++++++++++++++++
tests/Makefile.am | 24 +++++++++++++-
tests/min_power_isa.c | 67 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 122 insertions(+), 1 deletion(-)
create mode 100644 tests/min_power_isa.c
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index d0e3b58..6feb32e 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -1143,6 +1143,38 @@ get_irop(IROp op)
return p->amd64 ? p : NULL;
#endif
#ifdef __powerpc__
+#define MIN_POWER_ISA "../../../tests/min_power_isa"
+
+ switch (op) {
+ case Iop_DivS64E:
+ case Iop_DivU64E:
+ case Iop_DivU32E:
+ case Iop_DivS32E:
+ case Iop_F64toI64U:
+ case Iop_F64toI32U:
+ case Iop_I64UtoF64:
+ case Iop_I64UtoF32:
+ case Iop_I64StoD64: {
+ int rc;
+ /* IROps require a processor that supports ISA 2.06 or newer */
+ rc = system(MIN_POWER_ISA " 2.06 ");
+ /* MIN_POWER_ISA returns 1 if underlying HW supports the
+ * specified ISA or newer.
+ */
+ if (rc == 0) return NULL;
+ if (rc > 2) {
+ fprintf(stderr,
+ " ERROR, min_power_isa() return code is invalid.\n");
+ exit(1);
+ }
+ }
+ break;
+
+ /* Other */
+ default:
+ break;
+ }
+
#ifdef __powerpc64__
return p->ppc64 ? p : NULL;
#else
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 708c28e..e3c51ab 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -1,6 +1,26 @@
include $(top_srcdir)/Makefile.tool-tests.am
+if HAS_ISA_2_05
+ISA_2_05_FLAG = -DHAS_ISA_2_05
+else
+ISA_2_05_FLAG =
+endif
+
+if HAS_ISA_2_06
+ISA_2_06_FLAG = -DHAS_ISA_2_06
+else
+ISA_2_06_FLAG =
+endif
+
+if HAS_ISA_2_07
+ISA_2_07_FLAG = -DHAS_ISA_2_07
+else
+ISA_2_07_FLAG =
+endif
+
+min_power_isa_FLAGS = $(HAS_ISA_2_05) $(HAS_ISA_2_06) $(HAS_ISA_2_07)
+
dist_noinst_SCRIPTS = \
check_headers_and_includes \
check_makefile_consistency \
@@ -29,7 +49,8 @@ check_PROGRAMS = \
s390x_features \
mips_features \
power_insn_available \
- is_ppc64_BE
+ is_ppc64_BE \
+ min_power_isa
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
@@ -40,3 +61,4 @@ else
x86_amd64_features_CFLAGS = $(AM_CFLAGS)
endif
+min_power_isa_CFLAGS = $(min_power_isa_FLAGS)
diff --git a/tests/min_power_isa.c b/tests/min_power_isa.c
new file mode 100644
index 0000000..6fed596
--- /dev/null
+++ b/tests/min_power_isa.c
@@ -0,0 +1,67 @@
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <signal.h>
+
+#define TRUE 1
+#define FALSE 0
+
+/* main() */
+int main(int argc, char **argv)
+{
+ /* This program is passed in a minimum ISA that the underlying hardwre
+ * needs to support. If the HW supports this ISA or newer, return 1
+ * for true. Otherwise, return 0 for false. Return 2 for usage error.
+ */
+ int status;
+ char *min_isa;
+ int isa_level = 0;
+
+ /* set the isa_level set by the Make */
+#ifdef HWCAP_HAS_ISA_2_05
+ isa_level = 5;
+#endif
+
+#ifdef HWCAP_HAS_ISA_2_06
+ isa_level = 6;
+#endif
+
+#ifdef HWCAP_HAS_ISA_2_07
+ isa_level = 7;
+#endif
+
+ if (argc != 2) {
+ fprintf(stderr, "usage: min_power_ISA <ISA>\n" );
+ exit(2);
+ }
+
+ min_isa = argv[1];
+
+ if (strcmp (min_isa, "2.05") == 0) {
+ if (isa_level >= 5) {
+ status = TRUE;
+ } else {
+ status = FALSE;
+ }
+
+ } else if (strcmp (min_isa, "2.06") == 0) {
+ if (isa_level >= 6) {
+ status = TRUE;
+ } else {
+ status = FALSE;
+ }
+
+ } else if (strcmp (min_isa, "2.07") == 0) {
+ if (isa_level >= 7) {
+ status = TRUE;
+ } else {
+ status = FALSE;
+ }
+
+ } else {
+ status = FALSE;
+ }
+
+ return status;
+}
--
2.1.0
|
|
From: Yue C. <yc...@gm...> - 2015-09-15 08:20:21
|
Hi, Due to instrumentation, when doing memory tracing using tool lackey (``--tool=lackey --trace-mem=yes''), the recorded instruction addresses seem different from the original program's (e.g., ``I 04002166, 2''), and only have a 32-bit format output. Is there any way that I can translate this address to the original one? My environment is x86-64 FreeBSD 10.1. Best, Yue |