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From: Zhu, Y. <Yan...@vi...> - 2015-04-15 18:12:50
|
Leonard,
I finally got valgrind compiled correctly. And I just run valgrind without attaching to any command in MIPS64 OCTEON target, I got the following error. Looks like some of the shared libraries are missing:
# uname -a
Linux ViaSat 3.10.20-rt14-Cavium-Octeon #1 SMP Wed Apr 15 09:30:37 EDT 2015 mips64 GNU/Linux
# which valgrind
/usr/bin/valgrind
# valgrind
valgrind: failed to start tool 'memcheck' for platform 'mips64-linux': No such file or directory
# strace valgrind
execve("/usr/bin/valgrind", ["valgrind"], [/* 20 vars */]) = 0
brk(0) = 0x100cb0f4
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x77dad000
uname({sys="Linux", node="ViaSat", ...}) = 0
access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory)
open("/lib32-fp/tls/octeon3/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/tls/octeon3", 0x7fad6050) = -1 ENOENT (No such file or directory)
open("/lib32-fp/tls/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/tls", 0x7fad6050) = -1 ENOENT (No such file or directory)
open("/lib32-fp/octeon3/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/octeon3", 0x7fad6050) = -1 ENOENT (No such file or directory)
Attached is my own makefile to build valgrind, maybe something is not right in that make file?
Thanks,
Yanwen
From: Crestez Dan Leonard [mailto:cdl...@gm...]
Sent: Tuesday, April 14, 2015 6:02 PM
To: Zhu, Yanwen; Valgrind Developers
Subject: Re: Valgrind 13854: Cross compiling for Cavium MIPS64, N32 ABI
Hello,
You seem to be building for mips32, this is wrong. Instead of _mips32_ those object files should all contain "_mips64n32_".
You need to make sure your configure target is some form of mips64*, not mips32. What this patch does is add support for the N32 ABI as a secondary arch of mips64. What used to only build valgrind for mips64 will now build a second set of binaries for the N32 ABI. The main valgrind launcher will pick the correct mips64/mips64n32 version of the tool based on flags in the elf header.
You also need to avoid including -mabi inside any explicit CFLAGS. Apparently gcc gets confused by multiple -mabi=* flags instead of just using the last option.
Maybe you show how you are running the configure script? Also make sure you reran autogen.sh after patching and cleaned any stale binaries.
I included the valgrind-developers list because this mail thread should be public in case anyone has similar issues.
Regards,
Leonard
On Wed, Apr 15, 2015 at 12:31 AM, Zhu, Yanwen <Yan...@vi...<mailto:Yan...@vi...>> wrote:
Leonard,
Thanks for your reply, I just fixed some errors during the patch. You’re right, not too bad, just 3 files that I had to manually port the changes.
I am building valgrind for MIPS64 with -mabi=n32 using the OCTEOM cross compiler and I am seeing the following error in the linking phase:
../coregrind/link_tool_exe_linux 0x38000000 /home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/ext/bin/mips64-octeon-linux-gnu-gcc --sysroot=/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 -march=octeon3 -I/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/toolchain/linux/include -Wno-long-long -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 -march=octeon3 -fno-stack-protector -mabi=n32 -Wl,-melf32btsmipn32 -march=octeon3 -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/lib -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/usr/lib -o memcheck-mips32-linux -O2 -g -Wall -Wmissing-prototypes -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Wno-format-zero-length -fno-strict-aliasing -fno-builtin -O2 -static -nodefaultlibs -nostartfiles -u __start memcheck_mips32_linux-mc_leakcheck.o memcheck_mips32_linux-mc_malloc_wrappers.o memcheck_mips32_linux-mc_main.o memcheck_mips32_linux-mc_translate.o memcheck_mips32_linux-mc_machine.o memcheck_mips32_linux-mc_errors.o ../coregrind/libcoregrind-mips32-linux.a ../VEX/libvex-mips32-linux.a -lgcc
../coregrind/libcoregrind-mips32-linux.a(libcoregrind_mips32_linux_a-m_main.o): In function `__start':
m_main.c:(.text+0xc): undefined reference to `_gp_disp'
m_main.c:(.text+0x10): undefined reference to `_gp_disp'
collect2: error: ld returned 1 exit status
make[4]: *** [memcheck-mips32-linux] Error 1
I don’t know what’s going on here, any suggestions?
Thanks,
Yanwen
From: Crestez Dan Leonard [mailto:cdl...@gm...<mailto:cdl...@gm...>]
Sent: Tuesday, April 14, 2015 3:08 PM
To: Zhu, Yanwen
Subject: Re: Valgrind 13854: Cross compiling for Cavium MIPS64, N32 ABI
Hello,
The patches are against SVN trunk at around the time the patches were posted (it differs between V1 and V2). Backporting them to 3.10.1 should not be terribly difficult. They won't apply cleanly but I expect the issues to be minor and easily solvable. Since the tilegx port was integrated a few days ago I expect they won't apply cleanly on svn trunk either, at least not until I rebase and post the next version.
You can also try to compile directly from the git repos mentioned in the tracker item. That should "just work".
If you have problems compiling you should mention the actual build errors as well as compiler/target details. Support for N32 should be generic but I'm only actually targeting octeon chips using the cavium gcc-4.7 toolchain.
Regards,
Leonard
On Tue, Apr 14, 2015 at 7:16 PM, <Yan...@vi...<mailto:Yan...@vi...>> wrote:
Hi Leonard,
I'm trying to apply your patches for mips64n32 on valgrind 3.10.1 and there some some errors, I manually fixed the patching errors, however, I have some problem compiling it. Looks to me that your patches were not made based on 3.10.1. What version of valgrind were your patches made from? Do you have patches for 3.10.1?
|
|
From: lin z. <man...@gm...> - 2015-04-15 10:05:50
|
Hi,
Here my current patch to libVEX. And not It can translate most arm
code, exception vfp ones. Please tell me if they are useful.
Comparing to libhoudini, my implementation is not as good when float
point instr met. But other integer part works well.
---
lin zuojian
|
|
From: Florian K. <fl...@ei...> - 2015-04-15 07:40:41
|
On 15.04.2015 05:11, sv...@va... wrote: > > Add Iop_Add8, Iop_Add16 and other 8 or 16 bit ALU Iop > in the host_tilegx_isel.c > > They were removed during the code review. But without > them, the memcheck's vbit-test failed. So, simply add > them back. > The change is OK but the reason is not. You could as well have chosen to set .tilegx = 0 in irops.c for the respective IRops. Which would perhaps have been more natural for your architecture. Florian |
|
From: <sv...@va...> - 2015-04-15 03:26:45
|
Author: zliu
Date: Wed Apr 15 04:26:38 2015
New Revision: 15097
Log:
To address memcheck/tests/leak-segv-jmp test failure for TILEGX
By: Zhi-Gang Liu zh...@gm...
Modified:
trunk/memcheck/tests/leak-segv-jmp.c
Modified: trunk/memcheck/tests/leak-segv-jmp.c
==============================================================================
--- trunk/memcheck/tests/leak-segv-jmp.c (original)
+++ trunk/memcheck/tests/leak-segv-jmp.c Wed Apr 15 04:26:38 2015
@@ -168,13 +168,13 @@
{
UWord out;
__asm__ __volatile__ (
- "move r10, r0\n\t"
- "move r0, r1\n\t"
- "move r1, r2\n\t"
- "move r2, r3\n\t"
- "move r3, r4\n\t"
- "move r4, r5\n\t"
- "move r5, r6\n\t"
+ "move r10, %1\n\t"
+ "move r0, %2\n\t"
+ "move r1, %3\n\t"
+ "move r2, %4\n\t"
+ "move r3, %5\n\t"
+ "move r4, %6\n\t"
+ "move r5, %7\n\t"
"swint1 \n\t"
"move %0, r0\n\t"
: /*out*/ "=r" (out)
|
|
From: <sv...@va...> - 2015-04-15 03:22:24
|
Author: zliu
Date: Wed Apr 15 04:22:17 2015
New Revision: 15096
Log:
Add TILEGX arch. specific syscall #245, __NR_cacheflush
By:Zhi-Gang Liu
Modified:
trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c
trunk/include/vki/vki-scnums-tilegx-linux.h
Modified: trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c Wed Apr 15 04:22:17 2015
@@ -474,43 +474,44 @@
aren't visible outside this file, but that requires even more macro
magic. */
-DECL_TEMPLATE(tilegx_linux, sys_clone);
-DECL_TEMPLATE(tilegx_linux, sys_rt_sigreturn);
-DECL_TEMPLATE(tilegx_linux, sys_socket);
-DECL_TEMPLATE(tilegx_linux, sys_setsockopt);
-DECL_TEMPLATE(tilegx_linux, sys_getsockopt);
-DECL_TEMPLATE(tilegx_linux, sys_connect);
-DECL_TEMPLATE(tilegx_linux, sys_accept);
-DECL_TEMPLATE(tilegx_linux, sys_accept4);
-DECL_TEMPLATE(tilegx_linux, sys_sendto);
-DECL_TEMPLATE(tilegx_linux, sys_recvfrom);
-DECL_TEMPLATE(tilegx_linux, sys_sendmsg);
-DECL_TEMPLATE(tilegx_linux, sys_recvmsg);
-DECL_TEMPLATE(tilegx_linux, sys_shutdown);
-DECL_TEMPLATE(tilegx_linux, sys_bind);
-DECL_TEMPLATE(tilegx_linux, sys_listen);
-DECL_TEMPLATE(tilegx_linux, sys_getsockname);
-DECL_TEMPLATE(tilegx_linux, sys_getpeername);
-DECL_TEMPLATE(tilegx_linux, sys_socketpair);
-DECL_TEMPLATE(tilegx_linux, sys_semget);
-DECL_TEMPLATE(tilegx_linux, sys_semop);
-DECL_TEMPLATE(tilegx_linux, sys_semtimedop);
-DECL_TEMPLATE(tilegx_linux, sys_semctl);
-DECL_TEMPLATE(tilegx_linux, sys_msgget);
-DECL_TEMPLATE(tilegx_linux, sys_msgrcv);
-DECL_TEMPLATE(tilegx_linux, sys_msgsnd);
-DECL_TEMPLATE(tilegx_linux, sys_msgctl);
-DECL_TEMPLATE(tilegx_linux, sys_shmget);
-DECL_TEMPLATE(tilegx_linux, wrap_sys_shmat);
-DECL_TEMPLATE(tilegx_linux, sys_shmdt);
-DECL_TEMPLATE(tilegx_linux, sys_shmdt);
-DECL_TEMPLATE(tilegx_linux, sys_shmctl);
-DECL_TEMPLATE(tilegx_linux, sys_arch_prctl);
-DECL_TEMPLATE(tilegx_linux, sys_ptrace);
-DECL_TEMPLATE(tilegx_linux, sys_fadvise64);
-DECL_TEMPLATE(tilegx_linux, sys_mmap);
-DECL_TEMPLATE(tilegx_linux, sys_syscall184);
-DECL_TEMPLATE(tilegx_linux, sys_set_dataplane);
+DECL_TEMPLATE (tilegx_linux, sys_clone);
+DECL_TEMPLATE (tilegx_linux, sys_rt_sigreturn);
+DECL_TEMPLATE (tilegx_linux, sys_socket);
+DECL_TEMPLATE (tilegx_linux, sys_setsockopt);
+DECL_TEMPLATE (tilegx_linux, sys_getsockopt);
+DECL_TEMPLATE (tilegx_linux, sys_connect);
+DECL_TEMPLATE (tilegx_linux, sys_accept);
+DECL_TEMPLATE (tilegx_linux, sys_accept4);
+DECL_TEMPLATE (tilegx_linux, sys_sendto);
+DECL_TEMPLATE (tilegx_linux, sys_recvfrom);
+DECL_TEMPLATE (tilegx_linux, sys_sendmsg);
+DECL_TEMPLATE (tilegx_linux, sys_recvmsg);
+DECL_TEMPLATE (tilegx_linux, sys_shutdown);
+DECL_TEMPLATE (tilegx_linux, sys_bind);
+DECL_TEMPLATE (tilegx_linux, sys_listen);
+DECL_TEMPLATE (tilegx_linux, sys_getsockname);
+DECL_TEMPLATE (tilegx_linux, sys_getpeername);
+DECL_TEMPLATE (tilegx_linux, sys_socketpair);
+DECL_TEMPLATE (tilegx_linux, sys_semget);
+DECL_TEMPLATE (tilegx_linux, sys_semop);
+DECL_TEMPLATE (tilegx_linux, sys_semtimedop);
+DECL_TEMPLATE (tilegx_linux, sys_semctl);
+DECL_TEMPLATE (tilegx_linux, sys_msgget);
+DECL_TEMPLATE (tilegx_linux, sys_msgrcv);
+DECL_TEMPLATE (tilegx_linux, sys_msgsnd);
+DECL_TEMPLATE (tilegx_linux, sys_msgctl);
+DECL_TEMPLATE (tilegx_linux, sys_shmget);
+DECL_TEMPLATE (tilegx_linux, wrap_sys_shmat);
+DECL_TEMPLATE (tilegx_linux, sys_shmdt);
+DECL_TEMPLATE (tilegx_linux, sys_shmdt);
+DECL_TEMPLATE (tilegx_linux, sys_shmctl);
+DECL_TEMPLATE (tilegx_linux, sys_arch_prctl);
+DECL_TEMPLATE (tilegx_linux, sys_ptrace);
+DECL_TEMPLATE (tilegx_linux, sys_fadvise64);
+DECL_TEMPLATE (tilegx_linux, sys_mmap);
+DECL_TEMPLATE (tilegx_linux, sys_syscall184);
+DECL_TEMPLATE (tilegx_linux, sys_cacheflush);
+DECL_TEMPLATE (tilegx_linux, sys_set_dataplane);
PRE(sys_clone)
{
@@ -1106,6 +1107,15 @@
/* ---------------------------------------------------------------
PRE/POST wrappers for TILEGX/Linux-variant specific syscalls
------------------------------------------------------------ */
+PRE(sys_cacheflush)
+{
+ PRINT("cacheflush (%lx, %lx, %lx)", ARG1, ARG2, ARG3);
+ PRE_REG_READ3(long, "cacheflush", unsigned long, addr,
+ int, nbytes, int, cache);
+ VG_ (discard_translations) ((Addr)ARG1, (ULong) ARG2,
+ "PRE(sys_cacheflush)");
+ SET_STATUS_Success(0);
+}
PRE(sys_set_dataplane)
{
@@ -1368,6 +1378,7 @@
PLAXY(__NR_accept4, sys_accept4), // 242
+ PLAX_(__NR_cacheflush, sys_cacheflush), // 245
PLAX_(__NR_set_dataplane, sys_set_dataplane), // 246
GENXY(__NR_wait4, sys_wait4), // 260
Modified: trunk/include/vki/vki-scnums-tilegx-linux.h
==============================================================================
--- trunk/include/vki/vki-scnums-tilegx-linux.h (original)
+++ trunk/include/vki/vki-scnums-tilegx-linux.h Wed Apr 15 04:22:17 2015
@@ -406,7 +406,8 @@
* starting with this value.
*/
#define __NR_arch_specific_syscall 244
-#define __NR_set_dataplane 246
+#define __NR_cacheflush 245
+#define __NR_set_dataplane 246
#define __NR_wait4 260
#define __NR_prlimit64 261
#define __NR_fanotify_init 262
|
|
From: <sv...@va...> - 2015-04-15 03:11:44
|
Author: zliu
Date: Wed Apr 15 04:11:38 2015
New Revision: 3133
Log:
Add Iop_Add8, Iop_Add16 and other 8 or 16 bit ALU Iop
in the host_tilegx_isel.c
They were removed during the code review. But without
them, the memcheck's vbit-test failed. So, simply add
them back.
-This line, and those below, will be ignored--
M host_tilegx_isel.c
Modified:
trunk/priv/host_tilegx_isel.c
Modified: trunk/priv/host_tilegx_isel.c
==============================================================================
--- trunk/priv/host_tilegx_isel.c (original)
+++ trunk/priv/host_tilegx_isel.c Wed Apr 15 04:11:38 2015
@@ -480,26 +480,36 @@
switch (e->Iex.Binop.op) {
+ case Iop_Add8:
+ case Iop_Add16:
case Iop_Add32:
case Iop_Add64:
aluOp = GXalu_ADD;
break;
+ case Iop_Sub8:
+ case Iop_Sub16:
case Iop_Sub32:
case Iop_Sub64:
aluOp = GXalu_SUB;
break;
+ case Iop_And8:
+ case Iop_And16:
case Iop_And32:
case Iop_And64:
aluOp = GXalu_AND;
break;
+ case Iop_Or8:
+ case Iop_Or16:
case Iop_Or32:
case Iop_Or64:
aluOp = GXalu_OR;
break;
+ case Iop_Xor8:
+ case Iop_Xor16:
case Iop_Xor32:
case Iop_Xor64:
aluOp = GXalu_XOR;
|
|
From: <sv...@va...> - 2015-04-15 02:56:28
|
Author: zliu
Date: Wed Apr 15 03:56:20 2015
New Revision: 15095
Log:
Fix the bigcode test failure for TILEGX
By: Zhi-Gang Liu
Modified:
trunk/perf/bigcode.c
Modified: trunk/perf/bigcode.c
==============================================================================
--- trunk/perf/bigcode.c (original)
+++ trunk/perf/bigcode.c Wed Apr 15 03:56:20 2015
@@ -15,10 +15,12 @@
#if defined(__mips__)
#include <asm/cachectl.h>
#include <sys/syscall.h>
+#elif defined(__tilegx__)
+#include <asm/cachectl.h>
#endif
#include "tests/sys_mman.h"
-#define FN_SIZE 996 // Must be big enough to hold the compiled f()
+#define FN_SIZE 1024 // Must be big enough to hold the compiled f()
#define N_LOOPS 20000 // Should be divisible by four
#define RATIO 4 // Ratio of code sizes between the two modes
@@ -71,6 +73,8 @@
#if defined(__mips__)
syscall(__NR_cacheflush, a, FN_SIZE * n_fns, ICACHE);
+#elif defined(__tilegx__)
+ cacheflush(a, FN_SIZE * n_fns, ICACHE);
#endif
for (h = 0; h < n_reps; h += 1) {
|
|
From: <sv...@va...> - 2015-04-15 02:33:16
|
Author: zliu
Date: Wed Apr 15 03:33:09 2015
New Revision: 15094
Log:
Address minor issues in Julian's last review.
For TILEGX only.
By: Zhi-Gang Liu
Modified:
trunk/coregrind/m_debuglog.c
trunk/coregrind/m_libcassert.c
Modified: trunk/coregrind/m_debuglog.c
==============================================================================
--- trunk/coregrind/m_debuglog.c (original)
+++ trunk/coregrind/m_debuglog.c Wed Apr 15 03:33:09 2015
@@ -508,13 +508,15 @@
: "$2" );
return (UInt)(__res);
}
+
#elif defined(VGP_tilegx_linux)
+
static UInt local_sys_write_stderr ( const HChar* buf, Int n )
{
volatile Long block[2];
block[0] = (Long)buf;
block[1] = n;
- ULong __res = 0;
+ Long __res = 0;
__asm__ volatile (
"movei r0, 2 \n\t" /* stderr */
"move r1, %1 \n\t" /* buf */
Modified: trunk/coregrind/m_libcassert.c
==============================================================================
--- trunk/coregrind/m_libcassert.c (original)
+++ trunk/coregrind/m_libcassert.c Wed Apr 15 03:33:09 2015
@@ -227,7 +227,7 @@
}
#elif defined(VGP_tilegx_linux)
# define GET_STARTREGS(srP) \
- { UInt pc, sp, fp, ra; \
+ { ULong pc, sp, fp, ra; \
__asm__ __volatile__( \
"move r8, lr \n" \
"jal 0f \n" \
|
|
From: <sv...@va...> - 2015-04-15 02:16:44
|
Author: zliu
Date: Wed Apr 15 03:16:37 2015
New Revision: 3132
Log:
Removed "extern"
Delete extern in front of function TILEGXInstr *TILEGXInstr_Acas(.)
in host_tilegx_defs.c.
By: Zhi-Gang Liu
Modified:
trunk/priv/host_tilegx_defs.c
Modified: trunk/priv/host_tilegx_defs.c
==============================================================================
--- trunk/priv/host_tilegx_defs.c (original)
+++ trunk/priv/host_tilegx_defs.c Wed Apr 15 03:16:37 2015
@@ -765,8 +765,8 @@
return i;
}
-extern TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old,
- HReg addr, HReg exp, HReg new, UInt sz )
+TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old,
+ HReg addr, HReg exp, HReg new, UInt sz )
{
TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
i->tag = GXin_Acas;
|
|
From: <sv...@va...> - 2015-04-15 02:05:09
|
Author: zliu
Date: Wed Apr 15 03:05:01 2015
New Revision: 3131
Log:
Removed #if __tilegx__ ... #endif in guest_tilegx_toIR.c
Also eliminated several gcc warning message for this file.
By: Zhi-Gang Liu
zh...@gm...
Modified:
trunk/priv/guest_tilegx_toIR.c
Modified: trunk/priv/guest_tilegx_toIR.c
==============================================================================
--- trunk/priv/guest_tilegx_toIR.c (original)
+++ trunk/priv/guest_tilegx_toIR.c Wed Apr 15 03:05:01 2015
@@ -42,7 +42,6 @@
#include "guest_tilegx_defs.h"
#include "tilegx_disasm.h"
-#if __tilegx__
/*------------------------------------------------------------*/
/*--- Globals ---*/
/*------------------------------------------------------------*/
@@ -237,7 +236,7 @@
((_n == 32) ? \
unop(Iop_32Sto64, _e) : \
((_n == 16) ? \
- (Iop_16Sto64, _e) : \
+ unop(Iop_16Sto64, _e) : \
(binop(Iop_Sar64, binop(Iop_Shl64, _e, mkU8(63 - (_n))), mkU8(63 - (_n))))))
static IRStmt* dis_branch ( IRExpr* guard, ULong imm )
@@ -276,7 +275,7 @@
{
struct tilegx_decoded_instruction
decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
- ULong cins, opcode, rd, ra, rb, imm;
+ ULong cins, opcode = -1, rd, ra, rb, imm = 0;
ULong opd[4];
ULong opd_src_map, opd_dst_map, opd_imm_map;
Int use_dirty_helper;
@@ -286,9 +285,8 @@
ULong rd_wb_reg[6];
/* Tilegx is a VLIW processor, we have to commit register write after read.*/
Int rd_wb_index;
- Int n, nr_insn;
+ Int n = 0, nr_insn;
DisResult dres;
- Int stmts_used;
/* The running delta */
Long delta = delta64;
@@ -311,7 +309,7 @@
dres.jk_StopHere = Ijk_INVALID;
/* Verify the code addr is 8-byte aligned. */
- vassert((((ULong)code) & 7) == 0);
+ vassert((((Addr)code) & 7) == 0);
/* Get the instruction bundle. */
cins = *((ULong *)(Addr) code);
@@ -393,20 +391,17 @@
/* To decode the given instruction bundle. */
nr_insn = parse_insn_tilegx((tilegx_bundle_bits)cins,
- (ULong)code,
+ (ULong)(Addr)code,
decoded);
if (vex_traceflags & VEX_TRACE_FE)
- decode_and_display(&cins, 1, (ULong)code);
+ decode_and_display(&cins, 1, (ULong)(Addr)code);
/* Init. rb_wb_index */
rd_wb_index = 0;
steering_pc = -1ULL;
- // Save the current stmts_used in case we need rollback.
- stmts_used = irsb->stmts_used;
-
for (n = 0; n < nr_insn; n++) {
opcode = decoded[n].opcode->mnemonic;
Int opi;
@@ -1392,13 +1387,17 @@
use_dirty_helper = 1;
break;
case 151: /* "mfspr" */
- if (imm == 0x2780) // Get Cmpexch value
- MARK_REG_WB(rd, getIReg(70));
- else if (imm == 0x2580) // Get EX_CONTEXT_0_0
- MARK_REG_WB(rd, getIReg(576/8));
- else if (imm == 0x2581) // Get EX_CONTEXT_0_1
- MARK_REG_WB(rd, getIReg(584/8));
- else
+ t2 = newTemp(Ity_I64);
+ if (imm == 0x2780) { // Get Cmpexch value
+ assign(t2, getIReg(70));
+ MARK_REG_WB(rd, t2);
+ } else if (imm == 0x2580) { // Get EX_CONTEXT_0_0
+ assign(t2, getIReg(576 / 8));
+ MARK_REG_WB(rd, t2);
+ } else if (imm == 0x2581) { // Get EX_CONTEXT_0_1
+ assign(t2, getIReg(584 / 8));
+ MARK_REG_WB(rd, t2);
+ } else
use_dirty_helper = 1;
break;
case 152: /* "mm" */
@@ -2469,7 +2468,6 @@
return dres;
}
-#endif
/*------------------------------------------------------------*/
/*--- Top-level fn ---*/
@@ -2494,7 +2492,6 @@
{
DisResult dres;
-#if __tilegx__
/* Set globals (see top of this file) */
vassert(guest_arch == VexArchTILEGX);
@@ -2507,9 +2504,7 @@
dres = disInstr_TILEGX_WRK(resteerOkFn, resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo, sigill_diag_IN);
-#else
- dres.whatNext = Dis_StopHere;
-#endif
+
return dres;
}
|
|
From: <sv...@va...> - 2015-04-15 01:15:38
|
Author: zliu
Date: Wed Apr 15 02:15:31 2015
New Revision: 3130
Log:
Fix the evCheck assertion for TileGX
Quote from Philippe's original email.
"When guest = amd64 and host = TILEGX, the
libvexmultiarch_test asserts in TILEGX code:
vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr):
Assertion `evCheckSzB_TILEGX() ==
(UChar*)p - (UChar*)p0' failed."
This patch make sure that evCheck always emits
exact 80 bytes instruction stream.
By: Zhi-Gang Liu
zh...@gm...
Modified:
trunk/priv/host_tilegx_defs.c
Modified: trunk/priv/host_tilegx_defs.c
==============================================================================
--- trunk/priv/host_tilegx_defs.c (original)
+++ trunk/priv/host_tilegx_defs.c Wed Apr 15 02:15:31 2015
@@ -1348,11 +1348,10 @@
static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am )
{
- UInt rA; //, idx;
+ UInt rA;
vassert(am->tag == GXam_IR);
rA = iregNo(am->GXam.IR.base);
- //idx = am->GXam.IR.index;
if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 ||
opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) {
@@ -1381,19 +1380,29 @@
return p;
}
-/* Generate a machine-word sized load or store. Simplified version of
- the GXin_Load and GXin_Store cases below. */
+/* Generate a machine-word sized load or store using exact 2 bundles.
+ Simplified version of the GXin_Load and GXin_Store cases below. */
static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt reg,
TILEGXAMode* am )
{
+ UInt rA = iregNo(am->GXam.IR.base);
+
if (am->tag != GXam_IR)
vpanic(__func__);
- if (isLoad) /* load */
- p = doAMode_IR(p, TILEGX_OPC_LD, reg, am);
- else /* store */
- p = doAMode_IR(p, TILEGX_OPC_ST, reg, am);
-
+ if (isLoad) /* load */ {
+ /* r51 is reserved scratch registers. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+ 51, rA, am->GXam.IR.index));
+ /* load from address in r51 to rSD. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51));
+ } else /* store */ {
+ /* r51 is reserved scratch registers. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+ 51, rA, am->GXam.IR.index));
+ /* store rSD to address in r51 */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg));
+ }
return p;
}
|
|
From: <sv...@va...> - 2015-04-15 00:56:48
|
Author: zliu
Date: Wed Apr 15 01:56:40 2015
New Revision: 15093
Log:
Add 'allexec.c' in "none/tests/tilegx"
The symbolic link 'allexec.c' -> ../allecec.c
By: Zhi-Gang Liu
zh...@gm...
Added:
trunk/none/tests/tilegx/allexec.c (with props)
Added: trunk/none/tests/tilegx/allexec.c
==============================================================================
--- trunk/none/tests/tilegx/allexec.c (added)
+++ trunk/none/tests/tilegx/allexec.c Wed Apr 15 01:56:40 2015
@@ -0,0 +1 @@
+link ../allexec.c
\ No newline at end of file
|
|
From: <sv...@va...> - 2015-04-15 00:48:41
|
Author: zliu
Date: Wed Apr 15 01:48:34 2015
New Revision: 15092
Log:
Remove allecec.c from none/tests/tilegx
Will add a symbolic link for that file next.
Zhi-Gang Liu
Removed:
trunk/none/tests/tilegx/allexec.c
Removed: trunk/none/tests/tilegx/allexec.c
==============================================================================
--- trunk/none/tests/tilegx/allexec.c (original)
+++ trunk/none/tests/tilegx/allexec.c (removed)
@@ -1 +0,0 @@
-link ../allexec.c
\ No newline at end of file
|
|
From: Crestez D. L. <cdl...@gm...> - 2015-04-14 22:02:51
|
Hello, You seem to be building for mips32, this is wrong. Instead of _mips32_ those object files should all contain "_mips64n32_". You need to make sure your configure target is some form of mips64*, not mips32. What this patch does is add support for the N32 ABI as a secondary arch of mips64. What used to only build valgrind for mips64 will now build a second set of binaries for the N32 ABI. The main valgrind launcher will pick the correct mips64/mips64n32 version of the tool based on flags in the elf header. You also need to avoid including -mabi inside any explicit CFLAGS. Apparently gcc gets confused by multiple -mabi=* flags instead of just using the last option. Maybe you show how you are running the configure script? Also make sure you reran autogen.sh after patching and cleaned any stale binaries. I included the valgrind-developers list because this mail thread should be public in case anyone has similar issues. Regards, Leonard On Wed, Apr 15, 2015 at 12:31 AM, Zhu, Yanwen <Yan...@vi...> wrote: > Leonard, > > > > Thanks for your reply, I just fixed some errors during the patch. You’re > right, not too bad, just 3 files that I had to manually port the changes. > > > > I am building valgrind for MIPS64 with -mabi=n32 using the OCTEOM cross > compiler and I am seeing the following error in the linking phase: > > > > ../coregrind/link_tool_exe_linux 0x38000000 > /home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/ext/bin/mips64-octeon-linux-gnu-gcc > --sysroot=/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools > -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE > -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 > -march=octeon3 > -I/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/toolchain/linux/include > -Wno-long-long -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE > -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 > -march=octeon3 -fno-stack-protector -mabi=n32 -Wl,-melf32btsmipn32 > -march=octeon3 > -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/lib > -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/usr/lib > -o memcheck-mips32-linux -O2 -g -Wall -Wmissing-prototypes -Wshadow > -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations > -Wno-format-zero-length -fno-strict-aliasing -fno-builtin -O2 -static > -nodefaultlibs -nostartfiles -u __start > memcheck_mips32_linux-mc_leakcheck.o > memcheck_mips32_linux-mc_malloc_wrappers.o memcheck_mips32_linux-mc_main.o > memcheck_mips32_linux-mc_translate.o memcheck_mips32_linux-mc_machine.o > memcheck_mips32_linux-mc_errors.o ../coregrind/libcoregrind-mips32-linux.a > ../VEX/libvex-mips32-linux.a -lgcc > > ../coregrind/libcoregrind-mips32-linux.a(libcoregrind_mips32_linux_a-m_main.o): > In function `__start': > > m_main.c:(.text+0xc): undefined reference to `_gp_disp' > > m_main.c:(.text+0x10): undefined reference to `_gp_disp' > > collect2: error: ld returned 1 exit status > > make[4]: *** [memcheck-mips32-linux] Error 1 > > > > I don’t know what’s going on here, any suggestions? > > > > Thanks, > > Yanwen > > > > *From:* Crestez Dan Leonard [mailto:cdl...@gm...] > *Sent:* Tuesday, April 14, 2015 3:08 PM > *To:* Zhu, Yanwen > *Subject:* Re: Valgrind 13854: Cross compiling for Cavium MIPS64, N32 ABI > > > > Hello, > > > > The patches are against SVN trunk at around the time the patches were > posted (it differs between V1 and V2). Backporting them to 3.10.1 should > not be terribly difficult. They won't apply cleanly but I expect the issues > to be minor and easily solvable. Since the tilegx port was integrated a few > days ago I expect they won't apply cleanly on svn trunk either, at least > not until I rebase and post the next version. > > > > You can also try to compile directly from the git repos mentioned in the > tracker item. That should "just work". > > > > If you have problems compiling you should mention the actual build errors > as well as compiler/target details. Support for N32 should be generic but > I'm only actually targeting octeon chips using the cavium gcc-4.7 toolchain. > > > > Regards, > > Leonard > > > > On Tue, Apr 14, 2015 at 7:16 PM, <Yan...@vi...> wrote: > > Hi Leonard, > > I'm trying to apply your patches for mips64n32 on valgrind 3.10.1 and > there some some errors, I manually fixed the patching errors, however, I > have some problem compiling it. Looks to me that your patches were not > made based on 3.10.1. What version of valgrind were your patches made > from? Do you have patches for 3.10.1? > |
Author: florian
Date: Tue Apr 14 20:59:21 2015
New Revision: 15091
Log:
Followup to r14974. That revision oversimplified a condition, part
of which was presumed to be redundant but wasn't. This caused code
to hang due to an infinite signal-delivery loop. Observed and
tracked down by Austin English.
Added:
trunk/none/tests/x86-linux/hang.c
trunk/none/tests/x86-linux/hang.stderr.exp
trunk/none/tests/x86-linux/hang.vgtest
Modified:
trunk/coregrind/m_signals.c
trunk/none/tests/x86-linux/ (props changed)
trunk/none/tests/x86-linux/Makefile.am
Modified: trunk/coregrind/m_signals.c
==============================================================================
--- trunk/coregrind/m_signals.c (original)
+++ trunk/coregrind/m_signals.c Tue Apr 14 20:59:21 2015
@@ -2427,7 +2427,7 @@
{
Addr fault;
Addr esp;
- NSegment const* seg;
+ NSegment const *seg, *seg_next;
if (info->si_signo != VKI_SIGSEGV)
return False;
@@ -2435,6 +2435,8 @@
fault = (Addr)info->VKI_SIGINFO_si_addr;
esp = VG_(get_SP)(tid);
seg = VG_(am_find_nsegment)(fault);
+ seg_next = seg ? VG_(am_next_nsegment)( seg, True/*fwds*/ )
+ : NULL;
if (VG_(clo_trace_signals)) {
if (seg == NULL)
@@ -2449,6 +2451,10 @@
if (info->si_code == VKI_SEGV_MAPERR
&& seg
+ && seg->kind == SkResvn
+ && seg->smode == SmUpper
+ && seg_next
+ && seg_next->kind == SkAnonC
&& fault >= fault_mask(esp - VG_STACK_REDZONE_SZB)) {
/* If the fault address is above esp but below the current known
stack segment base, and it was a fault because there was
Modified: trunk/none/tests/x86-linux/Makefile.am
==============================================================================
--- trunk/none/tests/x86-linux/Makefile.am (original)
+++ trunk/none/tests/x86-linux/Makefile.am Tue Apr 14 20:59:21 2015
@@ -5,10 +5,12 @@
filter_stderr
EXTRA_DIST = \
+ hang.stderr.exp hang.vgtest \
seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest
check_PROGRAMS = \
+ hang \
seg_override \
sigcontext
Added: trunk/none/tests/x86-linux/hang.c
==============================================================================
--- trunk/none/tests/x86-linux/hang.c (added)
+++ trunk/none/tests/x86-linux/hang.c Tue Apr 14 20:59:21 2015
@@ -0,0 +1,5 @@
+int main ( void )
+{
+ *(volatile char *)0xDEADBEEF = 'x';
+ return 0;
+}
Added: trunk/none/tests/x86-linux/hang.stderr.exp
==============================================================================
--- trunk/none/tests/x86-linux/hang.stderr.exp (added)
+++ trunk/none/tests/x86-linux/hang.stderr.exp Tue Apr 14 20:59:21 2015
@@ -0,0 +1,9 @@
+
+Process terminating with default action of signal 11 (SIGSEGV)
+ Access not within mapped region at address 0x........
+ at 0x........: main (hang.c:3)
+ If you believe this happened as a result of a stack
+ overflow in your program's main thread (unlikely but
+ possible), you can try to increase the size of the
+ main thread stack using the --main-stacksize= flag.
+ The main thread stack size used in this run was ....
Added: trunk/none/tests/x86-linux/hang.vgtest
==============================================================================
--- trunk/none/tests/x86-linux/hang.vgtest (added)
+++ trunk/none/tests/x86-linux/hang.vgtest Tue Apr 14 20:59:21 2015
@@ -0,0 +1,5 @@
+# r14974 introduced a bug which cause code to hang due to
+# an infinite signal-delivery loop.
+# Can only be reproduced on an x86 box running a 32-bit kernel.
+prog: hang
+vgopts: -q
|
|
From: Philippe W. <phi...@sk...> - 2015-04-14 19:36:40
|
On Mon, 2015-04-13 at 18:39 -0400, Zhi-Gang Liu wrote: > Philippe > > Have you ever tried the patch I post in this mail chain for the TileGX > evCheck issue? > > If works for you I will commit it once I have SVN access. Sorry, I did not had the chance to look at it before. I just tried on an amd64 box. With the patch, the libvexmultiarch_test can properly use tilegx as a host. (of course, I could only test that, nothing of the tilegx behaviour itself). So, whenever you commit this patch, I will cleanup the libvex_test.c code that disables tilegx as host. Thanks Philippe |
|
From: <sv...@va...> - 2015-04-14 19:23:35
|
Author: sewardj
Date: Tue Apr 14 20:23:28 2015
New Revision: 15090
Log:
Add an NCode template for 32-bit loads on 32 bit targets.
Modified:
branches/NCODE/memcheck/mc_include.h
branches/NCODE/memcheck/mc_main.c
branches/NCODE/memcheck/mc_translate.c
Modified: branches/NCODE/memcheck/mc_include.h
==============================================================================
--- branches/NCODE/memcheck/mc_include.h (original)
+++ branches/NCODE/memcheck/mc_include.h Tue Apr 14 20:23:28 2015
@@ -605,6 +605,8 @@
extern NCodeTemplate* MC_(tmpl__LOADV16le_on_64);
extern NCodeTemplate* MC_(tmpl__LOADV8_on_64);
+extern NCodeTemplate* MC_(tmpl__LOADV32le_on_32);
+
/* Helper functions defined in mc_main.c */
Modified: branches/NCODE/memcheck/mc_main.c
==============================================================================
--- branches/NCODE/memcheck/mc_main.c (original)
+++ branches/NCODE/memcheck/mc_main.c Tue Apr 14 20:23:28 2015
@@ -4279,6 +4279,8 @@
VG_REGPARM(1) static ULong mc_LOADV16le_on_64_slow ( Addr a );
VG_REGPARM(1) static ULong mc_LOADV8_on_64_slow ( Addr a );
+VG_REGPARM(1) static UInt mc_LOADV32le_on_32_slow ( Addr a );
+
static void* ncode_alloc ( UInt n ) {
return VG_(malloc)("mc.ncode_alloc (NCode, permanent)", n);
}
@@ -4299,6 +4301,8 @@
NCodeTemplate* MC_(tmpl__LOADV16le_on_64) = NULL;
NCodeTemplate* MC_(tmpl__LOADV8_on_64) = NULL;
+NCodeTemplate* MC_(tmpl__LOADV32le_on_32) = NULL;
+
static NCodeTemplate* mk_tmpl__LOADV64le_on_64 ( NAlloc na )
{
NInstr** hot = na((11+1) * sizeof(NInstr*));
@@ -4609,6 +4613,68 @@
return tmpl;
}
+static NCodeTemplate* mk_tmpl__LOADV32le_on_32 ( NAlloc na )
+{
+ NInstr** hot = na((11+1) * sizeof(NInstr*));
+ NInstr** cold = na((6+1) * sizeof(NInstr*));
+
+ NReg rINVALID = mkNRegINVALID();
+
+ NReg r0 = mkNReg(Nrr_Result, 0);
+ NReg a0 = mkNReg(Nrr_Argument, 0);
+ NReg s0 = mkNReg(Nrr_Scratch, 0);
+
+ /* NCode [r0] = "LOADV32le_on_32" [a0] s0 {
+ hot:
+ 0 tst.w a0, #3 high?
+ 1 bnz cold.4 yes, goto slow path
+ 2 shr.w s0, a0, #16 s0 = pri-map-ix
+ 3 ld.32 s0, [&pri_map[0] + s0 << #2] s0 = sec-map
+ 4 and.w r0, a0, #0xFFFF r0 = sec-map-offB
+ 5 shr.w r0, r0, #2 r0 = sec-map-ix
+ 6 ld.8 r0, [s0 + r0] r0 = sec-map-VABITS8
+ 7 cmp.w r0, #0xAA r0 == VABITS8_DEFINED?
+ 8 bnz cold.0 no, goto cold.0
+ 9 imm.w r0, #0x0 VBITS32_DEFINED
+ 10 nop continue
+ cold:
+ 0 mov.w s0, r0 s0 = sec-map-VABITS8
+ 1 imm.w r0, #0xFFFFFFFF VBITS32_UNDEFINED
+ 2 cmp.w s0, #0x55 s0 == VABITS8_UNDEFINED?
+ 3 bz hot.10 yes, continue
+ 4 call r0 = mc_LOADV32le_on_32_slow[..](a0) call helper
+ 5 b hot.10 continue
+ }
+ */
+ hot[0] = NInstr_SetFlagsWri (na, Nsf_TEST, a0, MASK(4));
+ hot[1] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 4));
+ hot[2] = NInstr_ShiftWri (na, Nsh_SHR, s0, a0, 16);
+ hot[3] = NInstr_LoadU (na, 8, s0, NEA_IRS(na, (HWord)&primary_map[0],
+ s0, 2));
+ hot[4] = NInstr_AluWri (na, Nalu_AND, r0, a0, 0xFFFF);
+ hot[5] = NInstr_ShiftWri (na, Nsh_SHR, r0, r0, 2);
+ hot[6] = NInstr_LoadU (na, 1, r0, NEA_RRS(na, s0, r0, 0));
+ hot[7] = NInstr_SetFlagsWri (na, Nsf_CMP, r0, VA_BITS8_DEFINED);
+ hot[8] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 0));
+ hot[9] = NInstr_ImmW (na, r0, V_BITS32_DEFINED);
+ hot[10] = NInstr_Nop (na);
+
+ cold[0] = NInstr_MovW (na, s0, r0);
+ cold[1] = NInstr_ImmW (na, r0, V_BITS32_UNDEFINED);
+ cold[2] = NInstr_SetFlagsWri (na, Nsf_CMP, s0, VA_BITS8_UNDEFINED);
+ cold[3] = NInstr_Branch (na, Ncc_Z, mkNLabel(Nlz_Hot, 10));
+ cold[4] = NInstr_Call (na, rINVALID, r0, mkNRegVec1(na, a0),
+ (void*)& mc_LOADV32le_on_32_slow,
+ "mc_LOADV32le_on_32_slow");
+ cold[5] = NInstr_Branch (na, Ncc_ALWAYS, mkNLabel(Nlz_Hot, 10));
+
+ hot[11] = cold[6] = NULL;
+ NCodeTemplate* tmpl
+ = mkNCodeTemplate(na,"LOADV32le_on_32",
+ /*res, parms, scratch*/1, 1, 1, hot, cold);
+ return tmpl;
+}
+
void MC_(create_ncode_templates) ( void )
{
@@ -4620,6 +4686,9 @@
MC_(tmpl__LOADV32le_on_64) = mk_tmpl__LOADV32le_on_64(ncode_alloc);
MC_(tmpl__LOADV16le_on_64) = mk_tmpl__LOADV16le_on_64(ncode_alloc);
MC_(tmpl__LOADV8_on_64) = mk_tmpl__LOADV8_on_64(ncode_alloc);
+
+ tl_assert(MC_(tmpl__LOADV32le_on_32) == NULL);
+ MC_(tmpl__LOADV32le_on_32) = mk_tmpl__LOADV32le_on_32(ncode_alloc);
}
@@ -4879,6 +4948,10 @@
{
return mc_LOADVn_slow( a, 32, False/*!isBigEndian*/ );
}
+VG_REGPARM(1) static UInt mc_LOADV32le_on_32_slow ( Addr a )
+{
+ return mc_LOADVn_slow( a, 32, False/*!isBigEndian*/ );
+}
static INLINE
Modified: branches/NCODE/memcheck/mc_translate.c
==============================================================================
--- branches/NCODE/memcheck/mc_translate.c (original)
+++ branches/NCODE/memcheck/mc_translate.c Tue Apr 14 20:23:28 2015
@@ -4625,6 +4625,7 @@
/* ty is now the shadow type for the load. */
/* ------ BEGIN inline NCode ? ------ */
+ /* NCode load cases for 64 bit hosts */
if (guardIsAlwaysTrue(guard) && mce->hWordTy == Ity_I64 && end == Iend_LE) {
switch (ty) {
case Ity_I64: {
@@ -4683,6 +4684,25 @@
break;
}
}
+ else
+ /* NCode load cases for 32 bit hosts */
+ if (guardIsAlwaysTrue(guard) && mce->hWordTy == Ity_I32 && end == Iend_LE) {
+ switch (ty) {
+ case Ity_I32: {
+ /* Unconditional LOAD32le on 32 bit host. Generate inline code. */
+ IRTemp datavbits32 = newTemp(mce, Ity_I32, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV32le_on_32);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_1( datavbits32 );
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ return mkexpr(datavbits32);
+ }
+ default:
+ /* else fall through */
+ break;
+ }
+ }
+
/* ------ END inline NCode ? ------ */
/* Now cook up a call to the relevant helper function, to read the
|
Author: sewardj
Date: Tue Apr 14 20:22:04 2015
New Revision: 3129
Log:
Initial arm32-specific infrastructure changes for doing NCode generation.
Most of this is changes to the arm32 assembler (emit_ARMInstr) to use
AssemblerBuffers. No actual NInstr handling yet.
Modified:
branches/NCODE/priv/host_amd64_defs.c
branches/NCODE/priv/host_amd64_defs.h
branches/NCODE/priv/host_arm_defs.c
branches/NCODE/priv/host_arm_defs.h
branches/NCODE/priv/host_generic_reg_alloc2.c
branches/NCODE/priv/host_generic_regs.h
branches/NCODE/priv/main_main.c
branches/NCODE/priv/main_util.h
Modified: branches/NCODE/priv/host_amd64_defs.c
==============================================================================
--- branches/NCODE/priv/host_amd64_defs.c (original)
+++ branches/NCODE/priv/host_amd64_defs.c Tue Apr 14 20:22:04 2015
@@ -2158,7 +2158,7 @@
/* --------- The amd64 assembler (bleh.) --------- */
-#define PUT(_ab, _byte) \
+#define PUT(_ab, _byte) \
do { UInt _off = (_ab)->bufUsed; \
(_ab)->buf[_off] = (_byte); \
(_ab)->bufUsed = _off + 1; \
Modified: branches/NCODE/priv/host_amd64_defs.h
==============================================================================
--- branches/NCODE/priv/host_amd64_defs.h (original)
+++ branches/NCODE/priv/host_amd64_defs.h Tue Apr 14 20:22:04 2015
@@ -838,9 +838,10 @@
extern void getRegUsage_AMD64Instr ( HRegUsage*, const AMD64Instr*, Bool );
extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool );
extern Bool isMove_AMD64Instr ( const AMD64Instr*, HReg*, HReg* );
-extern Bool emit_AMD64Instr ( /*MOD*/AssemblyBuffer*,
- const AMD64Instr*, Bool, VexEndness,
- const VexDispatcherAddresses* );
+
+extern Bool emit_AMD64Instr ( /*MOD*/AssemblyBuffer*,
+ const AMD64Instr*, Bool mode64, VexEndness,
+ const VexDispatcherAddresses* );
extern Bool emit_AMD64NCodeBlock ( /*MOD*/AssemblyBuffer* ab_hot,
/*MOD*/AssemblyBuffer* ab_cold,
@@ -856,15 +857,15 @@
extern const RRegUniverse* getRRegUniverse_AMD64 ( void );
-extern HInstrArray* iselSB_AMD64 ( const IRSB*,
- VexArch,
- const VexArchInfo*,
- const VexAbiInfo*,
- Int offs_Host_EvC_Counter,
- Int offs_Host_EvC_FailAddr,
- Bool chainingAllowed,
- Bool addProfInc,
- Addr max_ga );
+extern HInstrArray* iselSB_AMD64 ( const IRSB*,
+ VexArch,
+ const VexArchInfo*,
+ const VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr max_ga );
/* How big is an event check? This is kind of a kludge because it
depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
Modified: branches/NCODE/priv/host_arm_defs.c
==============================================================================
--- branches/NCODE/priv/host_arm_defs.c (original)
+++ branches/NCODE/priv/host_arm_defs.c Tue Apr 14 20:22:04 2015
@@ -2554,12 +2554,13 @@
condition codes. */
void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
- HReg rreg, Int offsetB, Bool mode64 )
+ HReg rreg, Bool spRel, Int offsetB, Bool mode64 )
{
HRegClass rclass;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == False);
+ vassert(!spRel);
*i1 = *i2 = NULL;
rclass = hregClass(rreg);
switch (rclass) {
@@ -2609,12 +2610,13 @@
}
void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
- HReg rreg, Int offsetB, Bool mode64 )
+ HReg rreg, Bool spRel, Int offsetB, Bool mode64 )
{
HRegClass rclass;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == False);
+ vassert(!spRel);
*i1 = *i2 = NULL;
rclass = hregClass(rreg);
switch (rclass) {
@@ -2664,6 +2666,17 @@
}
+/* --------- The arm32 assembler (bleh.) --------- */
+
+#define PUT(_ab, _word32) \
+ do { const UInt _off = (_ab)->bufUsed; \
+ (_ab)->buf[_off + 0] = ((_word32) >> 0) & 0xFF; \
+ (_ab)->buf[_off + 1] = ((_word32) >> 8) & 0xFF; \
+ (_ab)->buf[_off + 2] = ((_word32) >> 16) & 0xFF; \
+ (_ab)->buf[_off + 3] = ((_word32) >> 24) & 0xFF; \
+ (_ab)->bufUsed = _off + 4; \
+ } while (0)
+
/* Emit an instruction into buf and return the number of bytes used.
Note that buf is not the insn's final place, and therefore it is
imperative to emit position-independent code. */
@@ -2796,7 +2809,7 @@
/* Get an immediate into a register, using only that
register. (very lame..) */
-static UInt* imm32_to_ireg ( UInt* p, Int rD, UInt imm32 )
+static void imm32_to_ireg ( /*MOD*/AssemblyBuffer* ab, Int rD, UInt imm32 )
{
UInt instr;
vassert(rD >= 0 && rD <= 14); // r15 not good to mess with!
@@ -2805,15 +2818,15 @@
/* mov with a immediate shifter operand of (0, imm32) (??) */
instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000);
instr |= imm32;
- *p++ = instr;
+ PUT(ab, instr);
} else {
// this is very bad; causes Dcache pollution
// ldr rD, [pc]
instr = XXXXX___(X1110,X0101,X1001,X1111,rD);
- *p++ = instr;
+ PUT(ab, instr);
// b .+8
instr = 0xEA000000;
- *p++ = instr;
+ PUT(ab, instr);
// .word imm32
*p++ = imm32;
}
@@ -2826,12 +2839,12 @@
instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
(lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
lo16 & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
if (hi16 != 0) {
instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
(hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
hi16 & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
}
} else {
UInt imm, rot;
@@ -2841,7 +2854,7 @@
imm = imm32 & 0xFF;
rot = 0;
instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
op = X1000;
rN = rD;
}
@@ -2849,7 +2862,7 @@
imm = (imm32 >> 24) & 0xFF;
rot = 4;
instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
op = X1000;
rN = rD;
}
@@ -2857,7 +2870,7 @@
imm = (imm32 >> 16) & 0xFF;
rot = 8;
instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
op = X1000;
rN = rD;
}
@@ -2865,20 +2878,20 @@
imm = (imm32 >> 8) & 0xFF;
rot = 12;
instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
op = X1000;
rN = rD;
}
}
#endif
- return p;
}
/* Get an immediate into a register, using only that register, and
generating exactly 2 instructions, regardless of the value of the
immediate. This is used when generating sections of code that need
to be patched later, so as to guarantee a specific size. */
-static UInt* imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
+static void imm32_to_ireg_EXACTLY2 ( /*MOD*/AssemblyBuffer* ab,
+ Int rD, UInt imm32 )
{
if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
/* Generate movw rD, #low16 ; movt rD, #high16. */
@@ -2888,15 +2901,14 @@
instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
(lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
lo16 & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
(hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
hi16 & 0xF);
- *p++ = instr;
+ PUT(ab, instr);
} else {
vassert(0); /* lose */
}
- return p;
}
/* Check whether p points at a 2-insn sequence cooked up by
@@ -2921,8 +2933,8 @@
}
-static UInt* do_load_or_store32 ( UInt* p,
- Bool isLoad, UInt rD, ARMAMode1* am )
+static void do_load_or_store32 ( /*MOD*/AssemblyBuffer* ab,
+ Bool isLoad, UInt rD, ARMAMode1* am )
{
vassert(rD <= 12);
vassert(am->tag == ARMam1_RI); // RR case is not handled
@@ -2942,29 +2954,26 @@
iregEnc(am->ARMam1.RI.reg),
rD);
instr |= simm12;
- *p++ = instr;
- return p;
+ PUT(ab, instr);
}
-/* Emit an instruction into buf and return the number of bytes used.
- Note that buf is not the insn's final place, and therefore it is
- imperative to emit position-independent code. If the emitted
- instruction was a profiler inc, set *is_profInc to True, else
- leave it unchanged. */
-
-Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
- UChar* buf, Int nbuf, const ARMInstr* i,
- Bool mode64, VexEndness endness_host,
- const void* disp_cp_chain_me_to_slowEP,
- const void* disp_cp_chain_me_to_fastEP,
- const void* disp_cp_xindir,
- const void* disp_cp_xassisted )
+/* Emit an instruction into |ab|. Note that |ab->buf| is not the
+ insn's final place, and therefore it is imperative to emit
+ position-independent code. If the emitted instruction was a
+ profiler inc, return True, else return False. This function must
+ also guarantee to generate 256 or fewer bytes for each instr, so
+ as to facilitate range checking in the caller. */
+
+Bool emit_ARMInstr ( /*MOD*/AssemblyBuffer* ab,
+ const ARMInstr* i,
+ Bool mode64, VexEndness endness_host,
+ const VexDispatcherAddresses* vda )
{
- UInt* p = (UInt*)buf;
- vassert(nbuf >= 32);
+ Bool is_profInc = False;
+ UChar* initialCursor = AssemblyBuffer__getCursor(ab);
vassert(mode64 == False);
- vassert(0 == (((HWord)buf) & 3));
+ vassert(IS_4_ALIGNED(initialCursor));
switch (i->tag) {
case ARMin_Alu: {
@@ -2992,7 +3001,7 @@
|| i->ARMin.Alu.op == ARMalu_SUBS) {
instr |= 1<<20; /* set the S bit */
}
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
case ARMin_Shift: {
@@ -3009,7 +3018,7 @@
instr = skeletal_RI5(argR);
instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM);
instr |= (subopc & 3) << 5;
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
case ARMin_Unary: {
@@ -3020,18 +3029,18 @@
case ARMun_CLZ:
instr = XXXXXXXX(X1110,X0001,X0110,X1111,
rDst,X1111,X0001,rSrc);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
case ARMun_NEG: /* RSB rD,rS,#0 */
instr = XXXXX___(X1110,0x2,0x6,rSrc,rDst);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
case ARMun_NOT: {
UInt subopc = X1111; /* MVN */
instr = rSrc;
instr |= XXXXX___(X1110, (1 & (subopc >> 3)),
(subopc << 1) & 0xF, 0, rDst);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
default:
@@ -3046,7 +3055,7 @@
instr |= XXXXX___(X1110, (1 & (subopc >> 3)),
((subopc << 1) & 0xF) | 1,
iregEnc(i->ARMin.CmpOrTst.argL), SBZ );
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
case ARMin_Mov: {
@@ -3056,12 +3065,12 @@
instr |= XXXXX___(X1110, (1 & (subopc >> 3)),
(subopc << 1) & 0xF, SBZ,
iregEnc(i->ARMin.Mov.dst));
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
case ARMin_Imm32: {
- p = imm32_to_ireg( (UInt*)p, iregEnc(i->ARMin.Imm32.dst),
- i->ARMin.Imm32.imm32 );
+ imm32_to_ireg( ab, iregEnc(i->ARMin.Imm32.dst),
+ i->ARMin.Imm32.imm32 );
goto done;
}
case ARMin_LdSt32:
@@ -3099,7 +3108,7 @@
iregEnc(am->ARMam1.RI.reg),
iregEnc(rD));
instr |= simm12;
- *p++ = instr;
+ PUT(ab, instr);
goto done;
} else {
// RR case
@@ -3132,21 +3141,21 @@
// strh
instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,0), iregEnc(rN),
iregEnc(rD), imm8hi, X1011, imm8lo);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
else if (bL == 1 && bS == 0) {
// ldrh
instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregEnc(rN),
iregEnc(rD), imm8hi, X1011, imm8lo);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
else if (bL == 1 && bS == 1) {
// ldrsh
instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregEnc(rN),
iregEnc(rD), imm8hi, X1111, imm8lo);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
else vassert(0); // ill-constructed insn
@@ -3177,7 +3186,7 @@
// ldrsb
instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregEnc(rN),
iregEnc(rD), imm8hi, X1101, imm8lo);
- *p++ = instr;
+ PUT(ab, instr);
goto done;
} else {
// RR case
@@ -3191,8 +3200,8 @@
/* We're generating chain-me requests here, so we need to be
sure this is actually allowed -- no-redir translations
can't use chain-me's. Hence: */
- vassert(disp_cp_chain_me_to_slowEP != NULL);
- vassert(disp_cp_chain_me_to_fastEP != NULL);
+ vassert(vda->disp_cp_chain_me_to_slowEP != NULL);
+ vassert(vda->disp_cp_chain_me_to_fastEP != NULL);
/* Use ptmp for backpatching conditional jumps. */
UInt* ptmp = NULL;
@@ -3202,37 +3211,37 @@
it that we will shortly fill in. */
if (i->ARMin.XDirect.cond != ARMcc_AL) {
vassert(i->ARMin.XDirect.cond != ARMcc_NV);
- ptmp = p;
- *p++ = 0;
+ ptmp = AssemblyBuffer__getCursor_4aligned(ab);
+ PUT(ab, 0);
}
/* Update the guest R15T. */
/* movw r12, lo16(dstGA) */
/* movt r12, hi16(dstGA) */
/* str r12, amR15T */
- p = imm32_to_ireg(p, /*r*/12, i->ARMin.XDirect.dstGA);
- p = do_load_or_store32(p, False/*!isLoad*/,
- /*r*/12, i->ARMin.XDirect.amR15T);
+ imm32_to_ireg(ab, /*r*/12, i->ARMin.XDirect.dstGA);
+ do_load_or_store32(ab, False/*!isLoad*/,
+ /*r*/12, i->ARMin.XDirect.amR15T);
/* --- FIRST PATCHABLE BYTE follows --- */
- /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
+ /* VG_(vda->disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
calling to) backs up the return address, so as to find the
address of the first patchable byte. So: don't change the
number of instructions (3) below. */
- /* movw r12, lo16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
- /* movt r12, hi16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
+ /* movw r12, lo16(vda->disp_cp_chain_me_to_{slowEP,fastEP}) */
+ /* movt r12, hi16(vda->disp_cp_chain_me_to_{slowEP,fastEP}) */
/* blx r12 (A1) */
const void* disp_cp_chain_me
- = i->ARMin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
- : disp_cp_chain_me_to_slowEP;
- p = imm32_to_ireg_EXACTLY2(p, /*r*/12,
- (UInt)(Addr)disp_cp_chain_me);
- *p++ = 0xE12FFF3C;
+ = i->ARMin.XDirect.toFastEP ? vda->disp_cp_chain_me_to_fastEP
+ : vda->disp_cp_chain_me_to_slowEP;
+ imm32_to_ireg_EXACTLY2(ab, /*r*/12, (UInt)(Addr)disp_cp_chain_me);
+ PUT(ab, 0xE12FFF3C);
/* --- END of PATCHABLE BYTES --- */
/* Fix up the conditional jump, if there was one. */
if (i->ARMin.XDirect.cond != ARMcc_AL) {
- Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ /* |delta| must be signed */
+ Int delta = AssemblyBuffer__getCursor(ab) - (UChar*)ptmp;
vassert(delta > 0 && delta < 40);
vassert((delta & 3) == 0);
UInt notCond = 1 ^ (UInt)i->ARMin.XDirect.cond;
@@ -3250,7 +3259,7 @@
translations without going through the scheduler. That
means no XDirects or XIndirs out from no-redir
translations. Hence: */
- vassert(disp_cp_xindir != NULL);
+ vassert(vda->disp_cp_xindir != NULL);
/* Use ptmp for backpatching conditional jumps. */
UInt* ptmp = NULL;
@@ -3260,25 +3269,26 @@
it that we will shortly fill in. */
if (i->ARMin.XIndir.cond != ARMcc_AL) {
vassert(i->ARMin.XIndir.cond != ARMcc_NV);
- ptmp = p;
- *p++ = 0;
+ ptmp = AssemblyBuffer__getCursor_4aligned(ab);
+ PUT(ab, 0);
}
/* Update the guest R15T. */
/* str r-dstGA, amR15T */
- p = do_load_or_store32(p, False/*!isLoad*/,
- iregEnc(i->ARMin.XIndir.dstGA),
- i->ARMin.XIndir.amR15T);
+ do_load_or_store32(ab, False/*!isLoad*/,
+ iregEnc(i->ARMin.XIndir.dstGA),
+ i->ARMin.XIndir.amR15T);
- /* movw r12, lo16(VG_(disp_cp_xindir)) */
- /* movt r12, hi16(VG_(disp_cp_xindir)) */
+ /* movw r12, lo16(vda->disp_cp_xindir) */
+ /* movt r12, hi16(vda->disp_cp_xindir) */
/* bx r12 (A1) */
- p = imm32_to_ireg(p, /*r*/12, (UInt)(Addr)disp_cp_xindir);
- *p++ = 0xE12FFF1C;
+ imm32_to_ireg(ab, /*r*/12, (UInt)(Addr)vda->disp_cp_xindir);
+ PUT(ab, 0xE12FFF1C);
/* Fix up the conditional jump, if there was one. */
if (i->ARMin.XIndir.cond != ARMcc_AL) {
- Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ /* |delta| must be signed */
+ Int delta = AssemblyBuffer__getCursor(ab) - (UChar*)ptmp;
vassert(delta > 0 && delta < 40);
vassert((delta & 3) == 0);
UInt notCond = 1 ^ (UInt)i->ARMin.XIndir.cond;
@@ -3298,15 +3308,15 @@
it that we will shortly fill in. */
if (i->ARMin.XAssisted.cond != ARMcc_AL) {
vassert(i->ARMin.XAssisted.cond != ARMcc_NV);
- ptmp = p;
- *p++ = 0;
+ ptmp = AssemblyBuffer__getCursor_4aligned(ab);
+ PUT(ab, 0);
}
/* Update the guest R15T. */
/* str r-dstGA, amR15T */
- p = do_load_or_store32(p, False/*!isLoad*/,
- iregEnc(i->ARMin.XAssisted.dstGA),
- i->ARMin.XAssisted.amR15T);
+ do_load_or_store32(ab, False/*!isLoad*/,
+ iregEnc(i->ARMin.XAssisted.dstGA),
+ i->ARMin.XAssisted.amR15T);
/* movw r8, $magic_number */
UInt trcval = 0;
@@ -3332,17 +3342,18 @@
vpanic("emit_ARMInstr.ARMin_XAssisted: unexpected jump kind");
}
vassert(trcval != 0);
- p = imm32_to_ireg(p, /*r*/8, trcval);
+ imm32_to_ireg(ab, /*r*/8, trcval);
- /* movw r12, lo16(VG_(disp_cp_xassisted)) */
- /* movt r12, hi16(VG_(disp_cp_xassisted)) */
+ /* movw r12, lo16(vda->disp_cp_xassisted) */
+ /* movt r12, hi16(vda->disp_cp_xassisted) */
/* bx r12 (A1) */
- p = imm32_to_ireg(p, /*r*/12, (UInt)(Addr)disp_cp_xassisted);
- *p++ = 0xE12FFF1C;
+ imm32_to_ireg(ab, /*r*/12, (UInt)(Addr)vda->disp_cp_xassisted);
+ PUT(ab, 0xE12FFF1C);
/* Fix up the conditional jump, if there was one. */
if (i->ARMin.XAssisted.cond != ARMcc_AL) {
- Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ /* |delta| must be signed */
+ Int delta = AssemblyBuffer__getCursor(ab) - (UChar*)ptmp;
vassert(delta > 0 && delta < 40);
vassert((delta & 3) == 0);
UInt notCond = 1 ^ (UInt)i->ARMin.XAssisted.cond;
@@ -3360,7 +3371,7 @@
instr |= XXXXX___(i->ARMin.CMov.cond, (1 & (subopc >> 3)),
(subopc << 1) & 0xF, SBZ,
iregEnc(i->ARMin.CMov.dst));
- *p++ = instr;
+ PUT(ab, instr);
goto done;
}
@@ -3383,13 +3394,12 @@
if (i->ARMin.Call.cond == ARMcc_AL/*call always happens*/
|| i->ARMin.Call.rloc.pri == RLPri_None/*no fixup action*/) {
// r"scratchNo" = &target
- p = imm32_to_ireg( (UInt*)p,
- scratchNo, (UInt)i->ARMin.Call.target );
+ imm32_to_ireg( ab, scratchNo, (UInt)i->ARMin.Call.target );
// blx{cond} r"scratchNo"
instr = XXX___XX(i->ARMin.Call.cond, X0001, X0010, /*___*/
X0011, scratchNo);
instr |= 0xFFF << 8; // stick in the SBOnes
- *p++ = instr;
+ PUT(ab, instr);
} else {
Int delta;
/* Complex case. We have to generate an if-then-else
@@ -3406,29 +3416,29 @@
// after:
// before:
- UInt* pBefore = p;
+ UInt* pBefore = AssemblyBuffer__getCursor_4aligned(ab);
// b{!cond} else: // ptmp1 points here
- *p++ = 0; // filled in later
+ PUT(ab, 0); // filled in later
// r"scratchNo" = &target
- p = imm32_to_ireg( (UInt*)p,
- scratchNo, (UInt)i->ARMin.Call.target );
+ imm32_to_ireg( ab, scratchNo, (UInt)i->ARMin.Call.target );
// blx{AL} r"scratchNo"
instr = XXX___XX(ARMcc_AL, X0001, X0010, /*___*/
X0011, scratchNo);
instr |= 0xFFF << 8; // stick in the SBOnes
- *p++ = instr;
+ PUT(ab, instr);
// preElse:
- UInt* pPreElse = p;
+ UInt* pPreElse = AssemblyBuffer__getCursor_4aligned(ab);
// b after:
- *p++ = 0; // filled in later
+ PUT(ab, 0); // filled in later
// else:
- delta = (UChar*)p - (UChar*)pBefore;
+ delta = AssemblyBuffer__getCursor(ab) - (UChar*)pBefore;
+ vassert(IS_4_ALIGNED(delta));
delta = (delta >> 2) - 2;
*pBefore
= XX______(1 ^ i->ARMin.Call.cond, X1010) | (delta & 0xFFFFFF);
@@ -3436,20 +3446,21 @@
/* Do the 'else' actions */
switch (i->ARMin.Call.rloc.pri) {
case RLPri_Int:
- p = imm32_to_ireg_EXACTLY2(p, /*r*/0, 0x55555555);
+ imm32_to_ireg_EXACTLY2(ab, /*r*/0, 0x55555555);
break;
case RLPri_2Int:
vassert(0); //ATC
- p = imm32_to_ireg_EXACTLY2(p, /*r*/0, 0x55555555);
+ imm32_to_ireg_EXACTLY2(ab, /*r*/0, 0x55555555);
/* mov r1, r0 */
- *p++ = 0xE1A01000;
+ PUT(ab, 0xE1A01000);
break;
case RLPri_None: case RLPri_INVALID: default:
vassert(0);
}
// after:
- delta = (UChar*)p - (UChar*)pPreElse;
+ delta = AssemblyBuffer__getCursor(ab) - (UChar*)pPreElse;
+ vassert(IS_4_ALIGNED(delta));
delta = (delta >> 2) - 2;
*pPreElse = XX______(ARMcc_AL, X1010) | (delta & 0xFFFFFF);
}
@@ -3463,9 +3474,9 @@
E0C10392 smull r0(LO), r1(HI), r2, r3
*/
switch (i->ARMin.Mul.op) {
- case ARMmul_PLAIN: *p++ = 0xE0000392; goto done;
- case ARMmul_ZX: *p++ = 0xE0810392; goto done;
- case ARMmul_SX: *p++ = 0xE0C10392; goto done;
+ case ARMmul_PLAIN: PUT(ab, 0xE0000392); goto done;
+ case ARMmul_ZX: PUT(ab, 0xE0810392); goto done;
+ case ARMmul_SX: PUT(ab, 0xE0C10392); goto done;
default: vassert(0);
}
goto bad;
@@ -3477,10 +3488,10 @@
E1B42F9F ldrexd r2, r3, [r4]
*/
switch (i->ARMin.LdrEX.szB) {
- case 1: *p++ = 0xE1D42F9F; goto done;
- case 2: *p++ = 0xE1F42F9F; goto done;
- case 4: *p++ = 0xE1942F9F; goto done;
- case 8: *p++ = 0xE1B42F9F; goto done;
+ case 1: PUT(ab, 0xE1D42F9F); goto done;
+ case 2: PUT(ab, 0xE1F42F9F); goto done;
+ case 4: PUT(ab, 0xE1942F9F); goto done;
+ case 8: PUT(ab, 0xE1B42F9F); goto done;
default: break;
}
goto bad;
@@ -3492,10 +3503,10 @@
E1A40F92 strexd r0, r2, r3, [r4]
*/
switch (i->ARMin.StrEX.szB) {
- case 1: *p++ = 0xE1C40F92; goto done;
- case 2: *p++ = 0xE1E40F92; goto done;
- case 4: *p++ = 0xE1840F92; goto done;
- case 8: *p++ = 0xE1A40F92; goto done;
+ case 1: PUT(ab, 0xE1C40F92); goto done;
+ case 2: PUT(ab, 0xE1E40F92); goto done;
+ case 4: PUT(ab, 0xE1840F92); goto done;
+ case 8: PUT(ab, 0xE1A40F92); goto done;
default: break;
}
goto bad;
@@ -3513,7 +3524,7 @@
vassert(0 == (off8 & 0xFFFFFF00));
insn = XXXXXX__(0xE,X1101,BITS4(bU,0,0,bL),rN,dD,X1011);
insn |= off8;
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VLdStS: {
@@ -3530,7 +3541,7 @@
vassert(0 == (off8 & 0xFFFFFF00));
insn = XXXXXX__(0xE,X1101,BITS4(bU,bD,0,bL),rN, (fD >> 1), X1010);
insn |= off8;
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VAluD: {
@@ -3552,7 +3563,7 @@
UInt bS = (pqrs >> 0) & 1;
UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,0,bQ,bR), dN, dD,
X1011, BITS4(0,bS,0,0), dM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VAluS: {
@@ -3578,7 +3589,7 @@
UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR),
(dN >> 1), (dD >> 1),
X1010, BITS4(bN,bS,bM,0), (dM >> 1));
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VUnaryD: {
@@ -3601,7 +3612,7 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VUnaryS: {
@@ -3632,15 +3643,15 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VCmpD: {
UInt dD = dregEnc(i->ARMin.VCmpD.argL);
UInt dM = dregEnc(i->ARMin.VCmpD.argR);
UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM);
- *p++ = insn; /* FCMPD dD, dM */
- *p++ = 0xEEF1FA10; /* FMSTAT */
+ PUT(ab, insn); /* FCMPD dD, dM */
+ PUT(ab, 0xEEF1FA10); /* FMSTAT */
goto done;
}
case ARMin_VCMovD: {
@@ -3649,7 +3660,7 @@
UInt dM = dregEnc(i->ARMin.VCMovD.src);
vassert(cc < 16 && cc != ARMcc_AL);
UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VCMovS: {
@@ -3660,7 +3671,7 @@
UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1),
X0000,(fD >> 1),X1010,
BITS4(0,1,(fM & 1),0), (fM >> 1));
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VCvtSD: {
@@ -3670,7 +3681,7 @@
UInt insn = XXXXXXXX(0xE, X1110, X1011, X0111, dD, X1010,
BITS4(1,1, (fM & 1), 0),
(fM >> 1));
- *p++ = insn;
+ PUT(ab, insn);
goto done;
} else {
UInt fD = fregEnc(i->ARMin.VCvtSD.dst);
@@ -3678,7 +3689,7 @@
UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1),
X0111, (fD >> 1),
X1011, X1100, dM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
}
@@ -3695,7 +3706,7 @@
= XXXXXXXX(0xE, 0xC, i->ARMin.VXferD.toD ? 4 : 5,
rHi, rLo, 0xB,
BITS4(0,0, ((dD >> 4) & 1), 1), (dD & 0xF));
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VXferS: {
@@ -3710,7 +3721,7 @@
= XXXXXXXX(0xE, 0xE, i->ARMin.VXferS.toS ? 0 : 1,
(fD >> 1) & 0xF, rLo, 0xA,
BITS4((fD & 1),0,0,1), 0);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_VCvtID: {
@@ -3723,7 +3734,7 @@
UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
X1011, BITS4(1,1,(regF & 1),0),
(regF >> 1) & 0xF);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
if (iToD && (!syned)) {
@@ -3733,7 +3744,7 @@
UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
X1011, BITS4(0,1,(regF & 1),0),
(regF >> 1) & 0xF);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
if ((!iToD) && syned) {
@@ -3743,7 +3754,7 @@
UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
X1101, (regF >> 1) & 0xF,
X1011, X0100, regD);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
if ((!iToD) && (!syned)) {
@@ -3753,7 +3764,7 @@
UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
X1100, (regF >> 1) & 0xF,
X1011, X0100, regD);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
/*UNREACHED*/
@@ -3764,7 +3775,7 @@
UInt iReg = iregEnc(i->ARMin.FPSCR.iReg);
if (toFPSCR) {
/* fmxr fpscr, iReg is EEE1 iReg A10 */
- *p++ = 0xEEE10A10 | ((iReg & 0xF) << 12);
+ PUT(ab, 0xEEE10A10 | ((iReg & 0xF) << 12));
goto done;
}
goto bad; // FPSCR -> iReg case currently ATC
@@ -3773,16 +3784,16 @@
// It's not clear (to me) how these relate to the ARMv7
// versions, so let's just use the v7 versions as they
// are at least well documented.
- //*p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */
- //*p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */
- //*p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */
- *p++ = 0xF57FF04F; /* DSB sy */
- *p++ = 0xF57FF05F; /* DMB sy */
- *p++ = 0xF57FF06F; /* ISB */
+ //PUT(ab, 0xEE070F9A); /* mcr 15,0,r0,c7,c10,4 (DSB) */
+ //PUT(ab, 0xEE070FBA); /* mcr 15,0,r0,c7,c10,5 (DMB) */
+ //PUT(ab, 0xEE070F95); /* mcr 15,0,r0,c7,c5,4 (ISB) */
+ PUT(ab, 0xF57FF04F); /* DSB sy */
+ PUT(ab, 0xF57FF05F); /* DMB sy */
+ PUT(ab, 0xF57FF06F); /* ISB */
goto done;
}
case ARMin_CLREX: {
- *p++ = 0xF57FF01F; /* clrex */
+ PUT(ab, 0xF57FF01F); /* clrex */
goto done;
}
@@ -3803,7 +3814,7 @@
}
insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
regN, regD, X1010, X1000, regM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NLdStD: {
@@ -3823,7 +3834,7 @@
}
insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
regN, regD, X0111, X1000, regM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NUnaryS: {
@@ -3854,7 +3865,7 @@
insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1),
(i->ARMin.NUnaryS.size & 0xf), regD,
X1100, BITS4(0,Q,M,0), regM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
case ARMneon_SETELEM:
regD = Q ? (qregEnc(i->ARMin.NUnaryS.dst->reg) << 1) :
@@ -3890,7 +3901,7 @@
insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0),
regD, regM, X1011,
BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
case ARMneon_GETELEMU:
regM = Q ? (qregEnc(i->ARMin.NUnaryS.src->reg) << 1) :
@@ -3931,7 +3942,7 @@
insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1),
regM, regD, X1011,
BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
case ARMneon_GETELEMS:
regM = Q ? (qregEnc(i->ARMin.NUnaryS.src->reg) << 1) :
@@ -3979,7 +3990,7 @@
insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1),
regM, regD, X1011,
BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
default:
goto bad;
@@ -4198,7 +4209,7 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NDual: {
@@ -4232,7 +4243,7 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NBinary: {
@@ -4458,7 +4469,7 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NShift: {
@@ -4501,7 +4512,7 @@
default:
goto bad;
}
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NShl64: {
@@ -4521,7 +4532,7 @@
UInt Vm = regM & 0xF;
UInt insn = XXXXXXXX(X1111,X0010, BITS4(1,D,(amt>>5)&1,(amt>>4)&1),
amt & 0xF, Vd, X0101, BITS4(L,Q,M,1), Vm);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NeonImm: {
@@ -4569,7 +4580,7 @@
}
insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD,
cmode, BITS4(0,Q,op,1), imm4);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_NCMovQ: {
@@ -4583,11 +4594,11 @@
vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV);
/* b!cc here+8: !cc A00 0000 */
UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0);
- *p++ = insn;
+ PUT(ab, insn);
/* vmov qD, qM */
insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0),
vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
case ARMin_Add32: {
@@ -4596,10 +4607,10 @@
UInt imm32 = i->ARMin.Add32.imm32;
vassert(regD != regN);
/* MOV regD, imm32 */
- p = imm32_to_ireg((UInt *)p, regD, imm32);
+ imm32_to_ireg(ab, regD, imm32);
/* ADD regD, regN, regD */
UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD);
- *p++ = insn;
+ PUT(ab, insn);
goto done;
}
@@ -4613,20 +4624,21 @@
bx r12
nofail:
*/
- UInt* p0 = p;
- p = do_load_or_store32(p, True/*isLoad*/, /*r*/12,
- i->ARMin.EvCheck.amCounter);
- *p++ = 0xE25CC001; /* subs r12, r12, #1 */
- p = do_load_or_store32(p, False/*!isLoad*/, /*r*/12,
- i->ARMin.EvCheck.amCounter);
- *p++ = 0x5A000001; /* bpl nofail */
- p = do_load_or_store32(p, True/*isLoad*/, /*r*/12,
- i->ARMin.EvCheck.amFailAddr);
- *p++ = 0xE12FFF1C; /* bx r12 */
+ UInt* p0 = AssemblyBuffer__getCursor_4aligned(ab);
+ do_load_or_store32(ab, True/*isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amCounter);
+ PUT(ab, 0xE25CC001); /* subs r12, r12, #1 */
+ do_load_or_store32(ab, False/*!isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amCounter);
+ PUT(ab, 0x5A000001); /* bpl nofail */
+ do_load_or_store32(ab, True/*isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amFailAddr);
+ PUT(ab, 0xE12FFF1C); /* bx r12 */
/* nofail: */
/* Crosscheck */
- vassert(evCheckSzB_ARM() == (UChar*)p - (UChar*)p0);
+ vassert(evCheckSzB_ARM()
+ == (UChar*)AssemblyBuffer__getCursor(ab) - (UChar*)p0);
goto done;
}
@@ -4645,16 +4657,16 @@
adc r11, r11, #0
str r11, [r12+4]
*/
- p = imm32_to_ireg_EXACTLY2(p, /*r*/12, 0x65556555);
- *p++ = 0xE59CB000;
- *p++ = 0xE29BB001;
- *p++ = 0xE58CB000;
- *p++ = 0xE59CB004;
- *p++ = 0xE2ABB000;
- *p++ = 0xE58CB004;
+ imm32_to_ireg_EXACTLY2(ab, /*r*/12, 0x65556555);
+ PUT(ab, 0xE59CB000);
+ PUT(ab, 0xE29BB001);
+ PUT(ab, 0xE58CB000);
+ PUT(ab, 0xE59CB004);
+ PUT(ab, 0xE2ABB000);
+ PUT(ab, 0xE58CB004);
/* Tell the caller .. */
- vassert(!(*is_profInc));
- *is_profInc = True;
+ vassert(!is_profInc);
+ is_profInc = True;
goto done;
}
@@ -4669,11 +4681,13 @@
/*NOTREACHED*/
done:
- vassert(((UChar*)p) - &buf[0] <= 32);
- return ((UChar*)p) - &buf[0];
+ vassert(AssemblyBuffer__getCursor(ab) - initialCursor <= 32);
+ return is_profInc;
}
+/* --------- Helpers for translation chaining. --------- */
+
/* How big is an event check? See case for ARMin_EvCheck in
emit_ARMInstr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
@@ -4756,9 +4770,11 @@
p[1] = 0xFF000000;
p[2] = 0xFF000000;
} else {
- (void)imm32_to_ireg_EXACTLY2(
- p, /*r*/12, (UInt)(Addr)place_to_jump_to);
- p[2] = 0xE12FFF1C;
+ AssemblyBuffer ab;
+ AssemblyBuffer__init(&ab, (UChar*)p, 12);
+ imm32_to_ireg_EXACTLY2(&ab, /*r*/12, (UInt)(Addr)place_to_jump_to);
+ PUT(&ab, 0xE12FFF1C);
+ vassert(AssemblyBuffer__getRemainingSize(&ab) == 0);
}
VexInvalRange vir = {(HWord)p, 12};
@@ -4822,9 +4838,11 @@
<8 bytes generated by imm32_to_ireg_EXACTLY2>
E1 2F FF 3C
*/
- (void)imm32_to_ireg_EXACTLY2(
- p, /*r*/12, (UInt)(Addr)disp_cp_chain_me);
- p[2] = 0xE12FFF3C;
+ AssemblyBuffer ab;
+ AssemblyBuffer__init(&ab, (UChar*)p, 12);
+ imm32_to_ireg_EXACTLY2(&ab, /*r*/12, (UInt)(Addr)disp_cp_chain_me);
+ PUT(&ab, 0xE12FFF3C);
+ vassert(AssemblyBuffer__getRemainingSize(&ab) == 0);
VexInvalRange vir = {(HWord)p, 12};
return vir;
}
@@ -4847,12 +4865,16 @@
vassert(p[5] == 0xE59CB004);
vassert(p[6] == 0xE2ABB000);
vassert(p[7] == 0xE58CB004);
- imm32_to_ireg_EXACTLY2(p, /*r*/12, (UInt)(Addr)location_of_counter);
+ AssemblyBuffer ab;
+ AssemblyBuffer__init(&ab, (UChar*)p, 8);
+ imm32_to_ireg_EXACTLY2(&ab, /*r*/12, (UInt)(Addr)location_of_counter);
+ vassert(AssemblyBuffer__getRemainingSize(&ab) == 0);
VexInvalRange vir = {(HWord)p, 8};
return vir;
}
+#undef PUT
#undef BITS4
#undef X0000
#undef X0001
Modified: branches/NCODE/priv/host_arm_defs.h
==============================================================================
--- branches/NCODE/priv/host_arm_defs.h (original)
+++ branches/NCODE/priv/host_arm_defs.h Tue Apr 14 20:22:04 2015
@@ -1027,31 +1027,28 @@
extern void getRegUsage_ARMInstr ( HRegUsage*, const ARMInstr*, Bool );
extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr*, Bool );
extern Bool isMove_ARMInstr ( const ARMInstr*, HReg*, HReg* );
-extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
- UChar* buf, Int nbuf, const ARMInstr* i,
- Bool mode64,
- VexEndness endness_host,
- const void* disp_cp_chain_me_to_slowEP,
- const void* disp_cp_chain_me_to_fastEP,
- const void* disp_cp_xindir,
- const void* disp_cp_xassisted );
+
+extern Bool emit_ARMInstr ( /*MOD*/AssemblyBuffer* ab,
+ const ARMInstr* i,
+ Bool mode64, VexEndness endness_host,
+ const VexDispatcherAddresses* vda );
extern void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
- HReg rreg, Int offset, Bool );
+ HReg rreg, Bool spRel, Int offset, Bool );
extern void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
- HReg rreg, Int offset, Bool );
+ HReg rreg, Bool spRel, Int offset, Bool );
extern const RRegUniverse* getRRegUniverse_ARM ( void );
-extern HInstrArray* iselSB_ARM ( const IRSB*,
- VexArch,
- const VexArchInfo*,
- const VexAbiInfo*,
- Int offs_Host_EvC_Counter,
- Int offs_Host_EvC_FailAddr,
- Bool chainingAllowed,
- Bool addProfInc,
- Addr max_ga );
+extern HInstrArray* iselSB_ARM ( const IRSB*,
+ VexArch,
+ const VexArchInfo*,
+ const VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr max_ga );
/* How big is an event check? This is kind of a kludge because it
depends on the offsets of host_EvC_FAILADDR and
Modified: branches/NCODE/priv/host_generic_reg_alloc2.c
==============================================================================
--- branches/NCODE/priv/host_generic_reg_alloc2.c (original)
+++ branches/NCODE/priv/host_generic_reg_alloc2.c Tue Apr 14 20:22:04 2015
@@ -301,8 +301,6 @@
/* Vectorised memset, copied from Valgrind's m_libcbase.c. */
static void* local_memset ( void *destV, Int c, SizeT sz )
{
-# define IS_4_ALIGNED(aaa_p) (0 == (((HWord)(aaa_p)) & ((HWord)0x3)))
-
UInt c4;
UChar* d = destV;
UChar uc = c;
@@ -336,8 +334,6 @@
sz--;
}
return destV;
-
-# undef IS_4_ALIGNED
}
Modified: branches/NCODE/priv/host_generic_regs.h
==============================================================================
--- branches/NCODE/priv/host_generic_regs.h (original)
+++ branches/NCODE/priv/host_generic_regs.h Tue Apr 14 20:22:04 2015
@@ -537,6 +537,16 @@
return &abuf->buf[abuf->bufUsed];
}
+static inline UInt* AssemblyBuffer__getCursor_4aligned ( const
+ AssemblyBuffer* abuf )
+{
+ UChar* addr = &abuf->buf[abuf->bufUsed];
+ vassert(IS_4_ALIGNED(addr));
+ /* Cast via HWord so that gcc on arm32 doesn't complain about the
+ increase of alignment requirements. */
+ return (UInt*)(HWord)addr;
+}
+
static inline UInt AssemblyBuffer__getNext ( const AssemblyBuffer* abuf )
{
return abuf->bufUsed;
Modified: branches/NCODE/priv/main_main.c
==============================================================================
--- branches/NCODE/priv/main_main.c (original)
+++ branches/NCODE/priv/main_main.c Tue Apr 14 20:22:04 2015
@@ -545,7 +545,7 @@
host_word_type = Ity_I64;
vassert(vta->archinfo_host.endness == VexEndnessBE);
break;
-
+#endif
case VexArchARM:
mode64 = False;
rRegUniv = ARMFN(getRRegUniverse_ARM());
@@ -562,7 +562,7 @@
host_word_type = Ity_I32;
vassert(vta->archinfo_host.endness == VexEndnessLE);
break;
-
+#if 0
case VexArchARM64:
mode64 = True;
rRegUniv = ARM64FN(getRRegUniverse_ARM64());
@@ -732,7 +732,7 @@
vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8);
vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8);
break;
-
+#endif
case VexArchARM:
preciseMemExnsFn
= ARMFN(guest_arm_state_requires_precise_mem_exns);
@@ -753,7 +753,7 @@
vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4);
vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4);
break;
-
+#if 0
case VexArchARM64:
preciseMemExnsFn
= ARM64FN(guest_arm64_state_requires_precise_mem_exns);
@@ -1214,7 +1214,8 @@
(see comment on definition of type Relocation) */
vassert(rl->rshift <= 2);
Long E =
- ((Long)(ULong)dst) + ((Long)rl->bias) - ((Long)(ULong)where);
+ ((Long)(ULong)(HWord)dst) + ((Long)rl->bias)
+ - ((Long)(ULong)(HWord)where);
E = E >>/*signed*/rl->rshift;
if (debug_reloc)
vex_printf("E = 0x%llx\n", E);
Modified: branches/NCODE/priv/main_util.h
==============================================================================
--- branches/NCODE/priv/main_util.h (original)
+++ branches/NCODE/priv/main_util.h Tue Apr 14 20:22:04 2015
@@ -50,6 +50,8 @@
# define offsetof(type,memb) ((SizeT)(HWord)&((type*)0)->memb)
#endif
+#define IS_4_ALIGNED(_addr) (0 == (((HWord)(_addr)) & ((HWord)0x3)))
+
// Poor man's static assert
#define STATIC_ASSERT(x) extern int vex__unused_array[(x) ? 1 : -1] \
__attribute__((unused))
|
|
From: <sv...@va...> - 2015-04-14 18:35:46
|
Author: sewardj
Date: Tue Apr 14 19:35:38 2015
New Revision: 15089
Log:
Add an NCode template for 16 bit loads on 64 bit targets.
Modified:
branches/NCODE/memcheck/mc_include.h
branches/NCODE/memcheck/mc_main.c
branches/NCODE/memcheck/mc_translate.c
Modified: branches/NCODE/memcheck/mc_include.h
==============================================================================
--- branches/NCODE/memcheck/mc_include.h (original)
+++ branches/NCODE/memcheck/mc_include.h Tue Apr 14 19:35:38 2015
@@ -602,6 +602,7 @@
extern NCodeTemplate* MC_(tmpl__LOADV64le_on_64);
extern NCodeTemplate* MC_(tmpl__LOADV32le_on_64);
+extern NCodeTemplate* MC_(tmpl__LOADV16le_on_64);
extern NCodeTemplate* MC_(tmpl__LOADV8_on_64);
Modified: branches/NCODE/memcheck/mc_main.c
==============================================================================
--- branches/NCODE/memcheck/mc_main.c (original)
+++ branches/NCODE/memcheck/mc_main.c Tue Apr 14 19:35:38 2015
@@ -4276,7 +4276,8 @@
VG_REGPARM(1) static ULong mc_LOADV64le_on_64_slow ( Addr a );
VG_REGPARM(1) static ULong mc_LOADV32le_on_64_slow ( Addr a );
-VG_REGPARM(1) static ULong mc_LOADV8_on_64_slow ( Addr a );
+VG_REGPARM(1) static ULong mc_LOADV16le_on_64_slow ( Addr a );
+VG_REGPARM(1) static ULong mc_LOADV8_on_64_slow ( Addr a );
static void* ncode_alloc ( UInt n ) {
return VG_(malloc)("mc.ncode_alloc (NCode, permanent)", n);
@@ -4295,6 +4296,7 @@
NCodeTemplate* MC_(tmpl__LOADV64le_on_64) = NULL;
NCodeTemplate* MC_(tmpl__LOADV32le_on_64) = NULL;
+NCodeTemplate* MC_(tmpl__LOADV16le_on_64) = NULL;
NCodeTemplate* MC_(tmpl__LOADV8_on_64) = NULL;
static NCodeTemplate* mk_tmpl__LOADV64le_on_64 ( NAlloc na )
@@ -4423,6 +4425,98 @@
return tmpl;
}
+static NCodeTemplate* mk_tmpl__LOADV16le_on_64 ( NAlloc na )
+{
+ NInstr** hot = na((11+1) * sizeof(NInstr*));
+ NInstr** cold = na((14+1) * sizeof(NInstr*));
+
+ NReg rINVALID = mkNRegINVALID();
+
+ NReg r0 = mkNReg(Nrr_Result, 0);
+ NReg a0 = mkNReg(Nrr_Argument, 0);
+ NReg s0 = mkNReg(Nrr_Scratch, 0);
+
+ /*
+ h0 tst.w a0, #0xFFFFFFF000000001 high-or-misaligned?
+ h1 bnz cold.12 yes, goto slow path
+ h2 shr.w s0, a0, #16 s0 = pri-map-ix
+ h3 ld.64 s0, [&pri_map[0] + s0 << #3] s0 = sec-map
+ h4 and.w r0, a0, #0xFFFF r0 = sec-map-offB
+ h5 shr.w r0, r0, #2 r0 = sec-map-ix
+ h6 ld.8 r0, [s0 + r0 << #0] r0 = sec-map-VABITS8
+ h7 cmp.w r0, #0xAA r0 == VABITS8_DEFINED?
+ h8 bnz cold.0 no, goto cold.0
+ h9 imm.w r0, #0xFFFFFFFFFFFF0000 VBITS8_DEFINED | top48safe
+ h10 nop continue
+
+ c0 cmp.w r0, #0x55 VABITS8_UNDEFINED
+ c1 bnz cold.4
+
+ c2 imm.w r0, #0xFFFFFFFFFFFFFFFF VBITS16_UNDEFINED | top48safe
+ c3 b hot.10
+
+ // r0 holds sec-map-VABITS8. a0 holds the address and is 2-aligned.
+ // Extract the relevant 4 bits of r0 and inspect.
+ c4 and.w s0, a0, #2 // addr & 2
+ c5 add.w s0, s0, s0 // 2 * (addr & 2)
+ c6 shr.w r0, r0, s0 // sec-map-VABITS8 >> (2 * (addr & 2))
+ c7 and.w r0, r0, #15 // (sec-map-VABITS8 >> (2 * (addr & 2))) & 15
+
+ c8 cmp.w r0, #A // VABITS4_DEFINED
+ c9 jz hot.9
+
+ c10 cmp.w r0, #5 // VABITS4_UNDEFINED
+ c11 jz cold.2
+
+ c12 call r0 = mc_LOADV16le_on_64_slow(a0)
+ c13 b hot.10
+ */
+ hot[0] = NInstr_SetFlagsWri (na, Nsf_TEST, a0, MASK(2));
+ hot[1] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 12));
+ hot[2] = NInstr_ShiftWri (na, Nsh_SHR, s0, a0, 16);
+ hot[3] = NInstr_LoadU (na, 8, s0, NEA_IRS(na, (HWord)&primary_map[0],
+ s0, 3));
+ hot[4] = NInstr_AluWri (na, Nalu_AND, r0, a0, 0xFFFF);
+ hot[5] = NInstr_ShiftWri (na, Nsh_SHR, r0, r0, 2);
+ hot[6] = NInstr_LoadU (na, 1, r0, NEA_RRS(na, s0, r0, 0));
+ hot[7] = NInstr_SetFlagsWri (na, Nsf_CMP, r0, VA_BITS8_DEFINED);
+ hot[8] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 0));
+ hot[9] = NInstr_ImmW (na, r0, 0xFFFFFFFFFFFF0000ULL
+ | (ULong)V_BITS16_DEFINED);
+ hot[10] = NInstr_Nop (na);
+
+ cold[0] = NInstr_SetFlagsWri (na, Nsf_CMP, r0, VA_BITS8_UNDEFINED);
+ cold[1] = NInstr_Branch (na, Ncc_NZ, mkNLabel(Nlz_Cold, 4));
+
+ cold[2] = NInstr_ImmW (na, r0, 0xFFFFFFFFFFFF0000ULL
+ | (ULong)V_BITS16_UNDEFINED);
+ cold[3] = NInstr_Branch (na, Ncc_ALWAYS, mkNLabel(Nlz_Hot, 10));
+
+ // r0 holds sec-map-VABITS8. a0 holds the address and is 2-aligned.
+ // Extract the relevant 4 bits of r0 and inspect.
+ cold[4] = NInstr_AluWri (na, Nalu_AND, s0, a0, 2);
+ cold[5] = NInstr_AluWrr (na, Nalu_ADD, s0, s0, s0);
+ cold[6] = NInstr_ShiftWrr (na, Nsh_SHR, r0, r0, s0);
+ cold[7] = NInstr_AluWri (na, Nalu_AND, r0, r0, 15);
+
+ cold[8] = NInstr_SetFlagsWri (na, Nsf_CMP, r0, 0xA);
+ cold[9] = NInstr_Branch (na, Ncc_Z, mkNLabel(Nlz_Hot, 9));
+
+ cold[10]= NInstr_SetFlagsWri (na, Nsf_CMP, r0, 0x5);
+ cold[11]= NInstr_Branch (na, Ncc_Z, mkNLabel(Nlz_Cold, 2));
+
+ cold[12]= NInstr_Call (na, rINVALID, r0, mkNRegVec1(na, a0),
+ (void*)& mc_LOADV16le_on_64_slow,
+ "mc_LOADV16le_on_64_slow");
+ cold[13]= NInstr_Branch (na, Ncc_ALWAYS, mkNLabel(Nlz_Hot, 10));
+
+ hot[11] = cold[14] = NULL;
+ NCodeTemplate* tmpl
+ = mkNCodeTemplate(na,"LOADV16le_on_64",
+ /*res, parms, scratch*/1, 1, 1, hot, cold);
+ return tmpl;
+}
+
static NCodeTemplate* mk_tmpl__LOADV8_on_64 ( NAlloc na )
{
NInstr** hot = na((11+1) * sizeof(NInstr*));
@@ -4520,9 +4614,11 @@
{
tl_assert(MC_(tmpl__LOADV64le_on_64) == NULL);
tl_assert(MC_(tmpl__LOADV32le_on_64) == NULL);
+ tl_assert(MC_(tmpl__LOADV16le_on_64) == NULL);
tl_assert(MC_(tmpl__LOADV8_on_64) == NULL);
MC_(tmpl__LOADV64le_on_64) = mk_tmpl__LOADV64le_on_64(ncode_alloc);
MC_(tmpl__LOADV32le_on_64) = mk_tmpl__LOADV32le_on_64(ncode_alloc);
+ MC_(tmpl__LOADV16le_on_64) = mk_tmpl__LOADV16le_on_64(ncode_alloc);
MC_(tmpl__LOADV8_on_64) = mk_tmpl__LOADV8_on_64(ncode_alloc);
}
@@ -4901,6 +4997,11 @@
{
return mc_LOADV16(a, False);
}
+VG_REGPARM(1) static ULong mc_LOADV16le_on_64_slow ( Addr a )
+{
+ return mc_LOADVn_slow( a, 16, False/*!isBigEndian*/ );
+}
+
/* True if the vabits4 in vabits8 indicate a and a+1 are accessible. */
static INLINE
Modified: branches/NCODE/memcheck/mc_translate.c
==============================================================================
--- branches/NCODE/memcheck/mc_translate.c (original)
+++ branches/NCODE/memcheck/mc_translate.c Tue Apr 14 19:35:38 2015
@@ -4626,42 +4626,62 @@
/* ------ BEGIN inline NCode ? ------ */
if (guardIsAlwaysTrue(guard) && mce->hWordTy == Ity_I64 && end == Iend_LE) {
- if (ty == Ity_I64) {
- /* Unconditional LOAD64le on 64 bit host. Generate inline code. */
- IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
- NCodeTemplate* tmpl = MC_(tmpl__LOADV64le_on_64);
- IRAtom** args = mkIRExprVec_1( addrAct );
- IRTemp* ress = mkIRTempVec_1( datavbits64 );
- stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
- return mkexpr(datavbits64);
- }
- if (ty == Ity_I32) {
- /* Unconditional LOAD32le on 64 bit host. Generate inline code. */
- IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
- NCodeTemplate* tmpl = MC_(tmpl__LOADV32le_on_64);
- IRAtom** args = mkIRExprVec_1( addrAct );
- IRTemp* ress = mkIRTempVec_1( datavbits64 );
- /* The NCode block produces a 64 bit value, but we need to
- truncate it to 32 bits. */
- stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
- IRAtom* datavbits32
- = assignNew('V', mce, Ity_I32, unop(Iop_64to32, mkexpr(datavbits64)));
- return datavbits32;
- }
- if (ty == Ity_I8) {
- /* Unconditional LOAD8 on 64 bit host. Generate inline code. */
- IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
- NCodeTemplate* tmpl = MC_(tmpl__LOADV8_on_64);
- IRAtom** args = mkIRExprVec_1( addrAct );
- IRTemp* ress = mkIRTempVec_1( datavbits64 );
- /* The NCode block produces a 64 bit value, but we need to
- truncate it to 8 bits. */
- stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
- IRAtom* datavbits8
- = assignNew('V', mce, Ity_I8, unop(Iop_64to8, mkexpr(datavbits64)));
- return datavbits8;
+ switch (ty) {
+ case Ity_I64: {
+ /* Unconditional LOAD64le on 64 bit host. Generate inline code. */
+ IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV64le_on_64);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_1( datavbits64 );
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ return mkexpr(datavbits64);
+ }
+ case Ity_I32: {
+ /* Unconditional LOAD32le on 64 bit host. Generate inline code. */
+ IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV32le_on_64);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_1( datavbits64 );
+ /* The NCode block produces a 64 bit value, but we need to
+ truncate it to 32 bits. */
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ IRAtom* datavbits32
+ = assignNew('V', mce, Ity_I32,
+ unop(Iop_64to32, mkexpr(datavbits64)));
+ return datavbits32;
+ }
+ case Ity_I16: {
+ /* Unconditional LOAD16le on 64 bit host. Generate inline code. */
+ IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV16le_on_64);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_1( datavbits64 );
+ /* The NCode block produces a 64 bit value, but we need to
+ truncate it to 16 bits. */
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ IRAtom* datavbits16
+ = assignNew('V', mce, Ity_I16,
+ unop(Iop_64to16, mkexpr(datavbits64)));
+ return datavbits16;
+ }
+ case Ity_I8: {
+ /* Unconditional LOAD8 on 64 bit host. Generate inline code. */
+ IRTemp datavbits64 = newTemp(mce, Ity_I64, VSh);
+ NCodeTemplate* tmpl = MC_(tmpl__LOADV8_on_64);
+ IRAtom** args = mkIRExprVec_1( addrAct );
+ IRTemp* ress = mkIRTempVec_1( datavbits64 );
+ /* The NCode block produces a 64 bit value, but we need to
+ truncate it to 8 bits. */
+ stmt( 'V', mce, IRStmt_NCode(tmpl, args, ress) );
+ IRAtom* datavbits8
+ = assignNew('V', mce, Ity_I8,
+ unop(Iop_64to8, mkexpr(datavbits64)));
+ return datavbits8;
+ }
+ default:
+ /* else fall through */
+ break;
}
- /* else fall through */
}
/* ------ END inline NCode ? ------ */
|
|
From: Zhi-Gang L. <zh...@gm...> - 2015-04-13 22:39:41
|
Philippe
Have you ever tried the patch I post in this mail chain for the TileGX
evCheck issue?
If works for you I will commit it once I have SVN access.
Thanks
ZhiGang
On Apr 12, 2015 1:25 AM, "Zhigang Liu" <zl...@ez...> wrote:
>
>
> ________________________________________
> From: Philippe Waroquiers <phi...@sk...>
> Sent: Saturday, April 11, 2015 7:30 AM
> To: Zhigang Liu
> Cc: Valgrind Developers
> Subject: Re: [Valgrind-developers] I need access to a TILEGX :) :
> libvexmultiarch_test failing with TILEGX host
>
> On Sat, 2015-04-11 at 01:12 +0200, Philippe Waroquiers wrote:
> > On Sat, 2015-04-11 at 01:02 +0200, Philippe Waroquiers wrote:
> > > Julian,
> > > do you agree that the offB_HOST_* offsets are depending on the host
> > > architecture, and not on the guest architecture ?
> > Moving the offB_HOST_* to the arch_host switch makes
> > guest amd64/host tilegx
> > work ok.
> >
> > It looks to me that this is the good thing to do
> After an irc discussion with Julian, it became clear that this
> is not the good thing to do, and that I misunderstood
> the somewhat misleading names offB_HOST_EvC_COUNTER and
> offB_HOST_EvC_FAILADDR.
>
> Here is what I understand now:
> These offB_HOST_* are really offset in the guest state,
> which give locations in the guest state that are used by the
> (generated) host code.
> Basically, a translation entry (generated host code) is doing
> if (-- guest_state->COUNTER) == 0) goto guest_state->FAILADDR
>
> So, COUNTER and FAILADDR are in the guest state.
> FAILADDR must be an host address
> (this is in fact wrongly defined in all 32 bits guest states.
> E.g. libvex_guest_x86.h and libvex_guest_ppc32.h defines
> UInt host_EvC_FAILADDR;
> while it should be the size of an host address (or at least
> big enough to hold a 64 bit host address, if the host would
> be 64 bits in a multiarch setup).
>
>
> So, now I think the problem guest amd64/host tilegx
> is better solved in the host tilegx code, that should ensure to always
> generate the same nr of bytes for the evCheck instructions
> (this was suggested by Zhigang)
> (or maybe dynamically compute
> the needed nr of instructions for an eventcheck, depending
> on the offsets of the host_EvC_*, that changes the size of the
> instructions).
>
> Zhigang, does the above look reasonable to do in tilegx ?
>
> Yes, thank you for finding this issue. I have a simple patch for this,
> would you mind to have a try.
> Thanks
> --- ZhiGang
>
> ******* Begin of the patch ******
> Index: priv/host_tilegx_defs.c
> ===================================================================
> --- priv/host_tilegx_defs.c (revision 3125)
> +++ priv/host_tilegx_defs.c (working copy)
> @@ -1348,11 +1348,10 @@
>
> static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode *
> am )
> {
> - UInt rA; //, idx;
> + UInt rA;
> vassert(am->tag == GXam_IR);
>
> rA = iregNo(am->GXam.IR.base);
> - //idx = am->GXam.IR.index;
>
> if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 ||
> opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) {
> @@ -1381,19 +1380,29 @@
> return p;
> }
>
> -/* Generate a machine-word sized load or store. Simplified version of
> - the GXin_Load and GXin_Store cases below. */
> +/* Generate a machine-word sized load or store using exact 2 bundles.
> + Simplified version of the GXin_Load and GXin_Store cases below. */
> static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt
> reg,
> TILEGXAMode* am )
> {
> + UInt rA = iregNo(am->GXam.IR.base);
> +
> if (am->tag != GXam_IR)
> vpanic(__func__);
>
> - if (isLoad) /* load */
> - p = doAMode_IR(p, TILEGX_OPC_LD, reg, am);
> - else /* store */
> - p = doAMode_IR(p, TILEGX_OPC_ST, reg, am);
> -
> + if (isLoad) /* load */ {
> + /* r51 is reserved scratch registers. */
> + p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
> + 51, rA, am->GXam.IR.index));
> + /* load from address in r51 to rSD. */
> + p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51));
> + } else /* store */ {
> + /* r51 is reserved scratch registers. */
> + p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
> + 51, rA, am->GXam.IR.index));
> + /* store rSD to address in r51 */
> + p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg));
> + }
> return p;
> }
> ******* END of the patch ******
>
>
> (waiting for this to be done, I could always disable in the test
> using tilegx as a host)
>
> Thanks
>
> Philippe
>
>
>
>
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From: Kandi, J. <jag...@in...> - 2015-04-13 22:23:45
|
Hi, I work for Intel Corporation as KNL middleware and tools enabling manager. I am wondering whether Valgrind community has any plans to make changes to this tool to support KNL Processor. If yes, who is the owner / right person to talk to? Regards, Jagan.... Software and Services Group Intel Corporation Mobile: 480-205-5812 Jag...@in...<mailto:Jag...@in...> |
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From: Peter B. <be...@vn...> - 2015-04-13 17:45:47
|
On Sat, 2015-04-11 at 16:36 -0700, John Reiser wrote: > > On MIPS (ASUS RT-N16): > > $ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP > > ### empty output from grep: no AT_HWCAP at all > > ... because the C library is uClibc, not glibc. Yes, the above is a neat trick from glibc. On linux, the AUXV is exported from the kernel via /proc/<pid>/auxv or /proc/self/auxv and it is also placed on the stack above the top most frame. We (IBM) also created a libauxv library which can help with reading and querying the AUXV contents: https://github.com/Libauxv/libauxv > Some digging shows that the AUX vector is: > 0x00000010 AT_HWCAP 0x00000000 [snip] > Still, AT_HWCAP is 0, which omits information such as support for mips16 and dsp > that is shown in /proc/cpuinfo below. The Linux kernel is 2.6.24 (dd-wrt + optware.) That seems like a kernel bug to me. > From the viewpoint of the end user, a commandline override such as --cpu=... > has an advantage because it allows working around bugs in AT_HWCAP > and/or /proc/cpuinfo. You'll get no argument from me on it being potentially useful to override the automatically detected cpu value. Peter |
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From: Rhys K. <rhy...@gm...> - 2015-04-13 11:57:57
|
Thanks Mark for the patch. On Monday, 13 April 2015, Julian Seward <js...@ac...> wrote: > On 13/04/15 00:50, Mark Pauley wrote: > > > a breaking change to the initimg interfaces without making sure > > to un-bust initimg-darwin.c > > Ach; that is my bad really, for failing to set up or arrange to have > set up, a nightly builder for MacOSX. > > > configure.am file is a bit too strict for Apple LLVM checking, > > Committed as r15087 and r15088. Thanks for the fixes. > > J > > > > ------------------------------------------------------------------------------ > BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT > Develop your own process in accordance with the BPMN 2 standard > Learn Process modeling best practices with Bonita BPM through live > exercises > http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- > event?utm_ > source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF > _______________________________________________ > Valgrind-developers mailing list > Val...@li... <javascript:;> > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |
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From: Julian S. <js...@ac...> - 2015-04-13 11:44:10
|
On 13/04/15 00:50, Mark Pauley wrote: > a breaking change to the initimg interfaces without making sure > to un-bust initimg-darwin.c Ach; that is my bad really, for failing to set up or arrange to have set up, a nightly builder for MacOSX. > configure.am file is a bit too strict for Apple LLVM checking, Committed as r15087 and r15088. Thanks for the fixes. J |
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From: <sv...@va...> - 2015-04-13 11:41:37
|
Author: sewardj
Date: Mon Apr 13 12:41:30 2015
New Revision: 15088
Log:
Make the version checking for Apple LLVM a bit less strict.
Modified:
trunk/configure.ac
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Mon Apr 13 12:41:30 2015
@@ -154,7 +154,7 @@
# Note: m4 arguments are quoted with [ and ] so square brackets in shell
# statements have to be quoted.
case "${is_clang}-${gcc_version}" in
- applellvm-5.1|applellvm-6.0*)
+ applellvm-5.1|applellvm-6.*)
AC_MSG_RESULT([ok (Apple LLVM version ${gcc_version})])
;;
icc-1[[3-9]].*)
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