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From: <sv...@va...> - 2014-11-23 17:56:32
|
Author: sewardj
Date: Sun Nov 23 17:56:25 2014
New Revision: 14767
Log:
Merge, from trunk, r14705
14705 Update system call lists.
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-amd64-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm64-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips32-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips64-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc32-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc64-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-s390x-linux.h
branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-x86-linux.h
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-amd64-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-amd64-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-amd64-linux.h Sun Nov 23 17:56:25 2014
@@ -394,6 +394,15 @@
#define __NR_process_vm_readv 310
#define __NR_process_vm_writev 311
#define __NR_kcmp 312
+#define __NR_finit_module 313
+#define __NR_sched_setattr 314
+#define __NR_sched_getattr 315
+#define __NR_renameat2 316
+#define __NR_seccomp 317
+#define __NR_getrandom 318
+#define __NR_memfd_create 319
+#define __NR_kexec_file_load 320
+#define __NR_bpf 321
#endif /* __VKI_SCNUMS_AMD64_LINUX_H */
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm-linux.h Sun Nov 23 17:56:25 2014
@@ -414,6 +414,14 @@
#define __NR_setns 375
#define __NR_process_vm_readv 376
#define __NR_process_vm_writev 377
+#define __NR_kcmp 378
+#define __NR_finit_module 379
+#define __NR_sched_setattr 380
+#define __NR_sched_getattr 381
+#define __NR_renameat2 382
+#define __NR_seccomp 383
+#define __NR_getrandom 384
+#define __NR_memfd_create 385
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm64-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm64-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-arm64-linux.h Sun Nov 23 17:56:25 2014
@@ -307,6 +307,13 @@
#define __NR_process_vm_writev 271
#define __NR_kcmp 272
#define __NR_finit_module 273
+#define __NR_sched_setattr 274
+#define __NR_sched_getattr 275
+#define __NR_renameat2 276
+#define __NR_seccomp 277
+#define __NR_getrandom 278
+#define __NR_memfd_create 279
+#define __NR_bpf 280
#undef __NR_syscalls
#define __NR_syscalls 274
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips32-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips32-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips32-linux.h Sun Nov 23 17:56:25 2014
@@ -382,6 +382,14 @@
#define __NR_syncfs (__NR_Linux + 342)
#define __NR_process_vm_readv (__NR_Linux + 345)
#define __NR_process_vm_writev (__NR_Linux + 346)
+#define __NR_kcmp (__NR_Linux + 347)
+#define __NR_finit_module (__NR_Linux + 348)
+#define __NR_sched_setattr (__NR_Linux + 349)
+#define __NR_sched_getattr (__NR_Linux + 350)
+#define __NR_renameat2 (__NR_Linux + 351)
+#define __NR_seccomp (__NR_Linux + 352)
+#define __NR_getrandom (__NR_Linux + 353)
+#define __NR_memfd_create (__NR_Linux + 354)
/*
* Offset of the last Linux o32 flavoured syscall
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips64-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips64-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-mips64-linux.h Sun Nov 23 17:56:25 2014
@@ -348,6 +348,9 @@
#define __NR_sched_setattr (__NR_Linux + 309)
#define __NR_sched_getattr (__NR_Linux + 310)
#define __NR_renameat2 (__NR_Linux + 311)
+#define __NR_seccomp (__NR_Linux + 312)
+#define __NR_getrandom (__NR_Linux + 313)
+#define __NR_memfd_create (__NR_Linux + 314)
#endif /* __VKI_SCNUMS_MIPS64_LINUX_H */
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc32-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc32-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc32-linux.h Sun Nov 23 17:56:25 2014
@@ -395,6 +395,14 @@
#define __NR_setns 350
#define __NR_process_vm_readv 351
#define __NR_process_vm_writev 352
+#define __NR_finit_module 353
+#define __NR_kcmp 354
+#define __NR_sched_setattr 355
+#define __NR_sched_getattr 356
+#define __NR_renameat2 357
+#define __NR_seccomp 358
+#define __NR_getrandom 359
+#define __NR_memfd_create 360
#endif /* __VKI_SCNUMS_PPC32_LINUX_H */
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc64-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc64-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-ppc64-linux.h Sun Nov 23 17:56:25 2014
@@ -387,6 +387,14 @@
#define __NR_setns 350
#define __NR_process_vm_readv 351
#define __NR_process_vm_writev 352
+#define __NR_finit_module 353
+#define __NR_kcmp 354
+#define __NR_sched_setattr 355
+#define __NR_sched_getattr 356
+#define __NR_renameat2 357
+#define __NR_seccomp 358
+#define __NR_getrandom 359
+#define __NR_memfd_create 360
#endif /* __VKI_SCNUMS_PPC64_LINUX_H */
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-s390x-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-s390x-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-s390x-linux.h Sun Nov 23 17:56:25 2014
@@ -313,7 +313,10 @@
#define __NR_sched_setattr 345
#define __NR_sched_getattr 346
#define __NR_renameat2 347
-#define NR_syscalls 348
+#define __NR_seccomp 348
+#define __NR_getrandom 349
+#define __NR_memfd_create 350
+#define NR_syscalls 351
/*
* There are some system calls that are not present on 64 bit, some
Modified: branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-x86-linux.h
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-x86-linux.h (original)
+++ branches/VALGRIND_3_10_BRANCH/include/vki/vki-scnums-x86-linux.h Sun Nov 23 17:56:25 2014
@@ -384,6 +384,14 @@
#define __NR_process_vm_readv 347
#define __NR_process_vm_writev 348
#define __NR_kcmp 349
+#define __NR_finit_module 350
+#define __NR_sched_setattr 351
+#define __NR_sched_getattr 352
+#define __NR_renameat2 353
+#define __NR_seccomp 354
+#define __NR_getrandom 355
+#define __NR_memfd_create 356
+#define __NR_bpf 357
#endif /* __VKI_SCNUMS_X86_LINUX_H */
|
|
From: <sv...@va...> - 2014-11-23 17:55:20
|
Author: sewardj
Date: Sun Nov 23 17:55:13 2014
New Revision: 14766
Log:
Merge, from trunk, r14689
14689 PRE(sys_openat): when checking whether ARG1 == VKI_AT_FDCWD [..]
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-linux.c (contents, props changed)
Modified: branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-linux.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-linux.c (original)
+++ branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-linux.c Sun Nov 23 17:55:13 2014
@@ -4372,10 +4372,11 @@
PRE_MEM_RASCIIZ( "openat(filename)", ARG2 );
/* For absolute filenames, dfd is ignored. If dfd is AT_FDCWD,
- filename is relative to cwd. */
+ filename is relative to cwd. When comparing dfd against AT_FDCWD,
+ be sure only to compare the bottom 32 bits. */
if (ML_(safe_to_deref)( (void*)ARG2, 1 )
&& *(Char *)ARG2 != '/'
- && ARG1 != VKI_AT_FDCWD
+ && ((Int)ARG1) != ((Int)VKI_AT_FDCWD)
&& !ML_(fd_allowed)(ARG1, "openat", tid, False))
SET_STATUS_Failure( VKI_EBADF );
|
|
From: <sv...@va...> - 2014-11-23 17:53:08
|
Author: sewardj
Date: Sun Nov 23 17:52:56 2014
New Revision: 14765
Log:
Merge, from trunk, r14686
340630 arm64: fchmod (52) and fchown (55) syscalls not recognized
14686
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c Sun Nov 23 17:52:56 2014
@@ -899,8 +899,10 @@
GENX_(__NR_chdir, sys_chdir), // 49
GENX_(__NR_fchdir, sys_fchdir), // 50
GENX_(__NR_chroot, sys_chroot), // 51
+ GENX_(__NR_fchmod, sys_fchmod), // 52
LINX_(__NR_fchmodat, sys_fchmodat), // 53
LINX_(__NR_fchownat, sys_fchownat), // 54
+ GENX_(__NR_fchown, sys_fchown), // 55
LINXY(__NR_openat, sys_openat), // 56
GENXY(__NR_close, sys_close), // 57
LINXY(__NR_pipe2, sys_pipe2), // 59
@@ -1129,7 +1131,6 @@
//ZZ GENXY(__NR_munmap, sys_munmap), // 91
//ZZ GENX_(__NR_truncate, sys_truncate), // 92
//ZZ GENX_(__NR_ftruncate, sys_ftruncate), // 93
-//ZZ GENX_(__NR_fchmod, sys_fchmod), // 94
//ZZ
//ZZ LINX_(__NR_fchown, sys_fchown16), // 95
//ZZ // GENX_(__NR_profil, sys_ni_syscall), // 98
@@ -1237,7 +1238,6 @@
//ZZ
//ZZ GENXY(__NR_getgroups32, sys_getgroups), // 205
//ZZ GENX_(__NR_setgroups32, sys_setgroups), // 206
-//ZZ GENX_(__NR_fchown32, sys_fchown), // 207
//ZZ LINX_(__NR_setresuid32, sys_setresuid), // 208
//ZZ LINXY(__NR_getresuid32, sys_getresuid), // 209
//ZZ
|
|
From: <sv...@va...> - 2014-11-23 17:51:45
|
Author: sewardj
Date: Sun Nov 23 17:51:34 2014
New Revision: 14764
Log:
Merge, from trunk, r14684
14684 arm64 Add tests for all SIMD FP instructions [..]
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c Sun Nov 23 17:51:34 2014
@@ -11,6 +11,9 @@
typedef signed int Int;
typedef unsigned char UChar;
typedef unsigned long long int ULong;
+typedef signed long long int Long;
+typedef double Double;
+typedef float Float;
typedef unsigned char Bool;
#define False ((Bool)0)
@@ -28,8 +31,8 @@
UShort u16[8];
UInt u32[4];
ULong u64[2];
- float f32[4];
- double f64[2];
+ Float f32[4];
+ Double f64[2];
};
typedef union _V128 V128;
@@ -78,6 +81,17 @@
printf("%02x", (Int)v->u8[i]);
}
+static void showBlock ( const char* msg, V128* block, Int nBlock )
+{
+ Int i;
+ printf("%s\n", msg);
+ for (i = 0; i < nBlock; i++) {
+ printf(" ");
+ showV128(&block[i]);
+ printf("\n");
+ }
+}
+
__attribute__((unused))
static void* memalign16(size_t szB)
{
@@ -88,11 +102,146 @@
return x;
}
+static ULong dup4x16 ( UInt x )
+{
+ ULong r = x & 0xF;
+ r |= (r << 4);
+ r |= (r << 8);
+ r |= (r << 16);
+ r |= (r << 32);
+ return r;
+}
+
+// Generate a random double-precision number. About 1 time in 2,
+// instead return a special value (+/- Inf, +/-Nan, denorm).
+// This ensures that many of the groups of 4 calls here will
+// return a special value.
+
+static Double special_values[10];
+static Bool special_values_initted = False;
+
+static __attribute__((noinline))
+Double negate ( Double d ) { return -d; }
+static __attribute__((noinline))
+Double divf64 ( Double x, Double y ) { return x/y; }
+
+static __attribute__((noinline))
+Double plusZero ( void ) { return 0.0; }
+static __attribute__((noinline))
+Double minusZero ( void ) { return negate(plusZero()); }
+
+static __attribute__((noinline))
+Double plusOne ( void ) { return 1.0; }
+static __attribute__((noinline))
+Double minusOne ( void ) { return negate(plusOne()); }
+
+static __attribute__((noinline))
+Double plusInf ( void ) { return 1.0 / 0.0; }
+static __attribute__((noinline))
+Double minusInf ( void ) { return negate(plusInf()); }
+
+static __attribute__((noinline))
+Double plusNaN ( void ) { return divf64(plusInf(),plusInf()); }
+static __attribute__((noinline))
+Double minusNaN ( void ) { return negate(plusNaN()); }
+
+static __attribute__((noinline))
+Double plusDenorm ( void ) { return 1.23e-315 / 1e3; }
+static __attribute__((noinline))
+Double minusDenorm ( void ) { return negate(plusDenorm()); }
+
+
+static void ensure_special_values_initted ( void )
+{
+ if (special_values_initted) return;
+ special_values[0] = plusZero();
+ special_values[1] = minusZero();
+ special_values[2] = plusOne();
+ special_values[3] = minusOne();
+ special_values[4] = plusInf();
+ special_values[5] = minusInf();
+ special_values[6] = plusNaN();
+ special_values[7] = minusNaN();
+ special_values[8] = plusDenorm();
+ special_values[9] = minusDenorm();
+ special_values_initted = True;
+ int i;
+ printf("\n");
+ for (i = 0; i < 10; i++) {
+ printf("special value %d = %e\n", i, special_values[i]);
+ }
+ printf("\n");
+}
+
+static Double randDouble ( void )
+{
+ ensure_special_values_initted();
+ UChar c = randUChar();
+ if (c >= 128) {
+ // return a normal number most of the time.
+ // 0 .. 2^63-1
+ ULong u64 = randULong(TyDF);
+ // -2^62 .. 2^62-1
+ Long s64 = (Long)u64;
+ // -2^55 .. 2^55-1
+ s64 >>= (62-55);
+ // and now as a float
+ return (Double)s64;
+ }
+ c = randUChar() % 10;
+ return special_values[c];
+}
+
+static Float randFloat ( void )
+{
+ ensure_special_values_initted();
+ UChar c = randUChar();
+ if (c >= 128) {
+ // return a normal number most of the time.
+ // 0 .. 2^63-1
+ ULong u64 = randULong(TyDF);
+ // -2^62 .. 2^62-1
+ Long s64 = (Long)u64;
+ // -2^25 .. 2^25-1
+ s64 >>= (62-25);
+ // and now as a float
+ return (Float)s64;
+ }
+ c = randUChar() % 10;
+ return special_values[c];
+}
+
+void randBlock_Doubles ( V128* block, Int nBlock )
+{
+ Int i;
+ for (i = 0; i < nBlock; i++) {
+ block[i].f64[0] = randDouble();
+ block[i].f64[1] = randDouble();
+ }
+}
+
+void randBlock_Floats ( V128* block, Int nBlock )
+{
+ Int i;
+ for (i = 0; i < nBlock; i++) {
+ block[i].f32[0] = randFloat();
+ block[i].f32[1] = randFloat();
+ block[i].f32[2] = randFloat();
+ block[i].f32[3] = randFloat();
+ }
+}
+
/* ---------------------------------------------------------------- */
-/* -- Test macros -- */
+/* -- Parameterisable test macros -- */
/* ---------------------------------------------------------------- */
+#define DO50(_action) \
+ do { \
+ Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
+ } while (0)
+
+
/* Note this also sets the destination register to a known value (0x55..55)
since it can sometimes be an input to the instruction too. */
#define GEN_UNARY_TEST(INSN,SUFFIXD,SUFFIXN) \
@@ -292,8 +441,58 @@
}
+/* Generate a test that involves four vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use v16, v17, v18 as scratch. */
+#define GEN_FOURVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO, \
+ VECREG3NO,VECREG4NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[8+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ randV128(&block[6], ty); \
+ randV128(&block[7], ty); \
+ __asm__ __volatile__( \
+ "mov x30, #0 ; msr fpsr, x30 ; " \
+ "ldr q"#VECREG1NO", [%0, #0] ; " \
+ "ldr q"#VECREG2NO", [%0, #16] ; " \
+ "ldr q"#VECREG3NO", [%0, #32] ; " \
+ "ldr q"#VECREG4NO", [%0, #48] ; " \
+ INSN " ; " \
+ "str q"#VECREG1NO", [%0, #64] ; " \
+ "str q"#VECREG2NO", [%0, #80] ; " \
+ "str q"#VECREG3NO", [%0, #96] ; " \
+ "str q"#VECREG4NO", [%0, #112] ; " \
+ "mrs x30, fpsr ; str x30, [%0, #128] " \
+ : : "r"(&block[0]) \
+ : "memory", "v"#VECREG1NO, "v"#VECREG2NO, \
+ "v"#VECREG3NO, "v"#VECREG4NO, \
+ "v16", "v17", "v18", "x30" \
+ ); \
+ printf(INSN " "); \
+ UInt fpsr = 0xFFFFFF60 & block[8].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf(" "); \
+ showV128(&block[6]); printf(" "); \
+ showV128(&block[7]); printf(" fpsr=%08x\n", fpsr); \
+ } \
+ }
+
+
/* ---------------------------------------------------------------- */
-/* -- Test functions -- */
+/* -- Test functions and non-parameterisable test macros -- */
/* ---------------------------------------------------------------- */
void test_UMINV ( void )
@@ -891,6 +1090,991 @@
}
+//======== FCCMP_D ========//
+
+#define GEN_test_FCCMP_D_D_0xF_EQ \
+ __attribute__((noinline)) static void test_FCCMP_D_D_0xF_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_D_D_0xF_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp d29, d11, #0xf, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_D_D_0xF_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_D_D_0xF_NE \
+ __attribute__((noinline)) static void test_FCCMP_D_D_0xF_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_D_D_0xF_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp d29, d11, #0xf, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_D_D_0xF_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_D_D_0x0_EQ \
+ __attribute__((noinline)) static void test_FCCMP_D_D_0x0_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_D_D_0x0_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp d29, d11, #0x0, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_D_D_0x0_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_D_D_0x0_NE \
+ __attribute__((noinline)) static void test_FCCMP_D_D_0x0_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_D_D_0x0_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp d29, d11, #0x0, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_D_D_0x0_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCCMP_S ========//
+
+#define GEN_test_FCCMP_S_S_0xF_EQ \
+ __attribute__((noinline)) static void test_FCCMP_S_S_0xF_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0xF_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp s29, s11, #0xf, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_S_S_0xF_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_S_S_0xF_NE \
+ __attribute__((noinline)) static void test_FCCMP_S_S_0xF_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0xF_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp s29, s11, #0xf, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_S_S_0xF_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_S_S_0x0_EQ \
+ __attribute__((noinline)) static void test_FCCMP_S_S_0x0_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0x0_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp s29, s11, #0x0, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_S_S_0x0_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMP_S_S_0x0_NE \
+ __attribute__((noinline)) static void test_FCCMP_S_S_0x0_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0x0_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmp s29, s11, #0x0, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMP_S_S_0x0_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCCMPE_D ========//
+
+#define GEN_test_FCCMPE_D_D_0xF_EQ \
+ __attribute__((noinline)) static void test_FCCMPE_D_D_0xF_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMPE_D_D_0xF_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe d29, d11, #0xf, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_D_D_0xF_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_D_D_0xF_NE \
+ __attribute__((noinline)) static void test_FCCMPE_D_D_0xF_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMPE_D_D_0xF_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe d29, d11, #0xf, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_D_D_0xF_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_D_D_0x0_EQ \
+ __attribute__((noinline)) static void test_FCCMPE_D_D_0x0_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMPE_D_D_0x0_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe d29, d11, #0x0, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_D_D_0x0_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_D_D_0x0_NE \
+ __attribute__((noinline)) static void test_FCCMPE_D_D_0x0_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMPE_D_D_0x0_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe d29, d11, #0x0, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_D_D_0x0_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCCMPE_S ========//
+
+#define GEN_test_FCCMPE_S_S_0xF_EQ \
+ __attribute__((noinline)) static void test_FCCMPE_S_S_0xF_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0xF_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe s29, s11, #0xf, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_S_S_0xF_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_S_S_0xF_NE \
+ __attribute__((noinline)) static void test_FCCMPE_S_S_0xF_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMPE_S_S_0xF_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe s29, s11, #0xf, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_S_S_0xF_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_S_S_0x0_EQ \
+ __attribute__((noinline)) static void test_FCCMPE_S_S_0x0_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0x0_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe s29, s11, #0x0, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_S_S_0x0_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+#define GEN_test_FCCMPE_S_S_0x0_NE \
+ __attribute__((noinline)) static void test_FCCMPE_S_S_0x0_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCCMP_S_S_0x0_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fccmpe s29, s11, #0x0, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCCMPE_S_S_0x0_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMEQ_D_D ========//
+
+#define GEN_test_FCMEQ_D_D \
+ __attribute__((noinline)) static void test_FCMEQ_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMEQ_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmeq d29, d11, d9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMEQ_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMEQ_S_S ========//
+
+#define GEN_test_FCMEQ_S_S \
+ __attribute__((noinline)) static void test_FCMEQ_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMEQ_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmeq s29, s11, s9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMEQ_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGE_D_D ========//
+
+#define GEN_test_FCMGE_D_D \
+ __attribute__((noinline)) static void test_FCMGE_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGE_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmge d29, d11, d9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGE_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGE_S_S ========//
+
+#define GEN_test_FCMGE_S_S \
+ __attribute__((noinline)) static void test_FCMGE_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGE_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmge s29, s11, s9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGE_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGT_D_D ========//
+
+#define GEN_test_FCMGT_D_D \
+ __attribute__((noinline)) static void test_FCMGT_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGT_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmgt d29, d11, d9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGT_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGT_S_S ========//
+
+#define GEN_test_FCMGT_S_S \
+ __attribute__((noinline)) static void test_FCMGT_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGT_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmgt s29, s11, s9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGT_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FACGT_D_D ========//
+
+#define GEN_test_FACGT_D_D \
+ __attribute__((noinline)) static void test_FACGT_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FACGT_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "facgt d29, d11, d9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FACGT_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FACGT_S_S ========//
+
+#define GEN_test_FACGT_S_S \
+ __attribute__((noinline)) static void test_FACGT_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FACGT_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "facgt s29, s11, s9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FACGT_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FACGE_D_D ========//
+
+#define GEN_test_FACGE_D_D \
+ __attribute__((noinline)) static void test_FACGE_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FACGE_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "facge d29, d11, d9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FACGE_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FACGE_S_S ========//
+
+#define GEN_test_FACGE_S_S \
+ __attribute__((noinline)) static void test_FACGE_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FACGE_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "facge s29, s11, s9; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FACGE_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMEQ_Z_D ========//
+
+#define GEN_test_FCMEQ_Z_D \
+ __attribute__((noinline)) static void test_FCMEQ_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMEQ_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmeq d29, d11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMEQ_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMEQ_Z_S ========//
+
+#define GEN_test_FCMEQ_Z_S \
+ __attribute__((noinline)) static void test_FCMEQ_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMEQ_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmeq s29, s11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMEQ_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGE_Z_D ========//
+
+#define GEN_test_FCMGE_Z_D \
+ __attribute__((noinline)) static void test_FCMGE_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGE_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmge d29, d11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGE_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGE_Z_S ========//
+
+#define GEN_test_FCMGE_Z_S \
+ __attribute__((noinline)) static void test_FCMGE_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGE_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmge s29, s11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGE_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGT_Z_D ========//
+
+#define GEN_test_FCMGT_Z_D \
+ __attribute__((noinline)) static void test_FCMGT_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGT_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmgt d29, d11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGT_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMGT_Z_S ========//
+
+#define GEN_test_FCMGT_Z_S \
+ __attribute__((noinline)) static void test_FCMGT_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMGT_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmgt s29, s11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMGT_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMLE_Z_D ========//
+
+#define GEN_test_FCMLE_Z_D \
+ __attribute__((noinline)) static void test_FCMLE_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMLE_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmle d29, d11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMLE_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMLE_Z_S ========//
+
+#define GEN_test_FCMLE_Z_S \
+ __attribute__((noinline)) static void test_FCMLE_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMLE_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmle s29, s11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMLE_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMLT_Z_D ========//
+
+#define GEN_test_FCMLT_Z_D \
+ __attribute__((noinline)) static void test_FCMLT_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMLT_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmlt d29, d11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMLT_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMLT_Z_S ========//
+
+#define GEN_test_FCMLT_Z_S \
+ __attribute__((noinline)) static void test_FCMLT_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMLT_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmlt s29, s11, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMLT_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMP_D_D ========//
+
+#define GEN_test_FCMP_D_D \
+ __attribute__((noinline)) static void test_FCMP_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMP_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmp d29, d11; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMP_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMP_S_S ========//
+
+#define GEN_test_FCMP_S_S \
+ __attribute__((noinline)) static void test_FCMP_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMP_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmp s29, s11; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMP_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMPE_D_D ========//
+
+#define GEN_test_FCMPE_D_D \
+ __attribute__((noinline)) static void test_FCMPE_D_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMPE_D_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmpe d29, d11; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMPE_D_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMPE_S_S ========//
+
+#define GEN_test_FCMPE_S_S \
+ __attribute__((noinline)) static void test_FCMPE_S_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMPE_S_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmpe s29, s11; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMPE_S_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMP_Z_D ========//
+
+#define GEN_test_FCMP_Z_D \
+ __attribute__((noinline)) static void test_FCMP_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMP_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmp d29, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMP_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMP_Z_S ========//
+
+#define GEN_test_FCMP_Z_S \
+ __attribute__((noinline)) static void test_FCMP_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMP_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmp s29, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMP_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMPE_Z_D ========//
+
+#define GEN_test_FCMPE_Z_D \
+ __attribute__((noinline)) static void test_FCMPE_Z_D ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMPE_Z_D before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmpe d29, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMPE_Z_D after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCMPE_Z_S ========//
+
+#define GEN_test_FCMPE_Z_S \
+ __attribute__((noinline)) static void test_FCMPE_Z_S ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Floats(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCMPE_Z_S before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcmpe s29, #0; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCMPE_Z_S after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCSEL_D_D_D_EQ ========//
+
+#define GEN_test_FCSEL_D_D_D_EQ \
+ __attribute__((noinline)) static void test_FCSEL_D_D_D_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCSEL_D_D_D_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcsel d29, d11, d9, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCSEL_D_D_D_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCSEL_D_D_D_NE ========//
+
+#define GEN_test_FCSEL_D_D_D_NE \
+ __attribute__((noinline)) static void test_FCSEL_D_D_D_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCSEL_D_D_D_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcsel d29, d11, d9, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCSEL_D_D_D_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCSEL_S_S_S_EQ ========//
+
+#define GEN_test_FCSEL_S_S_S_EQ \
+ __attribute__((noinline)) static void test_FCSEL_S_S_S_EQ ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCSEL_S_S_S_EQ before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcsel s29, s11, s9, eq; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCSEL_S_S_S_EQ after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+//======== FCSEL_S_S_S_NE ========//
+
+#define GEN_test_FCSEL_S_S_S_NE \
+ __attribute__((noinline)) static void test_FCSEL_S_S_S_NE ( void ) \
+ { \
+ V128 block[4]; \
+ randBlock_Doubles(&block[0], 3); \
+ block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
+ showBlock("FCSEL_S_S_S_NE before", &block[0], 4); \
+ __asm__ __volatile__( \
+ "ldr x9, [%0, 48]; msr nzcv, x9; " \
+ "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
+ "fcsel s29, s11, s9, ne; " \
+ "mrs x9, nzcv; str x9, [%0, 48]; " \
+ "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
+ ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
+ ); \
+ showBlock("FCSEL_S_S_S_NE after", &block[0], 4); \
+ printf("\n"); \
+ }
+
+
/* ---------------------------------------------------------------- */
/* -- Tests, in the same order that they appear in main() -- */
/* ---------------------------------------------------------------- */
@@ -939,49 +2123,90 @@
GEN_THREEVEC_TEST(faddp_4s_4s_4s, "faddp v2.4s, v23.4s, v11.4s", 2, 23, 11)
GEN_THREEVEC_TEST(faddp_2s_2s_2s, "faddp v2.2s, v23.2s, v11.2s", 2, 23, 11)
-// fccmp d,s
-// fccmpe d,s
-
-// fcmeq d,s
-// fcmge d,s
-// fcmgt d,s
-// facgt d,s (floating abs compare GE)
-// facge d,s (floating abs compare GE)
-
-GEN_BINARY_TEST(fcmeq, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmeq, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmeq, 2s, 2s, 2s)
-GEN_BINARY_TEST(fcmge, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmge, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmge, 2s, 2s, 2s)
-GEN_BINARY_TEST(fcmgt, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmgt, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmgt, 2s, 2s, 2s)
-GEN_BINARY_TEST(facge, 2d, 2d, 2d)
-GEN_BINARY_TEST(facge, 4s, 4s, 4s)
-GEN_BINARY_TEST(facge, 2s, 2s, 2s)
-GEN_BINARY_TEST(facgt, 2d, 2d, 2d)
-GEN_BINARY_TEST(facgt, 4s, 4s, 4s)
-GEN_BINARY_TEST(facgt, 2s, 2s, 2s)
-
-// fcmeq_z d,s
-// fcmge_z d,s
-// fcmgt_z d,s
-// fcmle_z d,s
-// fcmlt_z d,s
-
-// fcmeq_z 2d,4s,2s
-// fcmge_z 2d,4s,2s
-// fcmgt_z 2d,4s,2s
-// fcmle_z 2d,4s,2s
-// fcmlt_z 2d,4s,2s
-
-// fcmp_z d,s
-// fcmpe_z d,s
-// fcmp d,s (floating point quiet, set flags)
-// fcmpe d,s (floating point signaling, set flags)
-
-// fcsel d,s (fp cond select)
+GEN_test_FCCMP_D_D_0xF_EQ
+GEN_test_FCCMP_D_D_0xF_NE
+GEN_test_FCCMP_D_D_0x0_EQ
+GEN_test_FCCMP_D_D_0x0_NE
+GEN_test_FCCMP_S_S_0xF_EQ
+GEN_test_FCCMP_S_S_0xF_NE
+GEN_test_FCCMP_S_S_0x0_EQ
+GEN_test_FCCMP_S_S_0x0_NE
+GEN_test_FCCMPE_D_D_0xF_EQ
+GEN_test_FCCMPE_D_D_0xF_NE
+GEN_test_FCCMPE_D_D_0x0_EQ
+GEN_test_FCCMPE_D_D_0x0_NE
+GEN_test_FCCMPE_S_S_0xF_EQ
+GEN_test_FCCMPE_S_S_0xF_NE
+GEN_test_FCCMPE_S_S_0x0_EQ
+GEN_test_FCCMPE_S_S_0x0_NE
+
+GEN_test_FCMEQ_D_D
+GEN_test_FCMEQ_S_S
+GEN_test_FCMGE_D_D
+GEN_test_FCMGE_S_S
+GEN_test_FCMGT_D_D
+GEN_test_FCMGT_S_S
+GEN_test_FACGT_D_D
+GEN_test_FACGT_S_S
+GEN_test_FACGE_D_D
+GEN_test_FACGE_S_S
+
+GEN_THREEVEC_TEST(fcmeq_2d_2d_2d, "fcmeq v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmeq_4s_4s_4s, "fcmeq v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmeq_2s_2s_2s, "fcmeq v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmge_2d_2d_2d, "fcmge v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmge_4s_4s_4s, "fcmge v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmge_2s_2s_2s, "fcmge v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmgt_2d_2d_2d, "fcmgt v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmgt_4s_4s_4s, "fcmgt v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fcmgt_2s_2s_2s, "fcmgt v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(facge_2d_2d_2d, "facge v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(facge_4s_4s_4s, "facge v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(facge_2s_2s_2s, "facge v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(facgt_2d_2d_2d, "facgt v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(facgt_4s_4s_4s, "facgt v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(facgt_2s_2s_2s, "facgt v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+GEN_test_FCMEQ_Z_D
+GEN_test_FCMEQ_Z_S
+GEN_test_FCMGE_Z_D
+GEN_test_FCMGE_Z_S
+GEN_test_FCMGT_Z_D
+GEN_test_FCMGT_Z_S
+GEN_test_FCMLE_Z_D
+GEN_test_FCMLE_Z_S
+GEN_test_FCMLT_Z_D
+GEN_test_FCMLT_Z_S
+
+GEN_TWOVEC_TEST(fcmeq_z_2d_2d, "fcmeq v2.2d, v23.2d, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmeq_z_4s_4s, "fcmeq v2.4s, v23.4s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmeq_z_2s_2s, "fcmeq v2.2s, v23.2s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmge_z_2d_2d, "fcmge v2.2d, v23.2d, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmge_z_4s_4s, "fcmge v2.4s, v23.4s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmge_z_2s_2s, "fcmge v2.2s, v23.2s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmgt_z_2d_2d, "fcmgt v2.2d, v23.2d, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmgt_z_4s_4s, "fcmgt v2.4s, v23.4s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmgt_z_2s_2s, "fcmgt v2.2s, v23.2s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmle_z_2d_2d, "fcmle v2.2d, v23.2d, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmle_z_4s_4s, "fcmle v2.4s, v23.4s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmle_z_2s_2s, "fcmle v2.2s, v23.2s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmlt_z_2d_2d, "fcmlt v2.2d, v23.2d, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmlt_z_4s_4s, "fcmlt v2.4s, v23.4s, #0", 2, 23)
+GEN_TWOVEC_TEST(fcmlt_z_2s_2s, "fcmlt v2.2s, v23.2s, #0", 2, 23)
+
+GEN_test_FCMP_Z_D
+GEN_test_FCMP_Z_S
+GEN_test_FCMPE_Z_D
+GEN_test_FCMPE_Z_S
+GEN_test_FCMP_D_D
+GEN_test_FCMP_S_S
+GEN_test_FCMPE_D_D
+GEN_test_FCMPE_S_S
+
+GEN_test_FCSEL_D_D_D_EQ
+GEN_test_FCSEL_D_D_D_NE
+GEN_test_FCSEL_S_S_S_EQ
+GEN_test_FCSEL_S_S_S_NE
GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29)
GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29)
@@ -989,52 +2214,85 @@
GEN_BINARY_TEST(fdiv, 4s, 4s, 4s)
GEN_BINARY_TEST(fdiv, 2s, 2s, 2s)
-// fmadd d,s
-// fnmadd d,s
-// fmsub d,s
-// fnmsub d,s
+GEN_FOURVEC_TEST(fmadd_d_d_d_d, "fmadd d2, d11, d29, d3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fmadd_s_s_s_s, "fmadd s2, s11, s29, s3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fnmadd_d_d_d_d, "fnmadd d2, d11, d29, d3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fnmadd_s_s_s_s, "fnmadd s2, s11, s29, s3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fmsub_d_d_d_d, "fmsub d2, d11, d29, d3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fmsub_s_s_s_s, "fmsub s2, s11, s29, s3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fnmsub_d_d_d_d, "fnmsub d2, d11, d29, d3", 2, 11, 29, 3)
+GEN_FOURVEC_TEST(fnmsub_s_s_s_s, "fnmsub s2, s11, s29, s3", 2, 11, 29, 3)
GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29)
GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29)
-// fmax d,s
-// fmin d,s
-// fmaxnm d,s ("max number")
-// fminnm d,s
-
-// fmax 2d,4s,2s
-// fmin 2d,4s,2s
-// fmaxnm 2d,4s,2s
-// fminnm 2d,4s,2s
-
-// fmaxnmp d_2d,s_2s ("max number pairwise")
-// fminnmp d_2d,s_2s
-
-// fmaxnmp 2d,4s,2s
-// fminnmp 2d,4s,2s
-
-// fmaxnmv s_4s (maxnum across vector)
-// fminnmv s_4s
-
-// fmaxp d_2d,s_2s (max of a pair)
-// fminp d_2d,s_2s (max of a pair)
-
-// fmaxp 2d,4s,2s (max pairwise)
-// fminp 2d,4s,2s
-
-// fmaxv s_4s (max across vector)
-// fminv s_4s
-
-// FIXME these need to be THREEVEC
-GEN_BINARY_TEST(fmla, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmla, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmla, 2s, 2s, 2s)
-GEN_BINARY_TEST(fmls, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmls, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmls, 2s, 2s, 2s)
-
-// fmla d_d_d[],s_s_s[] (by element)
-// fmls d_d_d[],s_s_s[] (by element)
+GEN_THREEVEC_TEST(fmax_d_d_d, "fmax d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmax_s_s_s, "fmax s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmin_d_d_d, "fmin d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmin_s_s_s, "fmin s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmaxnm_d_d_d, "fmaxnm d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmaxnm_s_s_s, "fmaxnm s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fminnm_d_d_d, "fminnm d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fminnm_s_s_s, "fminnm s2, s11, s29", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fmax_2d_2d_2d, "fmax v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmax_4s_4s_4s, "fmax v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmax_2s_2s_2s, "fmax v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmin_2d_2d_2d, "fmin v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmin_4s_4s_4s, "fmin v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmin_2s_2s_2s, "fmin v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxnm_2d_2d_2d, "fmaxnm v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxnm_4s_4s_4s, "fmaxnm v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxnm_2s_2s_2s, "fmaxnm v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnm_2d_2d_2d, "fminnm v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnm_4s_4s_4s, "fminnm v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnm_2s_2s_2s, "fminnm v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+GEN_TWOVEC_TEST(fmaxnmp_d_2d, "fmaxnmp d2, v23.2d", 2, 23)
+GEN_TWOVEC_TEST(fmaxnmp_s_2s, "fmaxnmp s2, v23.2s", 2, 23)
+GEN_TWOVEC_TEST(fminnmp_d_2d, "fminnmp d2, v23.2d", 2, 23)
+GEN_TWOVEC_TEST(fminnmp_s_2s, "fminnmp s2, v23.2s", 2, 23)
+
+GEN_THREEVEC_TEST(fmaxnmp_2d_2d_2d, "fmaxnmp v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxnmp_4s_4s_4s, "fmaxnmp v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxnmp_2s_2s_2s, "fmaxnmp v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnmp_2d_2d_2d, "fminnmp v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnmp_4s_4s_4s, "fminnmp v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminnmp_2s_2s_2s, "fminnmp v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+GEN_TWOVEC_TEST(fmaxnmv_s_4s, "fmaxnmv s2, v23.4s", 2, 23)
+GEN_TWOVEC_TEST(fminnmv_s_4s, "fminnmv s2, v23.4s", 2, 23)
+
+GEN_TWOVEC_TEST(fmaxp_d_2d, "fmaxp d2, v23.2d", 2, 23)
+GEN_TWOVEC_TEST(fmaxp_s_2s, "fmaxp s2, v23.2s", 2, 23)
+GEN_TWOVEC_TEST(fminp_d_2d, "fminp d2, v23.2d", 2, 23)
+GEN_TWOVEC_TEST(fminp_s_2s, "fminp s2, v23.2s", 2, 23)
+
+GEN_THREEVEC_TEST(fmaxp_2d_2d_2d, "fmaxp v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxp_4s_4s_4s, "fmaxp v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmaxp_2s_2s_2s, "fmaxp v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminp_2d_2d_2d, "fminp v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fminp_4s_4s_4s, "fminp v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fminp_2s_2s_2s, "fminp v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+GEN_TWOVEC_TEST(fmaxv_s_4s, "fmaxv s2, v23.4s", 2, 23)
+GEN_TWOVEC_TEST(fminv_s_4s, "fminv s2, v23.4s", 2, 23)
+
+GEN_THREEVEC_TEST(fmla_2d_2d_2d, "fmla v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmla_4s_4s_4s, "fmla v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmla_2s_2s_2s, "fmla v2.2s, v23.2s, v11.2s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmls_2d_2d_2d, "fmls v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(fmls_4s_4s_4s, "fmls v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(fmls_2s_2s_2s, "fmls v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+GEN_THREEVEC_TEST(fmla_d_d_d0, "fmla d2, d11, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_d_d_d1, "fmla d2, d11, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_s_s_s0, "fmla s2, s11, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_s_s_s3, "fmla s2, s11, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_d_d_d0, "fmls d2, d11, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_d_d_d1, "fmls d2, d11, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_s_s_s0, "fmls s2, s11, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_s_s_s3, "fmls s2, s11, v29.s[3]", 2, 11, 29)
GEN_THREEVEC_TEST(fmla_2d_2d_d0, "fmla v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
GEN_THREEVEC_TEST(fmla_2d_2d_d1, "fmla v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
@@ -1078,7 +2336,10 @@
GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23)
GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23)
-// fmul d_d_d[],s_s_s[]
+GEN_THREEVEC_TEST(fmul_d_d_d0, "fmul d2, d11, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_d_d_d1, "fmul d2, d11, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s_s_s0, "fmul s2, s11, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s_s_s3, "fmul s2, s11, v29.s[3]", 2, 11, 29)
GEN_THREEVEC_TEST(fmul_2d_2d_d0, "fmul v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
GEN_THREEVEC_TEST(fmul_2d_2d_d1, "fmul v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
@@ -1087,47 +2348,92 @@
GEN_THREEVEC_TEST(fmul_2s_2s_s0, "fmul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
GEN_THREEVEC_TEST(fmul_2s_2s_s3, "fmul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
-GEN_BINARY_TEST(fmul, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmul, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmul, 2s, 2s, 2s)
-
-// fmulx d_d_d[],s_s_s[]
-// fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
-
-// fmulx d,s
-// fmulx 2d,4s,2s
-
-// frecpe d,s (recip estimate)
-// frecpe 2d,4s,2s
-
-// frecps d,s (recip step)
-// frecps 2d,4s,2s
-
-// frecpx d,s (recip exponent)
-
-// frinta d,s
-// frinti d,s
-// frintm d,s
-// frintn d,s
-// frintp d,s
-// frintx d,s
-// frintz d,s
-
-// frinta 2d,4s,2s (round to integral, nearest away)
-// frinti 2d,4s,2s (round to integral, per FPCR)
-// frintm 2d,4s,2s (round to integral, minus inf)
-// frintn 2d,4s,2s (round to integral, nearest, to even)
-// frintp 2d,4s,2s (round to integral, plus inf)
-// frintx 2d,4s,2s (round to integral exact, per FPCR)
-// frintz 2d,4s,2s (round to integral, zero)
-
-// frsqrte d,s (est)
-// frsqrte 2d,4s,2s
-
-// frsqrts d,s (step)
-// frsqrts 2d,4s,2s
+GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2d_2d_2d, "fmul v2.2d, v11.2d, v29.2d", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_4s_4s_4s, "fmul v2.4s, v11.4s, v29.4s", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2s_2s_2s, "fmul v2.2s, v11.2s, v29.2s", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fmulx_d_d_d0, "fmulx d2, d11, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_d_d_d1, "fmulx d2, d11, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_s_s_s0, "fmulx s2, s11, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_s_s_s3, "fmulx s2, s11, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2d_2d_d0, "fmulx v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2d_2d_d1, "fmulx v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_4s_4s_s0, "fmulx v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_4s_4s_s3, "fmulx v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2s_2s_s0, "fmulx v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2s_2s_s3, "fmulx v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fmulx_d_d_d, "fmulx d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_s_s_s, "fmulx s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2d_2d_2d, "fmulx v2.2d, v11.2d, v29.2d", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_4s_4s_4s, "fmulx v2.4s, v11.4s, v29.4s", 2, 11, 29)
+GEN_THREEVEC_TEST(fmulx_2s_2s_2s, "fmulx v2.2s, v11.2s, v29.2s", 2, 11, 29)
+
+GEN_TWO...
[truncated message content] |
|
From: <sv...@va...> - 2014-11-23 17:50:31
|
Author: sewardj
Date: Sun Nov 23 17:50:19 2014
New Revision: 14763
Log:
Merge, from trunk, r14681
14681 arm64 Rearrange the test case generators [..]
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c Sun Nov 23 17:50:19 2014
@@ -90,7 +90,7 @@
/* ---------------------------------------------------------------- */
-/* -- Test functions -- */
+/* -- Test macros -- */
/* ---------------------------------------------------------------- */
/* Note this also sets the destination register to a known value (0x55..55)
@@ -292,6 +292,10 @@
}
+/* ---------------------------------------------------------------- */
+/* -- Test functions -- */
+/* ---------------------------------------------------------------- */
+
void test_UMINV ( void )
{
int i;
@@ -887,347 +891,314 @@
}
-GEN_BINARY_TEST(umax, 4s, 4s, 4s)
-GEN_BINARY_TEST(umax, 2s, 2s, 2s)
-GEN_BINARY_TEST(umax, 8h, 8h, 8h)
-GEN_BINARY_TEST(umax, 4h, 4h, 4h)
-GEN_BINARY_TEST(umax, 16b, 16b, 16b)
-GEN_BINARY_TEST(umax, 8b, 8b, 8b)
+/* ---------------------------------------------------------------- */
+/* -- Tests, in the same order that they appear in main() -- */
+/* ---------------------------------------------------------------- */
-GEN_BINARY_TEST(umin, 4s, 4s, 4s)
-GEN_BINARY_TEST(umin, 2s, 2s, 2s)
-GEN_BINARY_TEST(umin, 8h, 8h, 8h)
-GEN_BINARY_TEST(umin, 4h, 4h, 4h)
-GEN_BINARY_TEST(umin, 16b, 16b, 16b)
-GEN_BINARY_TEST(umin, 8b, 8b, 8b)
+// ======================== FP ========================
-GEN_BINARY_TEST(smax, 4s, 4s, 4s)
-GEN_BINARY_TEST(smax, 2s, 2s, 2s)
-GEN_BINARY_TEST(smax, 8h, 8h, 8h)
-GEN_BINARY_TEST(smax, 4h, 4h, 4h)
-GEN_BINARY_TEST(smax, 16b, 16b, 16b)
-GEN_BINARY_TEST(smax, 8b, 8b, 8b)
+GEN_TWOVEC_TEST(fabs_d_d, "fabs d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fabs_s_s, "fabs s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fabs_2d_2d, "fabs v22.2d, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fabs_4s_4s, "fabs v22.4s, v23.4s", 22, 23)
+GEN_TWOVEC_TEST(fabs_2s_2s, "fabs v22.2s, v23.2s", 22, 23)
+
+GEN_TWOVEC_TEST(fneg_d_d, "fneg d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fneg_s_s, "fneg s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fneg_2d_2d, "fneg v22.2d, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fneg_4s_4s, "fneg v22.4s, v23.4s", 22, 23)
+GEN_TWOVEC_TEST(fneg_2s_2s, "fneg v22.2s, v23.2s", 22, 23)
+
+GEN_TWOVEC_TEST(fsqrt_d_d, "fsqrt d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_s_s, "fsqrt s22, s23", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_2d_2d, "fsqrt v22.2d, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_4s_4s, "fsqrt v22.4s, v23.4s", 22, 23)
+GEN_TWOVEC_TEST(fsqrt_2s_2s, "fsqrt v22.2s, v23.2s", 22, 23)
-GEN_BINARY_TEST(smin, 4s, 4s, 4s)
-GEN_BINARY_TEST(smin, 2s, 2s, 2s)
-GEN_BINARY_TEST(smin, 8h, 8h, 8h)
-GEN_BINARY_TEST(smin, 4h, 4h, 4h)
-GEN_BINARY_TEST(smin, 16b, 16b, 16b)
-GEN_BINARY_TEST(smin, 8b, 8b, 8b)
+GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fsub_s_s_s, "fsub s2, s11, s29", 2, 11, 29)
-GEN_BINARY_TEST(add, 2d, 2d, 2d)
-GEN_BINARY_TEST(add, 4s, 4s, 4s)
-GEN_BINARY_TEST(add, 2s, 2s, 2s)
-GEN_BINARY_TEST(add, 8h, 8h, 8h)
-GEN_BINARY_TEST(add, 4h, 4h, 4h)
-GEN_BINARY_TEST(add, 16b, 16b, 16b)
-GEN_BINARY_TEST(add, 8b, 8b, 8b)
+GEN_BINARY_TEST(fadd, 2d, 2d, 2d)
+GEN_BINARY_TEST(fadd, 4s, 4s, 4s)
+GEN_BINARY_TEST(fadd, 2s, 2s, 2s)
+GEN_BINARY_TEST(fsub, 2d, 2d, 2d)
+GEN_BINARY_TEST(fsub, 4s, 4s, 4s)
+GEN_BINARY_TEST(fsub, 2s, 2s, 2s)
-GEN_BINARY_TEST(sub, 2d, 2d, 2d)
-GEN_BINARY_TEST(sub, 4s, 4s, 4s)
-GEN_BINARY_TEST(sub, 2s, 2s, 2s)
-GEN_BINARY_TEST(sub, 8h, 8h, 8h)
-GEN_BINARY_TEST(sub, 4h, 4h, 4h)
-GEN_BINARY_TEST(sub, 16b, 16b, 16b)
-GEN_BINARY_TEST(sub, 8b, 8b, 8b)
+GEN_THREEVEC_TEST(fabd_d_d_d, "fabd d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fabd_s_s_s, "fabd s2, s11, s29", 2, 11, 29)
+GEN_BINARY_TEST(fabd, 2d, 2d, 2d)
+GEN_BINARY_TEST(fabd, 4s, 4s, 4s)
+GEN_BINARY_TEST(fabd, 2s, 2s, 2s)
-GEN_BINARY_TEST(mul, 4s, 4s, 4s)
-GEN_BINARY_TEST(mul, 2s, 2s, 2s)
-GEN_BINARY_TEST(mul, 8h, 8h, 8h)
-GEN_BINARY_TEST(mul, 4h, 4h, 4h)
-GEN_BINARY_TEST(mul, 16b, 16b, 16b)
-GEN_BINARY_TEST(mul, 8b, 8b, 8b)
+GEN_TWOVEC_TEST(faddp_d_2d, "faddp d2, v23.2d", 2, 23)
+GEN_TWOVEC_TEST(faddp_s_2s, "faddp s2, v23.2s", 2, 23)
+GEN_THREEVEC_TEST(faddp_2d_2d_2d, "faddp v2.2d, v23.2d, v11.2d", 2, 23, 11)
+GEN_THREEVEC_TEST(faddp_4s_4s_4s, "faddp v2.4s, v23.4s, v11.4s", 2, 23, 11)
+GEN_THREEVEC_TEST(faddp_2s_2s_2s, "faddp v2.2s, v23.2s, v11.2s", 2, 23, 11)
+
+// fccmp d,s
+// fccmpe d,s
+
+// fcmeq d,s
+// fcmge d,s
+// fcmgt d,s
+// facgt d,s (floating abs compare GE)
+// facge d,s (floating abs compare GE)
-GEN_BINARY_TEST(mla, 4s, 4s, 4s)
-GEN_BINARY_TEST(mla, 2s, 2s, 2s)
-GEN_BINARY_TEST(mla, 8h, 8h, 8h)
-GEN_BINARY_TEST(mla, 4h, 4h, 4h)
-GEN_BINARY_TEST(mla, 16b, 16b, 16b)
-GEN_BINARY_TEST(mla, 8b, 8b, 8b)
+GEN_BINARY_TEST(fcmeq, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmeq, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmeq, 2s, 2s, 2s)
+GEN_BINARY_TEST(fcmge, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmge, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmge, 2s, 2s, 2s)
+GEN_BINARY_TEST(fcmgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(fcmgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(fcmgt, 2s, 2s, 2s)
+GEN_BINARY_TEST(facge, 2d, 2d, 2d)
+GEN_BINARY_TEST(facge, 4s, 4s, 4s)
+GEN_BINARY_TEST(facge, 2s, 2s, 2s)
+GEN_BINARY_TEST(facgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(facgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(facgt, 2s, 2s, 2s)
-GEN_BINARY_TEST(mls, 4s, 4s, 4s)
-GEN_BINARY_TEST(mls, 2s, 2s, 2s)
-GEN_BINARY_TEST(mls, 8h, 8h, 8h)
-GEN_BINARY_TEST(mls, 4h, 4h, 4h)
-GEN_BINARY_TEST(mls, 16b, 16b, 16b)
-GEN_BINARY_TEST(mls, 8b, 8b, 8b)
+// fcmeq_z d,s
+// fcmge_z d,s
+// fcmgt_z d,s
+// fcmle_z d,s
+// fcmlt_z d,s
+
+// fcmeq_z 2d,4s,2s
+// fcmge_z 2d,4s,2s
+// fcmgt_z 2d,4s,2s
+// fcmle_z 2d,4s,2s
+// fcmlt_z 2d,4s,2s
+
+// fcmp_z d,s
+// fcmpe_z d,s
+// fcmp d,s (floating point quiet, set flags)
+// fcmpe d,s (floating point signaling, set flags)
-GEN_BINARY_TEST(and, 16b, 16b, 16b)
-GEN_BINARY_TEST(and, 8b, 8b, 8b)
+// fcsel d,s (fp cond select)
-GEN_BINARY_TEST(bic, 16b, 16b, 16b)
-GEN_BINARY_TEST(bic, 8b, 8b, 8b)
+GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29)
+GEN_BINARY_TEST(fdiv, 2d, 2d, 2d)
+GEN_BINARY_TEST(fdiv, 4s, 4s, 4s)
+GEN_BINARY_TEST(fdiv, 2s, 2s, 2s)
-GEN_BINARY_TEST(orr, 16b, 16b, 16b)
-GEN_BINARY_TEST(orr, 8b, 8b, 8b)
+// fmadd d,s
+// fnmadd d,s
+// fmsub d,s
+// fnmsub d,s
-GEN_BINARY_TEST(orn, 16b, 16b, 16b)
-GEN_BINARY_TEST(orn, 8b, 8b, 8b)
+GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29)
-GEN_BINARY_TEST(eor, 16b, 16b, 16b)
-GEN_BINARY_TEST(eor, 8b, 8b, 8b)
+// fmax d,s
+// fmin d,s
+// fmaxnm d,s ("max number")
+// fminnm d,s
-GEN_BINARY_TEST(bsl, 16b, 16b, 16b)
-GEN_BINARY_TEST(bsl, 8b, 8b, 8b)
+// fmax 2d,4s,2s
+// fmin 2d,4s,2s
+// fmaxnm 2d,4s,2s
+// fminnm 2d,4s,2s
-GEN_BINARY_TEST(bit, 16b, 16b, 16b)
-GEN_BINARY_TEST(bit, 8b, 8b, 8b)
+// fmaxnmp d_2d,s_2s ("max number pairwise")
+// fminnmp d_2d,s_2s
-GEN_BINARY_TEST(bif, 16b, 16b, 16b)
-GEN_BINARY_TEST(bif, 8b, 8b, 8b)
+// fmaxnmp 2d,4s,2s
+// fminnmp 2d,4s,2s
-GEN_BINARY_TEST(cmeq, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmeq, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmeq, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmeq, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmeq, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmeq, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmeq, 8b, 8b, 8b)
+// fmaxnmv s_4s (maxnum across vector)
+// fminnmv s_4s
-GEN_BINARY_TEST(cmtst, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmtst, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmtst, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmtst, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmtst, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmtst, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmtst, 8b, 8b, 8b)
+// fmaxp d_2d,s_2s (max of a pair)
+// fminp d_2d,s_2s (max of a pair)
-GEN_BINARY_TEST(cmhi, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmhi, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmhi, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmhi, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmhi, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmhi, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmhi, 8b, 8b, 8b)
+// fmaxp 2d,4s,2s (max pairwise)
+// fminp 2d,4s,2s
-GEN_BINARY_TEST(cmgt, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmgt, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmgt, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmgt, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmgt, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmgt, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmgt, 8b, 8b, 8b)
+// fmaxv s_4s (max across vector)
+// fminv s_4s
-GEN_BINARY_TEST(cmhs, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmhs, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmhs, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmhs, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmhs, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmhs, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmhs, 8b, 8b, 8b)
+// FIXME these need to be THREEVEC
+GEN_BINARY_TEST(fmla, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmla, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmla, 2s, 2s, 2s)
+GEN_BINARY_TEST(fmls, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmls, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmls, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmge, 2d, 2d, 2d)
-GEN_BINARY_TEST(cmge, 4s, 4s, 4s)
-GEN_BINARY_TEST(cmge, 2s, 2s, 2s)
-GEN_BINARY_TEST(cmge, 8h, 8h, 8h)
-GEN_BINARY_TEST(cmge, 4h, 4h, 4h)
-GEN_BINARY_TEST(cmge, 16b, 16b, 16b)
-GEN_BINARY_TEST(cmge, 8b, 8b, 8b)
+// fmla d_d_d[],s_s_s[] (by element)
+// fmls d_d_d[],s_s_s[] (by element)
-GEN_SHIFT_TEST(ushr, 2d, 2d, 1)
-GEN_SHIFT_TEST(ushr, 2d, 2d, 13)
-GEN_SHIFT_TEST(ushr, 2d, 2d, 64)
-GEN_SHIFT_TEST(sshr, 2d, 2d, 1)
-GEN_SHIFT_TEST(sshr, 2d, 2d, 13)
-GEN_SHIFT_TEST(sshr, 2d, 2d, 64)
-GEN_SHIFT_TEST(shl, 2d, 2d, 0)
-GEN_SHIFT_TEST(shl, 2d, 2d, 13)
-GEN_SHIFT_TEST(shl, 2d, 2d, 63)
+GEN_THREEVEC_TEST(fmla_2d_2d_d0, "fmla v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2d_2d_d1, "fmla v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_4s_4s_s0, "fmla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_4s_4s_s3, "fmla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2s_2s_s0, "fmla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2s_2s_s3, "fmla v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
-GEN_SHIFT_TEST(ushr, 4s, 4s, 1)
-GEN_SHIFT_TEST(ushr, 4s, 4s, 13)
-GEN_SHIFT_TEST(ushr, 4s, 4s, 32)
-GEN_SHIFT_TEST(sshr, 4s, 4s, 1)
-GEN_SHIFT_TEST(sshr, 4s, 4s, 13)
-GEN_SHIFT_TEST(sshr, 4s, 4s, 32)
-GEN_SHIFT_TEST(shl, 4s, 4s, 0)
-GEN_SHIFT_TEST(shl, 4s, 4s, 13)
-GEN_SHIFT_TEST(shl, 4s, 4s, 31)
+GEN_THREEVEC_TEST(fmls_2d_2d_d0, "fmls v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2d_2d_d1, "fmls v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_4s_4s_s0, "fmls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_4s_4s_s3, "fmls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2s_2s_s0, "fmls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2s_2s_s3, "fmls v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
-GEN_SHIFT_TEST(ushr, 2s, 2s, 1)
-GEN_SHIFT_TEST(ushr, 2s, 2s, 13)
-GEN_SHIFT_TEST(ushr, 2s, 2s, 32)
-GEN_SHIFT_TEST(sshr, 2s, 2s, 1)
-GEN_SHIFT_TEST(sshr, 2s, 2s, 13)
-GEN_SHIFT_TEST(sshr, 2s, 2s, 32)
-GEN_SHIFT_TEST(shl, 2s, 2s, 0)
-GEN_SHIFT_TEST(shl, 2s, 2s, 13)
-GEN_SHIFT_TEST(shl, 2s, 2s, 31)
+GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_01, "fmov v22.4s, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_02, "fmov v22.4s, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_4s_imm_03, "fmov v22.4s, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_01, "fmov v22.2s, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_02, "fmov v22.2s, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_2s_imm_03, "fmov v22.2s, #1.0", 22, 23)
-GEN_SHIFT_TEST(ushr, 8h, 8h, 1)
-GEN_SHIFT_TEST(ushr, 8h, 8h, 13)
-GEN_SHIFT_TEST(ushr, 8h, 8h, 16)
-GEN_SHIFT_TEST(sshr, 8h, 8h, 1)
-GEN_SHIFT_TEST(sshr, 8h, 8h, 13)
-GEN_SHIFT_TEST(sshr, 8h, 8h, 16)
-GEN_SHIFT_TEST(shl, 8h, 8h, 0)
-GEN_SHIFT_TEST(shl, 8h, 8h, 13)
-GEN_SHIFT_TEST(shl, 8h, 8h, 15)
+GEN_TWOVEC_TEST(fmov_d_d, "fmov d22, d23", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_s, "fmov s22, s23", 22, 23)
-GEN_SHIFT_TEST(ushr, 4h, 4h, 1)
-GEN_SHIFT_TEST(ushr, 4h, 4h, 13)
-GEN_SHIFT_TEST(ushr, 4h, 4h, 16)
-GEN_SHIFT_TEST(sshr, 4h, 4h, 1)
-GEN_SHIFT_TEST(sshr, 4h, 4h, 13)
-GEN_SHIFT_TEST(sshr, 4h, 4h, 16)
-GEN_SHIFT_TEST(shl, 4h, 4h, 0)
-GEN_SHIFT_TEST(shl, 4h, 4h, 13)
-GEN_SHIFT_TEST(shl, 4h, 4h, 15)
+GEN_ONEINT_ONEVEC_TEST(fmov_s_w, "fmov s7, w15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_d_x, "fmov d7, x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_d1_x, "fmov v7.d[1], x15", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_w_s, "fmov w15, s7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7)
+GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7)
-GEN_SHIFT_TEST(ushr, 16b, 16b, 1)
-GEN_SHIFT_TEST(ushr, 16b, 16b, 8)
-GEN_SHIFT_TEST(sshr, 16b, 16b, 1)
-GEN_SHIFT_TEST(sshr, 16b, 16b, 8)
-GEN_SHIFT_TEST(shl, 16b, 16b, 0)
-GEN_SHIFT_TEST(shl, 16b, 16b, 7)
+/* overkill -- don't need two vecs, only one */
+GEN_TWOVEC_TEST(fmov_d_imm_01, "fmov d22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_d_imm_02, "fmov d22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_d_imm_03, "fmov d22, #1.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_01, "fmov s22, #0.125", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23)
+GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23)
-GEN_SHIFT_TEST(ushr, 8b, 8b, 1)
-GEN_SHIFT_TEST(ushr, 8b, 8b, 8)
-GEN_SHIFT_TEST(sshr, 8b, 8b, 1)
-GEN_SHIFT_TEST(sshr, 8b, 8b, 8)
-GEN_SHIFT_TEST(shl, 8b, 8b, 0)
-GEN_SHIFT_TEST(shl, 8b, 8b, 7)
+// fmul d_d_d[],s_s_s[]
-GEN_SHIFT_TEST(ushll, 2d, 2s, 0)
-GEN_SHIFT_TEST(ushll, 2d, 2s, 15)
-GEN_SHIFT_TEST(ushll, 2d, 2s, 31)
-GEN_SHIFT_TEST(ushll2, 2d, 4s, 0)
-GEN_SHIFT_TEST(ushll2, 2d, 4s, 15)
-GEN_SHIFT_TEST(ushll2, 2d, 4s, 31)
-GEN_SHIFT_TEST(ushll, 4s, 4h, 0)
-GEN_SHIFT_TEST(ushll, 4s, 4h, 7)
-GEN_SHIFT_TEST(ushll, 4s, 4h, 15)
-GEN_SHIFT_TEST(ushll2, 4s, 8h, 0)
-GEN_SHIFT_TEST(ushll2, 4s, 8h, 7)
-GEN_SHIFT_TEST(ushll2, 4s, 8h, 15)
-GEN_SHIFT_TEST(ushll, 8h, 8b, 0)
-GEN_SHIFT_TEST(ushll, 8h, 8b, 3)
-GEN_SHIFT_TEST(ushll, 8h, 8b, 7)
-GEN_SHIFT_TEST(ushll2, 8h, 16b, 0)
-GEN_SHIFT_TEST(ushll2, 8h, 16b, 3)
-GEN_SHIFT_TEST(ushll2, 8h, 16b, 7)
+GEN_THREEVEC_TEST(fmul_2d_2d_d0, "fmul v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2d_2d_d1, "fmul v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_4s_4s_s0, "fmul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_4s_4s_s3, "fmul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2s_2s_s0, "fmul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_2s_2s_s3, "fmul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
-GEN_SHIFT_TEST(sshll, 2d, 2s, 0)
-GEN_SHIFT_TEST(sshll, 2d, 2s, 15)
-GEN_SHIFT_TEST(sshll, 2d, 2s, 31)
-GEN_SHIFT_TEST(sshll2, 2d, 4s, 0)
-GEN_SHIFT_TEST(sshll2, 2d, 4s, 15)
-GEN_SHIFT_TEST(sshll2, 2d, 4s, 31)
-GEN_SHIFT_TEST(sshll, 4s, 4h, 0)
-GEN_SHIFT_TEST(sshll, 4s, 4h, 7)
-GEN_SHIFT_TEST(sshll, 4s, 4h, 15)
-GEN_SHIFT_TEST(sshll2, 4s, 8h, 0)
-GEN_SHIFT_TEST(sshll2, 4s, 8h, 7)
-GEN_SHIFT_TEST(sshll2, 4s, 8h, 15)
-GEN_SHIFT_TEST(sshll, 8h, 8b, 0)
-GEN_SHIFT_TEST(sshll, 8h, 8b, 3)
-GEN_SHIFT_TEST(sshll, 8h, 8b, 7)
-GEN_SHIFT_TEST(sshll2, 8h, 16b, 0)
-GEN_SHIFT_TEST(sshll2, 8h, 16b, 3)
-GEN_SHIFT_TEST(sshll2, 8h, 16b, 7)
+GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
+GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
+GEN_BINARY_TEST(fmul, 2d, 2d, 2d)
+GEN_BINARY_TEST(fmul, 4s, 4s, 4s)
+GEN_BINARY_TEST(fmul, 2s, 2s, 2s)
+// fmulx d_d_d[],s_s_s[]
+// fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
-GEN_UNARY_TEST(xtn, 2s, 2d)
-GEN_UNARY_TEST(xtn2, 4s, 2d)
-GEN_UNARY_TEST(xtn, 4h, 4s)
-GEN_UNARY_TEST(xtn2, 8h, 4s)
-GEN_UNARY_TEST(xtn, 8b, 8h)
-GEN_UNARY_TEST(xtn2, 16b, 8h)
+// fmulx d,s
+// fmulx 2d,4s,2s
-GEN_ONEINT_ONEVEC_TEST(umov_x_d0, "umov x9, v10.d[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_x_d1, "umov x9, v10.d[1]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_s0, "umov w9, v10.s[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_s3, "umov w9, v10.s[3]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_h0, "umov w9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_h7, "umov w9, v10.h[7]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_b0, "umov w9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(umov_w_b15, "umov w9, v10.b[15]", 9, 10)
+// frecpe d,s (recip estimate)
+// frecpe 2d,4s,2s
-GEN_ONEINT_ONEVEC_TEST(smov_x_s0, "smov x9, v10.s[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_x_s3, "smov x9, v10.s[3]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_x_h0, "smov x9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_x_h7, "smov x9, v10.h[7]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_w_h0, "smov w9, v10.h[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_w_h7, "smov w9, v10.h[7]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_x_b0, "smov x9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_x_b15, "smov x9, v10.b[15]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_w_b0, "smov w9, v10.b[0]", 9, 10)
-GEN_ONEINT_ONEVEC_TEST(smov_w_b15, "smov w9, v10.b[15]", 9, 10)
+// frecps d,s (recip step)
+// frecps 2d,4s,2s
-GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23)
-GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23)
+// frecpx d,s (recip exponent)
-GEN_UNARY_TEST(neg, 2d, 2d)
-GEN_UNARY_TEST(neg, 4s, 4s)
-GEN_UNARY_TEST(neg, 2s, 2s)
-GEN_UNARY_TEST(neg, 8h, 8h)
-GEN_UNARY_TEST(neg, 4h, 4h)
-GEN_UNARY_TEST(neg, 16b, 16b)
-GEN_UNARY_TEST(neg, 8b, 8b)
+// frinta d,s
+// frinti d,s
+// frintm d,s
+// frintn d,s
+// frintp d,s
+// frintx d,s
+// frintz d,s
-GEN_BINARY_TEST(fadd, 2d, 2d, 2d)
-GEN_BINARY_TEST(fadd, 4s, 4s, 4s)
-GEN_BINARY_TEST(fadd, 2s, 2s, 2s)
-GEN_BINARY_TEST(fsub, 2d, 2d, 2d)
-GEN_BINARY_TEST(fsub, 4s, 4s, 4s)
-GEN_BINARY_TEST(fsub, 2s, 2s, 2s)
-GEN_BINARY_TEST(fmul, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmul, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmul, 2s, 2s, 2s)
-GEN_BINARY_TEST(fdiv, 2d, 2d, 2d)
-GEN_BINARY_TEST(fdiv, 4s, 4s, 4s)
-GEN_BINARY_TEST(fdiv, 2s, 2s, 2s)
-GEN_BINARY_TEST(fmla, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmla, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmla, 2s, 2s, 2s)
-GEN_BINARY_TEST(fmls, 2d, 2d, 2d)
-GEN_BINARY_TEST(fmls, 4s, 4s, 4s)
-GEN_BINARY_TEST(fmls, 2s, 2s, 2s)
-GEN_BINARY_TEST(fabd, 2d, 2d, 2d)
-GEN_BINARY_TEST(fabd, 4s, 4s, 4s)
-GEN_BINARY_TEST(fabd, 2s, 2s, 2s)
+// frinta 2d,4s,2s (round to integral, nearest away)
+// frinti 2d,4s,2s (round to integral, per FPCR)
+// frintm 2d,4s,2s (round to integral, minus inf)
+// frintn 2d,4s,2s (round to integral, nearest, to even)
+// frintp 2d,4s,2s (round to integral, plus inf)
+// frintx 2d,4s,2s (round to integral exact, per FPCR)
+// frintz 2d,4s,2s (round to integral, zero)
-GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23)
-GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23)
+// frsqrte d,s (est)
+// frsqrte 2d,4s,2s
-/* overkill -- don't need two vecs, only one */
-GEN_TWOVEC_TEST(fmov_d_imm_01, "fmov d22, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_d_imm_02, "fmov d22, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_d_imm_03, "fmov d22, #1.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_s_imm_01, "fmov s22, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23)
+// frsqrts d,s (step)
+// frsqrts 2d,4s,2s
-GEN_ONEINT_ONEVEC_TEST(fmov_s_w, "fmov s7, w15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_d_x, "fmov d7, x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_d1_x, "fmov v7.d[1], x15", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_w_s, "fmov w15, s7", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7)
-GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7)
+// ======================== CONV ========================
-GEN_THREEVEC_TEST(fmla_2d_2d_d0, "fmla v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmla_2d_2d_d1, "fmla v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmla_4s_4s_s0, "fmla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmla_4s_4s_s3, "fmla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmla_2s_2s_s0, "fmla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmla_2s_2s_s3, "fmla v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+// fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
-GEN_THREEVEC_TEST(fmls_2d_2d_d0, "fmls v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmls_2d_2d_d1, "fmls v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmls_4s_4s_s0, "fmls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmls_4s_4s_s3, "fmls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmls_2s_2s_s0, "fmls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmls_2s_2s_s3, "fmls v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+// fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
-GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_4s_imm_01, "fmov v22.4s, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_4s_imm_02, "fmov v22.4s, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_4s_imm_03, "fmov v22.4s, #1.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_2s_imm_01, "fmov v22.2s, #0.125", 22, 23)
-GEN_TWOVEC_TEST(fmov_2s_imm_02, "fmov v22.2s, #-4.0", 22, 23)
-GEN_TWOVEC_TEST(fmov_2s_imm_03, "fmov v22.2s, #1.0", 22, 23)
+// fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
+// INCOMPLETE
+GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23)
+GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23)
+
+// fcvtas d,s (fcvt to signed int, nearest, ties away)
+// fcvtau d,s (fcvt to unsigned int, nearest, ties away)
+// fcvtas 2d,4s,2s
+// fcvtau 2d,4s,2s
+// fcvtas w_s,x_s,w_d,x_d
+// fcvtau w_s,x_s,w_d,x_d
+
+// fcvtms d,s (fcvt to signed int, minus inf)
+// fcvtmu d,s (fcvt to unsigned int, minus inf)
+// fcvtms 2d,4s,2s
+// fcvtmu 2d,4s,2s
+// fcvtms w_s,x_s,w_d,x_d
+// fcvtmu w_s,x_s,w_d,x_d
+
+// fcvtns d,s (fcvt to signed int, nearest)
+// fcvtnu d,s (fcvt to unsigned int, nearest)
+// fcvtns 2d,4s,2s
+// fcvtnu 2d,4s,2s
+// fcvtns w_s,x_s,w_d,x_d
+// fcvtnu w_s,x_s,w_d,x_d
+
+// fcvtps d,s (fcvt to signed int, plus inf)
+// fcvtpu d,s (fcvt to unsigned int, plus inf)
+// fcvtps 2d,4s,2s
+// fcvtpu 2d,4s,2s
+// fcvtps w_s,x_s,w_d,x_d
+// fcvtpu w_s,x_s,w_d,x_d
+
+// fcvtzs d,s (fcvt to signed integer, to zero)
+// fcvtzu d,s (fcvt to unsigned integer, to zero)
+// fcvtzs 2d,4s,2s
+// fcvtzu 2d,4s,2s
+// fcvtzs w_s,x_s,w_d,x_d
+// fcvtzu w_s,x_s,w_d,x_d
+
+// fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits)
+// fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
+// fcvtzs 2d,4s,2s
+// fcvtzu 2d,4s,2s
+// fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
+// fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
+
+// fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
+// fcvtxn 2s_2d,4s_2d
+
+// scvtf d,s _#fbits
+// ucvtf d,s _#fbits
+
+// scvtf 2d,4s,2s _#fbits
+// ucvtf 2d,4s,2s _#fbits
+
+// scvtf d,s
+// ucvtf d,s
+
+// scvtf 2d,4s,2s
+// ucvtf 2d,4s,2s
+
+// scvtf s_w, d_w, s_x, d_x, _#fbits
+// ucvtf s_w, d_w, s_x, d_x, _#fbits
GEN_ONEINT_ONEVEC_TEST(scvtf_s_w, "scvtf s7, w15", 15, 7)
GEN_ONEINT_ONEVEC_TEST(scvtf_d_w, "scvtf d7, w15", 15, 7)
@@ -1238,172 +1209,7 @@
GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x, "ucvtf s7, x15", 15, 7)
GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x, "ucvtf d7, x15", 15, 7)
-GEN_THREEVEC_TEST(fmul_2d_2d_d0, "fmul v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_2d_2d_d1, "fmul v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_4s_4s_s0, "fmul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_4s_4s_s3, "fmul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_2s_2s_s0, "fmul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_2s_2s_s3, "fmul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
-
-GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fsub_s_s_s, "fsub s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29)
-GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29)
-
-GEN_THREEVEC_TEST(fabd_d_d_d, "fabd d2, d11, d29", 2, 11, 29)
-GEN_THREEVEC_TEST(fabd_s_s_s, "fabd s2, s11, s29", 2, 11, 29)
-
-GEN_TWOVEC_TEST(fmov_d_d, "fmov d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fmov_s_s, "fmov s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fabs_d_d, "fabs d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fabs_s_s, "fabs s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fneg_d_d, "fneg d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fneg_s_s, "fneg s22, s23", 22, 23)
-GEN_TWOVEC_TEST(fsqrt_d_d, "fsqrt d22, d23", 22, 23)
-GEN_TWOVEC_TEST(fsqrt_s_s, "fsqrt s22, s23", 22, 23)
-
-GEN_UNARY_TEST(fneg, 2d, 2d)
-GEN_UNARY_TEST(fneg, 4s, 4s)
-GEN_UNARY_TEST(fneg, 2s, 2s)
-GEN_UNARY_TEST(fabs, 2d, 2d)
-GEN_UNARY_TEST(fabs, 4s, 4s)
-GEN_UNARY_TEST(fabs, 2s, 2s)
-
-GEN_BINARY_TEST(fcmeq, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmeq, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmeq, 2s, 2s, 2s)
-GEN_BINARY_TEST(fcmge, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmge, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmge, 2s, 2s, 2s)
-GEN_BINARY_TEST(fcmgt, 2d, 2d, 2d)
-GEN_BINARY_TEST(fcmgt, 4s, 4s, 4s)
-GEN_BINARY_TEST(fcmgt, 2s, 2s, 2s)
-GEN_BINARY_TEST(facge, 2d, 2d, 2d)
-GEN_BINARY_TEST(facge, 4s, 4s, 4s)
-GEN_BINARY_TEST(facge, 2s, 2s, 2s)
-GEN_BINARY_TEST(facgt, 2d, 2d, 2d)
-GEN_BINARY_TEST(facgt, 4s, 4s, 4s)
-GEN_BINARY_TEST(facgt, 2s, 2s, 2s)
-
-// Uses v15 as the first table entry
-GEN_THREEVEC_TEST(
- tbl_16b_1reg, "tbl v21.16b, {v15.16b}, v23.16b", 21, 15, 23)
-// and v15 ^ v21 as the second table entry
-GEN_THREEVEC_TEST(
- tbl_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
- "tbl v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23)
-// and v15 ^ v23 as the third table entry
-GEN_THREEVEC_TEST(
- tbl_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "tbl v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b",
- 21, 15, 23)
-// and v21 ^ v23 as the fourth table entry
-GEN_THREEVEC_TEST(
- tbl_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "eor v18.16b, v21.16b, v23.16b ; "
- "tbl v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b",
- 21, 15, 23)
-
-// Same register scheme for tbl .8b, tbx .16b, tbx.8b
-GEN_THREEVEC_TEST(
- tbl_8b_1reg, "tbl v21.8b, {v15.16b}, v23.8b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbl_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
- "tbl v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbl_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "tbl v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b",
- 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbl_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "eor v18.16b, v21.16b, v23.16b ; "
- "tbl v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b",
- 21, 15, 23)
-
-GEN_THREEVEC_TEST(
- tbx_16b_1reg, "tbx v21.16b, {v15.16b}, v23.16b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
- "tbx v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "tbx v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b",
- 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "eor v18.16b, v21.16b, v23.16b ; "
- "tbx v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b",
- 21, 15, 23)
-
-// Same register scheme for tbx .8b, tbx .16b, tbx.8b
-GEN_THREEVEC_TEST(
- tbx_8b_1reg, "tbx v21.8b, {v15.16b}, v23.8b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
- "tbx v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "tbx v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b",
- 21, 15, 23)
-GEN_THREEVEC_TEST(
- tbx_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
- "eor v17.16b, v15.16b, v23.16b ; "
- "eor v18.16b, v21.16b, v23.16b ; "
- "tbx v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b",
- 21, 15, 23)
-
-GEN_TWOVEC_TEST(cmge_zero_2d_2d, "cmge v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_4s_4s, "cmge v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_2s_2s, "cmge v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_8h_8h, "cmge v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_4h_4h, "cmge v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_16b_16b, "cmge v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmge_zero_8b_8b, "cmge v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmgt_zero_2d_2d, "cmgt v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_4s_4s, "cmgt v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_2s_2s, "cmgt v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_8h_8h, "cmgt v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_4h_4h, "cmgt v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_16b_16b, "cmgt v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmgt_zero_8b_8b, "cmgt v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmle_zero_2d_2d, "cmle v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_4s_4s, "cmle v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_2s_2s, "cmle v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_8h_8h, "cmle v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_4h_4h, "cmle v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_16b_16b, "cmle v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmle_zero_8b_8b, "cmle v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmeq_zero_2d_2d, "cmeq v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_4s_4s, "cmeq v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_2s_2s, "cmeq v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_8h_8h, "cmeq v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_4h_4h, "cmeq v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_16b_16b, "cmeq v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmeq_zero_8b_8b, "cmeq v5.8b, v22.8b, #0", 5, 22)
-
-GEN_TWOVEC_TEST(cmlt_zero_2d_2d, "cmlt v5.2d, v22.2d, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_4s_4s, "cmlt v5.4s, v22.4s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_2s_2s, "cmlt v5.2s, v22.2s, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_8h_8h, "cmlt v5.8h, v22.8h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_4h_4h, "cmlt v5.4h, v22.4h, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_16b_16b, "cmlt v5.16b, v22.16b, #0", 5, 22)
-GEN_TWOVEC_TEST(cmlt_zero_8b_8b, "cmlt v5.8b, v22.8b, #0", 5, 22)
+// ======================== INT ========================
GEN_TWOVEC_TEST(abs_d_d, "abs d22, d23", 22, 23)
GEN_TWOVEC_TEST(neg_d_d, "neg d22, d23", 22, 23)
@@ -1415,6 +1221,31 @@
GEN_UNARY_TEST(abs, 4h, 4h)
GEN_UNARY_TEST(abs, 16b, 16b)
GEN_UNARY_TEST(abs, 8b, 8b)
+GEN_UNARY_TEST(neg, 2d, 2d)
+GEN_UNARY_TEST(neg, 4s, 4s)
+GEN_UNARY_TEST(neg, 2s, 2s)
+GEN_UNARY_TEST(neg, 8h, 8h)
+GEN_UNARY_TEST(neg, 4h, 4h)
+GEN_UNARY_TEST(neg, 16b, 16b)
+GEN_UNARY_TEST(neg, 8b, 8b)
+
+GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23)
+GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23)
+
+GEN_BINARY_TEST(add, 2d, 2d, 2d)
+GEN_BINARY_TEST(add, 4s, 4s, 4s)
+GEN_BINARY_TEST(add, 2s, 2s, 2s)
+GEN_BINARY_TEST(add, 8h, 8h, 8h)
+GEN_BINARY_TEST(add, 4h, 4h, 4h)
+GEN_BINARY_TEST(add, 16b, 16b, 16b)
+GEN_BINARY_TEST(add, 8b, 8b, 8b)
+GEN_BINARY_TEST(sub, 2d, 2d, 2d)
+GEN_BINARY_TEST(sub, 4s, 4s, 4s)
+GEN_BINARY_TEST(sub, 2s, 2s, 2s)
+GEN_BINARY_TEST(sub, 8h, 8h, 8h)
+GEN_BINARY_TEST(sub, 4h, 4h, 4h)
+GEN_BINARY_TEST(sub, 16b, 16b, 16b)
+GEN_BINARY_TEST(sub, 8b, 8b, 8b)
GEN_BINARY_TEST(addhn, 2s, 2d, 2d)
GEN_BINARY_TEST(addhn2, 4s, 2d, 2d)
@@ -1457,6 +1288,15 @@
GEN_TWOVEC_TEST(addv_b_16b, "addv b22, v23.16b", 22, 23)
GEN_TWOVEC_TEST(addv_b_8b, "addv b22, v23.8b", 22, 23)
+GEN_BINARY_TEST(and, 16b, 16b, 16b)
+GEN_BINARY_TEST(and, 8b, 8b, 8b)
+GEN_BINARY_TEST(bic, 16b, 16b, 16b)
+GEN_BINARY_TEST(bic, 8b, 8b, 8b)
+GEN_BINARY_TEST(orr, 16b, 16b, 16b)
+GEN_BINARY_TEST(orr, 8b, 8b, 8b)
+GEN_BINARY_TEST(orn, 16b, 16b, 16b)
+GEN_BINARY_TEST(orn, 8b, 8b, 8b)
+
/* overkill -- don't need two vecs, only one */
GEN_TWOVEC_TEST(orr_8h_0x5A_lsl0, "orr v22.8h, #0x5A, LSL #0", 22, 23)
GEN_TWOVEC_TEST(orr_8h_0xA5_lsl8, "orr v22.8h, #0xA5, LSL #8", 22, 23)
@@ -1483,13 +1323,21 @@
GEN_TWOVEC_TEST(bic_2s_0x49_lsl16, "bic v22.2s, #0x49, LSL #16", 22, 23)
GEN_TWOVEC_TEST(bic_2s_0x3D_lsl24, "bic v22.2s, #0x3D, LSL #24", 22, 23)
+GEN_BINARY_TEST(bif, 16b, 16b, 16b)
+GEN_BINARY_TEST(bif, 8b, 8b, 8b)
+GEN_BINARY_TEST(bit, 16b, 16b, 16b)
+GEN_BINARY_TEST(bit, 8b, 8b, 8b)
+GEN_BINARY_TEST(bsl, 16b, 16b, 16b)
+GEN_BINARY_TEST(bsl, 8b, 8b, 8b)
+GEN_BINARY_TEST(eor, 16b, 16b, 16b)
+GEN_BINARY_TEST(eor, 8b, 8b, 8b)
+
GEN_UNARY_TEST(cls, 4s, 4s)
GEN_UNARY_TEST(cls, 2s, 2s)
GEN_UNARY_TEST(cls, 8h, 8h)
GEN_UNARY_TEST(cls, 4h, 4h)
GEN_UNARY_TEST(cls, 16b, 16b)
GEN_UNARY_TEST(cls, 8b, 8b)
-
GEN_UNARY_TEST(clz, 4s, 4s)
GEN_UNARY_TEST(clz, 2s, 2s)
GEN_UNARY_TEST(clz, 8h, 8h)
@@ -1504,12 +1352,91 @@
GEN_THREEVEC_TEST(cmhs_d_d_d, "cmhs d2, d11, d29", 2, 11, 29)
GEN_THREEVEC_TEST(cmtst_d_d_d, "cmtst d2, d11, d29", 2, 11, 29)
+GEN_BINARY_TEST(cmeq, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmeq, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmeq, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmeq, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmeq, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmeq, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmeq, 8b, 8b, 8b)
+GEN_BINARY_TEST(cmge, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmge, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmge, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmge, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmge, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmge, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmge, 8b, 8b, 8b)
+GEN_BINARY_TEST(cmgt, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmgt, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmgt, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmgt, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmgt, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmgt, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmgt, 8b, 8b, 8b)
+GEN_BINARY_TEST(cmhi, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmhi, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmhi, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmhi, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmhi, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmhi, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmhi, 8b, 8b, 8b)
+GEN_BINARY_TEST(cmhs, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmhs, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmhs, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmhs, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmhs, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmhs, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmhs, 8b, 8b, 8b)
+GEN_BINARY_TEST(cmtst, 2d, 2d, 2d)
+GEN_BINARY_TEST(cmtst, 4s, 4s, 4s)
+GEN_BINARY_TEST(cmtst, 2s, 2s, 2s)
+GEN_BINARY_TEST(cmtst, 8h, 8h, 8h)
+GEN_BINARY_TEST(cmtst, 4h, 4h, 4h)
+GEN_BINARY_TEST(cmtst, 16b, 16b, 16b)
+GEN_BINARY_TEST(cmtst, 8b, 8b, 8b)
+
GEN_TWOVEC_TEST(cmeq_zero_d_d, "cmeq d2, d11, #0", 2, 11)
GEN_TWOVEC_TEST(cmge_zero_d_d, "cmge d2, d11, #0", 2, 11)
GEN_TWOVEC_TEST(cmgt_zero_d_d, "cmgt d2, d11, #0", 2, 11)
GEN_TWOVEC_TEST(cmle_zero_d_d, "cmle d2, d11, #0", 2, 11)
GEN_TWOVEC_TEST(cmlt_zero_d_d, "cmlt d2, d11, #0", 2, 11)
+GEN_TWOVEC_TEST(cmeq_zero_2d_2d, "cmeq v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_4s_4s, "cmeq v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_2s_2s, "cmeq v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_8h_8h, "cmeq v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_4h_4h, "cmeq v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_16b_16b, "cmeq v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmeq_zero_8b_8b, "cmeq v5.8b, v22.8b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_2d_2d, "cmge v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_4s_4s, "cmge v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_2s_2s, "cmge v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_8h_8h, "cmge v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_4h_4h, "cmge v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_16b_16b, "cmge v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmge_zero_8b_8b, "cmge v5.8b, v22.8b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_2d_2d, "cmgt v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_4s_4s, "cmgt v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_2s_2s, "cmgt v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_8h_8h, "cmgt v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_4h_4h, "cmgt v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_16b_16b, "cmgt v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmgt_zero_8b_8b, "cmgt v5.8b, v22.8b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_2d_2d, "cmle v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_4s_4s, "cmle v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_2s_2s, "cmle v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_8h_8h, "cmle v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_4h_4h, "cmle v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_16b_16b, "cmle v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmle_zero_8b_8b, "cmle v5.8b, v22.8b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_2d_2d, "cmlt v5.2d, v22.2d, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_4s_4s, "cmlt v5.4s, v22.4s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_2s_2s, "cmlt v5.2s, v22.2s, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_8h_8h, "cmlt v5.8h, v22.8h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_4h_4h, "cmlt v5.4h, v22.4h, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_16b_16b, "cmlt v5.16b, v22.16b, #0", 5, 22)
+GEN_TWOVEC_TEST(cmlt_zero_8b_8b, "cmlt v5.8b, v22.8b, #0", 5, 22)
+
GEN_UNARY_TEST(cnt, 16b, 16b)
GEN_UNARY_TEST(cnt, 8b, 8b)
@@ -1594,27 +1521,25 @@
GEN_THREEVEC_TEST(ext_8b_8b_8b_0x7,
"ext v2.8b, v11.8b, v29.8b, #7", 2, 11, 29)
-
GEN_TWOVEC_TEST(ins_d0_d0, "ins v3.d[0], v24.d[0]", 3, 24)
GEN_TWOVEC_TEST(ins_d0_d1, "ins v3.d[0], v24.d[1]", 3, 24)
GEN_TWOVEC_TEST(ins_d1_d0, "ins v3.d[1], v24.d[0]", 3, 24)
GEN_TWOVEC_TEST(ins_d1_d1, "ins v3.d[1], v24.d[1]", 3, 24)
-
GEN_TWOVEC_TEST(ins_s0_s2, "ins v3.s[0], v24.s[2]", 3, 24)
GEN_TWOVEC_TEST(ins_s3_s0, "ins v3.s[3], v24.s[0]", 3, 24)
GEN_TWOVEC_TEST(ins_s2_s1, "ins v3.s[2], v24.s[1]", 3, 24)
GEN_TWOVEC_TEST(ins_s1_s3, "ins v3.s[1], v24.s[3]", 3, 24)
-
GEN_TWOVEC_TEST(ins_h0_h6, "ins v3.h[0], v24.h[6]", 3, 24)
GEN_TWOVEC_TEST(ins_h7_h0, "ins v3.h[7], v24.h[0]", 3, 24)
GEN_TWOVEC_TEST(ins_h6_h1, "ins v3.h[6], v24.h[1]", 3, 24)
GEN_TWOVEC_TEST(ins_h1_h7, "ins v3.h[1], v24.h[7]", 3, 24)
-
GEN_TWOVEC_TEST(ins_b0_b14, "ins v3.b[0], v24.b[14]", 3, 24)
GEN_TWOVEC_TEST(ins_b15_b8, "ins v3.b[15], v24.b[8]", 3, 24)
GEN_TWOVEC_TEST(ins_b13_b9, "ins v3.b[13], v24.b[9]", 3, 24)
GEN_TWOVEC_TEST(ins_b5_b12, "ins v3.b[5], v24.b[12]", 3, 24)
+// test_INS_general is a handwritten function
+
GEN_THREEVEC_TEST(mla_4s_4s_s0, "mla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
GEN_THREEVEC_TEST(mla_4s_4s_s3, "mla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
GEN_THREEVEC_TEST(mla_2s_2s_s0, "mla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
@@ -1624,7 +1549,6 @@
GEN_THREEVEC_TEST(mla_8h_8h_h5, "mla v2.8h, v11.8h, v2.h[5]", 2, 11, 9)
GEN_THREEVEC_TEST(mla_4h_4h_h2, "mla v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
GEN_THREEVEC_TEST(mla_4h_4h_h7, "mla v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
-
GEN_THREEVEC_TEST(mls_4s_4s_s0, "mls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
GEN_THREEVEC_TEST(mls_4s_4s_s3, "mls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
GEN_THREEVEC_TEST(mls_2s_2s_s0, "mls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
@@ -1634,7 +1558,6 @@
GEN_THREEVEC_TEST(mls_8h_8h_h5, "mls v2.8h, v11.8h, v2.h[5]", 2, 11, 9)
GEN_THREEVEC_TEST(mls_4h_4h_h2, "mls v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
GEN_THREEVEC_TEST(mls_4h_4h_h7, "mls v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
-
GEN_THREEVEC_TEST(mul_4s_4s_s0, "mul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
GEN_THREEVEC_TEST(mul_4s_4s_s3, "mul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
GEN_THREEVEC_TEST(mul_2s_2s_s0, "mul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
@@ -1645,13 +1568,38 @@
GEN_THREEVEC_TEST(mul_4h_4h_h2, "mul v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
GEN_THREEVEC_TEST(mul_4h_4h_h7, "mul v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
+GEN_BINARY_TEST(mla, 4s, 4s, 4s)
+GEN_BINARY_TEST(mla, 2s, 2s, 2s)
+GEN_BINARY_TEST(mla, 8h, 8h, 8h)
+GEN_BINARY_TEST(mla, 4h, 4h, 4h)
+GEN_BINARY_TEST(mla, 16b, 16b, 16b)
+GEN_BINARY_TEST(mla, 8b, 8b, 8b)
+GEN_BINARY_TEST(mls, 4s, 4s, 4s)
+GEN_BINARY_TEST(mls, 2s, 2s, 2s)
+GEN_BINARY_TEST(mls, 8h, 8h, 8h)
+GEN_BINARY_TEST(mls, 4h, 4h, 4h)
+GEN_BINARY_TEST(mls, 16b, 16b, 16b)
+GEN_BINARY_TEST(mls, 8b, 8b, 8b)
+GEN_BINARY_TEST(mul, 4s, 4s, 4s)
+GEN_BINARY_TEST(mul, 2s, 2s, 2s)
+GEN_BINARY_TEST(mul, 8h, 8h, 8h)
+GEN_BINARY_TEST(mul, 4h, 4h, 4h)
+GEN_BINARY_TEST(mul, 16b, 16b, 16b)
+GEN_BINARY_TEST(mul, 8b, 8b, 8b)
+
/* overkill -- don't need two vecs, only one */
GEN_TWOVEC_TEST(movi_16b_0x9C_lsl0, "movi v22.16b, #0x9C, LSL #0", 22, 23)
GEN_TWOVEC_TEST(movi_8b_0x8B_lsl0, "movi v22.8b, #0x8B, LSL #0", 22, 23)
+
GEN_TWOVEC_TEST(movi_8h_0x5A_lsl0, "movi v22.8h, #0x5A, LSL #0", 22, 23)
GEN_TWOVEC_TEST(movi_8h_0xA5_lsl8, "movi v22.8h, #0xA5, LSL #8", 22, 23)
GEN_TWOVEC_TEST(movi_4h_0x5A_lsl0, "movi v22.4h, #0x5A, LSL #0", 22, 23)
GEN_TWOVEC_TEST(movi_4h_0xA5_lsl8, "movi v22.4h, #0xA5, LSL #8", 22, 23)
+GEN_TWOVEC_TEST(mvni_8h_0x5A_lsl0, "mvni v22.8h, #0x5A, LSL #0", 22, 23)
+GEN_TWOVEC_TEST(mvni_8h_0xA5_lsl8, "mvni v22.8h, #0xA5, LSL #8", 22, 23)
+GEN_TWOVEC_TEST(mvni_4h_0x5A_lsl0, "mvni v22.4h, #0x5A, LSL #0", 22, 23)
+GEN_TWOVEC_TEST(mvni_4h_0xA5_lsl8, "mvni v22.4h, #0xA5, LSL #8", 22, 23)
+
GEN_TWOVEC_TEST(movi_4s_0x5A_lsl0, "movi v22.4s, #0x5A, LSL #0", 22, 23)
GEN_TWOVEC_TEST(movi_4s_0x6B_lsl8, "movi v22.4s, #0x6B, LSL #8", 22, 23)
GEN_TWOVEC_TEST(movi_4s_0x49_lsl16, "movi v22.4s, #0x49, LSL #16", 22, 23)
@@ -1660,19 +1608,6 @@
GEN_TWOVEC_TEST(movi_2s_0x6B_lsl8, "movi v22.2s, #0x6B, LSL #8", 22, 23)
GEN_TWOVEC_TEST(movi_2s_0x49_lsl16, "movi v22.2s, #0x49, LSL #16", 22, 23)
GEN_TWOVEC_TEST(movi_2s_0x3D_lsl24, "movi v22.2s, #0x3D, LSL #24", 22, 23)
-GEN_TWOVEC_TEST(movi_4s_0x6B_msl8, "movi v22.4s, #0x6B, MSL #8", 22, 23)
-GEN_TWOVEC_TEST(movi_4s_0x94_msl16, "movi v22.4s, #0x94, MSL #16", 22, 23)
-GEN_TWOVEC_TEST(movi_2s_0x7A_msl8, "movi v22.2s, #0x7A, MSL #8", 22, 23)
-GEN_TWOVEC_TEST(movi_2s_0xA5_msl16, "movi v22.2s, #0xA5, MSL #16", 22, 23)
-
-GEN_TWOVEC_TEST(movi_d_0xA5, "movi d22, #0xFF00FF0000FF00FF", 22, 23)
-GEN_TWOVEC_TEST(movi_2d_0xB4, "movi v22.2d, #0xFF00FFFF00FF0000", 22, 23)
-
-/* overkill -- don't need two vecs, only one */
-GEN_TWOVEC_TEST(mvni_8h_0x5A_lsl0, "mvni v22.8h, #0x5A, LSL #0", 22, 23)
-GEN_TWOVEC_TEST(mvni_8h_0xA5_lsl8, "mvni v22.8h, #0xA5, LSL #8", 22, 23)
-GEN_TWOVEC_TEST(mvni_4h_0x5A_lsl0, "mvni v22.4h, #0x5A, LSL #0", 22, 23)
-GEN_TWOVEC_TEST(mvni_4h_0xA5_lsl8, "mvni v22.4h, #0xA5, LSL #8", 22, 23)
GEN_TWOVEC_TEST(mvni_4s_0x5A_lsl0, "mvni v22.4s, #0x5A, LSL #0", 22, 23)
GEN_TWOVEC_TEST(mvni_4s_0x6B_lsl8, "mvni v22.4s, #0x6B, LSL #8", 22, 23)
GEN_TWOVEC_TEST(mvni_4s_0x49_lsl16, "mvni v22.4s, #0x49, LSL #16", 22, 23)
@@ -1681,11 +1616,20 @@
GEN_TWOVEC_TEST(mvni_2s_0x6B_lsl8, "mvni v22.2s, #0x6B, LSL #8", 22, 23)
GEN_TWOVEC_TEST(mvni_2s_0x49_lsl16, "mvni v22.2s, #0x49, LSL #16", 22, 23)
GEN_TWOVEC_TEST(mvni_2s_0x3D_lsl24, "mvni v22.2s, #0x3D, LSL #24", 22, 23)
+
+/* overkill -- don't need two vecs, only one */
+GEN_TWOVEC_TEST(movi_4s_0x6B_msl8, "movi v22.4s, #0x6B, MSL #8", 22, 23)
+GEN_TWOVEC_TEST(movi_4s_0x94_msl16, "movi v22.4s, #0x94, MSL #16", 22, 23)
+GEN_TWOVEC_TEST(movi_2s_0x7A_msl8, "movi v22.2s, #0x7A, MSL #8", 22, 23)
+GEN_TWOVEC_TEST(movi_2s_0xA5_msl16, "movi v22.2s, #0xA5, MSL #16", 22, 23)
GEN_TWOVEC_TEST(mvni_4s_0x6B_msl8, "mvni v22.4s, #0x6B, MSL #8", 22, 23)
GEN_TWOVEC_TEST(mvni_4s_0x94_msl16, "mvni v22.4s, #0x94, MSL #16", 22, 23)
GEN_TWOVEC_TEST(mvni_2s_0x7A_msl8, "mvni v22.2s, #0x7A, MSL #8", 22, 23)
GEN_TWOVEC_TEST(mvni_2s_0xA5_msl16, "mvni v22.2s, #0xA5, MSL #16", 22, 23)
+GEN_TWOVEC_TEST(movi_d_0xA5, "movi d22, #0xFF00FF0000FF00FF", 22, 23)
+GEN_TWOVEC_TEST(movi_2d_0xB4, "movi v22.2d, #0xFF00FFFF00FF0000", 22, 23)
+
GEN_UNARY_TEST(not, 16b, 16b)
GEN_UNARY_TEST(not, 8b, 8b)
@@ -1718,7 +1662,6 @@
GEN_BINARY_TEST(saba, 4h, 4h, 4h)
GEN_BINARY_TEST(saba, 16b, 16b, 16b)
GEN_BINARY_TEST(saba, 8b, 8b, 8b)
-
GEN_BINARY_TEST(uaba, 4s, 4s, 4s)
GEN_BINARY_TEST(uaba, 2s, 2s, 2s)
GEN_BINARY_TEST(uaba, 8h, 8h, 8h)
@@ -1728,20 +1671,15 @@
GEN_THREEVEC_TEST(sabal_2d_2s_2s, "sabal v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(sabal2_2d_4s_4s, "sabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(sabal_4s_4h_4h, "sabal v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(sabal2_4s_8h_8h, "sabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(sabal_8h_8b_8b, "sabal v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(sabal2_8h_16b_16b,
"sabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabal_2d_2s_2s, "uabal v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uabal2_2d_4s_4s, "uabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabal_4s_4h_4h, "uabal v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(uabal2_4s_8h_8h, "uabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabal_8h_8b_8b, "uabal v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(uabal2_8h_16b_16b,
"uabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
@@ -1752,7 +1690,6 @@
GEN_THREEVEC_TEST(sabd_4h_4h_4h, "sabd v2.4h, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(sabd_16b_16b_16b, "sabd v2.16b, v11.16b, v29.16b", 2, 11, 29)
GEN_THREEVEC_TEST(sabd_8b_8b_8b, "sabd v2.8b, v11.8b, v29.8b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabd_4s_4s_4s, "uabd v2.4s, v11.4s, v29.4s", 2, 11, 29)
GEN_THREEVEC_TEST(uabd_2s_2s_2s, "uabd v2.2s, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uabd_8h_8h_8h, "uabd v2.8h, v11.8h, v29.8h", 2, 11, 29)
@@ -1762,20 +1699,15 @@
GEN_THREEVEC_TEST(sabdl_2d_2s_2s, "sabdl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(sabdl2_2d_4s_4s, "sabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(sabdl_4s_4h_4h, "sabdl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(sabdl2_4s_8h_8h, "sabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(sabdl_8h_8b_8b, "sabdl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(sabdl2_8h_16b_16b,
"sabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabdl_2d_2s_2s, "uabdl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uabdl2_2d_4s_4s, "uabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabdl_4s_4h_4h, "uabdl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(uabdl2_4s_8h_8h, "uabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(uabdl_8h_8b_8b, "uabdl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(uabdl2_8h_16b_16b,
"uabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
@@ -1786,7 +1718,6 @@
GEN_TWOVEC_TEST(sadalp_4s_8h, "sadalp v3.4s, v19.8h", 3, 19)
GEN_TWOVEC_TEST(sadalp_1d_2s, "sadalp v3.1d, v19.2s", 3, 19)
GEN_TWOVEC_TEST(sadalp_2d_4s, "sadalp v3.2d, v19.4s", 3, 19)
-
GEN_TWOVEC_TEST(uadalp_4h_8b, "uadalp v3.4h, v19.8b", 3, 19)
GEN_TWOVEC_TEST(uadalp_8h_16b, "uadalp v3.8h, v19.16b", 3, 19)
GEN_TWOVEC_TEST(uadalp_2s_4h, "uadalp v3.2s, v19.4h", 3, 19)
@@ -1796,40 +1727,29 @@
GEN_THREEVEC_TEST(saddl_2d_2s_2s, "saddl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(saddl2_2d_4s_4s, "saddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(saddl_4s_4h_4h, "saddl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(saddl2_4s_8h_8h, "saddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(saddl_8h_8b_8b, "saddl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(saddl2_8h_16b_16b,
"saddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uaddl_2d_2s_2s, "uaddl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uaddl2_2d_4s_4s, "uaddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(uaddl_4s_4h_4h, "uaddl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(uaddl2_4s_8h_8h, "uaddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(uaddl_8h_8b_8b, "uaddl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(uaddl2_8h_16b_16b,
"uaddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
-
GEN_THREEVEC_TEST(ssubl_2d_2s_2s, "ssubl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(ssubl2_2d_4s_4s, "ssubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(ssubl_4s_4h_4h, "ssubl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(ssubl2_4s_8h_8h, "ssubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(ssubl_8h_8b_8b, "ssubl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(ssubl2_8h_16b_16b,
"ssubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
-
GEN_THREEVEC_TEST(usubl_2d_2s_2s, "usubl v2.2d, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(usubl2_2d_4s_4s, "usubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
-
GEN_THREEVEC_TEST(usubl_4s_4h_4h, "usubl v2.4s, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(usubl2_4s_8h_8h, "usubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
-
GEN_THREEVEC_TEST(usubl_8h_8b_8b, "usubl v2.8h, v11.8b, v29.8b", 2, 11, 29)
GEN_THREEVEC_TEST(usubl2_8h_16b_16b,
"usubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
@@ -1840,7 +1760,6 @@
GEN_TWOVEC_TEST(saddlp_4s_8h, "saddlp v3.4s, v19.8h", 3, 19)
GEN_TWOVEC_TEST(saddlp_1d_2s, "saddlp v3.1d, v19.2s", 3, 19)
GEN_TWOVEC_TEST(saddlp_2d_4s, "saddlp v3.2d, v19.4s", 3, 19)
-
GEN_TWOVEC_TEST(uaddlp_4h_8b, "uaddlp v3.4h, v19.8b", 3, 19)
GEN_TWOVEC_TEST(uaddlp_8h_16b, "uaddlp v3.8h, v19.16b", 3, 19)
GEN_TWOVEC_TEST(uaddlp_2s_4h, "uaddlp v3.2s, v19.4h", 3, 19)
@@ -1853,7 +1772,6 @@
GEN_TWOVEC_TEST(saddlv_s_8h, "saddlv s3, v19.8h", 3, 19)
GEN_TWOVEC_TEST(saddlv_s_4h, "saddlv s3, v19.4h", 3, 19)
GEN_TWOVEC_TEST(saddlv_d_4s, "saddlv d3, v19.4s", 3, 19)
-
GEN_TWOVEC_TEST(uaddlv_h_16b, "uaddlv h3, v19.16b", 3, 19)
GEN_TWOVEC_TEST(uaddlv_h_8b, "uaddlv h3, v19.8b", 3, 19)
GEN_TWOVEC_TEST(uaddlv_s_8h, "uaddlv s3, v19.8h", 3, 19)
@@ -1866,21 +1784,18 @@
GEN_THREEVEC_TEST(saddw_4s_4s_4h, "saddw v5.4s, v13.4s, v31.4h", 5, 13, 31)
GEN_THREEVEC_TEST(saddw2_2d_2d_4s, "saddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
GEN_THREEVEC_TEST(saddw_2d_2d_2s, "saddw v5.2d, v13.2d, v31.2s", 5, 13, 31)
-
GEN_THREEVEC_TEST(uaddw2_8h_8h_16b, "uaddw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
GEN_THREEVEC_TEST(uaddw_8h_8h_8b, "uaddw v5.8h, v13.8h, v31.8b", 5, 13, 31)
GEN_THREEVEC_TEST(uaddw2_4s_4s_8h, "uaddw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
GEN_THREEVEC_TEST(uaddw_4s_4s_4h, "uaddw v5.4s, v13.4s, v31.4h", 5, 13, 31)
GEN_THREEVEC_TEST(uaddw2_2d_2d_4s, "uaddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
GEN_THREEVEC_TEST(uaddw_2d_2d_2s, "uaddw v5.2d, v13.2d, v31.2s", 5, 13, 31)
-
GEN_THREEVEC_TEST(ssubw2_8h_8h_16b, "ssubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
GEN_THREEVEC_TEST(ssubw_8h_8h_8b, "ssubw v5.8h, v13.8h, v31.8b", 5, 13, 31)
GEN_THREEVEC_TEST(ssubw2_4s_4s_8h, "ssubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
GEN_THREEVEC_TEST(ssubw_4s_4s_4h, "ssubw v5.4s, v13.4s, v31.4h", 5, 13, 31)
GEN_THREEVEC_TEST(ssubw2_2d_2d_4s, "ssubw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
GEN_THREEVEC_TEST(ssubw_2d_2d_2s, "ssubw v5.2d, v13.2d, v31.2s", 5, 13, 31)
-
GEN_THREEVEC_TEST(usubw2_8h_8h_16b, "usubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
GEN_THREEVEC_TEST(usubw_8h_8h_8b, "usubw v5.8h, v13.8h, v31.8b", 5, 13, 31)
GEN_THREEVEC_TEST(usubw2_4s_4s_8h, "usubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
@@ -1894,21 +1809,18 @@
GEN_THREEVEC_TEST(shadd_4h_4h_4h, "shadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(shadd_16b_16b_16b,"shadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
GEN_THREEVEC_TEST(shadd_8b_8b_8b, "shadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uhadd_4s_4s_4s, "uhadd v2.4s, v11.4s, v29.4s", 2, 11, 29)
GEN_THREEVEC_TEST(uhadd_2s_2s_2s, "uhadd v2.2s, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uhadd_8h_8h_8h, "uhadd v2.8h, v11.8h, v29.8h", 2, 11, 29)
GEN_THREEVEC_TEST(uhadd_4h_4h_4h, "uhadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(uhadd_16b_16b_16b,"uhadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
GEN_THREEVEC_TEST(uhadd_8b_8b_8b, "uhadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
-
GEN_THREEVEC_TEST(shsub_4s_4s_4s, "shsub v2.4s, v11.4s, v29.4s", 2, 11, 29)
GEN_THREEVEC_TEST(shsub_2s_2s_2s, "shsub v2.2s, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(shsub_8h_8h_8h, "shsub v2.8h, v11.8h, v29.8h", 2, 11, 29)
GEN_THREEVEC_TEST(shsub_4h_4h_4h, "shsub v2.4h, v11.4h, v29.4h", 2, 11, 29)
GEN_THREEVEC_TEST(shsub_16b_16b_16b,"shsub v2.16b, v11.16b, v29.16b", 2, 11, 29)
GEN_THREEVEC_TEST(shsub_8b_8b_8b, "shsub v2.8b, v11.8b, v29.8b", 2, 11, 29)
-
GEN_THREEVEC_TEST(uhsub_4s_4s_4s, "uhsub v2.4s, v11.4s, v29.4s", 2, 11, 29)
GEN_THREEVEC_TEST(uhsub_2s_2s_2s, "uhsub v2.2s, v11.2s, v29.2s", 2, 11, 29)
GEN_THREEVEC_TEST(uhsub_8h_8h_8h, "uhsub v2.8h, v11.8h, v29.8h", 2, 11, 29)
@@ -1935,7 +1847,6 @@
GEN_TWOVEC_TEST(shrn_8b_8h_8, "shrn v4.8b, v29.8h, #8", 4, 29)
GEN_TWOVEC_TEST(shrn2_16b_8h_1, "shrn2 v4.16b, v29.8h, #1", 4, 29)
GEN_TWOVEC_TEST(shrn2_16b_8h_8, "shrn2 v4.16b, v29.8h, #8", 4, 29)
-
GEN_TWOVEC_TEST(rshrn_2s_2d_1, "rshrn v4.2s, v29.2d, #1", 4, 29)
GEN_TWOVEC_TEST(rshrn_2s_2d_32, "rshrn v4.2s, v29.2d, #32", 4, 29)
GEN_TWOVEC_TEST(rshrn2_4s_2d_1, "rshrn2 v4.4s, v29.2d, #1", 4, 29)
@@ -1977,7 +1888,6 @@
GEN_TWOVEC_TEST(sli_8b_8b_0, "sli v6.8b, v27.8b, #0", 6, 27)
GEN_TWOVEC_TEST(sli_8b_8b_3, "sli v6.8b, v27.8b, #3", 6, 27)
GEN_TWOVEC_TEST(sli_8b_8b_7, "sli v6.8b, v27.8b, #7", 6, 27)
-
GEN_TWOVEC_TEST(sri_2d_2d_1, "sri v6.2d, v27.2d, #1", 6, 27)
GEN_TWOVEC_TEST(sri_2d_2d_33, "sri v6.2d, v27.2d, #33", 6, 27)
GEN_TWOVEC_TEST(sri_2d_2d_64, "sri v6.2d, v27.2d, #64", 6, 27)
@@ -2000,27 +1910,49 @@
GEN_TWOVEC_TEST(sri_8b_8b_4, "sri v6.8b, v27.8b, #4", 6, 27)
GEN_TWOVEC_TEST(sri_8b_8b_8, "sri v6.8b, v27.8b, #8", 6, 27)
+GEN_BINARY_TEST(smax, 4s, 4s, 4s)
+GEN_BINARY_TEST(smax, 2s, 2s, 2s)
+GEN_BINARY_TEST(smax, 8h, 8h, 8h)
+GEN_BINARY_TEST(smax, 4h, 4h, 4h)
+GEN_BINARY_TEST(smax, 16b, 16b, 16b)
+GEN_BINARY_TEST(smax, 8b, 8b, 8b)
+GEN_BINARY_TEST(umax, 4s, 4s, 4s)
+GEN_BINARY_TEST(umax, 2s, 2s, 2s)
+GEN_BINARY_TEST(umax, 8h, 8h, 8h)
+GEN_BINARY_TEST(umax, 4h, 4h, 4h)
+GEN_BINARY_TEST(umax, 16b, 16b, 16b)
+GEN_BINARY_TEST(umax, 8b, 8b, 8b)
+GEN_BINARY_TEST(smin, 4s, 4s, 4s)
+GEN_BINARY_TEST(smin, 2s, 2s, 2s)
+GEN_BINARY_TEST(smin, 8h, 8h, 8h)
+GEN_BINARY_TEST(smin, 4h, 4h, 4h)
+GEN_BINARY_TEST(smin, 16b, 16b, 16b)
+GEN_BINARY_TEST(smin, 8b, 8b, 8b)
+GEN_BINARY_TEST(umin, 4s, 4s, 4s)
+GEN_BINARY_TEST(umin, 2s, 2s, 2s)
+GEN_BINARY_TEST(umin, 8h, 8h, 8h)
+GEN_BINARY_TEST(umin, 4h, 4h, 4h)
+GEN_BINARY_TEST(umin, 16b, 16b, 16b)
+GEN_BINARY_TEST(umin, 8b, 8b, 8b)
+
GEN_BINARY_TEST(smaxp, 4s, 4s, 4s)
GEN_BINARY_TEST(smaxp, 2s, 2s, 2s)
GEN_BINARY_TEST(smaxp, 8h, 8h, 8h)
GEN_BINARY_TEST(smaxp, 4h, 4h, 4h)
GEN_BINARY_TEST(smaxp, 16b, 16b, 16b)
GEN_BINARY_TEST(smaxp, 8b, 8b, 8b)
-
GEN_BINARY_TEST(umaxp, 4s, 4s, 4s)
GEN_BINARY_TEST(umaxp, 2s, 2s, 2s)
GEN_BINARY_TEST(umaxp, 8h, 8h, 8h)
GEN_BINARY_TEST(umaxp, 4h, 4h, 4h)
GEN_BINARY_TEST(umaxp, 16b, 16b, 16b)
GEN_BINARY_TEST(umaxp, 8b, 8b, 8b)
-
GEN_BINARY_TEST(sminp, 4s, 4s, 4s)
GEN_BINARY_TEST(sminp, 2s, 2s, 2s)
GEN_BINARY_TEST(sminp, 8h, 8h, 8h)
GEN_BINARY_TEST(sminp, 4h, 4h, 4h)
GEN_BINARY_TEST(sminp, 16b, 16b, 16b)
GEN_BINARY_TEST(sminp, 8b, 8b, 8b)
-
GEN_BINARY_TEST(uminp, 4s, 4s, 4s)
GEN_BINARY_TEST(uminp, 2s, 2s, 2s)
GEN_BINARY_TEST(uminp, 8h, 8h, 8h)
@@ -2028,6 +1960,11 @@
GEN_BINARY_TEST(uminp, 16b, 16b, 16b)
GEN_BINARY_TEST(uminp, 8b, 8b, 8b)
+// test_SMAXV is a handwritten function
+// test_UMAXV is a handwritten function
+// test_SMINV is a handwritten function
+// test_UMINV is a handwritten function
+
GEN_THREEVEC_TEST(smlal_2d_2s_s0, "smlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
GEN_THREEVEC_TEST(smlal_2d_2s_s3, "smlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
GEN_THREEVEC_TEST(smlal2_2d_4s_s1, "smlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
@@ -2036,7 +1973,6 @@
GEN_THREEVEC_TEST(smlal_4s_4h_h7, "smlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
GEN_THREEVEC_TEST(smlal2_4s_8h_h1, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
GEN_THREEVEC_TEST(smlal2_4s_8h_h4, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
-
GEN_THREEVEC_TEST(umlal_2d_2s_s0, "umlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
GEN_THREEVEC_TEST(umlal_2d_2s_s3, "umlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
GEN_THREEVEC_TEST(umlal2_2d_4s_s1, "umlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
@@ -2045,7 +1981,6 @@
GEN_THREEVEC_TEST(umlal_4s_4h_h7, "umlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
GEN_THREEVEC_TEST(umlal2_4s_8h_h1, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
GEN_THREEVEC_TEST(umlal2_4s_8h_h4, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
-
GEN_THREEVEC_TEST(smlsl_2d_2s_s0, "smlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
GEN_THREEVEC_TEST(smlsl_2d_2s_s3, "smlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
GEN_THREEVEC_TEST(smlsl2_2d_4s_s1, "smlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
@@ -2054,7 +1989,6 @@
GEN_THREEVEC_TEST(smlsl_4s_4h_h7, "smlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
GEN_THREEVEC_TEST(smlsl2_4s_8h_h1, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
GEN_THREEVEC_TEST(smlsl2_4s_8h_h4, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
-
GEN_THREEVEC_TEST(umlsl_2d_2s_s0, "umlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
GEN_THREEVEC_TEST(umlsl_2d_2s_s3, "umlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
GEN_THREEVEC_TEST(umlsl2_2d_4s_s1, "umlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
@@ -2063,7 +1997,6 @@
GEN_THREEVEC_TEST(umlsl_4s_4h_h7, "umlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
GEN_THREEVEC_TEST(umlsl2_4s_8h_h1, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
GEN_THREEVEC_TEST(umlsl2_4s_8h_h4, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
-
GEN_THREEVEC_TEST(smull_2d_2s_s0, "smull v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
GEN_THREEVEC_TEST(smull_2d_2s_s3, "smull v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
...
[truncated message content] |
Author: sewardj
Date: Sun Nov 23 17:49:05 2014
New Revision: 14762
Log:
Merge, from trunk, 14679
14679 Add test cases for arm64 FMLA etc
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/memory.c
branches/VALGRIND_3_10_BRANCH/none/tests/arm64/memory.stdout.exp
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.c Sun Nov 23 17:49:05 2014
@@ -1205,6 +1205,20 @@
GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7)
GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7)
+GEN_THREEVEC_TEST(fmla_2d_2d_d0, "fmla v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2d_2d_d1, "fmla v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_4s_4s_s0, "fmla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_4s_4s_s3, "fmla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2s_2s_s0, "fmla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmla_2s_2s_s3, "fmla v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+
+GEN_THREEVEC_TEST(fmls_2d_2d_d0, "fmls v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2d_2d_d1, "fmls v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_4s_4s_s0, "fmls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_4s_4s_s3, "fmls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2s_2s_s0, "fmls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
+GEN_THREEVEC_TEST(fmls_2s_2s_s3, "fmls v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
+
GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23)
GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23)
GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23)
@@ -3144,6 +3158,18 @@
// fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[]
// fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[]
+ if (1) test_fmla_2d_2d_d0(TyDF);
+ if (1) test_fmla_2d_2d_d1(TyDF);
+ if (1) test_fmla_4s_4s_s0(TySF);
+ if (1) test_fmla_4s_4s_s3(TySF);
+ if (1) test_fmla_2s_2s_s0(TySF);
+ if (1) test_fmla_2s_2s_s3(TySF);
+ if (1) test_fmls_2d_2d_d0(TyDF);
+ if (1) test_fmls_2d_2d_d1(TyDF);
+ if (1) test_fmls_4s_4s_s0(TySF);
+ if (1) test_fmls_4s_4s_s3(TySF);
+ if (1) test_fmls_2s_2s_s0(TySF);
+ if (1) test_fmls_2s_2s_s3(TySF);
// fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
// INCOMPLETE
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm64/fp_and_simd.stdout.exp Sun Nov 23 17:49:05 2014
@@ -53,1924 +53,1936 @@
fmls v9.2d, v7.2d, v8.2d 1541139c8b1cd0d1a11d81326f4e7880 30c9028972f8733d11f7fa4450de2529 a1cd852d9cd970502d146432e64644c9 fpsr=00000000
fmls v9.4s, v7.4s, v8.4s 25c80a060da03fb0c33ebc4b44b8ddd8 5791e2f2a78f37627c9fe23c60c5d82b bde3fe0e304791cd7f800000e60eded1 fpsr=00000000
fmls v9.2s, v7.2s, v8.2s 94d7265949ca62b46a8a793cf9d5f0d1 35e7926e777aa43f56470887bfdd3daf 0000000000000000ff800000fa38e471 fpsr=00000000
-fmov v22.2d, #0.125 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 3fc00000000000003fc0000000000000 84db9fe3e4b100d48d969e225f9318a0 fpsr=00000000
-fmov v22.2d, #-4.0 f0fdf0aee1dda4e888e2774acbc13287 f30110c432a534d0478d5d7e053a4e0c c010000000000000c010000000000000 f30110c432a534d0478d5d7e053a4e0c fpsr=00000000
-fmov v22.2d, #1.0 1adad8978cbfb47829861f0d48dc87f5 62bbc77143b71e92668b24fb9133bf52 3ff00000000000003ff0000000000000 62bbc77143b71e92668b24fb9133bf52 fpsr=00000000
-fmov d22, d23 b168a24af5479e7bc9f1d5f8e2de4bd3 894d9fe1f98d1aa0861ef69cf4e34e11 0000000000000000861ef69cf4e34e11 894d9fe1f98d1aa0861ef69cf4e34e11 fpsr=00000000
-fmov s22, s23 7b813bf15120fbc8683cbc58f8b23fca 74876ac63afb7562c67d2c86fa7c09a3 000000000000000000000000fa7c09a3 74876ac63afb7562c67d2c86fa7c09a3 fpsr=00000000
-fmov s7, w15 c501b4c64209aa2e0719232dba0b82d5 077815d35567232e66c997070e860c39 0000000000000000000000000e860c39 9ce5d1a297a56adb66c997070e860c39 fpsr=00000000
-fmov d7, x15 462deabeada6093241150c7a1a4df892 89ad76dc21a1f8f15acd7ad9f991bada 00000000000000005acd7ad9f991bada 2a1f00ed91e9071d5acd7ad9f991bada fpsr=00000000
-fmov v7.d[1], x15 df63bd3c7359f634f791559ff8d88161 fba1981add7938e3067d74917c37833e 067d74917c37833ef791559ff8d88161 70050d9d72825295067d74917c37833e fpsr=00000000
-fmov w15, s7 de62d56351fe96dabe7a2cefcf2b96bb 9cdd1a32cd007ff7daac12cf3a64acbd de62d56351fe96dabe7a2cefcf2b96bb d973ba438b80fdb500000000cf2b96bb fpsr=00000000
-fmov x15, d7 6fa194a173e020c0ede3baf27b7b85bb 8514e93e478d067a5a4ac156a6cb98bf 6fa194a173e020c0ede3baf27b7b85bb fa0ba48e9db3d6f2ede3baf27b7b85bb fpsr=00000000
-fmov x15, v7.d[1] 71a4885bc70f501cf18441c67d4b9e45 95a6e59e2a7fabcb65b86284a1cb27a3 71a4885bc70f501cf18441c67d4b9e45 b330aadc8a7cbfaf71a4885bc70f501c fpsr=00000000
-fmov d22, #0.125 c3ca90f22dec084fa9bca1cab4fdc2ba aef4eeb358364f4add55d3bb09c439c9 00000000000000003fc0000000000000 aef4eeb358364f4add55d3bb09c439c9 fpsr=00000000
-fmov d22, #-4.0 45738ec585d726b8f4ecb95e02f1d179 af5de4ddb013d258a082f55bbf17ae91 0000000000000000c010000000000000 af5de4ddb013d258a082f55bbf17ae91 fpsr=00000000
-fmov d22, #1.0 d6006035af2e8bb7b3736be34585abe2 7742a77a117513548f9ea7c3a323665c 00000000000000003ff0000000000000 7742a77a117513548f9ea7c3a323665c fpsr=00000000
-fmov s22, #0.125 57d0e8a18b5417adc6b295b85f1c3056 e70216ec5cbcf49e8a09cb539549408a 0000000000000000000000003e000000 e70216ec5cbcf49e8a09cb539549408a fpsr=00000000
+fmla v2.2d, v11.2d, v29.d[0] 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 04b4378bce1492e08680a7399beeae16 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 04b4378bce1492e08680a7399beeae16 fpsr=00000000
+fmla v2.2d, v11.2d, v29.d[1] 2e467d8e98e7468c75a0cbeda561e618 9c86e5cb54c594021c25022200a7415e 1adad8978cbfb47829861f0d48dc87f5 2e467d8e98e7468c75a0cbeda561e618 9c86e5cb54c594021c25022200a7415e 1adad8978cbfb47829861f0d48dc87f5 fpsr=00000000
+fmla v2.4s, v11.4s, v29.s[0] b168a24af5479e7bc9f1d5f8e2de4bd3 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 b168a24a7f800000c9f1d5f87f800000 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 fpsr=00000000
+fmla v2.4s, v11.4s, v29.s[3] 07121ecd88441b7dd2cc3eca9347d80f 6e1d4703bf5de53fd97270f257c73303 c501b4c64209aa2e0719232dba0b82d5 f39f5fb044e0da6b5ef5ac39dd49dabd 6e1d4703bf5de53fd97270f257c73303 c501b4c64209aa2e0719232dba0b82d5 fpsr=00000000
+fmla v2.2s, v11.2s, v29.s[0] 462deabeada6093241150c7a1a4df892 89ad76dc21a1f8f15acd7ad9f991bada c201829797974fddfe5d063c8be33ce1 000000000000000041150c7a46015b57 89ad76dc21a1f8f15acd7ad9f991bada c201829797974fddfe5d063c8be33ce1 fpsr=00000000
+fmla v2.2s, v11.2s, v29.s[3] f82db3448c8c9a654f1c8c8db3b639e1 70050d9d7282529509eddffd330cfda3 de62d56351fe96dabe7a2cefcf2b96bb 00000000000000004f1c8c8dd1f9dadf 70050d9d7282529509eddffd330cfda3 de62d56351fe96dabe7a2cefcf2b96bb fpsr=00000000
+fmls v2.2d, v11.2d, v29.d[0] 6fa194a173e020c0ede3baf27b7b85bb 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 6fa194a173e020c0fff0000000000000 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 fpsr=00000000
+fmls v2.2d, v11.2d, v29.d[1] a20cab554a62dd2468a718ec4422710c b330aadc8a7cbfaf26fbc229d962e2d7 c3ca90f22dec084fa9bca1cab4fdc2ba b70baca46a0735fb68a718ec4422710c b330aadc8a7cbfaf26fbc229d962e2d7 c3ca90f22dec084fa9bca1cab4fdc2ba fpsr=00000000
+fmls v2.4s, v11.4s, v29.s[0] 45738ec585d726b8f4ecb95e02f1d179 af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 45738ec507ac8542f4ecb95e16bed2ea af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 fpsr=00000000
+fmls v2.4s, v11.4s, v29.s[3] 0bd9cf5599014e9dc435b32da92a7aa5 2ca02ba32b169299fd646dd04c2dd191 57d0e8a18b5417adc6b295b85f1c3056 c502b501c375bfe07f800000e48dd839 2ca02ba32b169299fd646dd04c2dd191 57d0e8a18b5417adc6b295b85f1c3056 fpsr=00000000
randV128: 256 calls, 266 iters
-fmov s22, #-4.0 a9430469f9a6aaf90d07193d2e134034 e0fd1393714954977124406c74e81e7a 000000000000000000000000c0800000 e0fd1393714954977124406c74e81e7a fpsr=00000000
-fmov s22, #-1.0 40947ccd307b129e244ee56d2260de8c d2b5bf6419898df003e6fe7283eff6cb 000000000000000000000000bf800000 d2b5bf6419898df003e6fe7283eff6cb fpsr=00000000
-fmul v2.2d, v11.2d, v29.d[0] e82632fc79b30f1483e79bb67d116120 3fa5c4d84771e518605a54f56dfe15b7 ddeb80fe57ce3c26f9fcb34432fe8249 f9b38630bd4f9a66fff0000000000000 3fa5c4d84771e518605a54f56dfe15b7 ddeb80fe57ce3c26f9fcb34432fe8249 fpsr=00000000
-fmul v2.2d, v11.2d, v29.d[1] 8cf3c5a6e236ba0ab0c81fb7053f6b55 8fbc05b829b247cac4e8bba2bda13050 98bf1ba36919393bc4d999db7390839e 00000000000000001db80b224604498d 8fbc05b829b247cac4e8bba2bda13050 98bf1ba36919393bc4d999db7390839e fpsr=00000000
-fmul v2.4s, v11.4s, v29.s[0] 45a92ebc1d99f6f68da34afe4ed3935a 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 c0711380ce499c1470026a6f6df4bb27 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 fpsr=00000000
-fmul v2.4s, v11.4s, v29.s[3] 1eca927d6d5eee012a6fe8ae3cfe5e6a 05dbe25a9a3951f70e8dc8821606fcca fe1783322bd1f4a0a92e2587172ec23f c482233358db5ca4cd27d3dcd49fc892 05dbe25a9a3951f70e8dc8821606fcca fe1783322bd1f4a0a92e2587172ec23f fpsr=00000000
-fmul v2.2s, v11.2s, v29.s[0] ca5b844f4549f54ebdaf0fabc405a22a 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 00000000000000007f8000005ba1e6e7 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 fpsr=00000000
-fmul v2.2s, v11.2s, v29.s[3] fe609a94181e600278e7d2d9d92a333d 4210b3d32431d146a45cad2eccb0e21a a2de962ffdd15c3e50063f9610e753cd 000000000000000007bfdfa43019cbd8 4210b3d32431d146a45cad2eccb0e21a a2de962ffdd15c3e50063f9610e753cd fpsr=00000000
-fmul d2, d11, d29 6ddc67b25da28240909c451c6eb3e447 ee7d691b146130944d3d038a0b69312c 4df433720fd7245dafacd5bdced9cd88 0000000000000000bcfa24e4714b959f ee7d691b146130944d3d038a0b69312c 4df433720fd7245dafacd5bdced9cd88 fpsr=00000000
-fmul s2, s11, s29 cdd47e0b8597b02c38527c577ae28aed e77b184466b967d624750ac67ebe825f 2533f6bc813a13365b808a28feded669 000000000000000000000000ff800000 e77b184466b967d624750ac67ebe825f 2533f6bc813a13365b808a28feded669 fpsr=00000000
-fmul v9.2d, v7.2d, v8.2d d04b750405c33deba68d8a6feefdf8d2 e11053b38ffdcd305e88d8c318f5aa57 716c04a72ed78195c526efee81706265 fpsr=00000000
-fmul v9.4s, v7.4s, v8.4s 1b8ce6e04f0e66e88ae9fdca101c70a3 dbd798f8ac487f46b581f3b7244eb4f5 b7ed542fbbdf0e6200ed8f4c00000001 fpsr=00000000
-fmul v9.2s, v7.2s, v8.2s 2b46de0152e87ea00ccf8549bf47029a 913db0cc02f1b3c72ff97f68cd517cb9 0000000000000000000194804d22da15 fpsr=00000000
-fcvtn v22.2s, v23.2d 2af3bd4b509e6608a513cfe482162be8 6f8ae74d5f7960b4a01933ef595f6af1 00000000000000007f80000080000000 6f8ae74d5f7960b4a01933ef595f6af1 fpsr=00000000
-fcvtn2 v22.4s, v23.2d b903f1b29f411487312d32f1bb069e61 95d26cc246074b10bda9f7bf92a71bac 80000000ad4fbdfd312d32f1bb069e61 95d26cc246074b10bda9f7bf92a71bac fpsr=00000000
-scvtf s7, w15 b8d75a9620326a7d927f8ecd4a783d65 e3761d8b97fa553a6508ac365a886f48 0000000000000000000000004eb510df 06ced856b4d046486508ac365a886f48 fpsr=00000000
-scvtf d7, w15 39d4db0931b25e927a9632b68f624628 527594f68adebded1af4c541ebe715af 0000000000000000c1b418ea51000000 85484a52397b894a1af4c541ebe715af fpsr=00000000
-scvtf s7, x15 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 0000000000000000000000005e00d00e 13a692ea909413e32034036b2540d210 fpsr=00000000
-scvtf d7, x15 7c44fda2c4f3ed4e66c03150c383fd2d 27c81bff702749760afcca34c46a4acc 000000000000000043a5f9946988d496 92478e7f987ac4720afcca34c46a4acc fpsr=00000000
-ucvtf s7, w15 2915227d7d3b3371fe1c6a2981899c14 b16fe6d6a518c184b9abfaffa9c65e42 0000000000000000000000004f29c65e e08c1f71338e7c57b9abfaffa9c65e42 fpsr=00000000
-ucvtf d7, w15 7be936badd6630980aa27329b5b3ecd2 d2bc96d6b1a87f5bc30eedfc43f567c8 000000000000000041d0fd59f2000000 fbc9f1302bfc1b23c30eedfc43f567c8 fpsr=00000000
-ucvtf s7, x15 6597ea0af6727713e0401415c692d5dd 3795df08065206478d94b3ff795f1228 0000000000000000000000005f0d94b4 e06c5cc8e1357d728d94b3ff795f1228 fpsr=00000000
-ucvtf d7, x15 4fd7e326d29b74541ae5bf20bcc2f9c2 549a65de5531bc5072bb7bf9cc326fbb 000000000000000043dcaedefe730c9c ed6bf4b500d2fe8f72bb7bf9cc326fbb fpsr=00000000
-abs d22, d23 190c026f4f4108bb97f152ac79a338e2 082a07b97ea580d954e0244c1dcf60e0 000000000000000054e0244c1dcf60e0 082a07b97ea580d954e0244c1dcf60e0 fpsr=00000000
-neg d22, d23 a29325444ec512a939c5af18dc96719b 35a6a7f8600f343f11658d574d95c3f7 0000000000000000ee9a72a8b26a3c09 35a6a7f8600f343f11658d574d95c3f7 fpsr=00000000
-abs v8.2d, v7.2dcccf2d05af86747edec1b4c5c4fa8650 3330d2fa50798b82213e4b3a3b0579b0 fpsr=00000000
-abs v8.4s, v7.4sc38dbdaccabb5bcc988bec41d1f55876 3c7242543544a434677413bf2e0aa78a fpsr=00000000
-abs v8.2s, v7.2s751dfa1352e40c98674442111330555e 0000000000000000674442111330555e fpsr=00000000
-abs v8.8h, v7.8h40c9e0a4e28cc38e27b63222a6b73935 40c91f5c1d743c7227b6322259493935 fpsr=00000000
-abs v8.4h, v7.4h4a5c32cf23cea86930f00f8bcd9f5fac 000000000000000030f00f8b32615fac fpsr=00000000
-abs v8.16b, v7.16b23de2e6573f9f357cd2f9fc5071aba58 23222e6573070d57332f613b071a4658 fpsr=00000000
-abs v8.8b, v7.8b16458560adcdd7091db23c3834cb4d4d 00000000000000001d4e3c3834354d4d fpsr=00000000
-neg v8.2d, v7.2d313cbec68670df4e1ab8e17b2178e568 cec34139798f20b2e5471e84de871a98 fpsr=00000000
-neg v8.4s, v7.4s17d247361590a45a8c419b68e9c69d73 e82db8caea6f5ba673be64981639628d fpsr=00000000
-neg v8.2s, v7.2s9a985ec5f0031343f3185309c7b360a0 00000000000000000ce7acf7384c9f60 fpsr=00000000
-neg v8.8h, v7.8h14dcfee0b45668b52a09854ad64de91c eb2401204baa974bd5f77ab629b316e4 fpsr=00000000
-neg v8.4h, v7.4he2e823f1fc15de5d0fe0ad1832a0f513 0000000000000000f02052e8cd600aed fpsr=00000000
-neg v8.16b, v7.16b6109ca6565cab2e77d69475df9b640b0 9ff7369b9b364e198397b9a3074ac050 fpsr=00000000
-neg v8.8b, v7.8beb8aeda98a0320fe506fd007449d8620 0000000000000000b09130f9bc637ae0 fpsr=00000000
-add d21, d22, d23 ddb98a28084c634f63bfc3013161828e 7e7d09937d452c872eb7cf99a14da407 94e09c4d7a2fb98594259c37dc0df227 0000000000000000c2dd6bd17d5b962e 7e7d09937d452c872eb7cf99a14da407 94e09c4d7a2fb98594259c37dc0df227 fpsr=00000000
-sub d21, d22, d23 bc4a103eacf98853bc63f107d94d1889 348ab47fa96b098734939ce54eb5d374 e6246ae1a4f77a426cd3657964fa47a9 0000000000000000c7c0376be9bb8bcb 348ab47fa96b098734939ce54eb5d374 e6246ae1a4f77a426cd3657964fa47a9 fpsr=00000000
-add v9.2d, v7.2d, v8.2d 329e49985ce0a08d4e504c0d1ea88aa7 e072c1566081a703100e83175782ed8c 13110aeebd6247905e5ecf24762b7833 fpsr=00000000
-add v9.4s, v7.4s, v8.4s 53a7ab02214be64e702ec38c9cf9ec6a 2e1c9d0c8757ad8f43446bb26e18386e 81c4480ea8a393ddb3732f3e0b1224d8 fpsr=00000000
-add v9.2s, v7.2s, v8.2s f4bac99b8dc500224c09e6f9f4b7ac8c 3637c27a144a5b20f8ab9814aff9c5f0 000000000000000044b57f0da4b1727c fpsr=00000000
-add v9.8h, v7.8h, v8.8h 5e28e61e7d9809fed89f25ffb69a16f0 dc31117d86c46bc9c3241e0a49fd7e17 3a59f79b045c75c79bc3440900979507 fpsr=00000000
-add v9.4h, v7.4h, v8.4h b6a224a9b26dfb35eb12d4ad50bc53dc e9dd4c503b8c78011defefc04a5c2f46 00000000000000000901c46d9b188322 fpsr=00000000
-add v9.16b, v7.16b, v8.16b 026a179172ccfc9a5caddec3a1b08243 7c4dbf374346e632cf6e8a894c18cbde 7eb7d6c8b512e2cc2b1b684cedc84d21 fpsr=00000000
-add v9.8b, v7.8b, v8.8b ae69f33c480a53cab65d9cff1df10031 7db5feb724386535623ea06909e69bf4 0000000000000000189b3c6826d79b25 fpsr=00000000
-sub v9.2d, v7.2d, v8.2d 53ca44aebd31b5254262bdc16b771596 b0e63d866320c355ed98b4a9e8d6e4c1 a2e407285a10f1d054ca091782a030d5 fpsr=00000000
-sub v9.4s, v7.4s, v8.4s 39df4ba2b0883fa0f57ab3b51afb0c56 fb4f5f827e66bca6095bd91417c2934b 3e8fec20322182faec1edaa10338790b fpsr=00000000
-sub v9.2s, v7.2s, v8.2s 84562c36ddb9ea8ea8c8d0e79a950eb5 23c025e6d5d2e99c2ac801d7a6e270f6 00000000000000007e00cf10f3b29dbf fpsr=00000000
-sub v9.8h, v7.8h, v8.8h 3d42e9e6e5cb90a60fca48c537bd2658 cf6c3250a58dc60da980fe7f83ce2785 6dd6b796403eca99664a4a46b3effed3 fpsr=00000000
-sub v9.4h, v7.4h, v8.4h 4912638e4626edfac3622c1b224d3e43 87e109bc0d20ad2cba8283f87c7f421f 000000000000000008e0a823a5cefc24 fpsr=00000000
-sub v9.16b, v7.16b, v8.16b 6f975f6b5d959b0038d06f14677d22db b0100d870c73d98e7631228f404d2c47 bf8752e45122c272c29f4d852730f694 fpsr=00000000
-sub v9.8b, v7.8b, v8.8b 56017d1a6a3e158cc6b5e33ff7e57be5 914b7f6c80ce6328d14c4ff05df12fe2 0000000000000000f569944f9af44c03 fpsr=00000000
-addhn v9.2s, v7.2d, v8.2d 83e142978babb4d3a4113b879f7ed584 5040828927db464ea3f35b2742837634 0000000000000000d421c520480496ae fpsr=00000000
-addhn2 v9.4s, v7.2d, v8.2d 5e270e3ebfc4b369e7450a380da0993e f502195aa1a15db4a2a879a23d7c0ae2 5329279989ed83da33c9ac40c2027b6e fpsr=00000000
-addhn v9.4h, v7.4s, v8.4s 2c2526cce3d22e428611c200d10412f6 640027bc6b896370654abc2d7db4d8f1 000000000000000090254f5beb5c4eb8 fpsr=00000000
-addhn2 v9.8h, v7.4s, v8.4s 168aaa5db77c1eb35895b6ea59c26bf2 660b6deae45bf2f5621a15f41064a8c4 7c969bd8baaf6a27e77616637239f19e fpsr=00000000
-addhn v9.8b, v7.8h, v8.8h 20669f6fdacc5d7113531763f353aed5 a0538e824a418418f0b95884e5242620 0000000000000000c02d25e1046fd8d4 fpsr=00000000
-addhn2 v9.16b, v7.8h, v8.8h 312ce5ddc92aa7904e2af939ce90c5a5 996a0d80bdc2740e452737c8cbeddc2b caf3861b93319aa1dc95746e47878c59 fpsr=00000000
-subhn v9.2s, v7.2d, v8.2d 11aa41e4e25f96857f5b4e96f8b07cc6 b83e4c403ac7fc6a78c5450f6f173567 0000000000000000596bf5a406960987 fpsr=00000000
-subhn2 v9.4s, v7.2d, v8.2d 651153206692a424fc88e808604c7cfc 42228e7fa19937237e53f304605c7bbb 22eec4a07e34f50346a8d94636311f44 fpsr=00000000
-subhn v9.4h, v7.4s, v8.4s b3f2a08f714e2da1fdaf7a7cd45d516c 5fc5f55aaedf1f8b30f295b30ed2d86a 0000000000000000542cc26fccbcc58a fpsr=00000000
-subhn2 v9.8h, v7.4s, v8.4s 643e888b037969929732973d033b649a 1438844d02a38f5943215d8ac5f35818 500600d554113d4858335bce32797f02 fpsr=00000000
-subhn v9.8b, v7.8h, v8.8h bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 00000000000000007132df327553c51b fpsr=00000000
-subhn2 v9.16b, v7.8h, v8.8h e3b7188215a149fe53ac1abaaba25024 c5af844c56a6d2d3c616893fedf747e7 1e94be778d91bd0847bb0dec2ea57f37 fpsr=00000000
-raddhn v9.2s, v7.2d, v8.2d dea5e516f24fc282024505efe2bb5e68 2cb55931f3d6b9c803bdb2d65bac2c31 00000000000000000b5b3e490602b8c6 fpsr=00000000
-raddhn2 v9.4s, v7.2d, v8.2d 957f97690fcf998c647b85644dc3143d 078c20e1106551b53bb68b07cdad1dcc 9d0bb84aa032106c46c4038221f7f388 fpsr=00000000
-raddhn v9.4h, v7.4s, v8.4s ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 0000000000000000893d782875f4ef48 fpsr=00000000
-raddhn2 v9.8h, v7.4s, v8.4s 2f9b99a465c8ac61fd23ec1fdce48589 8ed3ed6fa5a46224d78477c55858ae69 be700b6dd4a8353d8ad25076fcb5b098 fpsr=00000000
-raddhn v9.8b, v7.8h, v8.8h 409d0d24fbf1bd35c23659debd8d75ea a9435828b945f0ef083a4f0c6dd2c295 0000000000000000ea65b5aecaa92b38 fpsr=00000000
-raddhn2 v9.16b, v7.8h, v8.8h 650eb2968b4fd6a0532863cf4c4877ad 10877f5c87275943cf05615f813bcd64 7632123022c5ce4547680aaab4228a0b fpsr=00000000
-rsubhn v9.2s, v7.2d, v8.2d e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc 00000000000000003d2f84cfe8f4c014 fpsr=00000000
-rsubhn2 v9.4s, v7.2d, v8.2d ebdd75a5f6276c6e9a0dfe589133bc4c 3fad6a0b2cb3893654bc5db73e9c4e61 ac300b9b4551a0a1b10a44033e825486 fpsr=00000000
+fmls v2.2s, v11.2s, v29.s[0] a9430469f9a6aaf90d07193d2e134034 e0fd1393714954977124406c74e81e7a d52f1cc78e47c9e383314ed9438203c8 0000000000000000f526d648f8ebc5cf e0fd1393714954977124406c74e81e7a d52f1cc78e47c9e383314ed9438203c8 fpsr=00000000
+fmls v2.2s, v11.2s, v29.s[3] 7d772f10f5706b75304780122c8b69f0 3b947b8f0a536415b779aada6ea680b0 e82632fc79b30f1483e79bb67d116120 0000000000000000e02216827f800000 3b947b8f0a536415b779aada6ea680b0 e82632fc79b30f1483e79bb67d116120 fpsr=00000000
+fmov v22.2d, #0.125 b71315802c502c586d5043a8665c8797 d4eaedef93c21b55bdb0c6ce36392d36 3fc00000000000003fc0000000000000 d4eaedef93c21b55bdb0c6ce36392d36 fpsr=00000000
+fmov v22.2d, #-4.0 98bf1ba36919393bc4d999db7390839e 44d5584589abea635dc49b10189f4c14 c010000000000000c010000000000000 44d5584589abea635dc49b10189f4c14 fpsr=00000000
+fmov v22.2d, #1.0 45a92ebc1d99f6f68da34afe4ed3935a 0b0b9f6018e987aeba97106bb88dbd45 3ff00000000000003ff0000000000000 0b0b9f6018e987aeba97106bb88dbd45 fpsr=00000000
+fmov d22, d23 71a6062013b6eaf839f583c290e85d6f 0beca39f21ddd399b28a073ef6656128 0000000000000000b28a073ef6656128 0beca39f21ddd399b28a073ef6656128 fpsr=00000000
+fmov s22, s23 fe1783322bd1f4a0a92e2587172ec23f 22d9446284e6ae8126fc5ee9b286181e 000000000000000000000000b286181e 22d9446284e6ae8126fc5ee9b286181e fpsr=00000000
+fmov s7, w15 ca5b844f4549f54ebdaf0fabc405a22a 3131620a2265f8c8f64df6cdcb51c286 000000000000000000000000cb51c286 dc2316810c4e5dddf64df6cdcb51c286 fpsr=00000000
+fmov d7, x15 b6d3ebd9407ecd6355d7239077cddd8e 1854ddf6d8b991ce01deaf4923243fc0 000000000000000001deaf4923243fc0 4210b3d32431d14601deaf4923243fc0 fpsr=00000000
+fmov v7.d[1], x15 a2de962ffdd15c3e50063f9610e753cd b7a39486894259f1290e68be98626e2d 290e68be98626e2d50063f9610e753cd d1587d7aa579647d290e68be98626e2d fpsr=00000000
+fmov w15, s7 6ddc67b25da28240909c451c6eb3e447 ee7d691b146130944d3d038a0b69312c 6ddc67b25da28240909c451c6eb3e447 685c54d57186f6e2000000006eb3e447 fpsr=00000000
+fmov x15, d7 f92e3cc13e4f1fc8f3fa1382738f705b 9c423a145875f5144ccc5e105c99661d f92e3cc13e4f1fc8f3fa1382738f705b e77b184466b967d6f3fa1382738f705b fpsr=00000000
+fmov x15, v7.d[1] 2533f6bc813a13365b808a28feded669 a353e8d137de89d3071b5bad6b52ee61 2533f6bc813a13365b808a28feded669 2d16a827667197b82533f6bc813a1336 fpsr=00000000
+fmov d22, #0.125 d04b750405c33deba68d8a6feefdf8d2 e11053b38ffdcd305e88d8c318f5aa57 00000000000000003fc0000000000000 e11053b38ffdcd305e88d8c318f5aa57 fpsr=00000000
+fmov d22, #-4.0 dbd798f8ac487f46b581f3b7244eb4f5 37d75b1941319f8c3175b6b243e17860 0000000000000000c010000000000000 37d75b1941319f8c3175b6b243e17860 fpsr=00000000
+fmov d22, #1.0 850ae0642ddae0466041d5d9cb7738db 2af3bd4b509e6608a513cfe482162be8 00000000000000003ff0000000000000 2af3bd4b509e6608a513cfe482162be8 fpsr=00000000
+fmov s22, #0.125 ab09c2f3335970becb4d15989216cc28 b903f1b29f411487312d32f1bb069e61 0000000000000000000000003e000000 b903f1b29f411487312d32f1bb069e61 fpsr=00000000
+fmov s22, #-4.0 8932e026330d2e5552f8564f761e13a8 b8d75a9620326a7d927f8ecd4a783d65 000000000000000000000000c0800000 b8d75a9620326a7d927f8ecd4a783d65 fpsr=00000000
+fmov s22, #-1.0 06ced856b4d04648a668c3da0fcbe652 39d4db0931b25e927a9632b68f624628 000000000000000000000000bf800000 39d4db0931b25e927a9632b68f624628 fpsr=00000000
+fmul v2.2d, v11.2d, v29.d[0] 85484a52397b894a4f49b178e95f7a8a 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 5693b6e02c47d98dbaf8482ca49a4e8f 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 fpsr=00000000
+fmul v2.2d, v11.2d, v29.d[1] 27c81bff702749760afcca34c46a4acc b00b3cdf75747e60035ee161b2ddaa1e 92478e7f987ac472db7137e460cce35a 02640d0b57656ea48000000000000000 b00b3cdf75747e60035ee161b2ddaa1e 92478e7f987ac472db7137e460cce35a fpsr=00000000
+fmul v2.4s, v11.4s, v29.s[0] e08c1f71338e7c577f778f72bc6577b1 7be936badd6630980aa27329b5b3ecd2 d2bc96d6b1a87f5bc30eedfc43f567c8 7f800000e1dca9d30f1bba11ba2c7a96 7be936badd6630980aa27329b5b3ecd2 d2bc96d6b1a87f5bc30eedfc43f567c8 fpsr=00000000
+fmul v2.4s, v11.4s, v29.s[3] 3795df08065206478d94b3ff795f1228 6c7f80e89ebd80a5e34bca20163ac21e e06c5cc8e1357d72cece7967d1f50cd5 ff8000003faef7467f800000b72c6ea3 6c7f80e89ebd80a5e34bca20163ac21e e06c5cc8e1357d72cece7967d1f50cd5 fpsr=00000000
+fmul v2.2s, v11.2s, v29.s[0] ed6bf4b500d2fe8f552735a28721f705 190c026f4f4108bb97f152ac79a338e2 082a07b97ea580d954e0244c1dcf60e0 000000000000000080000006580438c3 190c026f4f4108bb97f152ac79a338e2 082a07b97ea580d954e0244c1dcf60e0 fpsr=00000000
+fmul v2.2s, v11.2s, v29.s[3] 35a6a7f8600f343f11658d574d95c3f7 35954eb164b81a015d181eb0d13422c0 fefa2b0bfdbeddb488c900901dc5368c 0000000000000000ff8000007f800000 35954eb164b81a015d181eb0d13422c0 fefa2b0bfdbeddb488c900901dc5368c fpsr=00000000
+fmul d2, d11, d29 c34a8a359bcdfb7cf3d1cf04bdfd4aa3 751dfa1352e40c98674442111330555e 76df5c23d344e7279f0d2317c41d637d 0000000000000000c6627216c7b45376 751dfa1352e40c98674442111330555e 76df5c23d344e7279f0d2317c41d637d fpsr=00000000
+fmul s2, s11, s29 8da998f88c8b32a6eaf8d1b431daa560 23de2e6573f9f357cd2f9fc5071aba58 c8746293ddf96221a55f780d618fa50b 000000000000000000000000292da3b0 23de2e6573f9f357cd2f9fc5071aba58 c8746293ddf96221a55f780d618fa50b fpsr=00000000
+fmul v9.2d, v7.2d, v8.2d bafa353551a2546746b48a7dd8000fc0 17d247361590a45a8c419b68e9c69d73 92ddf080af5794de93069aaa08ee51e6 fpsr=00000000
+fmul v9.4s, v7.4s, v8.4s 9a985ec5f0031343f3185309c7b360a0 16da21aeefac01e48b55d9bb9a9e8466 800000007f8000003efe7d4822de24d0 fpsr=00000000
+fmul v9.2s, v7.2s, v8.2s ef3804f7e2035f7c3d1ff6252d13375a e2e823f1fc15de5d0fe0ad1832a0f513 00000000000000000d8c638920391f0e fpsr=00000000
+fcvtn v22.2s, v23.2d 6109ca6565cab2e77d69475df9b640b0 c34d90bb1a1256ba10a38a2b40833c5f 0000000000000000da6c85d900000000 c34d90bb1a1256ba10a38a2b40833c5f fpsr=00000000
+fcvtn2 v22.4s, v23.2d ddb98a28084c634f63bfc3013161828e 7e7d09937d452c872eb7cf99a14da407 7f8000000000000063bfc3013161828e 7e7d09937d452c872eb7cf99a14da407 fpsr=00000000
+scvtf s7, w15 6a4d20867d3a5b4dbd6dd8955fad8f17 02284fdfe9fec14278baa5d030d04fb1 0000000000000000000000004e43413f 348ab47fa96b098778baa5d030d04fb1 fpsr=00000000
+scvtf d7, w15 e6246ae1a4f77a426cd3657964fa47a9 2daf41013f9df44bce0cec2fcc6d1cbd 0000000000000000c1c9c971a1800000 48e3f1cf4820c03bce0cec2fcc6d1cbd fpsr=00000000
+scvtf s7, x15 329e49985ce0a08d4e504c0d1ea88aa7 e072c1566081a703100e83175782ed8c 0000000000000000000000005d807419 53a7ab02214be64e100e83175782ed8c fpsr=00000000
+scvtf d7, x15 2e1c9d0c8757ad8f43446bb26e18386e fbcfad402a0ab8c91e1f4ce7b072a07d 000000000000000043be1f4ce7b072a0 3637c27a144a5b201e1f4ce7b072a07d fpsr=00000000
+ucvtf s7, w15 bafd469c03bb81a72d0fa3c734a93060 5e28e61e7d9809fed89f25ffb69a16f0 0000000000000000000000004f369a17 d1f115970180fe0fd89f25ffb69a16f0 fpsr=00000000
+ucvtf d7, w15 b6a224a9b26dfb35eb12d4ad50bc53dc e9dd4c503b8c78011defefc04a5c2f46 000000000000000041d2970bd1800000 026a179172ccfc9a1defefc04a5c2f46 fpsr=00000000
+ucvtf s7, x15 7c4dbf374346e632cf6e8a894c18cbde 2c59ee263f9ae6eb5ef02a0e24fd533c 0000000000000000000000005ebde054 7db5feb7243865355ef02a0e24fd533c fpsr=00000000
+ucvtf d7, x15 f6d81f33742433f2cc7dd6bb9c2cca19 53ca44aebd31b5254262bdc16b771596 000000000000000043d098af705addc5 09e4bb78a81214674262bdc16b771596 fpsr=00000000
+abs d22, d23 39df4ba2b0883fa0f57ab3b51afb0c56 fb4f5f827e66bca6095bd91417c2934b 0000000000000000095bd91417c2934b fb4f5f827e66bca6095bd91417c2934b fpsr=00000000
+neg d22, d23 23c025e6d5d2e99c2ac801d7a6e270f6 02471f026197d9cd943b5e67093fabba 00000000000000006bc4a198f6c05446 02471f026197d9cd943b5e67093fabba fpsr=00000000
+abs v8.2d, v7.2d95de8b5fc46113474bc49f812043d857 6a2174a03b9eecb94bc49f812043d857 fpsr=00000000
+abs v8.4s, v7.4s87e109bc0d20ad2cba8283f87c7f421f 781ef6440d20ad2c457d7c087c7f421f fpsr=00000000
+abs v8.2s, v7.2s6f975f6b5d959b0038d06f14677d22db 000000000000000038d06f14677d22db fpsr=00000000
+abs v8.8h, v7.8ha94b87d74f4b1970a17adfc3fe4a32b8 56b578294f4b19705e86203d01b632b8 fpsr=00000000
+abs v8.4h, v7.4h914b7f6c80ce6328d14c4ff05df12fe2 00000000000000002eb44ff05df12fe2 fpsr=00000000
+abs v8.16b, v7.16b83e142978babb4d3a4113b879f7ed584 7d1f426975554c2d5c113b79617e2b7c fpsr=00000000
+abs v8.8b, v7.8bdb5accc20d6d491ef5972073e0fedfcb 00000000000000000b69207320022135 fpsr=00000000
+neg v8.2d, v7.2df502195aa1a15db4a2a879a23d7c0ae2 0afde6a55e5ea24c5d57865dc283f51e fpsr=00000000
+neg v8.4s, v7.4s2c2526cce3d22e428611c200d10412f6 d3dad9341c2dd1be79ee3e002efbed0a fpsr=00000000
+neg v8.2s, v7.2sde0fee83708cf6737d9e7877b9a3b333 000000000000000082618789465c4ccd fpsr=00000000
+neg v8.8h, v7.8h660b6deae45bf2f5621a15f41064a8c4 99f592161ba50d0b9de6ea0cef9c573c fpsr=00000000
+neg v8.4h, v7.4h20669f6fdacc5d7113531763f353aed5 0000000000000000ecade89d0cad512b fpsr=00000000
+neg v8.16b, v7.16b676d807dee6a75966a13f9b17d7d8194 9993808312968b6a96ed074f83837f6c fpsr=00000000
+neg v8.8b, v7.8b996a0d80bdc2740e452737c8cbeddc2b 0000000000000000bbd9c938351324d5 fpsr=00000000
+add d21, d22, d23 11aa41e4e25f96857f5b4e96f8b07cc6 b83e4c403ac7fc6a78c5450f6f173567 2a781815facd19a8f37bb80620d01d92 00000000000000006c40fd158fe752f9 b83e4c403ac7fc6a78c5450f6f173567 2a781815facd19a8f37bb80620d01d92 fpsr=00000000
+sub d21, d22, d23 b3f2a08f714e2da1fdaf7a7cd45d516c 5fc5f55aaedf1f8b30f295b30ed2d86a db3648af097836cf4a5aca5a97e15cd2 0000000000000000e697cb5876f17b98 5fc5f55aaedf1f8b30f295b30ed2d86a db3648af097836cf4a5aca5a97e15cd2 fpsr=00000000
+add v9.2d, v7.2d, v8.2d bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 07306f0815aab7891095104d3236e538 fpsr=00000000
+add v9.4s, v7.4s, v8.4s e3b7188215a149fe53ac1abaaba25024 c5af844c56a6d2d3c616893fedf747e7 a9669cce6c481cd119c2a3f99999980b fpsr=00000000
+add v9.2s, v7.2s, v8.2s dea5e516f24fc282024505efe2bb5e68 2cb55931f3d6b9c803bdb2d65bac2c31 00000000000000000602b8c53e678a99 fpsr=00000000
+add v9.8h, v7.8h, v8.8h 957f97690fcf998c647b85644dc3143d 078c20e1106551b53bb68b07cdad1dcc 9d0bb84a2034eb41a031106b1b703209 fpsr=00000000
+add v9.4h, v7.4h, v8.4h ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 000000000000000075f33262ef47c343 fpsr=00000000
+add v9.16b, v7.16b, v8.16b 2f9b99a465c8ac61fd23ec1fdce48589 8ed3ed6fa5a46224d78477c55858ae69 bd6e86130a6c0e85d4a763e4343c33f2 fpsr=00000000
+add v9.8b, v7.8b, v8.8b 409d0d24fbf1bd35c23659debd8d75ea a9435828b945f0ef083a4f0c6dd2c295 0000000000000000ca70a8ea2a5f377f fpsr=00000000
+sub v9.2d, v7.2d, v8.2d 650eb2968b4fd6a0532863cf4c4877ad 10877f5c87275943cf05615f813bcd64 5487333a04287d5d8423026fcb0caa49 fpsr=00000000
+sub v9.4s, v7.4s, v8.4s e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc 3d2f84cf6674ba63e8f4c01557601dda fpsr=00000000
+sub v9.2s, v7.2s, v8.2s ebdd75a5f6276c6e9a0dfe589133bc4c 3fad6a0b2cb3893654bc5db73e9c4e61 00000000000000004551a0a152976deb fpsr=00000000
randV128: 512 calls, 530 iters
-rsubhn v9.4h, v7.4s, v8.4s 78fcbada2d54bed9dca1146904f43511 7490935e9f4d651fe1890b76e4653ab7 0000000000000000046c8e07fb18208f fpsr=00000000
-rsubhn2 v9.8h, v7.4s, v8.4s 740c78331916c2ee0656d19da0e92b0a d04842df070a47229d2e7eb283be0602 a3c4120c69281d2bfc3d11658d19e2ac fpsr=00000000
-rsubhn v9.8b, v7.8h, v8.8h a7dc73ed183713208e6e2a227349679c b9c7d9eb61d469d49e0a48b8c8011cc8 0000000000000000ee9ab6a9f0e1ab4b fpsr=00000000
-rsubhn2 v9.16b, v7.8h, v8.8h b59e4ea568df2b44ca89f0846cae958b 765d9b3d8cf2e62adcdeda3442e5c8ed 3fb3dc45ee162acd5b8587b3952b0921 fpsr=00000000
-addp d22, v23.2d 27e28a572897658ef2a6d6ae590f40fd 2ebbabf3470db8782ccb8833608433b6 00000000000000005b873426a791ec2e 2ebbabf3470db8782ccb8833608433b6 fpsr=00000000
-addp v9.2d, v7.2d, v8.2d e7f00989302dba7246518421715669c6 b6badcdef8a78c420365b8d34bfc9c8a ba2095b244a428cc2e418daaa1842438 fpsr=00000000
-addp v9.4s, v7.4s, v8.4s 876d9bdcc5bca72ebf51e0cba2325322 dea946e0b179bef5361cb20c2785c541 902305d55da2774d4d2a430a618433ed fpsr=00000000
-addp v9.2s, v7.2s, v8.2s d50420276581181f0f0b8f5d0353bc2f 0bb64f05552e696e2762baa7a1d0708a 0000000000000000c9332b31125f4b8c fpsr=00000000
-addp v9.8h, v7.8h, v8.8h 77e43d084fa5891a8b20646381504fb2 84323c09c110a7a3ccf943504995e94a c03b68b3104932dfb4ecd8bfef83d102 fpsr=00000000
-addp v9.4h, v7.4h, v8.4h f49e747ba1b053546a8f11cbec2196ce 6fce2e08b6c871e8fc009f148dec59c5 00000000000000009b14e7b17c5a82ef fpsr=00000000
-addp v9.16b, v7.16b, v8.16b b32227dc5a8cb261c3bb28e1f220fb09 d399277fd05ca4f26ef8025fbb4dcba1 6ca62c966661086cd503e6137e091204 fpsr=00000000
-addp v9.8b, v7.8b, v8.8b fac199e95780c0368c621d512005ca47 97050b4a8f37f9d4b7c27dfe029229e0 0000000000000000797b9409ee6e2511 fpsr=00000000
-addv s22, v23.4s ef2cecbc583577269ca64127e7e72ccc 81e19ba751200b054e9e031d71f33fe9 0000000000000000000000009392e9b2 81e19ba751200b054e9e031d71f33fe9 fpsr=00000000
-addv h22, v23.8h 37607b3155405557892d6649f507b77e 0fbdaa1a958555027b09baf22fda37cd 00000000000000000000000000004200 0fbdaa1a958555027b09baf22fda37cd fpsr=00000000
-addv h22, v23.4h ae17ffe2435999be0baa45fb18692c7b 86b5a6a102107e8ef40422303b1b9254 0000000000000000000000000000e3a3 86b5a6a102107e8ef40422303b1b9254 fpsr=00000000
-addv b22, v23.16b c4276f9d7a2066089aed1b36751530dd a5d2c97f7788bae1eca9a838c108ae44 00000000000000000000000000000089 a5d2c97f7788bae1eca9a838c108ae44 fpsr=00000000
-addv b22, v23.8b aa75e46ddb16edd04b278464bc28f0c8 a936258b9666b4d4f37549976fb022ff 00000000000000000000000000000088 a936258b9666b4d4f37549976fb022ff fpsr=00000000
-and v9.16b, v7.16b, v8.16b 19fee7710650f247e80f3f1bf2b5b476 ec6d05a4b6a1a4cd9e88325743eb11d5 086c05200600a0458808321342a11054 fpsr=00000000
-and v9.8b, v7.8b, v8.8b eb961e83edc02ffa57cb79e901fcadd7 ef23560adb3157cc50072abaf61c5a46 0000000000000000500328a8001c0846 fpsr=00000000
-bic v9.16b, v7.16b, v8.16b 270ecc3cebbd43a2f727286eebfe18c9 727e8a02b5bb9511dbbd140db245d8e8 0500443c4a0442a22402286249ba0001 fpsr=00000000
-bic v9.8b, v7.8b, v8.8b b2d6d57a7db0e9535f056177dd93e04f fd0f238763c9b9d176aaa13e475e17e0 0000000000000000090540419881e00f fpsr=00000000
-orr v9.16b, v7.16b, v8.16b 52bffb790361bc8206a61431e6f4cfcd f4c785f8e443fea0362f659862c280b3 f6fffff9e763fea236af75b9e6f6cfff fpsr=00000000
-orr v9.8b, v7.8b, v8.8b b0f9e0d5b9fa370241a91527f6b99009 a0f5f10f15717d72120cd2c993275e44 000000000000000053add7eff7bfde4d fpsr=00000000
-orn v9.16b, v7.16b, v8.16b 5015078bc002b309470f1546d9dbad27 264b8be9b6fd329ce1613adc48a6dcd9 d9b5779fc902ff6b5f9fd567ffdbaf27 fpsr=00000000
-orn v9.8b, v7.8b, v8.8b 9a04d2f816626c2c2f38a8db40b290ab 8dd9540466eef7d359b0d13fcfb80416 0000000000000000af7faedb70f7fbeb fpsr=00000000
-orr v22.8h, #0x5A, LSL #0 d31583d898627c5eefe64192b7f7857a bc0f303ba1ad862b11d8a7bd5735c0ff d35f83da987a7c5eeffe41dab7ff857a bc0f303ba1ad862b11d8a7bd5735c0ff fpsr=00000000
-orr v22.8h, #0xA5, LSL #8 78bee0cbc8037a197f1bb183ee56dcf9 3e8e322a4ff6b6d1b75f0f9fb4e98c0d fdbee5cbed03ff19ff1bb583ef56fdf9 3e8e322a4ff6b6d1b75f0f9fb4e98c0d fpsr=00000000
-orr v22.4h, #0x5A, LSL #0 a6a3c9f2c2e8f683fbfe73fd132e3739 15a929c7b1735a67b7d0887be445bb91 0000000000000000fbfe73ff137e377b 15a929c7b1735a67b7d0887be445bb91 fpsr=00000000
-orr v22.4h, #0xA5, LSL #8 e266a78d90ffdc91cea49ae5c06573d8 725aaa117e7599eb792f879592071e89 0000000000000000efa4bfe5e565f7d8 725aaa117e7599eb792f879592071e89 fpsr=00000000
-orr v22.4s, #0x5A, LSL #0 8737670045ac078c562d87a75d3333b4 db00a0567c2a86afc40047f4038de9d3 8737675a45ac07de562d87ff5d3333fe db00a0567c2a86afc40047f4038de9d3 fpsr=00000000
-orr v22.4s, #0x6B, LSL #8 349f42f2e67983ac302a67122627dc71 216a7d91960bd145f0fdfb1c6ec3212c 349f6bf2e679ebac302a6f122627ff71 216a7d91960bd145f0fdfb1c6ec3212c fpsr=00000000
-orr v22.4s, #0x49, LSL #16 58f31949403befabe5870936cd45f720 96584f08a2f98312aff067d5f03b44cf 58fb1949407befabe5cf0936cd4df720 96584f08a2f98312aff067d5f03b44cf fpsr=00000000
-orr v22.4s, #0x3D, LSL #24 d592cd65355229e856a34b7132ed6522 dadbd02a2efc4a4c3cb79f06723292b0 fd92cd653d5229e87fa34b713fed6522 dadbd02a2efc4a4c3cb79f06723292b0 fpsr=00000000
-orr v22.2s, #0x5A, LSL #0 913d502c107e9cd06a3eec76b56ecb74 3edf14402e48bffaabe616bb98dc80c1 00000000000000006a3eec7eb56ecb7e 3edf14402e48bffaabe616bb98dc80c1 fpsr=00000000
-orr v22.2s, #0x6B, LSL #8 d6f4419831d4c3802458c320b8e9ef36 2a1fe48bf7d8b25706c5dff7abfe7295 00000000000000002458eb20b8e9ef36 2a1fe48bf7d8b25706c5dff7abfe7295 fpsr=00000000
-orr v22.2s, #0x49, LSL #16 cbafa6c1c5b8d1e7f3e9d3da51267dc3 7ef922696a0f05c22cb3d81c8dfb468b 0000000000000000f3e9d3da516f7dc3 7ef922696a0f05c22cb3d81c8dfb468b fpsr=00000000
-orr v22.2s, #0x3D, LSL #24 50cd6006aa89a564b651fc046084577a 1acfac3d674a969cff10e3891c30dd04 0000000000000000bf51fc047d84577a 1acfac3d674a969cff10e3891c30dd04 fpsr=00000000
-bic v22.8h, #0x5A, LSL #0 45af4ec7c2a821574df11effc5645bbb de016364cdeb46445e3dde9f39ff175e 45a54e85c2a021054da11ea5c5245ba1 de016364cdeb46445e3dde9f39ff175e fpsr=00000000
-bic v22.8h, #0xA5, LSL #8 8ab45265eb7423219729192a5f256ae7 aaee27407e51f51a2899aabdc5c8d4fc 0ab452654a7402211229182a5a254ae7 aaee27407e51f51a2899aabdc5c8d4fc fpsr=00000000
-bic v22.4h, #0x5A, LSL #0 ff3c4b3f064d8c217557cde51027645d 5df6d73059dd837e3e8527449ee9f43b 00000000000000007505cda510256405 5df6d73059dd837e3e8527449ee9f43b fpsr=00000000
-bic v22.4h, #0xA5, LSL #8 83a818b6f3943cb7c8dd1991b6cb297d d97955953deed0d281603593a4c5577d 000000000000000048dd189112cb087d d97955953deed0d281603593a4c5577d fpsr=00000000
-bic v22.4s, #0x5A, LSL #0 fcd880ce0be4bb73cf8ab30ab9b9dc22 51c6f6af2a1de39526bc45f7a76187ef fcd880840be4bb21cf8ab300b9b9dc20 51c6f6af2a1de39526bc45f7a76187ef fpsr=00000000
-bic v22.4s, #0x6B, LSL #8 a773373ba32026c309648309bc276589 124ecb70f79979a7ae01844088bd7bbe a773143ba32004c309648009bc270489 124ecb70f79979a7ae01844088bd7bbe fpsr=00000000
-bic v22.4s, #0x49, LSL #16 baa85b3de501ef210e4d83f18c6ed012 f209069ea7d3e520baedeb496f09ca07 baa05b3de500ef210e0483f18c26d012 f209069ea7d3e520baedeb496f09ca07 fpsr=00000000
-bic v22.4s, #0x3D, LSL #24 15dacc33b1e8f8eec0a594220beffe1d d2588598182a085f2ae05c723ca7542a 00dacc3380e8f8eec0a5942202effe1d d2588598182a085f2ae05c723ca7542a fpsr=00000000
-bic v22.2s, #0x5A, LSL #0 919b29bf2bfec2c5dd3bb51ccef7f987 ae2d4071b09e34d197ade8b4986d6b05 0000000000000000dd3bb504cef7f985 ae2d4071b09e34d197ade8b4986d6b05 fpsr=00000000
-bic v22.2s, #0x6B, LSL #8 1130d272c0b0f3b1b55dd7a60757997f 5136e60ea8b68eb60aff985d1d21b4da 0000000000000000b55d94a60757907f 5136e60ea8b68eb60aff985d1d21b4da fpsr=00000000
-bic v22.2s, #0x49, LSL #16 30796011b79f7a8390a6a371c6291371 4c8b686f3a23b6d93a12e81f605f5002 000000000000000090a6a371c6201371 4c8b686f3a23b6d93a12e81f605f5002 fpsr=00000000
-bic v22.2s, #0x3D, LSL #24 d0d6b3fdf02b399c4f77f7dceacd49be 7e8ba7f547468d9a0543b959418620dc 00000000000000004277f7dcc2cd49be 7e8ba7f547468d9a0543b959418620dc fpsr=00000000
-bif v9.16b, v7.16b, v8.16b cfa6ab954bb50e5bd22fb34754a219c5 c89783ffad7ef35a4cf4eb6ba0f602c9 8f372b70cbd7df43d26b7b6fd45419cc fpsr=00000000
-bif v9.8b, v7.8b, v8.8b 1c9fc204c8c052c704da5f3444a81014 0e492839a79cda20f92eb913e40864e6 0000000000000000edd45e3644a05430 fpsr=00000000
-bit v9.16b, v7.16b, v8.16b 8c280e5e7c11533370670d2b81b02e0f ee30cd29d94c9218e8bf66df043a1230 8d2f0c4a7e017f5464678c0b7a700a82 fpsr=00000000
-bit v9.8b, v7.8b, v8.8b 2450922107afec54cd54f29957327e59 0f7c166980b896167145c55bed24b56c 00000000000000004956fa99552176cb fpsr=00000000
-bsl v9.16b, v7.16b, v8.16b cc893028e602d73eb2831f4bf609ebf8 f6be84f8bb673f4fc8c387756fbfd9bd f4ad9428ae43572e88839769ffadf9fc fpsr=00000000
-bsl v9.8b, v7.8b, v8.8b 4aa3aaaf78d5b0659635886e6d6a3f50 0be77b318842c856059940783863e7a8 000000000000000097b988783d632718 fpsr=00000000
-eor v9.16b, v7.16b, v8.16b 44cea455fc4eef9fce09fd8da9f12525 94463cd1c7914d221e876212d6c92a13 d08898843bdfa2bdd08e9f9f7f380f36 fpsr=00000000
-eor v9.8b, v7.8b, v8.8b 419ca01490f7f11f910033957a94279b b78debf535fec705eaad3f4eb709cd41 00000000000000007bad0cdbcd9deada fpsr=00000000
-cls v8.4s, v7.4sa8fb004a32b8ef7bf67abbd38dacaf39 00000000000000010000000300000000 fpsr=00000000
-cls v8.2s, v7.2s392f0631401ae5027aa91a00bcc34007 00000000000000000000000000000000 fpsr=00000000
-cls v8.8h, v7.8hc773fa18fab0e4465406d6c1605a3bd8 00010004000400020000000100000001 fpsr=00000000
-cls v8.4h, v7.4hac14d76afd052af45e5d6d02967e5ed8 00000000000000000000000000000000 fpsr=00000000
-cls v8.16b, v7.16b455d9993e4a5f1b876795aaf7a3a6332 00000000020003000000000000010001 fpsr=00000000
-cls v8.8b, v7.8bee9c3c004c1c753e762819b5269b0613 00000000000000000001020001000402 fpsr=00000000
-clz v8.4s, v7.4s031cbc1bd0f7f4313c3427feb9ab05a7 00000006000000000000000200000000 fpsr=00000000
-clz v8.2s, v7.2se02816510cc1a83da26aff774c781a19 00000000000000000000000000000001 fpsr=00000000
-clz v8.8h, v7.8he10d450f9d06ce0f86961d0dfe0e0295 00000001000000000000000300000006 fpsr=00000000
-clz v8.4h, v7.4h621745bf1e53a253c283fdabe8787949 00000000000000000000000000000001 fpsr=00000000
-clz v8.16b, v7.16bbf9212cf2c335fb533ff1b3c28c23a5e 00000300020201000200030202000201 fpsr=00000000
-clz v8.8b, v7.8b54caa9aa633342e0b5d4f4aedaf80203 00000000000000000000000000000606 fpsr=00000000
-cmeq d2, d11, d29 7d0a04bc5edd878025d002ec19278d62 091a1f4f5923c556de8f49b6eb14daf9 95a02171b9c06a425dbdc3e2025a96a7 00000000000000000000000000000000 091a1f4f5923c556de8f49b6eb14daf9 95a02171b9c06a425dbdc3e2025a96a7 fpsr=00000000
-cmge d2, d11, d29 07f98f74015af8db989c4ca73ffe1597 edcf0197e7c200c7409e243038d0ce7b 1855d89a262a1b0a53270c4dcc860398 00000000000000000000000000000000 edcf0197e7c200c7409e243038d0ce7b 1855d89a262a1b0a53270c4dcc860398 fpsr=00000000
-cmgt d2, d11, d29 b5e8784c7c8c4889516eeebe4f40e68b 539af0a5cbcde8d1860844ed2dee1843 fab6c9afe737c9314bc208617c8954d4 00000000000000000000000000000000 539af0a5cbcde8d1860844ed2dee1843 fab6c9afe737c9314bc208617c8954d4 fpsr=00000000
-cmhi d2, d11, d29 3bda55a84439ccad82c8fc163b30d4e2 ee7f7fdd7908d297e250bfd0beb18ef3 f0c7891470a9c6d97711cd0105a75eff 0000000000000000ffffffffffffffff ee7f7fdd7908d297e250bfd0beb18ef3 f0c7891470a9c6d97711cd0105a75eff fpsr=00000000
-cmhs d2, d11, d29 4dd3b8ebcc24d76b5f2e8993f914b241 738244a36537113d88fba7bfdd5d0131 ad8bac2d354666290b996d125b24f4bd 0000000000000000ffffffffffffffff 738244a36537113d88fba7bfdd5d0131 ad8bac2d354666290b996d125b24f4bd fpsr=00000000
+sub v9.8h, v7.8h, v8.8h 78fcbada2d54bed9dca1146904f43511 7490935e9f4d651fe1890b76e4653ab7 046c277c8e0759bafb1808f3208ffa5a fpsr=00000000
+sub v9.4h, v7.4h, v8.4h 740c78331916c2ee0656d19da0e92b0a d04842df070a47229d2e7eb283be0602 0000000000000000692852eb1d2b2508 fpsr=00000000
+sub v9.16b, v7.16b, v8.16b a7dc73ed183713208e6e2a227349679c b9c7d9eb61d469d49e0a48b8c8011cc8 ee159a02b763aa4cf064e26aab484bd4 fpsr=00000000
+sub v9.8b, v7.8b, v8.8b b59e4ea568df2b44ca89f0846cae958b 765d9b3d8cf2e62adcdeda3442e5c8ed 0000000000000000eeab16502ac9cd9e fpsr=00000000
+addhn v9.2s, v7.2d, v8.2d 27e28a572897658ef2a6d6ae590f40fd 2ebbabf3470db8782ccb8833608433b6 0000000000000000569e364a1f725ee1 fpsr=00000000
+addhn2 v9.4s, v7.2d, v8.2d 62988b5f5746fb941b276fefe9c6d174 e7f00989302dba7246518421715669c6 4a8894e86178f4110365b8d34bfc9c8a fpsr=00000000
+addhn v9.4h, v7.4s, v8.4s ad11927ad336084a3ccd2df1aa8a93d7 876d9bdcc5bca72ebf51e0cba2325322 0000000000000000347f98f2fc1f4cbc fpsr=00000000
+addhn2 v9.8h, v7.4s, v8.4s 2ffdc2c55b0f87032db762c30b75b069 d50420276581181f0f0b8f5d0353bc2f 0501c0903cc20ec92762baa7a1d0708a fpsr=00000000
+addhn v9.8b, v7.8h, v8.8h ed6e1ebb8cda5175a26641cf5aff34ce 77e43d084fa5891a8b20646381504fb2 0000000000000000655bdcda2da6dc84 fpsr=00000000
+addhn2 v9.16b, v7.8h, v8.8h cfd2893ae6ff22b433bbdde4c7ff080c f49e747ba1b053546a8f11cbec2196ce c4fd88769eefb49efc009f148dec59c5 fpsr=00000000
+subhn v9.2s, v7.2d, v8.2d 9bfcc47ec746943556f6272c5eb0f887 b32227dc5a8cb261c3bb28e1f220fb09 0000000000000000e8da9ca2933afe4a fpsr=00000000
+subhn2 v9.4s, v7.2d, v8.2d f71b72246ed821cc62b7f4350fa9ad03 fac199e95780c0368c621d512005ca47 fc59d83bd655d6e3b7c27dfe029229e0 fpsr=00000000
+subhn v9.4h, v7.4s, v8.4s 6ac01727f93e24ad8d00f4eca9e2b2a5 ef2cecbc583577269ca64127e7e72ccc 00000000000000007b93a108f05ac1fb fpsr=00000000
+subhn2 v9.8h, v7.4s, v8.4s 5bdb13e5665fd76eee30ba9cd9b572f2 997223d4fcb4b3e7a908c6d194412d3c c26869ab45274574892d6649f507b77e fpsr=00000000
+subhn v9.8b, v7.8h, v8.8h 0fbdaa1a958555027b09baf22fda37cd de05200cbf652c8e4966c11a56eab69e 0000000000000000318ad62831f9d881 fpsr=00000000
+subhn2 v9.16b, v7.8h, v8.8h ae17ffe2435999be0baa45fb18692c7b 86b5a6a102107e8ef40422303b1b9254 2759411b1723dd9aa9c470d95890d444 fpsr=00000000
+raddhn v9.2s, v7.2d, v8.2d 3ef813ba0fe17c5753958e24e4db5aa2 c4276f9d7a2066089aed1b36751530dd 0000000000000000031f8358ee82a95b fpsr=00000000
+raddhn2 v9.4s, v7.2d, v8.2d 748db6b4df58784ca3da435209d5ce30 ad90647a7432d6af490cad91217056d5 221e1b2fece6f0e34b278464bc28f0c8 fpsr=00000000
+raddhn v9.4h, v7.4s, v8.4s a936258b9666b4d4f37549976fb022ff c32cf63309e402406e9f5a58ac1a54d1 00000000000000006c63a04b62151bca fpsr=00000000
+raddhn2 v9.8h, v7.4s, v8.4s 19fee7710650f247e80f3f1bf2b5b476 ec6d05a4b6a1a4cd9e88325743eb11d5 066cbcf3869736a19444b197ac07cce3 fpsr=00000000
+raddhn v9.8b, v7.8h, v8.8h eb961e83edc02ffa57cb79e901fcadd7 ef23560adb3157cc50072abaf61c5a46 0000000000000000db75c988a8a5f808 fpsr=00000000
+raddhn2 v9.16b, v7.8h, v8.8h 270ecc3cebbd43a2f727286eebfe18c9 727e8a02b5bb9511dbbd140db245d8e8 9a56a1d9d33c9ef2656f27a1a7bbc398 fpsr=00000000
+rsubhn v9.2s, v7.2d, v8.2d b2d6d57a7db0e9535f056177dd93e04f fd0f238763c9b9d176aaa13e475e17e0 0000000000000000b5c7b1f3e85ac03a fpsr=00000000
+rsubhn2 v9.4s, v7.2d, v8.2d 52bffb790361bc8206a61431e6f4cfcd f4c785f8e443fea0362f659862c280b3 5df87580d076ae9af02dfb66a188a88b fpsr=00000000
+rsubhn v9.4h, v7.4s, v8.4s b0f9e0d5b9fa370241a91527f6b99009 a0f5f10f15717d72120cd2c993275e44 00000000000000001004a4892f9c6392 fpsr=00000000
+rsubhn2 v9.8h, v7.4s, v8.4s 5015078bc002b309470f1546d9dbad27 264b8be9b6fd329ce1613adc48a6dcd9 29c9090665ae91356a0141c98eb2505e fpsr=00000000
+rsubhn v9.8b, v7.8h, v8.8h 9a04d2f816626c2c2f38a8db40b290ab 8dd9540466eef7d359b0d13fcfb80416 00000000000000000c7faf74d6d8718d fpsr=00000000
+rsubhn2 v9.16b, v7.8h, v8.8h d31583d898627c5eefe64192b7f7857a bc0f303ba1ad862b11d8a7bd5735c0ff 1754f7f6de9a61c407700db0637e8eb7 fpsr=00000000
+addp d22, v23.2d 23fa3e4706acddf45d393078afc3b5d8 78bee0cbc8037a197f1bb183ee56dcf9 0000000000000000f7da924fb65a5712 78bee0cbc8037a197f1bb183ee56dcf9 fpsr=00000000
+addp v9.2d, v7.2d, v8.2d 6917085019174d71f918c11e83b301c8 a6a3c9f2c2e8f683fbfe73fd132e3739 a2a23defd6172dbc622fc96e9cca4f39 fpsr=00000000
+addp v9.4s, v7.4s, v8.4s 5f3646169d10a4a4a96e8ad5ed65b981 3b2220ae6674d2fb42f1655f05df749c a196f3a948d0d9fbfc46eaba96d44456 fpsr=00000000
+addp v9.2s, v7.2s, v8.2s 725aaa117e7599eb792f879592071e89 e5bad9f874f6c1ee4d9b6cfdcd38bc65 00000000000000001ad429620b36a61e fpsr=00000000
+addp v9.8h, v7.8h, v8.8h 8737670045ac078c562d87a75d3333b4 db00a0567c2a86afc40047f4038de9d3 7b5602d90bf4ed60ee374d38ddd490e7 fpsr=00000000
+addp v9.4h, v7.4h, v8.4h 868b2e22d97fdd69760648ac6426460c 349f42f2e67983ac302a67122627dc71 0000000000000000973c0298beb2aa32 fpsr=00000000
+addp v9.16b, v7.16b, v8.16b 2906701b0eb55d7aa1e722b770cb3d54 08eb890f505a9fef0fb2dc303e71375e f398aa8ec10caf952f8bc3d788d93b91 fpsr=00000000
+addp v9.8b, v7.8b, v8.8b 96584f08a2f98312aff067d5f03b44cf 1eb33ae9199674ecd8d7987a5aa2c601 0000000000000000af12fcc79f3c2b13 fpsr=00000000
+addv s22, v23.4s d592cd65355229e856a34b7132ed6522 dadbd02a2efc4a4c3cb79f06723292b0 000000000000000000000000b8c24c2c dadbd02a2efc4a4c3cb79f06723292b0 fpsr=00000000
+addv h22, v23.8h 913d502c107e9cd06a3eec76b56ecb74 3edf14402e48bffaabe616bb98dc80c1 00000000000000000000000000001d9f 3edf14402e48bffaabe616bb98dc80c1 fpsr=00000000
+addv h22, v23.4h d6f4419831d4c3802458c320b8e9ef36 2a1fe48bf7d8b25706c5dff7abfe7295 0000000000000000000000000000054f 2a1fe48bf7d8b25706c5dff7abfe7295 fpsr=00000000
+addv b22, v23.16b cbafa6c1c5b8d1e7f3e9d3da51267dc3 7ef922696a0f05c22cb3d81c8dfb468b 0000000000000000000000000000006e 7ef922696a0f05c22cb3d81c8dfb468b fpsr=00000000
+addv b22, v23.8b 50cd6006aa89a564b651fc046084577a 1acfac3d674a969cff10e3891c30dd04 000000000000000000000000000000a8 1acfac3d674a969cff10e3891c30dd04 fpsr=00000000
+and v9.16b, v7.16b, v8.16b 45af4ec7c2a821574df11effc5645bbb de016364cdeb46445e3dde9f39ff175e 44014244c0a800444c311e9f0164131a fpsr=00000000
+and v9.8b, v7.8b, v8.8b f57a25258fdf807367ff0cd7231ec7ef 8ab45265eb7423219729192a5f256ae7 000000000000000007290802030442e7 fpsr=00000000
+bic v9.16b, v7.16b, v8.16b 10a112344c596d04e61bbedf67380ca3 59a8632038cce2e47cd7343d3907fab1 0001101444110d0082088ac246380402 fpsr=00000000
+bic v9.8b, v7.8b, v8.8b 5df6d73059dd837e3e8527449ee9f43b b1cff9f1b4ddbe2322a9c22776ff3042 00000000000000001c0425408800c439 fpsr=00000000
+orr v9.16b, v7.16b, v8.16b 83a818b6f3943cb7c8dd1991b6cb297d d97955953deed0d281603593a4c5577d dbf95db7fffefcf7c9fd3d93b6cf7f7d fpsr=00000000
+orr v9.8b, v7.8b, v8.8b f7579b2891a813446e1bdf8d327099a8 fcd880ce0be4bb73cf8ab30ab9b9dc22 0000000000000000ef9bff8fbbf9ddaa fpsr=00000000
+orn v9.16b, v7.16b, v8.16b 1378cc285014632fa05bf3836f7b0267 3ca9b2f8c2eaf1274870fd3a6577943d d37ecd2f7d156fffb7dff3c7fffb6be7 fpsr=00000000
+orn v9.8b, v7.8b, v8.8b 124ecb70f79979a7ae01844088bd7bbe 1614be74a19641dae470df8abcc9c0b3 0000000000000000bf8fa475cbbf7ffe fpsr=00000000
+orr v22.8h, #0x5A, LSL #0 baa85b3de501ef210e4d83f18c6ed012 f209069ea7d3e520baedeb496f09ca07 bafa5b7fe55bef7b0e5f83fb8c7ed05a f209069ea7d3e520baedeb496f09ca07 fpsr=00000000
+orr v22.8h, #0xA5, LSL #8 15dacc33b1e8f8eec0a594220beffe1d d2588598182a085f2ae05c723ca7542a b5daed33b5e8fdeee5a5b522afefff1d d2588598182a085f2ae05c723ca7542a fpsr=00000000
+orr v22.4h, #0x5A, LSL #0 919b29bf2bfec2c5dd3bb51ccef7f987 ae2d4071b09e34d197ade8b4986d6b05 0000000000000000dd7bb55ecefff9df ae2d4071b09e34d197ade8b4986d6b05 fpsr=00000000
+orr v22.4h, #0xA5, LSL #8 1130d272c0b0f3b1b55dd7a60757997f 5136e60ea8b68eb60aff985d1d21b4da 0000000000000000b55df7a6a757bd7f 5136e60ea8b68eb60aff985d1d21b4da fpsr=00000000
+orr v22.4s, #0x5A, LSL #0 30796011b79f7a8390a6a371c6291371 4c8b686f3a23b6d93a12e81f605f5002 3079605bb79f7adb90a6a37bc629137b 4c8b686f3a23b6d93a12e81f605f5002 fpsr=00000000
+orr v22.4s, #0x6B, LSL #8 d0d6b3fdf02b399c4f77f7dceacd49be 7e8ba7f547468d9a0543b959418620dc d0d6fbfdf02b7b9c4f77ffdceacd6bbe 7e8ba7f547468d9a0543b959418620dc fpsr=00000000
+orr v22.4s, #0x49, LSL #16 cfa6ab954bb50e5bd22fb34754a219c5 c89783ffad7ef35a4cf4eb6ba0f602c9 cfefab954bfd0e5bd26fb34754eb19c5 c89783ffad7ef35a4cf4eb6ba0f602c9 fpsr=00000000
+orr v22.4s, #0x3D, LSL #24 0e492839a79cda20f92eb913e40864e6 0a0edcee4d2cc878ef855eb65c10d628 3f492839bf9cda20fd2eb913fd0864e6 0a0edcee4d2cc878ef855eb65c10d628 fpsr=00000000
+orr v22.2s, #0x5A, LSL #0 6d1f094ae6417d4ca4d5e89f7a600a82 2450922107afec54cd54f29957327e59 0000000000000000a4d5e8df7a600ada 2450922107afec54cd54f29957327e59 fpsr=00000000
+orr v22.2s, #0x6B, LSL #8 cc893028e602d73eb2831f4bf609ebf8 f6be84f8bb673f4fc8c387756fbfd9bd 0000000000000000b2837f4bf609ebf8 f6be84f8bb673f4fc8c387756fbfd9bd fpsr=00000000
+orr v22.2s, #0x49, LSL #16 0be77b318842c856059940783863e7a8 60b794d448b4a0c8be32fda98514c6b3 000000000000000005d94078386be7a8 60b794d448b4a0c8be32fda98514c6b3 fpsr=00000000
+orr v22.2s, #0x3D, LSL #24 0a97cbc7ac5e30f57b7629851fcfdef3 419ca01490f7f11f910033957a94279b 00000000000000007f7629853fcfdef3 419ca01490f7f11f910033957a94279b fpsr=00000000
+bic v22.8h, #0x5A, LSL #0 a8fb004a32b8ef7bf67abbd38dacaf39 7bcc8918719010b51f8d0a9a2b9cdad6 a8a1000032a0ef21f620bb818da4af21 7bcc8918719010b51f8d0a9a2b9cdad6 fpsr=00000000
+bic v22.8h, #0xA5, LSL #8 c773fa18fab0e4465406d6c1605a3bd8 eca72f41cddddee9493a63177b8ec0c3 42735a185ab04046500652c1405a1ad8 eca72f41cddddee9493a63177b8ec0c3 fpsr=00000000
+bic v22.4h, #0x5A, LSL #0 455d9993e4a5f1b876795aaf7a3a6332 768d72ee82413c1cef651c6c49c9b9c3 000000000000000076215aa57a206320 768d72ee82413c1cef651c6c49c9b9c3 fpsr=00000000
+bic v22.4h, #0xA5, LSL #8 031cbc1bd0f7f4313c3427feb9ab05a7 f7df3280711908adf17116fa75aea535 0000000000000000183402fe18ab00a7 f7df3280711908adf17116fa75aea535 fpsr=00000000
+bic v22.4s, #0x5A, LSL #0 e10d450f9d06ce0f86961d0dfe0e0295 50fd4f567ac722fc2fbc3120de9c6479 e10d45059d06ce0586961d05fe0e0285 50fd4f567ac722fc2fbc3120de9c6479 fpsr=00000000
+bic v22.4s, #0x6B, LSL #8 bf9212cf2c335fb533ff1b3c28c23a5e 6146a9d07daa6c6a88a64c3f65f3d5f0 bf9210cf2c3314b533ff103c28c2105e 6146a9d07daa6c6a88a64c3f65f3d5f0 fpsr=00000000
+bic v22.4s, #0x49, LSL #16 7d0a04bc5edd878025d002ec19278d62 091a1f4f5923c556de8f49b6eb14daf9 7d0204bc5e948780259002ec19268d62 091a1f4f5923c556de8f49b6eb14daf9 fpsr=00000000
+bic v22.4s, #0x3D, LSL #24 fad6fc35116526d23a68b37db09eda00 2ad99232f0910c210fd806e54e5e51f5 c2d6fc35006526d20268b37d809eda00 2ad99232f0910c210fd806e54e5e51f5 fpsr=00000000
+bic v22.2s, #0x5A, LSL #0 1855d89a262a1b0a53270c4dcc860398 a2e4e3d92054232afde0652d6f311b42 000000000000000053270c05cc860380 a2e4e3d92054232afde0652d6f311b42 fpsr=00000000
+bic v22.2s, #0x6B, LSL #8 b5e8784c7c8c4889516eeebe4f40e68b 539af0a5cbcde8d1860844ed2dee1843 0000000000000000516e84be4f40848b 539af0a5cbcde8d1860844ed2dee1843 fpsr=00000000
+bic v22.2s, #0x49, LSL #16 b2edbeaaf5ec8bae129c392f172a6438 1b5c9af6cf5b3c778baf84856af42855 00000000000000001294392f17226438 1b5c9af6cf5b3c778baf84856af42855 fpsr=00000000
+bic v22.2s, #0x3D, LSL #24 f0c7891470a9c6d97711cd0105a75eff db89c02a0d5fff7bec35055605a42bda 00000000000000004211cd0100a75eff db89c02a0d5fff7bec35055605a42bda fpsr=00000000
+bif v9.16b, v7.16b, v8.16b 4dd3b8ebcc24d76b5f2e8993f914b241 738244a36537113d88fba7bfdd5d0131 2dd3bc69ad06c66b5f9d2d127904b271 fpsr=00000000
+bif v9.8b, v7.8b, v8.8b d6087fa761d26d73d373fa7ba73bb1fa a9732d8eebbc9fc3ac524f46d3d3415d 00000000000000005361fa39f77bb0bb fpsr=00000000
randV128: 768 calls, 793 iters
-cmtst d2, d11, d29 9ed8377b8811bde81e25ab197c2f544b e606c65eabd1fe423ddefd787344eab3 ab54e2e2e2e9a17df5c4cddac86ba5d7 0000000000000000ffffffffffffffff e606c65eabd1fe423ddefd787344eab3 ab54e2e2e2e9a17df5c4cddac86ba5d7 fpsr=00000000
-cmeq v9.2d, v7.2d, v8.2d 0aefbd68c882e0ba8688124d9a8034e6 4f3e6b0b450ee14a3f6391173f4b1584 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.4s, v7.4s, v8.4s c2d574b34771ed36d20bf7d72a1e1546 d015d40d6e016dac0dd5facfa21a36f1 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.2s, v7.2s, v8.2s 9c342f9777c1646445ad3ed3b57d49d5 b166e8214114a950baae5dda57a6295a 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.8h, v7.8h, v8.8h a42d5ff531c8df470f895737f09f7c94 18551cd87e8cde3ca5964fc72c731ed5 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.4h, v7.4h, v8.4h 80efa667b5aedab485401690c81e5949 4b33b2ee05b02563c54f4243ae396147 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.16b, v7.16b, v8.16b b70b87ec21fcaee0ded12dca0df26a17 70b1ce7f93297a1aeff889594c121bf4 00000000000000000000000000000000 fpsr=00000000
-cmeq v9.8b, v7.8b, v8.8b b07164e0739a975f319f2e316c731984 8ede7208c800b715da12557654765782 00000000000000000000000000000000 fpsr=00000000
-cmge v9.2d, v7.2d, v8.2d b17280fe8bd0af2574688c737559b274 8c2c7f66219d966a1d7eba67f53dfff3 ffffffffffffffffffffffffffffffff fpsr=00000000
-cmge v9.4s, v7.4s, v8.4s e0bffd642647f0887e4e9a9b96be5e2b 306bbad4fdc8b28c2e7caa583d9fdfad 00000000ffffffffffffffff00000000 fpsr=00000000
-cmge v9.2s, v7.2s, v8.2s 4467de8de308363b05d28a171d1a294d 20cbc3f09aaa865164adf8d51b36a175 000000000000000000000000ffffffff fpsr=00000000
-cmge v9.8h, v7.8h, v8.8h c4dc0557417a3954a0d36eb33845fce0 e3dd1fb618cc6becf41055cc5eface6f 00000000ffff00000000ffff0000ffff fpsr=00000000
-cmge v9.4h, v7.4h, v8.4h df912f8374159df2f7085589b343d21f d99d3da4e6e56fdba00fc29a5d63c6e3 0000000000000000ffffffff0000ffff fpsr=00000000
-cmge v9.16b, v7.16b, v8.16b 5b3835128dd0355762546ab8a9c9f869 7a591efbe94e37d632c5c500931264b7 0000ffff000000ffffffff00ff0000ff fpsr=00000000
-cmge v9.8b, v7.8b, v8.8b 7e83558122a32f710b14e766b0a66893 3a5ee3fa671d74b80b650cfe693570ed 0000000000000000ff0000ff00000000 fpsr=00000000
-cmgt v9.2d, v7.2d, v8.2d 4e81904cd19865f4aac9fdff14522f41 bddc2f3f9e7ca05380906821cd649648 ffffffffffffffffffffffffffffffff fpsr=00000000
-cmgt v9.4s, v7.4s, v8.4s b1a4ca4f181791f3d454c04f06a53778 8c6485c6adf116dec9468c558d9860ec ffffffffffffffffffffffffffffffff fpsr=00000000
-cmgt v9.2s, v7.2s, v8.2s 6ebcc4c757e84ee401f6228492d84a9b 0ce747ec936710ebfbe70be75829395f 0000000000000000ffffffff00000000 fpsr=00000000
-cmgt v9.8h, v7.8h, v8.8h 2bf92251cb35169b864df529a983126f 84b4b96d2e26a96f0d355683bcd06b85 ffffffff0000ffff0000000000000000 fpsr=00000000
-cmgt v9.4h, v7.4h, v8.4h 70ed65e99385444d9a5ced2c189f1b19 1a7dfb643cd5dcc0d64fc13628a521a2 00000000000000000000ffff00000000 fpsr=00000000
-cmgt v9.16b, v7.16b, v8.16b a286f1ebadc1138d54839bd88d84ce1e d55211505c7e82920db77e6cea21645b 000000000000ff00ff00000000000000 fpsr=00000000
-cmgt v9.8b, v7.8b, v8.8b 07170714f9319c52aa8271db98eb7661 9ca3dd0d0d8957f8464ca0f2311c20b5 00000000000000000000ff000000ffff fpsr=00000000
-cmhi v9.2d, v7.2d, v8.2d c74ecb80347fdbee7379c440a7ec3e28 354122d6adbff468fb4f18f40bcf2013 ffffffffffffffff0000000000000000 fpsr=00000000
-cmhi v9.4s, v7.4s, v8.4s e93e3eadfdb2aa1765eac47508003017 465c83497b47d5b77f61bafe67d20d3b ffffffffffffffff0000000000000000 fpsr=00000000
-cmhi v9.2s, v7.2s, v8.2s 51564476d333c3e117b48545ea003632 5685816295ab54170b8338fe141e7250 0000000000000000ffffffffffffffff fpsr=00000000
-cmhi v9.8h, v7.8h, v8.8h c8679e1814cac1c1ff19f9de5b231cdd cbad7f7df9d3ab1fb513253fbf0bbad8 0000ffff0000ffffffffffff00000000 fpsr=00000000
-cmhi v9.4h, v7.4h, v8.4h f2a2f02ffea11e8b73b8f2cb4a028bde ed24c0578608f5c373d4f26ff7522fb6 00000000000000000000ffff0000ffff fpsr=00000000
-cmhi v9.16b, v7.16b, v8.16b 5896bbb9b13f3573ab9223f985960f59 e19a660dfbf22d561be6f39a2c0cfb30 0000ffff0000ffffff0000ffffff00ff fpsr=00000000
-cmhi v9.8b, v7.8b, v8.8b 603563102a8d410ebd081fb5bb3711d3 ad1f741bf6992c8e65c95a2baab02aea 0000000000000000ff0000ffff000000 fpsr=00000000
-cmhs v9.2d, v7.2d, v8.2d 4fce29f348d45b519eda58ac7a9edc2f 3926cc5df566ae80e65d3af1a217a5e8 ffffffffffffffff0000000000000000 fpsr=00000000
-cmhs v9.4s, v7.4s, v8.4s 4c13317dcabb7f91272820e931e49bb2 4c7d311058224c9e16e48416217a378f 00000000ffffffffffffffffffffffff fpsr=00000000
-cmhs v9.2s, v7.2s, v8.2s 5f147c2c4d4d86800c74abd92f805802 8a5546d05cf482bf4afd0c2915728ba3 000000000000000000000000ffffffff fpsr=00000000
-cmhs v9.8h, v7.8h, v8.8h 6d42eeda52f02c35e59e0949a14bfd21 7b408c9b2067aa17b9a984144ef62b49 0000ffffffff0000ffff0000ffffffff fpsr=00000000
-cmhs v9.4h, v7.4h, v8.4h 3d6c48c6356e0b2329e52f65977e5676 862d66cca261fe397b497f257a5f8205 000000000000000000000000ffff0000 fpsr=00000000
-cmhs v9.16b, v7.16b, v8.16b 75c32e8b36ee9d202debefbafeb20cc3 f16c1720c22c991b849d6e092767dabd 00ffffff00ffffff00ffffffffff00ff fpsr=00000000
-cmhs v9.8b, v7.8b, v8.8b 9cd9212673fb3d5f28b1fa34a6deaa2f e2b0c1b33d707512acc6a5cbc3245db3 00000000000000000000ff0000ffff00 fpsr=00000000
-cmtst v9.2d, v7.2d, v8.2d 199d84f3ea7b26753196e4203c5c9b3d 61076702b3356dd0a94456d89e10168e ffffffffffffffffffffffffffffffff fpsr=00000000
-cmtst v9.4s, v7.4s, v8.4s 32609bb07bb871573e5b1e2950e32ad2 52e2ebeaa1e43c6c12f793fde604f150 ffffffffffffffffffffffffffffffff fpsr=00000000
-cmtst v9.2s, v7.2s, v8.2s 0dd28678e35a1a582621fd5e508d7f32 7e1210a766467c5a5d215066a937b660 0000000000000000ffffffffffffffff fpsr=00000000
-cmtst v9.8h, v7.8h, v8.8h b10449c8c169fa2f9e68b12a89d1a702 8ac878d54083a66de0615ea0d6431181 ffffffffffffffffffffffffffffffff fpsr=00000000
-cmtst v9.4h, v7.4h, v8.4h 0467c77c934fcdee3f104d5a2c898c46 fd94a6714f2317dcd3b96f983c1f8cd8 0000000000000000ffffffffffffffff fpsr=00000000
-cmtst v9.16b, v7.16b, v8.16b cdcac1d1b9d32d0b7e5bc51a46ecf763 3d66fcd8901008394c881899882591e9 ffffffffffffffffffff00ff00ffffff fpsr=00000000
-cmtst v9.8b, v7.8b, v8.8b b35fdb64701e945ab1e9eaf6c694941e 918fbdc5e291947a408fc950490c6c99 000000000000000000ffffffffffffff fpsr=00000000
-cmeq d2, d11, #0 3cb59631d8b85d1010b970dc7a78ee9a 20bf0b56034fb5f388efd6c9eeee462c 0000000000...
[truncated message content] |
|
From: <sv...@va...> - 2014-11-23 17:47:23
|
Author: sewardj
Date: Sun Nov 23 17:47:16 2014
New Revision: 14761
Log:
Merge, from trunk, r14677
340236 4 unhandled syscalls on aarch64/arm64: mknodat (33), fchdir
(50), chroot (51), fchownat (54)
14677
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c Sun Nov 23 17:47:16 2014
@@ -880,6 +880,7 @@
LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 27
LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 28
LINXY(__NR_ioctl, sys_ioctl), // 29
+ LINX_(__NR_mknodat, sys_mknodat), // 33
LINX_(__NR_mkdirat, sys_mkdirat), // 34
LINX_(__NR_unlinkat, sys_unlinkat), // 35
LINX_(__NR_symlinkat, sys_symlinkat), // 36
@@ -896,7 +897,10 @@
LINX_(__NR_fallocate, sys_fallocate), // 47
LINX_(__NR_faccessat, sys_faccessat), // 48
GENX_(__NR_chdir, sys_chdir), // 49
+ GENX_(__NR_fchdir, sys_fchdir), // 50
+ GENX_(__NR_chroot, sys_chroot), // 51
LINX_(__NR_fchmodat, sys_fchmodat), // 53
+ LINX_(__NR_fchownat, sys_fchownat), // 54
LINXY(__NR_openat, sys_openat), // 56
GENXY(__NR_close, sys_close), // 57
LINXY(__NR_pipe2, sys_pipe2), // 59
@@ -1093,7 +1097,6 @@
//ZZ // GENX_(__NR_ulimit, sys_ni_syscall), // 58
//ZZ //zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete
//ZZ //zz
-//ZZ GENX_(__NR_chroot, sys_chroot), // 61
//ZZ //zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated
//ZZ GENXY(__NR_dup2, sys_dup2), // 63
//ZZ GENX_(__NR_getppid, sys_getppid), // 64
@@ -1165,7 +1168,6 @@
//ZZ //zz // Nb: get_kernel_syms() was removed 2.4-->2.6
//ZZ // GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130
//ZZ GENX_(__NR_getpgid, sys_getpgid), // 132
-//ZZ GENX_(__NR_fchdir, sys_fchdir), // 133
//ZZ //zz // (__NR_bdflush, sys_bdflush), // 134 */Linux
//ZZ //zz
//ZZ //zz // (__NR_sysfs, sys_sysfs), // 135 SVr4
@@ -1329,8 +1331,6 @@
//ZZ LINX_(__NR_inotify_init, sys_inotify_init), // 291
//ZZ // LINX_(__NR_migrate_pages, sys_migrate_pages), // 294
//ZZ
-//ZZ LINX_(__NR_mknodat, sys_mknodat), // 297
-//ZZ LINX_(__NR_fchownat, sys_fchownat), // 298
//ZZ LINX_(__NR_futimesat, sys_futimesat), // 326 on arm
//ZZ
//ZZ PLAXY(__NR_fstatat64, sys_fstatat64), // 300
|
|
From: <sv...@va...> - 2014-11-23 17:46:12
|
Author: sewardj
Date: Sun Nov 23 17:46:06 2014
New Revision: 14760
Log:
Merge, from trunk, r14676
340028 unhandled syscalls for arm64 (msync, pread64, setreuid and setregid)
14676
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c Sun Nov 23 17:46:06 2014
@@ -910,6 +910,7 @@
GENX_(__NR_write, sys_write), // 64
GENXY(__NR_readv, sys_readv), // 65
GENX_(__NR_writev, sys_writev), // 66
+ GENXY(__NR_pread64, sys_pread64), // 67
GENX_(__NR_pwrite64, sys_pwrite64), // 68
LINX_(__NR_pselect6, sys_pselect6), // 72
LINXY(__NR_ppoll, sys_ppoll), // 73
@@ -951,6 +952,8 @@
PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139
GENX_(__NR_setpriority, sys_setpriority), // 140
GENX_(__NR_getpriority, sys_getpriority), // 141
+ GENX_(__NR_setregid, sys_setregid), // 143
+ GENX_(__NR_setreuid, sys_setreuid), // 145
LINX_(__NR_setresuid, sys_setresuid), // 147
LINXY(__NR_getresuid, sys_getresuid), // 148
LINXY(__NR_getresgid, sys_getresgid), // 150
@@ -1017,6 +1020,7 @@
PLAX_(__NR3264_fadvise64, sys_fadvise64), // 223
GENXY(__NR_mprotect, sys_mprotect), // 226
+ GENX_(__NR_msync, sys_msync), // 227
GENX_(__NR_mlock, sys_mlock), // 228
GENX_(__NR_mlockall, sys_mlockall), // 230
GENX_(__NR_madvise, sys_madvise), // 233
@@ -1099,8 +1103,6 @@
//ZZ //zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C)
//ZZ //zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C)
//ZZ //zz
-//ZZ LINX_(__NR_setreuid, sys_setreuid16), // 70
-//ZZ LINX_(__NR_setregid, sys_setregid16), // 71
//ZZ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72
//ZZ LINXY(__NR_sigpending, sys_sigpending), // 73
//ZZ //zz // (__NR_sethostname, sys_sethostname), // 74 */*
@@ -1176,7 +1178,6 @@
//ZZ GENXY(__NR_getdents, sys_getdents), // 141
//ZZ GENX_(__NR__newselect, sys_select), // 142
//ZZ GENX_(__NR_flock, sys_flock), // 143
-//ZZ GENX_(__NR_msync, sys_msync), // 144
//ZZ
//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149
//ZZ
@@ -1207,7 +1208,6 @@
//ZZ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 176
//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177
//ZZ
-//ZZ GENXY(__NR_pread64, sys_pread64), // 180
//ZZ LINX_(__NR_chown, sys_chown16), // 182
//ZZ
//ZZ LINX_(__NR_capset, sys_capset), // 185
|
|
From: <sv...@va...> - 2014-11-23 17:44:55
|
Author: sewardj
Date: Sun Nov 23 17:44:49 2014
New Revision: 14759
Log:
Merge, from trunk, r14675
339940 arm64: unhandled syscall: 83 (sys_fdatasync) + patch
14675
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
Modified: branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ branches/VALGRIND_3_10_BRANCH/coregrind/m_syswrap/syswrap-arm64-linux.c Sun Nov 23 17:44:49 2014
@@ -922,6 +922,7 @@
LINX_(__NR_utimensat, sys_utimensat), // 88
GENX_(__NR_fsync, sys_fsync), // 82
+ GENX_(__NR_fdatasync, sys_fdatasync), // 83
LINXY(__NR_timerfd_create, sys_timerfd_create), // 85
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87
@@ -1177,7 +1178,6 @@
//ZZ GENX_(__NR_flock, sys_flock), // 143
//ZZ GENX_(__NR_msync, sys_msync), // 144
//ZZ
-//ZZ GENX_(__NR_fdatasync, sys_fdatasync), // 148
//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149
//ZZ
//ZZ GENX_(__NR_munlock, sys_munlock), // 151
|
|
From: <sv...@va...> - 2014-11-23 17:39:08
|
Author: sewardj
Date: Sun Nov 23 17:39:02 2014
New Revision: 3022
Log:
Merge from trunk, r2997.
2997 arm64: enable FCVT{A,N}S X,S.
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:39:02 2014
@@ -12502,6 +12502,7 @@
|| (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */
/* F32toI64S */
|| (iop == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */
+ || (iop == Iop_F32toI64S && irrm == Irrm_NEAREST)/* FCVT{A,N}S X,S */
/* F32toI64U */
|| (iop == Iop_F32toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Sn */
|| (iop == Iop_F32toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Sn */
|
|
From: <sv...@va...> - 2014-11-23 17:37:37
|
Author: sewardj
Date: Sun Nov 23 17:37:29 2014
New Revision: 3021
Log:
Merge from trunk, r2996
2996 arm64: Implement {S,U}CVTF (scalar, fixedpt).
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:37:29 2014
@@ -8081,6 +8081,16 @@
}
+/* Returns 2.0 ^ (-n) for n in 1 .. 64 */
+static Double two_to_the_minus ( Int n )
+{
+ if (n == 1) return 0.5;
+ vassert(n >= 2 && n <= 64);
+ Int half = n / 2;
+ return two_to_the_minus(half) * two_to_the_minus(n - half);
+}
+
+
/*------------------------------------------------------------*/
/*--- SIMD and FP instructions ---*/
/*------------------------------------------------------------*/
@@ -12320,9 +12330,78 @@
static
-Bool dis_AdvSIMD_fp_to_fixedp_conv(/*MB_OUT*/DisResult* dres, UInt insn)
+Bool dis_AdvSIMD_fp_to_from_fixedp_conv(/*MB_OUT*/DisResult* dres, UInt insn)
{
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ /* 31 30 29 28 23 21 20 18 15 9 4
+ sf 0 0 11110 type 0 rmode opcode scale n d
+ The first 3 bits are really "sf 0 S", but S is always zero.
+ Decode fields: sf,type,rmode,opcode
+ */
+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(30,29) != BITS2(0,0)
+ || INSN(28,24) != BITS5(1,1,1,1,0)
+ || INSN(21,21) != 0) {
+ return False;
+ }
+ UInt bitSF = INSN(31,31);
+ UInt ty = INSN(23,22); // type
+ UInt rm = INSN(20,19); // rmode
+ UInt op = INSN(18,16); // opcode
+ UInt sc = INSN(15,10); // scale
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ // op = 010, 011
+ /* -------------- {S,U}CVTF (scalar, fixedpt) -------------- */
+ /* (ix) sf S 28 ty rm op 15 9 4
+ 0 0 0 0 11110 00 0 00 010 scale n d SCVTF Sd, Wn, #fbits
+ 1 0 0 0 11110 01 0 00 010 scale n d SCVTF Dd, Wn, #fbits
+ 2 1 0 0 11110 00 0 00 010 scale n d SCVTF Sd, Xn, #fbits
+ 3 1 0 0 11110 01 0 00 010 scale n d SCVTF Dd, Xn, #fbits
+
+ 4 0 0 0 11110 00 0 00 011 scale n d UCVTF Sd, Wn, #fbits
+ 5 0 0 0 11110 01 0 00 011 scale n d UCVTF Dd, Wn, #fbits
+ 6 1 0 0 11110 00 0 00 011 scale n d UCVTF Sd, Xn, #fbits
+ 7 1 0 0 11110 01 0 00 011 scale n d UCVTF Dd, Xn, #fbits
+
+ These are signed/unsigned conversion from integer registers to
+ FP registers, all 4 32/64-bit combinations, rounded per FPCR,
+ scaled per |scale|.
+ */
+ if (ty <= X01 && rm == X00
+ && (op == BITS3(0,1,0) || op == BITS3(0,1,1))
+ && (bitSF == 1 || ((sc >> 5) & 1) == 1)) {
+ Bool isI64 = bitSF == 1;
+ Bool isF64 = (ty & 1) == 1;
+ Bool isU = (op & 1) == 1;
+ UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
+
+ Int fbits = 64 - sc;
+ vassert(fbits >= 1 && fbits <= (isI64 ? 64 : 32));
+
+ Double scale = two_to_the_minus(fbits);
+ IRExpr* scaleE = isF64 ? IRExpr_Const(IRConst_F64(scale))
+ : IRExpr_Const(IRConst_F32( (Float)scale ));
+ IROp opMUL = isF64 ? Iop_MulF64 : Iop_MulF32;
+
+ const IROp ops[8]
+ = { Iop_I32StoF32, Iop_I32StoF64, Iop_I64StoF32, Iop_I64StoF64,
+ Iop_I32UtoF32, Iop_I32UtoF64, Iop_I64UtoF32, Iop_I64UtoF64 };
+ IRExpr* src = getIRegOrZR(isI64, nn);
+ IRExpr* res = (isF64 && !isI64)
+ ? unop(ops[ix], src)
+ : binop(ops[ix],
+ mkexpr(mk_get_IR_rounding_mode()), src);
+ putQReg128(dd, mkV128(0));
+ putQRegLO(dd, triop(opMUL, mkU32(Irrm_NEAREST), res, scaleE));
+
+ DIP("%ccvtf %s, %s, #%d\n",
+ isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32),
+ nameIRegOrZR(isI64, nn), fbits);
+ return True;
+ }
+
return False;
# undef INSN
}
@@ -12488,7 +12567,8 @@
IRExpr* src = getIRegOrZR(isI64, nn);
IRExpr* res = (isF64 && !isI64)
? unop(ops[ix], src)
- : binop(ops[ix], mkexpr(mk_get_IR_rounding_mode()), src);
+ : binop(ops[ix],
+ mkexpr(mk_get_IR_rounding_mode()), src);
putQReg128(dd, mkV128(0));
putQRegLO(dd, res);
DIP("%ccvtf %s, %s\n",
@@ -12631,7 +12711,7 @@
if (UNLIKELY(ok)) return True;
ok = dis_AdvSIMD_fp_immediate(dres, insn);
if (UNLIKELY(ok)) return True;
- ok = dis_AdvSIMD_fp_to_fixedp_conv(dres, insn);
+ ok = dis_AdvSIMD_fp_to_from_fixedp_conv(dres, insn);
if (UNLIKELY(ok)) return True;
ok = dis_AdvSIMD_fp_to_from_int_conv(dres, insn);
if (UNLIKELY(ok)) return True;
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c Sun Nov 23 17:37:29 2014
@@ -2965,6 +2965,16 @@
addInstr(env, ARM64Instr_VDfromX(dst, src));
return dst;
}
+ if (con->tag == Ico_F64) {
+ HReg src = newVRegI(env);
+ HReg dst = newVRegD(env);
+ union { Double d64; ULong u64; } u;
+ vassert(sizeof(u) == 8);
+ u.d64 = con->Ico.F64;
+ addInstr(env, ARM64Instr_Imm64(src, u.u64));
+ addInstr(env, ARM64Instr_VDfromX(dst, src));
+ return dst;
+ }
}
if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
@@ -3134,6 +3144,16 @@
addInstr(env, ARM64Instr_VDfromX(dst, src));
return dst;
}
+ if (con->tag == Ico_F32) {
+ HReg src = newVRegI(env);
+ HReg dst = newVRegD(env);
+ union { Float f32; UInt u32; } u;
+ vassert(sizeof(u) == 4);
+ u.f32 = con->Ico.F32;
+ addInstr(env, ARM64Instr_Imm64(src, (ULong)u.u32));
+ addInstr(env, ARM64Instr_VDfromX(dst, src));
+ return dst;
+ }
}
if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
|
|
From: <sv...@va...> - 2014-11-23 17:35:45
|
Author: sewardj
Date: Sun Nov 23 17:35:36 2014
New Revision: 14758
Log:
Merge from trunk, r14736.
340807 disInstr(arm): unhandled instruction: 0xEE989B20
2995, testcase=14736.
Modified:
branches/VALGRIND_3_10_BRANCH/ (props changed)
branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.c
branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.stdout.exp
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.c
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.c (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.c Sun Nov 23 17:35:36 2014
@@ -178,5 +178,105 @@
TESTINSN_bin_f32("vfms.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0));
TESTINSN_bin_f32("vfms.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0));
+ printf("---- VFNMA (fp, VFPv4) ----\n");
+ TESTINSN_bin_f64("vfnma.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnma.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnma.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0));
+ TESTINSN_bin_f64("vfnma.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f64("vfnma.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnma.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687));
+ TESTINSN_bin_f64("vfnma.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346));
+ TESTINSN_bin_f64("vfnma.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476));
+ TESTINSN_bin_f64("vfnma.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065));
+ TESTINSN_bin_f64("vfnma.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76));
+ TESTINSN_bin_f64("vfnma.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346));
+ TESTINSN_bin_f64("vfnma.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089));
+ TESTINSN_bin_f64("vfnma.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065));
+ TESTINSN_bin_f64("vfnma.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009));
+ TESTINSN_bin_f64("vfnma.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575));
+ TESTINSN_bin_f64("vfnma.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107));
+ TESTINSN_bin_f64("vfnma.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6));
+ TESTINSN_bin_f64("vfnma.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109));
+ TESTINSN_bin_f64("vfnma.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752));
+ TESTINSN_bin_f64("vfnma.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47));
+ TESTINSN_bin_f64("vfnma.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676));
+ TESTINSN_bin_f64("vfnma.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY));
+ TESTINSN_bin_f64("vfnma.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f64("vfnma.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f32("vfnma.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnma.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnma.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0));
+ TESTINSN_bin_f32("vfnma.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0));
+ TESTINSN_bin_f32("vfnma.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnma.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687));
+ TESTINSN_bin_f32("vfnma.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346));
+ TESTINSN_bin_f32("vfnma.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476));
+ TESTINSN_bin_f32("vfnma.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065));
+ TESTINSN_bin_f32("vfnma.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76));
+ TESTINSN_bin_f32("vfnma.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346));
+ TESTINSN_bin_f32("vfnma.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089));
+ TESTINSN_bin_f32("vfnma.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065));
+ TESTINSN_bin_f32("vfnma.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009));
+ TESTINSN_bin_f32("vfnma.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575));
+ TESTINSN_bin_f32("vfnma.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107));
+ TESTINSN_bin_f32("vfnma.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6));
+ TESTINSN_bin_f32("vfnma.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109));
+ TESTINSN_bin_f32("vfnma.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752));
+ TESTINSN_bin_f32("vfnma.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47));
+ TESTINSN_bin_f32("vfnma.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676));
+ TESTINSN_bin_f32("vfnma.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY));
+ TESTINSN_bin_f32("vfnma.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0));
+ TESTINSN_bin_f32("vfnma.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0));
+
+ printf("---- VFNMS (fp, VFPv4) ----\n");
+ TESTINSN_bin_f64("vfnms.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnms.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnms.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0));
+ TESTINSN_bin_f64("vfnms.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f64("vfnms.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN));
+ TESTINSN_bin_f64("vfnms.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687));
+ TESTINSN_bin_f64("vfnms.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346));
+ TESTINSN_bin_f64("vfnms.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476));
+ TESTINSN_bin_f64("vfnms.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065));
+ TESTINSN_bin_f64("vfnms.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76));
+ TESTINSN_bin_f64("vfnms.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346));
+ TESTINSN_bin_f64("vfnms.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089));
+ TESTINSN_bin_f64("vfnms.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065));
+ TESTINSN_bin_f64("vfnms.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009));
+ TESTINSN_bin_f64("vfnms.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575));
+ TESTINSN_bin_f64("vfnms.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107));
+ TESTINSN_bin_f64("vfnms.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6));
+ TESTINSN_bin_f64("vfnms.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109));
+ TESTINSN_bin_f64("vfnms.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752));
+ TESTINSN_bin_f64("vfnms.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47));
+ TESTINSN_bin_f64("vfnms.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676));
+ TESTINSN_bin_f64("vfnms.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY));
+ TESTINSN_bin_f64("vfnms.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f64("vfnms.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0));
+ TESTINSN_bin_f32("vfnms.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnms.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnms.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0));
+ TESTINSN_bin_f32("vfnms.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0));
+ TESTINSN_bin_f32("vfnms.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN));
+ TESTINSN_bin_f32("vfnms.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687));
+ TESTINSN_bin_f32("vfnms.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346));
+ TESTINSN_bin_f32("vfnms.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476));
+ TESTINSN_bin_f32("vfnms.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065));
+ TESTINSN_bin_f32("vfnms.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76));
+ TESTINSN_bin_f32("vfnms.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346));
+ TESTINSN_bin_f32("vfnms.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089));
+ TESTINSN_bin_f32("vfnms.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065));
+ TESTINSN_bin_f32("vfnms.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009));
+ TESTINSN_bin_f32("vfnms.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575));
+ TESTINSN_bin_f32("vfnms.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107));
+ TESTINSN_bin_f32("vfnms.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6));
+ TESTINSN_bin_f32("vfnms.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109));
+ TESTINSN_bin_f32("vfnms.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752));
+ TESTINSN_bin_f32("vfnms.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47));
+ TESTINSN_bin_f32("vfnms.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676));
+ TESTINSN_bin_f32("vfnms.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY));
+ TESTINSN_bin_f32("vfnms.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0));
+ TESTINSN_bin_f32("vfnms.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0));
+
return 0;
}
Modified: branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.stdout.exp
==============================================================================
--- branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.stdout.exp (original)
+++ branches/VALGRIND_3_10_BRANCH/none/tests/arm/vfpv4_fma.stdout.exp Sun Nov 23 17:35:36 2014
@@ -96,3 +96,101 @@
vfms.f32 s0, s5, s2 :: Qd 0x55555555 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
vfms.f32 s20, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
vfms.f32 s10, s23, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
+---- VFNMA (fp, VFPv4) ----
+vfnma.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
+vfnma.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
+vfnma.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
+vfnma.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
+vfnma.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
+vfnma.f64 d20, d25, d22 :: Qd 0x40906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
+vfnma.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
+vfnma.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
+vfnma.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
+vfnma.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
+vfnma.f64 d23, d24, d5 :: Qd 0xc0df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000
+vfnma.f64 d10, d11, d2 :: Qd 0xc1895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
+vfnma.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
+vfnma.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
+vfnma.f64 d27, d21, d6 :: Qd 0xbfb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
+vfnma.f64 d30, d31, d2 :: Qd 0xc111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
+vfnma.f64 d13, d24, d5 :: Qd 0xc132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
+vfnma.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
+vfnma.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
+vfnma.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
+vfnma.f64 d27, d21, d16 :: Qd 0x40aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
+vfnma.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
+vfnma.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
+vfnma.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
+vfnma.f32 s0, s11, s12 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
+vfnma.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
+vfnma.f32 s0, s5, s2 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
+vfnma.f32 s10, s13, s15 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
+vfnma.f32 s10, s13, s15 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
+vfnma.f32 s20, s25, s22 :: Qd 0x55555555 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
+vfnma.f32 s23, s24, s25 :: Qd 0x55555555 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
+vfnma.f32 s20, s31, s12 :: Qd 0x55555555 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
+vfnma.f32 s19, s25, s27 :: Qd 0x55555555 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
+vfnma.f32 s30, s15, s2 :: Qd 0x55555555 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
+vfnma.f32 s23, s24, s5 :: Qd 0x55555555 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
+vfnma.f32 s10, s11, s2 :: Qd 0x55555555 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
+vfnma.f32 s29, s15, s7 :: Qd 0x55555555 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
+vfnma.f32 s30, s11, s12 :: Qd 0x55555555 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
+vfnma.f32 s27, s21, s6 :: Qd 0x55555555 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
+vfnma.f32 s30, s31, s2 :: Qd 0x55555555 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
+vfnma.f32 s13, s24, s5 :: Qd 0x55555555 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
+vfnma.f32 s10, s11, s2 :: Qd 0x55555555 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
+vfnma.f32 s29, s25, s7 :: Qd 0x55555555 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
+vfnma.f32 s0, s11, s12 :: Qd 0x55555555 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
+vfnma.f32 s27, s21, s16 :: Qd 0x55555555 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
+vfnma.f32 s0, s5, s2 :: Qd 0x55555555 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
+vfnma.f32 s20, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
+vfnma.f32 s10, s23, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
+---- VFNMS (fp, VFPv4) ----
+vfnms.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
+vfnms.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
+vfnms.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
+vfnms.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
+vfnms.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
+vfnms.f64 d20, d25, d22 :: Qd 0xc09067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
+vfnms.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
+vfnms.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
+vfnms.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
+vfnms.f64 d30, d15, d2 :: Qd 0x420524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
+vfnms.f64 d23, d24, d5 :: Qd 0x40df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000
+vfnms.f64 d10, d11, d2 :: Qd 0x41895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
+vfnms.f64 d29, d15, d7 :: Qd 0x41b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
+vfnms.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
+vfnms.f64 d27, d21, d6 :: Qd 0x3fb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
+vfnms.f64 d30, d31, d2 :: Qd 0x4111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
+vfnms.f64 d13, d24, d5 :: Qd 0x4132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
+vfnms.f64 d10, d11, d2 :: Qd 0x40e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
+vfnms.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
+vfnms.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
+vfnms.f64 d27, d21, d16 :: Qd 0xc0aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
+vfnms.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
+vfnms.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
+vfnms.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
+vfnms.f32 s0, s11, s12 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
+vfnms.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
+vfnms.f32 s0, s5, s2 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
+vfnms.f32 s10, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
+vfnms.f32 s10, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
+vfnms.f32 s20, s25, s22 :: Qd 0x55555555 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
+vfnms.f32 s23, s24, s25 :: Qd 0x55555555 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
+vfnms.f32 s20, s31, s12 :: Qd 0x55555555 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
+vfnms.f32 s19, s25, s27 :: Qd 0x55555555 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
+vfnms.f32 s30, s15, s2 :: Qd 0x55555555 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
+vfnms.f32 s23, s24, s5 :: Qd 0x55555555 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
+vfnms.f32 s10, s11, s2 :: Qd 0x55555555 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
+vfnms.f32 s29, s15, s7 :: Qd 0x55555555 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
+vfnms.f32 s30, s11, s12 :: Qd 0x55555555 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
+vfnms.f32 s27, s21, s6 :: Qd 0x55555555 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
+vfnms.f32 s30, s31, s2 :: Qd 0x55555555 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
+vfnms.f32 s13, s24, s5 :: Qd 0x55555555 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
+vfnms.f32 s10, s11, s2 :: Qd 0x55555555 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
+vfnms.f32 s29, s25, s7 :: Qd 0x55555555 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
+vfnms.f32 s0, s11, s12 :: Qd 0x55555555 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
+vfnms.f32 s27, s21, s16 :: Qd 0x55555555 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
+vfnms.f32 s0, s5, s2 :: Qd 0x55555555 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
+vfnms.f32 s20, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
+vfnms.f32 s10, s23, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
|
|
From: <sv...@va...> - 2014-11-23 17:35:01
|
Author: sewardj
Date: Sun Nov 23 17:34:54 2014
New Revision: 3020
Log:
Merge, from trunk, r2995
340807 disInstr(arm): unhandled instruction: 0xEE989B20
2995, testcase=14736.
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm_toIR.c Sun Nov 23 17:34:54 2014
@@ -13529,6 +13529,28 @@
condT);
DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
goto decode_success_vfp;
+ case BITS4(1,0,1,0): /* VNFMS: -(d - n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putDReg(dD, triop(Iop_AddF64, rm,
+ unop(Iop_NegF64, getDReg(dD)),
+ triop(Iop_MulF64, rm,
+ getDReg(dN),
+ getDReg(dM))),
+ condT);
+ DIP("vfnmsd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+ goto decode_success_vfp;
+ case BITS4(1,0,1,1): /* VNFMA: -(d + n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putDReg(dD, triop(Iop_AddF64, rm,
+ unop(Iop_NegF64, getDReg(dD)),
+ triop(Iop_MulF64, rm,
+ unop(Iop_NegF64, getDReg(dN)),
+ getDReg(dM))),
+ condT);
+ DIP("vfnmad%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+ goto decode_success_vfp;
case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */
/* XXXROUNDINGFIXME look up ARM reference for fused
multiply-add rounding */
@@ -14014,6 +14036,28 @@
condT);
DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
goto decode_success_vfp;
+ case BITS4(1,0,1,0): /* VNFMS: -(d - n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putFReg(fD, triop(Iop_AddF32, rm,
+ unop(Iop_NegF32, getFReg(fD)),
+ triop(Iop_MulF32, rm,
+ getFReg(fN),
+ getFReg(fM))),
+ condT);
+ DIP("vfnmss%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+ goto decode_success_vfp;
+ case BITS4(1,0,1,1): /* VNFMA: -(d + n * m) (fused) */
+ /* XXXROUNDINGFIXME look up ARM reference for fused
+ multiply-add rounding */
+ putFReg(fD, triop(Iop_AddF32, rm,
+ unop(Iop_NegF32, getFReg(fD)),
+ triop(Iop_MulF32, rm,
+ unop(Iop_NegF32, getFReg(fN)),
+ getFReg(fM))),
+ condT);
+ DIP("vfnmas%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+ goto decode_success_vfp;
case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */
/* XXXROUNDINGFIXME look up ARM reference for fused
multiply-add rounding */
|
|
From: <sv...@va...> - 2014-11-23 17:32:13
|
Author: sewardj
Date: Sun Nov 23 17:32:07 2014
New Revision: 3019
Log:
Merge, from trunk, r2994
2994 fix stupid bug introduced in 2993
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:32:07 2014
@@ -12171,9 +12171,11 @@
}
if (opcode <= BITS4(0,0,1,1)) {
// This is really not good code. TODO: avoid width-changing
+ IRTemp res = newTemp(ity);
+ assign(res, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
+ getQRegLO(nn, ity), getQRegLO(mm, ity)));
putQReg128(dd, mkV128(0));
- putQRegLO(dd, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn, ity), getQRegLO(mm, ity)));
+ putQRegLO(dd, mkexpr(res));
} else {
putQReg128(dd, unop(mkVecZEROHIxxOFV128(ty+2),
binop(iop, getQReg128(nn), getQReg128(mm))));
|
|
From: <sv...@va...> - 2014-11-23 17:31:17
|
Author: sewardj
Date: Sun Nov 23 17:31:10 2014
New Revision: 3018
Log:
Merge, from trunk, r2993
2993 arm64: implement ADDP etc
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c
branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h
branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:31:10 2014
@@ -29,48 +29,21 @@
The GNU General Public License is contained in the file COPYING.
*/
-//ZZ /* XXXX thumb to check:
-//ZZ that all cases where putIRegT writes r15, we generate a jump.
-//ZZ
-//ZZ All uses of newTemp assign to an IRTemp and not a UInt
-//ZZ
-//ZZ For all thumb loads and stores, including VFP ones, new-ITSTATE is
-//ZZ backed out before the memory op, and restored afterwards. This
-//ZZ needs to happen even after we go uncond. (and for sure it doesn't
-//ZZ happen for VFP loads/stores right now).
-//ZZ
-//ZZ VFP on thumb: check that we exclude all r13/r15 cases that we
-//ZZ should.
-//ZZ
-//ZZ XXXX thumb to do: improve the ITSTATE-zeroing optimisation by
-//ZZ taking into account the number of insns guarded by an IT.
-//ZZ
-//ZZ remove the nasty hack, in the spechelper, of looking for Or32(...,
-//ZZ 0xE0) in as the first arg to armg_calculate_condition, and instead
-//ZZ use Slice44 as specified in comments in the spechelper.
-//ZZ
-//ZZ add specialisations for armg_calculate_flag_c and _v, as they
-//ZZ are moderately often needed in Thumb code.
-//ZZ
-//ZZ Correctness: ITSTATE handling in Thumb SVCs is wrong.
-//ZZ
-//ZZ Correctness (obscure): in m_transtab, when invalidating code
-//ZZ address ranges, invalidate up to 18 bytes after the end of the
-//ZZ range. This is because the ITSTATE optimisation at the top of
-//ZZ _THUMB_WRK below analyses up to 18 bytes before the start of any
-//ZZ given instruction, and so might depend on the invalidated area.
-//ZZ */
-//ZZ
-//ZZ /* Limitations, etc
-//ZZ
-//ZZ - pretty dodgy exception semantics for {LD,ST}Mxx and {LD,ST}RD.
-//ZZ These instructions are non-restartable in the case where the
-//ZZ transfer(s) fault.
-//ZZ
-//ZZ - SWP: the restart jump back is Ijk_Boring; it should be
-//ZZ Ijk_NoRedir but that's expensive. See comments on casLE() in
-//ZZ guest_x86_toIR.c.
-//ZZ */
+/* KNOWN LIMITATIONS 2014-Nov-16
+
+ * Correctness: FMAXNM, FMINNM are implemented the same as FMAX/FMIN.
+
+ Also FP comparison "unordered" .. is implemented as normal FP
+ comparison.
+
+ Both should be fixed. They behave incorrectly in the presence of
+ NaNs.
+
+ * Floating multiply-add (etc) insns. Are split into a multiply and
+ an add, and so suffer double rounding and hence sometimes the
+ least significant mantissa bit is incorrect. Fix: use the IR
+ multiply-add IROps instead.
+*/
/* "Special" instructions.
@@ -989,6 +962,26 @@
return ops[size];
}
+static IROp mkVecADDF ( UInt size ) {
+ const IROp ops[4]
+ = { Iop_INVALID, Iop_INVALID, Iop_Add32Fx4, Iop_Add64Fx2 };
+ vassert(size < 4);
+ return ops[size];
+}
+
+static IROp mkVecMAXF ( UInt size ) {
+ const IROp ops[4]
+ = { Iop_INVALID, Iop_INVALID, Iop_Max32Fx4, Iop_Max64Fx2 };
+ vassert(size < 4);
+ return ops[size];
+}
+
+static IROp mkVecMINF ( UInt size ) {
+ const IROp ops[4]
+ = { Iop_INVALID, Iop_INVALID, Iop_Min32Fx4, Iop_Min64Fx2 };
+ vassert(size < 4);
+ return ops[size];
+}
/* Generate IR to create 'arg rotated right by imm', for sane values
of 'ty' and 'imm'. */
@@ -8039,6 +8032,55 @@
}
+/* Generate IR to rearrange two vector values in a way which is useful
+ for doing S/D add-pair etc operations. There are 3 cases:
+
+ 2d: [m1 m0] [n1 n0] --> [m1 n1] [m0 n0]
+
+ 4s: [m3 m2 m1 m0] [n3 n2 n1 n0] --> [m3 m1 n3 n1] [m2 m0 n2 n0]
+
+ 2s: [m2 m2 m1 m0] [n3 n2 n1 n0] --> [0 0 m1 n1] [0 0 m0 n0]
+
+ The cases are distinguished as follows:
+ isD == True, bitQ == 1 => 2d
+ isD == False, bitQ == 1 => 4s
+ isD == False, bitQ == 0 => 2s
+*/
+static
+void math_REARRANGE_FOR_FLOATING_PAIRWISE (
+ /*OUT*/IRTemp* rearrL, /*OUT*/IRTemp* rearrR,
+ IRTemp vecM, IRTemp vecN, Bool isD, UInt bitQ
+ )
+{
+ vassert(rearrL && *rearrL == IRTemp_INVALID);
+ vassert(rearrR && *rearrR == IRTemp_INVALID);
+ *rearrL = newTempV128();
+ *rearrR = newTempV128();
+ if (isD) {
+ // 2d case
+ vassert(bitQ == 1);
+ assign(*rearrL, binop(Iop_InterleaveHI64x2, mkexpr(vecM), mkexpr(vecN)));
+ assign(*rearrR, binop(Iop_InterleaveLO64x2, mkexpr(vecM), mkexpr(vecN)));
+ }
+ else if (!isD && bitQ == 1) {
+ // 4s case
+ assign(*rearrL, binop(Iop_CatOddLanes32x4, mkexpr(vecM), mkexpr(vecN)));
+ assign(*rearrR, binop(Iop_CatEvenLanes32x4, mkexpr(vecM), mkexpr(vecN)));
+ } else {
+ // 2s case
+ vassert(!isD && bitQ == 0);
+ IRTemp m1n1m0n0 = newTempV128();
+ IRTemp m0n0m1n1 = newTempV128();
+ assign(m1n1m0n0, binop(Iop_InterleaveLO32x4,
+ mkexpr(vecM), mkexpr(vecN)));
+ assign(m0n0m1n1, triop(Iop_SliceV128,
+ mkexpr(m1n1m0n0), mkexpr(m1n1m0n0), mkU8(8)));
+ assign(*rearrL, unop(Iop_ZeroHI64ofV128, mkexpr(m1n1m0n0)));
+ assign(*rearrR, unop(Iop_ZeroHI64ofV128, mkexpr(m0n0m1n1)));
+ }
+}
+
+
/*------------------------------------------------------------*/
/*--- SIMD and FP instructions ---*/
/*------------------------------------------------------------*/
@@ -8931,6 +8973,26 @@
return True;
}
+ if (bitU == 1 && sz <= X01 && opcode == BITS5(0,1,1,0,1)) {
+ /* -------- 1,00,01101 ADDP s_2s -------- */
+ /* -------- 1,01,01101 ADDP d_2d -------- */
+ Bool isD = sz == X01;
+ IROp opZHI = mkVecZEROHIxxOFV128(isD ? 3 : 2);
+ IROp opADD = mkVecADDF(isD ? 3 : 2);
+ IRTemp src = newTempV128();
+ IRTemp argL = newTempV128();
+ IRTemp argR = newTempV128();
+ assign(src, getQReg128(nn));
+ assign(argL, unop(opZHI, mkexpr(src)));
+ assign(argR, unop(opZHI, triop(Iop_SliceV128, mkexpr(src), mkexpr(src),
+ mkU8(isD ? 8 : 4))));
+ putQReg128(dd, unop(opZHI,
+ triop(opADD, mkexpr(mk_get_IR_rounding_mode()),
+ mkexpr(argL), mkexpr(argR))));
+ DIP(isD ? "faddp d%u, v%u.2d\n" : "faddp s%u, v%u.2s\n", dd, nn);
+ return True;
+ }
+
return False;
# undef INSN
}
@@ -11000,6 +11062,30 @@
return True;
}
+ if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,0,1,0)) {
+ /* -------- 1,0x,11010 FADDP 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
+ Bool isD = size == X01;
+ if (bitQ == 0 && isD) return False; // implied 1d case
+ IRTemp srcN = newTempV128();
+ IRTemp srcM = newTempV128();
+ IRTemp preL = IRTemp_INVALID;
+ IRTemp preR = IRTemp_INVALID;
+ assign(srcN, getQReg128(nn));
+ assign(srcM, getQReg128(mm));
+ math_REARRANGE_FOR_FLOATING_PAIRWISE(&preL, &preR,
+ srcM, srcN, isD, bitQ);
+ putQReg128(
+ dd, math_MAYBE_ZERO_HI64_fromE(
+ bitQ,
+ triop(mkVecADDF(isD ? 3 : 2),
+ mkexpr(mk_get_IR_rounding_mode()),
+ mkexpr(preL), mkexpr(preR))));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%s\n", "faddp",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
if (bitU == 1 && size <= X01 && opcode == BITS5(1,1,1,1,1)) {
/* -------- 1,0x,11111 FDIV 2d_2d_2d, 4s_4s_4s, 2s_2s_2s -------- */
Bool isD = (size & 1) == 1;
@@ -12047,6 +12133,7 @@
/* 31 28 23 21 20 15 11 9 4
000 11110 ty 1 m opcode 10 n d
The first 3 bits are really "M 0 S", but M and S are always zero.
+ Decode fields: ty, opcode
*/
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
if (INSN(31,24) != BITS8(0,0,0,1,1,1,1,0)
@@ -12059,27 +12146,38 @@
UInt nn = INSN(9,5);
UInt dd = INSN(4,0);
- if (ty <= X01 && opcode <= BITS4(0,0,1,1)) {
+ if (ty <= X01 && opcode <= BITS4(0,1,1,1)) {
/* ------- 0x,0000: FMUL d_d, s_s ------- */
/* ------- 0x,0001: FDIV d_d, s_s ------- */
/* ------- 0x,0010: FADD d_d, s_s ------- */
/* ------- 0x,0011: FSUB d_d, s_s ------- */
+ /* ------- 0x,0100: FMAX d_d, s_s ------- */
+ /* ------- 0x,0101: FMIN d_d, s_s ------- */
+ /* ------- 0x,0110: FMAXNM d_d, s_s ------- (FIXME KLUDGED) */
+ /* ------- 0x,0111: FMINNM d_d, s_s ------- (FIXME KLUDGED) */
IRType ity = ty == X00 ? Ity_F32 : Ity_F64;
IROp iop = Iop_INVALID;
const HChar* nm = "???";
switch (opcode) {
- case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ity); break;
- case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ity); break;
- case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ity); break;
- case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ity); break;
+ case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ity); break;
+ case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ity); break;
+ case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ity); break;
+ case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ity); break;
+ case BITS4(0,1,0,0): nm = "fmax"; iop = mkVecMAXF(ty+2); break;
+ case BITS4(0,1,0,1): nm = "fmin"; iop = mkVecMINF(ty+2); break;
+ case BITS4(0,1,1,0): nm = "fmaxnm"; iop = mkVecMAXF(ty+2); break; //!!
+ case BITS4(0,1,1,1): nm = "fminnm"; iop = mkVecMINF(ty+2); break; //!!
default: vassert(0);
}
- IRExpr* resE = triop(iop, mkexpr(mk_get_IR_rounding_mode()),
- getQRegLO(nn, ity), getQRegLO(mm, ity));
- IRTemp res = newTemp(ity);
- assign(res, resE);
- putQReg128(dd, mkV128(0));
- putQRegLO(dd, mkexpr(res));
+ if (opcode <= BITS4(0,0,1,1)) {
+ // This is really not good code. TODO: avoid width-changing
+ putQReg128(dd, mkV128(0));
+ putQRegLO(dd, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
+ getQRegLO(nn, ity), getQRegLO(mm, ity)));
+ } else {
+ putQReg128(dd, unop(mkVecZEROHIxxOFV128(ty+2),
+ binop(iop, getQReg128(nn), getQReg128(mm))));
+ }
DIP("%s %s, %s, %s\n",
nm, nameQRegLO(dd, ity), nameQRegLO(nn, ity), nameQRegLO(mm, ity));
return True;
@@ -12330,6 +12428,7 @@
|| (iop == Iop_F64toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Dn */
|| (iop == Iop_F64toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Dn */
|| (iop == Iop_F64toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Dn */
+ || (iop == Iop_F64toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,D */
/* F64toI32U */
|| (iop == Iop_F64toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Dn */
|| (iop == Iop_F64toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Dn */
@@ -12338,7 +12437,7 @@
|| (iop == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */
|| (iop == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */
|| (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
- || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST) /* FCVT{A,N}S Xd,Dn */
+ || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST)/* FCVT{A,N}S X,D */
/* F64toI64U */
|| (iop == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */
|| (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c Sun Nov 23 17:31:10 2014
@@ -589,6 +589,10 @@
case ARM64vecb_FSUB32x4: *nm = "fsub "; *ar = "4s"; return;
case ARM64vecb_FMUL32x4: *nm = "fmul "; *ar = "4s"; return;
case ARM64vecb_FDIV32x4: *nm = "fdiv "; *ar = "4s"; return;
+ case ARM64vecb_FMAX64x2: *nm = "fmax "; *ar = "2d"; return;
+ case ARM64vecb_FMAX32x4: *nm = "fmax "; *ar = "4s"; return;
+ case ARM64vecb_FMIN64x2: *nm = "fmin "; *ar = "2d"; return;
+ case ARM64vecb_FMIN32x4: *nm = "fmin "; *ar = "4s"; return;
case ARM64vecb_UMAX32x4: *nm = "umax "; *ar = "4s"; return;
case ARM64vecb_UMAX16x8: *nm = "umax "; *ar = "8h"; return;
case ARM64vecb_UMAX8x16: *nm = "umax "; *ar = "16b"; return;
@@ -4054,6 +4058,11 @@
011 01110 01 1 m 111111 n d FDIV Vd.2d, Vn.2d, Vm.2d
011 01110 00 1 m 111111 n d FDIV Vd.4s, Vn.4s, Vm.4s
+ 010 01110 01 1 m 111101 n d FMAX Vd.2d, Vn.2d, Vm.2d
+ 010 01110 00 1 m 111101 n d FMAX Vd.4s, Vn.4s, Vm.4s
+ 010 01110 11 1 m 111101 n d FMIN Vd.2d, Vn.2d, Vm.2d
+ 010 01110 10 1 m 111101 n d FMIN Vd.4s, Vn.4s, Vm.4s
+
011 01110 10 1 m 011001 n d UMAX Vd.4s, Vn.4s, Vm.4s
011 01110 01 1 m 011001 n d UMAX Vd.8h, Vn.8h, Vm.8h
011 01110 00 1 m 011001 n d UMAX Vd.16b, Vn.16b, Vm.16b
@@ -4230,6 +4239,19 @@
*p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X111111, vN, vD);
break;
+ case ARM64vecb_FMAX64x2:
+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X111101, vN, vD);
+ break;
+ case ARM64vecb_FMAX32x4:
+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X111101, vN, vD);
+ break;
+ case ARM64vecb_FMIN64x2:
+ *p++ = X_3_8_5_6_5_5(X010, X01110111, vM, X111101, vN, vD);
+ break;
+ case ARM64vecb_FMIN32x4:
+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X111101, vN, vD);
+ break;
+
case ARM64vecb_UMAX32x4:
*p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X011001, vN, vD);
break;
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h Sun Nov 23 17:31:10 2014
@@ -317,6 +317,8 @@
ARM64vecb_FSUB64x2, ARM64vecb_FSUB32x4,
ARM64vecb_FMUL64x2, ARM64vecb_FMUL32x4,
ARM64vecb_FDIV64x2, ARM64vecb_FDIV32x4,
+ ARM64vecb_FMAX64x2, ARM64vecb_FMAX32x4,
+ ARM64vecb_FMIN64x2, ARM64vecb_FMIN32x4,
ARM64vecb_UMAX32x4,
ARM64vecb_UMAX16x8, ARM64vecb_UMAX8x16,
ARM64vecb_UMIN32x4,
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c Sun Nov 23 17:31:10 2014
@@ -2405,6 +2405,8 @@
case Iop_Rsh32Sx4: case Iop_Rsh64Sx2:
case Iop_Rsh8Ux16: case Iop_Rsh16Ux8:
case Iop_Rsh32Ux4: case Iop_Rsh64Ux2:
+ case Iop_Max64Fx2: case Iop_Max32Fx4:
+ case Iop_Min64Fx2: case Iop_Min32Fx4:
{
HReg res = newVRegV(env);
HReg argL = iselV128Expr(env, e->Iex.Binop.arg1);
@@ -2522,6 +2524,10 @@
case Iop_Rsh16Ux8: op = ARM64vecb_URSHL16x8; break;
case Iop_Rsh32Ux4: op = ARM64vecb_URSHL32x4; break;
case Iop_Rsh64Ux2: op = ARM64vecb_URSHL64x2; break;
+ case Iop_Max64Fx2: op = ARM64vecb_FMAX64x2; break;
+ case Iop_Max32Fx4: op = ARM64vecb_FMAX32x4; break;
+ case Iop_Min64Fx2: op = ARM64vecb_FMIN64x2; break;
+ case Iop_Min32Fx4: op = ARM64vecb_FMIN32x4; break;
default: vassert(0);
}
if (sw) {
|
|
From: <sv...@va...> - 2014-11-23 17:29:17
|
Author: sewardj
Date: Sun Nov 23 17:29:10 2014
New Revision: 3017
Log:
Merge, from trunk, r2992.
2992 arm64: Implement "fcvtpu w, s". n-i-bz.
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:29:10 2014
@@ -12319,6 +12319,7 @@
/* F32toI32U */
|| (iop == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */
|| (iop == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */
+ || (iop == Iop_F32toI32U && irrm == Irrm_PosINF) /* FCVTPU Wd,Sn */
|| (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */
/* F32toI64S */
|| (iop == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */
|
|
From: <sv...@va...> - 2014-11-23 17:28:25
|
Author: sewardj
Date: Sun Nov 23 17:28:18 2014
New Revision: 3016
Log:
Merge, from trunk, r2991.
340856 disInstr(arm64): unhandled instruction 0x1E634C45 (fcsel)
2991
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c
branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h
branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:28:18 2014
@@ -11844,7 +11844,40 @@
static
Bool dis_AdvSIMD_fp_conditional_select(/*MB_OUT*/DisResult* dres, UInt insn)
{
+ /* 31 23 21 20 15 11 9 5
+ 000 11110 ty 1 m cond 11 n d
+ The first 3 bits are really "M 0 S", but M and S are always zero.
+ Decode fields: ty
+ */
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,24) != BITS8(0,0,0,1,1,1,1,0) || INSN(21,21) != 1
+ || INSN(11,10) != BITS2(1,1)) {
+ return False;
+ }
+ UInt ty = INSN(23,22);
+ UInt mm = INSN(20,16);
+ UInt cond = INSN(15,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ if (ty <= X01) {
+ /* -------- 00: FCSEL s_s -------- */
+ /* -------- 00: FCSEL d_d -------- */
+ IRType ity = ty == X01 ? Ity_F64 : Ity_F32;
+ IRTemp srcT = newTemp(ity);
+ IRTemp srcF = newTemp(ity);
+ IRTemp res = newTemp(ity);
+ assign(srcT, getQRegLO(nn, ity));
+ assign(srcF, getQRegLO(mm, ity));
+ assign(res, IRExpr_ITE(
+ unop(Iop_64to1, mk_arm64g_calculate_condition(cond)),
+ mkexpr(srcT), mkexpr(srcF)));
+ putQReg128(dd, mkV128(0x0000));
+ putQRegLO(dd, mkexpr(res));
+ DIP("fcsel %s, %s, %s, %s\n",
+ nameQRegLO(dd, ity), nameQRegLO(nn, ity), nameQRegLO(mm, ity),
+ nameCC(cond));
+ return True;
+ }
return False;
# undef INSN
}
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_defs.c Sun Nov 23 17:28:18 2014
@@ -1112,6 +1112,17 @@
i->ARM64in.VCmpS.argR = argR;
return i;
}
+ARM64Instr* ARM64Instr_VFCSel ( HReg dst, HReg argL, HReg argR,
+ ARM64CondCode cond, Bool isD ) {
+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
+ i->tag = ARM64in_VFCSel;
+ i->ARM64in.VFCSel.dst = dst;
+ i->ARM64in.VFCSel.argL = argL;
+ i->ARM64in.VFCSel.argR = argR;
+ i->ARM64in.VFCSel.cond = cond;
+ i->ARM64in.VFCSel.isD = isD;
+ return i;
+}
ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ) {
ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr));
i->tag = ARM64in_FPCR;
@@ -1646,6 +1657,18 @@
vex_printf(", ");
ppHRegARM64asSreg(i->ARM64in.VCmpS.argR);
return;
+ case ARM64in_VFCSel: {
+ void (*ppHRegARM64fp)(HReg)
+ = (i->ARM64in.VFCSel.isD ? ppHRegARM64 : ppHRegARM64asSreg);
+ vex_printf("fcsel ");
+ ppHRegARM64fp(i->ARM64in.VFCSel.dst);
+ vex_printf(", ");
+ ppHRegARM64fp(i->ARM64in.VFCSel.argL);
+ vex_printf(", ");
+ ppHRegARM64fp(i->ARM64in.VFCSel.argR);
+ vex_printf(", %s", showARM64CondCode(i->ARM64in.VFCSel.cond));
+ return;
+ }
case ARM64in_FPCR:
if (i->ARM64in.FPCR.toFPCR) {
vex_printf("msr fpcr, ");
@@ -2028,6 +2051,11 @@
addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argL);
addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argR);
return;
+ case ARM64in_VFCSel:
+ addHRegUse(u, HRmRead, i->ARM64in.VFCSel.argL);
+ addHRegUse(u, HRmRead, i->ARM64in.VFCSel.argR);
+ addHRegUse(u, HRmWrite, i->ARM64in.VFCSel.dst);
+ return;
case ARM64in_FPCR:
if (i->ARM64in.FPCR.toFPCR)
addHRegUse(u, HRmRead, i->ARM64in.FPCR.iReg);
@@ -2256,6 +2284,11 @@
i->ARM64in.VCmpS.argL = lookupHRegRemap(m, i->ARM64in.VCmpS.argL);
i->ARM64in.VCmpS.argR = lookupHRegRemap(m, i->ARM64in.VCmpS.argR);
return;
+ case ARM64in_VFCSel:
+ i->ARM64in.VFCSel.argL = lookupHRegRemap(m, i->ARM64in.VFCSel.argL);
+ i->ARM64in.VFCSel.argR = lookupHRegRemap(m, i->ARM64in.VFCSel.argR);
+ i->ARM64in.VFCSel.dst = lookupHRegRemap(m, i->ARM64in.VFCSel.dst);
+ return;
case ARM64in_FPCR:
i->ARM64in.FPCR.iReg = lookupHRegRemap(m, i->ARM64in.FPCR.iReg);
return;
@@ -3958,6 +3991,21 @@
*p++ = X_3_8_5_6_5_5(X000, X11110001, sM, X001000, sN, X00000);
goto done;
}
+ case ARM64in_VFCSel: {
+ /* 31 23 21 20 15 11 9 5
+ 000 11110 00 1 m cond 11 n d FCSEL Sd,Sn,Sm,cond
+ 000 11110 01 1 m cond 11 n d FCSEL Dd,Dn,Dm,cond
+ */
+ Bool isD = i->ARM64in.VFCSel.isD;
+ UInt dd = dregNo(i->ARM64in.VFCSel.dst);
+ UInt nn = dregNo(i->ARM64in.VFCSel.argL);
+ UInt mm = dregNo(i->ARM64in.VFCSel.argR);
+ UInt cond = (UInt)i->ARM64in.VFCSel.cond;
+ vassert(cond < 16);
+ *p++ = X_3_8_5_6_5_5(X000, isD ? X11110011 : X11110001,
+ mm, (cond << 2) | X000011, nn, dd);
+ goto done;
+ }
case ARM64in_FPCR: {
Bool toFPCR = i->ARM64in.FPCR.toFPCR;
UInt iReg = iregNo(i->ARM64in.FPCR.iReg);
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_defs.h Sun Nov 23 17:28:18 2014
@@ -491,6 +491,7 @@
ARM64in_VBinS,
ARM64in_VCmpD,
ARM64in_VCmpS,
+ ARM64in_VFCSel,
ARM64in_FPCR,
ARM64in_FPSR,
/* ARM64in_V*V: vector ops on vector registers */
@@ -743,6 +744,15 @@
HReg argL;
HReg argR;
} VCmpS;
+ /* 32- or 64-bit FP conditional select */
+ struct {
+ HReg dst;
+ HReg argL;
+ HReg argR;
+ ARM64CondCode cond;
+ Bool isD;
+ }
+ VFCSel;
/* Move a 32-bit value to/from the FPCR */
struct {
Bool toFPCR;
@@ -889,6 +899,8 @@
extern ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, HReg, HReg, HReg );
extern ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR );
extern ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR );
+extern ARM64Instr* ARM64Instr_VFCSel ( HReg dst, HReg argL, HReg argR,
+ ARM64CondCode cond, Bool isD );
extern ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg );
extern ARM64Instr* ARM64Instr_FPSR ( Bool toFPSR, HReg iReg );
extern ARM64Instr* ARM64Instr_VBinV ( ARM64VecBinOp op, HReg, HReg, HReg );
Modified: branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c (original)
+++ branches/VEX_3_10_BRANCH/priv/host_arm64_isel.c Sun Nov 23 17:28:18 2014
@@ -3067,6 +3067,17 @@
}
}
+ if (e->tag == Iex_ITE) {
+ /* ITE(ccexpr, iftrue, iffalse) */
+ ARM64CondCode cc;
+ HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue);
+ HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse);
+ HReg dst = newVRegD(env);
+ cc = iselCondCode(env, e->Iex.ITE.cond);
+ addInstr(env, ARM64Instr_VFCSel(dst, r1, r0, cc, True/*64-bit*/));
+ return dst;
+ }
+
ppIRExpr(e);
vpanic("iselDblExpr_wrk");
}
@@ -3222,6 +3233,17 @@
}
}
+ if (e->tag == Iex_ITE) {
+ /* ITE(ccexpr, iftrue, iffalse) */
+ ARM64CondCode cc;
+ HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
+ HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
+ HReg dst = newVRegD(env);
+ cc = iselCondCode(env, e->Iex.ITE.cond);
+ addInstr(env, ARM64Instr_VFCSel(dst, r1, r0, cc, False/*!64-bit*/));
+ return dst;
+ }
+
ppIRExpr(e);
vpanic("iselFltExpr_wrk");
}
|
|
From: <sv...@va...> - 2014-11-23 17:27:18
|
Author: sewardj
Date: Sun Nov 23 17:27:11 2014
New Revision: 3015
Log:
Merge, from trunk, r2990.
2990 Add detection of old ppc32 magic instructions from bug 278808.
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_ppc_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_ppc_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_ppc_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_ppc_toIR.c Sun Nov 23 17:27:11 2014
@@ -18782,10 +18782,26 @@
UInt word2 = mode64 ? 0x78006800 : 0x5400683E;
UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E;
UInt word4 = mode64 ? 0x78009802 : 0x5400983E;
+ Bool is_special_preamble = False;
if (getUIntPPCendianly(code+ 0) == word1 &&
getUIntPPCendianly(code+ 4) == word2 &&
getUIntPPCendianly(code+ 8) == word3 &&
getUIntPPCendianly(code+12) == word4) {
+ is_special_preamble = True;
+ } else if (! mode64 &&
+ getUIntPPCendianly(code+ 0) == 0x54001800 &&
+ getUIntPPCendianly(code+ 4) == 0x54006800 &&
+ getUIntPPCendianly(code+ 8) == 0x5400E800 &&
+ getUIntPPCendianly(code+12) == 0x54009800) {
+ static Bool reported = False;
+ if (!reported) {
+ vex_printf("disInstr(ppc): old ppc32 instruction magic detected. Code might clobber r0.\n");
+ vex_printf("disInstr(ppc): source needs to be recompiled against latest valgrind.h.\n");
+ reported = True;
+ }
+ is_special_preamble = True;
+ }
+ if (is_special_preamble) {
/* Got a "Special" instruction preamble. Which one is it? */
if (getUIntPPCendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) {
/* %R3 = client_request ( %R4 ) */
|
|
From: <sv...@va...> - 2014-11-23 17:26:00
|
Author: sewardj
Date: Sun Nov 23 17:25:53 2014
New Revision: 3014
Log:
Merge, from trunk, r2988
340725 AVX2: Incorrect decoding of vpbroadcast{b,w} reg,reg forms
2988
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_amd64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_amd64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_amd64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_amd64_toIR.c Sun Nov 23 17:25:53 2014
@@ -28661,6 +28661,7 @@
IRTemp t8 = newTemp(Ity_I8);
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
} else {
@@ -28687,6 +28688,7 @@
IRTemp t8 = newTemp(Ity_I8);
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
DIP("vpbroadcastb %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
assign(t8, unop(Iop_32to8, getXMMRegLane32(rE, 0)));
} else {
@@ -28717,6 +28719,7 @@
IRTemp t16 = newTemp(Ity_I16);
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
} else {
@@ -28741,6 +28744,7 @@
IRTemp t16 = newTemp(Ity_I16);
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx, modrm);
+ delta++;
DIP("vpbroadcastw %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
assign(t16, unop(Iop_32to16, getXMMRegLane32(rE, 0)));
} else {
|
|
From: <sv...@va...> - 2014-11-23 17:24:58
|
Author: sewardj
Date: Sun Nov 23 17:24:51 2014
New Revision: 3013
Log:
Merge, from trunk, r2987
340632 arm64: unhandled instruction fcvtas
2987
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:24:51 2014
@@ -12304,6 +12304,7 @@
|| (iop == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */
|| (iop == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */
|| (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
+ || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST) /* FCVT{A,N}S Xd,Dn */
/* F64toI64U */
|| (iop == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */
|| (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */
|
|
From: <sv...@va...> - 2014-11-23 17:23:31
|
Author: sewardj
Date: Sun Nov 23 17:23:24 2014
New Revision: 3012
Log:
Merge, from trunk, r2986
340033 arm64: unhandled instruction for dmb ishld and some other
isb-dmb-dsb variants...
2986
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:23:24 2014
@@ -6763,29 +6763,25 @@
}
/* ------------------ ISB, DMB, DSB ------------------ */
- if (INSN(31,0) == 0xD5033FDF) {
- stmt(IRStmt_MBE(Imbe_Fence));
- DIP("isb\n");
- return True;
- }
- if (INSN(31,0) == 0xD5033FBF) {
- stmt(IRStmt_MBE(Imbe_Fence));
- DIP("dmb sy\n");
- return True;
- }
- if (INSN(31,0) == 0xD5033BBF) {
- stmt(IRStmt_MBE(Imbe_Fence));
- DIP("dmb ish\n");
- return True;
- }
- if (INSN(31,0) == 0xD5033ABF) {
- stmt(IRStmt_MBE(Imbe_Fence));
- DIP("dmb ishst\n");
- return True;
- }
- if (INSN(31,0) == 0xD5033B9F) {
+ /* 31 21 11 7 6 4
+ 11010 10100 0 00 011 0011 CRm 1 01 11111 DMB opt
+ 11010 10100 0 00 011 0011 CRm 1 00 11111 DSB opt
+ 11010 10100 0 00 011 0011 CRm 1 10 11111 ISB opt
+ */
+ if (INSN(31,22) == BITS10(1,1,0,1,0,1,0,1,0,0)
+ && INSN(21,12) == BITS10(0,0,0,0,1,1,0,0,1,1)
+ && INSN(7,7) == 1
+ && INSN(6,5) <= BITS2(1,0) && INSN(4,0) == BITS5(1,1,1,1,1)) {
+ UInt opc = INSN(6,5);
+ UInt CRm = INSN(11,8);
+ vassert(opc <= 2 && CRm <= 15);
stmt(IRStmt_MBE(Imbe_Fence));
- DIP("dsb ish\n");
+ const HChar* opNames[3]
+ = { "dsb", "dmb", "isb" };
+ const HChar* howNames[16]
+ = { "#0", "oshld", "oshst", "osh", "#4", "nshld", "nshst", "nsh",
+ "#8", "ishld", "ishst", "ish", "#12", "ld", "st", "sy" };
+ DIP("%s %s\n", opNames[opc], howNames[CRm]);
return True;
}
|
|
From: <sv...@va...> - 2014-11-23 17:22:23
|
Author: sewardj
Date: Sun Nov 23 17:22:16 2014
New Revision: 3011
Log:
Merge, from trunk, r2985
335713 arm64: unhanded instruction: prfm (immediate)
2985
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:22:16 2014
@@ -6358,6 +6358,22 @@
return True;
}
+ /* ------------------ PRFM (immediate) ------------------ */
+ /* 31 21 9 4
+ 11 111 00110 imm12 n t PRFM pfrop=Rt, [Xn|SP, #pimm]
+ */
+ if (INSN(31,22) == BITS10(1,1,1,1,1,0,0,1,1,0)) {
+ UInt imm12 = INSN(21,10);
+ UInt nn = INSN(9,5);
+ UInt tt = INSN(4,0);
+ /* Generating any IR here is pointless, except for documentation
+ purposes, as it will get optimised away later. */
+ IRTemp ea = newTemp(Ity_I64);
+ assign(ea, binop(Iop_Add64, getIReg64orSP(nn), mkU64(imm12 * 8)));
+ DIP("prfm prfop=%u, [%s, #%u]\n", tt, nameIReg64orSP(nn), imm12 * 8);
+ return True;
+ }
+
vex_printf("ARM64 front end: load_store\n");
return False;
# undef INSN
|
|
From: <sv...@va...> - 2014-11-23 17:21:19
|
Author: sewardj
Date: Sun Nov 23 17:21:12 2014
New Revision: 3010
Log:
Merge, from trunk, r2984
340509 arm64: unhandled instruction fcvtas
2984
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:21:12 2014
@@ -12189,6 +12189,7 @@
/* 31 30 29 28 23 21 20 18 15 9 4
sf 0 0 11110 type 1 rmode opcode 000000 n d
The first 3 bits are really "sf 0 S", but S is always zero.
+ Decode fields: sf,type,rmode,opcode
*/
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
if (INSN(30,29) != BITS2(0,0)
@@ -12205,7 +12206,7 @@
UInt dd = INSN(4,0);
// op = 000, 001
- /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */
+ /* -------- FCVT{N,P,M,Z,A}{S,U} (scalar, integer) -------- */
/* 30 23 20 18 15 9 4
sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to
sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest)
@@ -12213,23 +12214,38 @@
---------------- 10 -------------- FCVTM-------- (round to -inf)
---------------- 11 -------------- FCVTZ-------- (round to zero)
+ ---------------- 00 100 ---------- FCVTAS------- (nearest, ties away)
+ ---------------- 00 101 ---------- FCVTAU------- (nearest, ties away)
+
Rd is Xd when sf==1, Wd when sf==0
Fn is Dn when x==1, Sn when x==0
20:19 carry the rounding mode, using the same encoding as FPCR
*/
- if (ty <= X01 && (op == BITS3(0,0,0) || op == BITS3(0,0,1))) {
+ if (ty <= X01
+ && ( ((op == BITS3(0,0,0) || op == BITS3(0,0,1)) && True)
+ || ((op == BITS3(1,0,0) || op == BITS3(1,0,1)) && rm == BITS2(0,0))
+ )
+ ) {
Bool isI64 = bitSF == 1;
Bool isF64 = (ty & 1) == 1;
Bool isU = (op & 1) == 1;
/* Decide on the IR rounding mode to use. */
IRRoundingMode irrm = 8; /*impossible*/
HChar ch = '?';
- switch (rm) {
- case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break;
- case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break;
- case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break;
- case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break;
- default: vassert(0);
+ if (op == BITS3(0,0,0) || op == BITS3(0,0,1)) {
+ switch (rm) {
+ case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break;
+ case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break;
+ case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break;
+ case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break;
+ default: vassert(0);
+ }
+ } else {
+ vassert(op == BITS3(1,0,0) || op == BITS3(1,0,1));
+ switch (rm) {
+ case BITS2(0,0): ch = 'a'; irrm = Irrm_NEAREST; break;
+ default: vassert(0);
+ }
}
vassert(irrm != 8);
/* Decide on the conversion primop, based on the source size,
@@ -12254,9 +12270,11 @@
(iop == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */
|| (iop == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */
|| (iop == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */
+ || (iop == Iop_F32toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,S */
/* F32toI32U */
|| (iop == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */
|| (iop == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */
+ || (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */
/* F32toI64S */
|| (iop == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */
/* F32toI64U */
|
|
From: <sv...@va...> - 2014-11-23 17:20:16
|
Author: sewardj
Date: Sun Nov 23 17:20:09 2014
New Revision: 3009
Log:
Merge, from trunk, r2983
339938 disInstr(arm64): unhandled instruction 0x4F8010A4 (fmla)
== 339950
2983
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:20:09 2014
@@ -11458,6 +11458,41 @@
vassert(size < 4);
vassert(bitH < 2 && bitM < 2 && bitL < 2);
+ if (bitU == 0 && size >= X10
+ && (opcode == BITS4(0,0,0,1) || opcode == BITS4(0,1,0,1))) {
+ /* -------- 0,1x,0001 FMLA 2d_2d_d[], 4s_4s_s[], 2s_2s_s[] -------- */
+ /* -------- 0,1x,0101 FMLS 2d_2d_d[], 4s_4s_s[], 2s_2s_s[] -------- */
+ if (bitQ == 0 && size == X11) return False; // implied 1d case
+ Bool isD = (size & 1) == 1;
+ Bool isSUB = opcode == BITS4(0,1,0,1);
+ UInt index;
+ if (!isD) index = (bitH << 1) | bitL;
+ else if (isD && bitL == 0) index = bitH;
+ else return False; // sz:L == x11 => unallocated encoding
+ vassert(index < (isD ? 2 : 4));
+ IRType ity = isD ? Ity_F64 : Ity_F32;
+ IRTemp elem = newTemp(ity);
+ UInt mm = (bitM << 4) | mmLO4;
+ assign(elem, getQRegLane(mm, index, ity));
+ IRTemp dupd = math_DUP_TO_V128(elem, ity);
+ IROp opADD = isD ? Iop_Add64Fx2 : Iop_Add32Fx4;
+ IROp opSUB = isD ? Iop_Sub64Fx2 : Iop_Sub32Fx4;
+ IROp opMUL = isD ? Iop_Mul64Fx2 : Iop_Mul32Fx4;
+ IRTemp rm = mk_get_IR_rounding_mode();
+ IRTemp t1 = newTempV128();
+ IRTemp t2 = newTempV128();
+ // FIXME: double rounding; use FMA primops instead
+ assign(t1, triop(opMUL, mkexpr(rm), getQReg128(nn), mkexpr(dupd)));
+ assign(t2, triop(isSUB ? opSUB : opADD,
+ mkexpr(rm), getQReg128(dd), mkexpr(t1)));
+ putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2));
+ const HChar* arr = bitQ == 0 ? "2s" : (isD ? "2d" : "4s");
+ DIP("%s %s.%s, %s.%s, %s.%c[%u]\n", isSUB ? "fmls" : "fmla",
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm),
+ isD ? 'd' : 's', index);
+ return True;
+ }
+
if (bitU == 0 && size >= X10 && opcode == BITS4(1,0,0,1)) {
/* -------- 0,1x,1001 FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[] -------- */
if (bitQ == 0 && size == X11) return False; // implied 1d case
|
|
From: <sv...@va...> - 2014-11-23 17:18:53
|
Author: sewardj
Date: Sun Nov 23 17:18:46 2014
New Revision: 3008
Log:
Merge, from trunk, r2982
339927 Unhandled instruction 0x9E7100C6 (fcvtmu) on aarch64
2982
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:18:46 2014
@@ -12241,6 +12241,7 @@
|| (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
/* F64toI64U */
|| (iop == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */
+ || (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */
|| (iop == Iop_F64toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Dn */
) {
/* validated */
|