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Author: carll
Date: Thu Aug 7 23:49:27 2014
New Revision: 14240
Log:
This commit is for Bugzilla 334836. The Bugzilla contains patch 3 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334384 and 334834. Note, there are no VEX changes in this patch.
PP64 Little Endian test case fixes.
This patch adds new LE and BE expect files where needed. In other
cases, the test was fixed to run correctly on LE and BE using based on
testing to see which platform is being used.
Where practical, the test cases have been changed so that the output
produced for BE and LE will be identical. The test cases that require
a major rewrite to make the output identical for BE and LE simply
had an additional expect file added.
Signed-off-by: Carl Love <ca...@us...>
Added:
trunk/none/tests/ppc32/jm-fp.stdout.exp-BE2
trunk/none/tests/ppc32/round.stdout.exp-RM-fix
trunk/none/tests/ppc64/jm-fp.stdout.exp-BE2
trunk/none/tests/ppc64/jm-fp.stdout.exp-LE
trunk/none/tests/ppc64/jm-fp.stdout.exp-LE2
trunk/none/tests/ppc64/jm-int.stdout.exp-LE
trunk/none/tests/ppc64/jm-vmx.stdout.exp-LE
trunk/none/tests/ppc64/round.stdout.exp-RM-fix
trunk/none/tests/ppc64/std_reg_imm.stdout.exp-LE
trunk/none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
trunk/tests/is_ppc64_BE.c
Modified:
trunk/coregrind/launcher-darwin.c
trunk/coregrind/vg_preloaded.c
trunk/helgrind/tests/tc11_XCHG.c
trunk/memcheck/tests/atomic_incs.c
trunk/memcheck/tests/badjump.c
trunk/memcheck/tests/ppc64/power_ISA2_05.c
trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
trunk/none/tests/amd64/xadd.c
trunk/none/tests/ppc32/Makefile.am
trunk/none/tests/ppc32/jm-insns.c
trunk/none/tests/ppc32/jm-int.stdout.exp
trunk/none/tests/ppc32/jm-vmx.stdout.exp
trunk/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
trunk/none/tests/ppc32/round.stdout.exp
trunk/none/tests/ppc32/test_dfp4.c
trunk/none/tests/ppc32/test_dfp5.c
trunk/none/tests/ppc32/test_isa_2_06_part1.c
trunk/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
trunk/none/tests/ppc32/test_isa_2_06_part2.c
trunk/none/tests/ppc32/test_isa_2_06_part3.c
trunk/none/tests/ppc32/test_isa_2_07_part2.stdout.exp
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/jm-fp.stdout.exp
trunk/none/tests/ppc64/jm-int.stdout.exp
trunk/none/tests/ppc64/jm-vmx.stdout.exp
trunk/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
trunk/none/tests/ppc64/lsw.vgtest
trunk/none/tests/ppc64/round.c
trunk/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
trunk/none/tests/ppc64/test_isa_2_07_part1.c
trunk/none/tests/ppc64/test_isa_2_07_part2.c
trunk/none/tests/ppc64/test_isa_2_07_part2.stdout.exp
trunk/tests/Makefile.am
trunk/tests/check_isa-2_06_cap
trunk/tests/check_isa-2_07_cap
Modified: trunk/coregrind/launcher-darwin.c
==============================================================================
--- trunk/coregrind/launcher-darwin.c (original)
+++ trunk/coregrind/launcher-darwin.c Thu Aug 7 23:49:27 2014
@@ -64,7 +64,6 @@
{ CPU_TYPE_ARM, "arm", "arm" },
{ CPU_TYPE_POWERPC, "ppc", "ppc32" },
{ CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
- { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" },
};
static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
Modified: trunk/coregrind/vg_preloaded.c
==============================================================================
--- trunk/coregrind/vg_preloaded.c (original)
+++ trunk/coregrind/vg_preloaded.c Thu Aug 7 23:49:27 2014
@@ -83,8 +83,8 @@
VALGRIND_GET_ORIG_FN(fn);
CALL_FN_W_v(result, fn);
-#if defined(VGP_ppc64_linux)
- /* ppc64 uses function descriptors, so get the actual function entry
+#if defined(VGP_ppc64be_linux)
+ /* ppc64be uses function descriptors, so get the actual function entry
address for the client request, but return the function descriptor
from this function.
result points to the function descriptor, which starts with the
Modified: trunk/helgrind/tests/tc11_XCHG.c
==============================================================================
--- trunk/helgrind/tests/tc11_XCHG.c (original)
+++ trunk/helgrind/tests/tc11_XCHG.c Thu Aug 7 23:49:27 2014
@@ -14,7 +14,7 @@
#undef PLAT_x86_linux
#undef PLAT_amd64_linux
#undef PLAT_ppc32_linux
-#undef PLAT_ppc64_linux
+#undef PLAT_ppc64be_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
#undef PLAT_mips32_linux
Modified: trunk/memcheck/tests/atomic_incs.c
==============================================================================
--- trunk/memcheck/tests/atomic_incs.c (original)
+++ trunk/memcheck/tests/atomic_incs.c Thu Aug 7 23:49:27 2014
@@ -79,6 +79,23 @@
: /*trash*/ "memory", "cc", "r15"
);
} while (success != 1);
+#elif defined(VGA_ppc64le)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+ do {
+ __asm__ __volatile__(
+ "ldarx 15,0,%1" "\n\t"
+ "add 15,15,%2" "\n\t"
+ "stdcx. 15,0,%1" "\n\t"
+ "mfcr %0" "\n\t"
+ "srwi %0,%0,29" "\n\t"
+ "andi. %0,%0,1" "\n"
+ : /*out*/"=b"(success)
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
#elif defined(VGA_arm)
unsigned int block[3]
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
@@ -278,6 +295,23 @@
: /*trash*/ "memory", "cc", "r15"
);
} while (success != 1);
+#elif defined(VGA_ppc64le)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+ do {
+ __asm__ __volatile__(
+ "ldarx 15,0,%1" "\n\t"
+ "add 15,15,%2" "\n\t"
+ "stdcx. 15,0,%1" "\n\t"
+ "mfcr %0" "\n\t"
+ "srwi %0,%0,29" "\n\t"
+ "andi. %0,%0,1" "\n"
+ : /*out*/"=b"(success)
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
#elif defined(VGA_arm)
unsigned int block[3]
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
@@ -474,6 +508,23 @@
: /*trash*/ "memory", "cc", "r15"
);
} while (success != 1);
+#elif defined(VGA_ppc64le)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+ do {
+ __asm__ __volatile__(
+ "ldarx 15,0,%1" "\n\t"
+ "add 15,15,%2" "\n\t"
+ "stdcx. 15,0,%1" "\n\t"
+ "mfcr %0" "\n\t"
+ "srwi %0,%0,29" "\n\t"
+ "andi. %0,%0,1" "\n"
+ : /*out*/"=b"(success)
+ : /*in*/ "b"(p), "b"(((unsigned long)n))
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
#elif defined(VGA_arm)
unsigned int block[3]
= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
@@ -574,7 +625,7 @@
"lock; addq %%rbx,(%%rax)" "\n"
: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
);
-#elif defined(VGA_ppc64be)
+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
unsigned long success;
do {
__asm__ __volatile__(
Modified: trunk/memcheck/tests/badjump.c
==============================================================================
--- trunk/memcheck/tests/badjump.c (original)
+++ trunk/memcheck/tests/badjump.c Thu Aug 7 23:49:27 2014
@@ -2,7 +2,7 @@
int main ( void )
{
-#if defined(__powerpc64__)
+#if defined(__powerpc64__) && _CALL_ELF != 2
/* on ppc64-linux, a function pointer points to a function
descriptor, not to the function's entry point. Hence to get
uniform behaviour on all supported targets - a jump to an
Modified: trunk/memcheck/tests/ppc64/power_ISA2_05.c
==============================================================================
--- trunk/memcheck/tests/ppc64/power_ISA2_05.c (original)
+++ trunk/memcheck/tests/ppc64/power_ISA2_05.c Thu Aug 7 23:49:27 2014
@@ -41,19 +41,25 @@
void test_lfiwax()
{
unsigned long base;
+ float foo_s;
typedef struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned int lo;
+ unsigned int hi;
+#else
unsigned int hi;
unsigned int lo;
+#endif
} int_pair_t;
int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
+ foo_s = -1024.0;
+ base = (unsigned long) &foo_s;
__asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
+ printf("lfiwax (%f) => FRT=(%x, %x)\n", foo_s, ip->hi, ip->lo);
}
@@ -167,24 +173,27 @@
void test_reservation()
{
- int RT;
+ unsigned long long RT;
unsigned long base;
unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
+ long arrL[] __attribute__ ((aligned (8))) = { 0xdeadbeef00112233ULL, 0xbad0beef44556677ULL, 0xbeefdead8899aabbULL, 0xbeef0badccddeeffULL };
+ int arrI[] __attribute__ ((aligned (4))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
+ base = (unsigned long) &arrI;
+ offset = ((unsigned long) &arrI[1]) - base;
__asm__ volatile ("ori 20, %0, 0"::"r" (base));
__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
__asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
+ printf("lwarx => 0x%llx\n", RT);
#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
+ base = (unsigned long) &arrL;
+ offset = ((unsigned long) &arrL[1]) - base;
+ __asm__ volatile ("ori 20, %0, 0"::"r" (base));
__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
__asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
+ printf("ldarx => 0x%llx\n", RT);
#endif
}
Modified: trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
==============================================================================
--- trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp (original)
+++ trunk/memcheck/tests/ppc64/power_ISA2_05.stdout.exp Thu Aug 7 23:49:27 2014
@@ -1,5 +1,5 @@
-lwarx => 0
-ldarx => bad0beef
+lwarx => 0xbad0beef
+ldarx => 0xbad0beef44556677
fcpsgn sign=10.101010, base=11.111111 => 11.111111
fcpsgn sign=10.101010, base=-0.000000 => 0.000000
fcpsgn sign=10.101010, base=0.000000 => 0.000000
@@ -20,7 +20,7 @@
stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
+lfiwax (-1024.000000) => FRT=(ffffffff, c4800000)
prtyd (0) => parity=0
prtyw (0) => parity=0
prtyd (1) => parity=1
Modified: trunk/none/tests/amd64/xadd.c
==============================================================================
--- trunk/none/tests/amd64/xadd.c (original)
+++ trunk/none/tests/amd64/xadd.c Thu Aug 7 23:49:27 2014
@@ -9,7 +9,7 @@
#undef PLAT_x86_linux
#undef PLAT_amd64_linux
#undef PLAT_ppc32_linux
-#undef PLAT_ppc64_linux
+#undef PLAT_ppc64be_linux
#if defined(__i386__)
# define PLAT_x86_linux 1
Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Thu Aug 7 23:49:27 2014
@@ -11,13 +11,13 @@
ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
jm-vmx.vgtest \
jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
- round.stderr.exp round.stdout.exp round.vgtest \
+ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix\
test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
test_fx.vgtest \
test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
@@ -113,29 +113,41 @@
test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
-test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
-test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_DFP)
-test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_DFP)
-test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_DFP)
-test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_DFP)
-test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_DFP)
-test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
-test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
-test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
-test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+test_isa_2_06_part3_LDADD = -lm
+test_dfp1_LDADD = -lm
+test_dfp2_LDADD = -lm
+test_dfp3_LDADD = -lm
+test_dfp4_LDADD = -lm
+test_dfp5_LDADD = -lm
+test_isa_2_07_part1_LDADD = -lm
+test_isa_2_07_part2_LDADD = -lm
+test_tm_LDADD = -lm
+test_touch_tm_LDADD = -lm
+
Added: trunk/none/tests/ppc32/jm-fp.stdout.exp-BE2
==============================================================================
--- trunk/none/tests/ppc32/jm-fp.stdout.exp-BE2 (added)
+++ trunk/none/tests/ppc32/jm-fp.stdout.exp-BE2 Thu Aug 7 23:49:27 2014
@@ -0,0 +1,1431 @@
+PPC floating point arith insns with three args:
+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+
+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+
+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+
+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+
+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+
+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+
+PPC floating point arith insns
+ with three args with flags update:
+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+
+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+
+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+
+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
+
+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
+
+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
+
+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
+
+PPC floating point arith insns with two args:
+ fadd 0010000000000001, 0010000000000001 => 0020000000000001
+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadd 0010000000000001, fff8000000000000 => fff8000000000000
+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
+ fadd 8000000000000000, 0010000000000001 => 0010000000000001
+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
+ fadd 8000000000000000, fff8000000000000 => fff8000000000000
+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fadd fff8000000000000, 0010000000000001 => fff8000000000000
+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fadd fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fadds 0010000000000001, 0010000000000001 => 0000000000000000
+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadds 0010000000000001, fff8000000000000 => fff8000000000000
+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
+ fadds 8000000000000000, 0010000000000001 => 0000000000000000
+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
+ fadds 8000000000000000, fff8000000000000 => fff8000000000000
+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fadds fff8000000000000, 0010000000000001 => fff8000000000000
+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fadds fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fsub 0010000000000001, 0010000000000001 => 0000000000000000
+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
+ fsub 0010000000000001, fff8000000000000 => fff8000000000000
+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
+ fsub 8000000000000000, 0010000000000001 => 8010000000000001
+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
+ fsub 8000000000000000, fff8000000000000 => fff8000000000000
+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fsub fff8000000000000, 0010000000000001 => fff8000000000000
+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fsub fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fmul 0010000000000001, 0010000000000001 => 0000000000000000
+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fmul 0010000000000001, fff8000000000000 => fff8000000000000
+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
+ fmul 8000000000000000, 0010000000000001 => 8000000000000000
+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
+ fmul 8000000000000000, fff8000000000000 => fff8000000000000
+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fmul fff8000000000000, 0010000000000001 => fff8000000000000
+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fmul fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
+
+PPC floating point arith insns
+ with two args with flags update:
+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
+
+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
+ fdivs. 7ff7ff...
[truncated message content] |
|
From: <sv...@va...> - 2014-08-07 23:36:12
|
Author: carll
Date: Thu Aug 7 23:35:54 2014
New Revision: 14239
Log:
This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334384 and 334836.
POWER PC, add the functional Little Endian support, patch 2
The IBM POWER processor now supports both Big Endian and Little Endian.
The ABI for Little Endian also changes. Specifically, the function
descriptor is not used, the stack size changed, accessing the TOC
changed. Functions now have a local and a global entry point. Register
r2 contains the TOC for local calls and register r12 contains the TOC
for global calls. This patch makes the functional changes to the
Valgrind tool. The patch makes the changes needed for the
none/tests/ppc32 and none/tests/ppc64 Makefile.am. A number of the
ppc specific tests have Endian dependencies that are not fixed in
this patch. They are fixed in the next patch.
Per Julian's comments renamed coregrind/m_dispatch/dispatch-ppc64-linux.S
to coregrind/m_dispatch/dispatch-ppc64be-linux.S Created new file for LE
coregrind/m_dispatch/dispatch-ppc64le-linux.S. The same was done for
coregrind/m_syswrap/syscall-ppc-linux.S.
Signed-off-by: Carl Love <ca...@us...>
Added:
trunk/coregrind/m_dispatch/dispatch-ppc64be-linux.S
trunk/coregrind/m_dispatch/dispatch-ppc64le-linux.S
trunk/coregrind/m_syswrap/syscall-ppc64be-linux.S
trunk/coregrind/m_syswrap/syscall-ppc64le-linux.S
Modified:
trunk/coregrind/Makefile.am
trunk/coregrind/launcher-darwin.c
trunk/coregrind/launcher-linux.c
trunk/coregrind/m_coredump/coredump-elf.c
trunk/coregrind/m_debuginfo/debuginfo.c
trunk/coregrind/m_debuginfo/priv_storage.h
trunk/coregrind/m_debuginfo/readelf.c
trunk/coregrind/m_debuginfo/readmacho.c
trunk/coregrind/m_debuginfo/storage.c
trunk/coregrind/m_dispatch/dispatch-ppc64-linux.S
trunk/coregrind/m_initimg/initimg-linux.c
trunk/coregrind/m_libcsetjmp.c
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_redir.c
trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c
trunk/coregrind/m_signals.c
trunk/coregrind/m_syscall.c
trunk/coregrind/m_syswrap/syscall-ppc64-linux.S
trunk/coregrind/m_syswrap/syswrap-main.c
trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
trunk/coregrind/m_trampoline.S
trunk/coregrind/m_translate.c
trunk/coregrind/m_ume/elf.c
trunk/coregrind/m_ume/macho.c
trunk/coregrind/pub_core_machine.h
trunk/coregrind/vgdb-invoker-ptrace.c
trunk/helgrind/hg_main.c
trunk/include/pub_tool_debuginfo.h
trunk/include/pub_tool_redir.h
trunk/include/valgrind.h
trunk/include/vki/vki-ppc64-linux.h
trunk/memcheck/mc_machine.c
trunk/tests/arch_test.c
Modified: trunk/coregrind/Makefile.am
==============================================================================
--- trunk/coregrind/Makefile.am (original)
+++ trunk/coregrind/Makefile.am Thu Aug 7 23:35:54 2014
@@ -336,7 +336,8 @@
m_dispatch/dispatch-x86-linux.S \
m_dispatch/dispatch-amd64-linux.S \
m_dispatch/dispatch-ppc32-linux.S \
- m_dispatch/dispatch-ppc64-linux.S \
+ m_dispatch/dispatch-ppc64be-linux.S \
+ m_dispatch/dispatch-ppc64le-linux.S \
m_dispatch/dispatch-arm-linux.S \
m_dispatch/dispatch-arm64-linux.S \
m_dispatch/dispatch-s390x-linux.S \
@@ -388,7 +389,8 @@
m_syswrap/syscall-x86-linux.S \
m_syswrap/syscall-amd64-linux.S \
m_syswrap/syscall-ppc32-linux.S \
- m_syswrap/syscall-ppc64-linux.S \
+ m_syswrap/syscall-ppc64be-linux.S \
+ m_syswrap/syscall-ppc64le-linux.S \
m_syswrap/syscall-arm-linux.S \
m_syswrap/syscall-arm64-linux.S \
m_syswrap/syscall-s390x-linux.S \
Modified: trunk/coregrind/launcher-darwin.c
==============================================================================
--- trunk/coregrind/launcher-darwin.c (original)
+++ trunk/coregrind/launcher-darwin.c Thu Aug 7 23:35:54 2014
@@ -64,6 +64,7 @@
{ CPU_TYPE_ARM, "arm", "arm" },
{ CPU_TYPE_POWERPC, "ppc", "ppc32" },
{ CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
+ { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" },
};
static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
Modified: trunk/coregrind/launcher-linux.c
==============================================================================
--- trunk/coregrind/launcher-linux.c (original)
+++ trunk/coregrind/launcher-linux.c Thu Aug 7 23:35:54 2014
@@ -228,6 +228,10 @@
(ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm64-linux";
+ } else if (ehdr->e_machine == EM_PPC64 &&
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ platform = "ppc64le-linux";
}
} else if (header[EI_DATA] == ELFDATA2MSB) {
# if !defined(VGPV_arm_linux_android) \
@@ -321,6 +325,7 @@
(0==strcmp(VG_PLATFORM,"amd64-linux")) ||
(0==strcmp(VG_PLATFORM,"ppc32-linux")) ||
(0==strcmp(VG_PLATFORM,"ppc64be-linux")) ||
+ (0==strcmp(VG_PLATFORM,"ppc64le-linux")) ||
(0==strcmp(VG_PLATFORM,"arm-linux")) ||
(0==strcmp(VG_PLATFORM,"arm64-linux")) ||
(0==strcmp(VG_PLATFORM,"s390x-linux")) ||
Modified: trunk/coregrind/m_coredump/coredump-elf.c
==============================================================================
--- trunk/coregrind/m_coredump/coredump-elf.c (original)
+++ trunk/coregrind/m_coredump/coredump-elf.c Thu Aug 7 23:35:54 2014
@@ -343,6 +343,27 @@
regs->dsisr = 0;
regs->result = 0;
+#elif defined(VGP_ppc64le_linux)
+# define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+# undef DO
+
+ regs->nip = arch->vex.guest_CIA;
+ regs->msr = 0xf033; /* pretty arbitrary */
+ regs->orig_gpr3 = arch->vex.guest_GPR3;
+ regs->ctr = arch->vex.guest_CTR;
+ regs->link = arch->vex.guest_LR;
+ regs->xer = LibVEX_GuestPPC64_get_XER( &((ThreadArchState*)arch)->vex );
+ regs->ccr = LibVEX_GuestPPC64_get_CR( &((ThreadArchState*)arch)->vex );
+ /* regs->mq = 0; */
+ regs->trap = 0;
+ regs->dar = 0; /* should be fault address? */
+ regs->dsisr = 0;
+ regs->result = 0;
+
#elif defined(VGP_arm_linux)
regs->ARM_r0 = arch->vex.guest_R0;
regs->ARM_r1 = arch->vex.guest_R1;
Modified: trunk/coregrind/m_debuginfo/debuginfo.c
==============================================================================
--- trunk/coregrind/m_debuginfo/debuginfo.c (original)
+++ trunk/coregrind/m_debuginfo/debuginfo.c Thu Aug 7 23:35:54 2014
@@ -1,4 +1,5 @@
+
/*--------------------------------------------------------------------*/
/*--- Top level management of symbols and debugging information. ---*/
/*--- debuginfo.c ---*/
@@ -4138,6 +4139,7 @@
Int idx,
/*OUT*/Addr* avma,
/*OUT*/Addr* tocptr,
+ /*OUT*/Addr* local_ep,
/*OUT*/UInt* size,
/*OUT*/HChar** pri_name,
/*OUT*/HChar*** sec_names,
@@ -4147,6 +4149,7 @@
vg_assert(idx >= 0 && idx < si->symtab_used);
if (avma) *avma = si->symtab[idx].addr;
if (tocptr) *tocptr = si->symtab[idx].tocptr;
+ if (local_ep) *local_ep = si->symtab[idx].local_ep;
if (size) *size = si->symtab[idx].size;
if (pri_name) *pri_name = si->symtab[idx].pri_name;
if (sec_names) *sec_names = (HChar **)si->symtab[idx].sec_names; // FIXME
Modified: trunk/coregrind/m_debuginfo/priv_storage.h
==============================================================================
--- trunk/coregrind/m_debuginfo/priv_storage.h (original)
+++ trunk/coregrind/m_debuginfo/priv_storage.h Thu Aug 7 23:35:54 2014
@@ -71,7 +71,8 @@
typedef
struct {
Addr addr; /* lowest address of entity */
- Addr tocptr; /* ppc64-linux only: value that R2 should have */
+ Addr tocptr; /* ppc64be-linux only: value that R2 should have */
+ Addr local_ep; /* address for local entry point, ppc64le */
HChar* pri_name; /* primary name, never NULL */
HChar** sec_names; /* NULL, or a NULL term'd array of other names */
// XXX: this could be shrunk (on 32-bit platforms) by using 30
@@ -816,7 +817,7 @@
Bool gotplt_present;
Addr gotplt_avma;
SizeT gotplt_size;
- /* .opd -- needed on ppc64-linux for finding symbols */
+ /* .opd -- needed on ppc64be-linux for finding symbols */
Bool opd_present;
Addr opd_avma;
SizeT opd_size;
Modified: trunk/coregrind/m_debuginfo/readelf.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readelf.c (original)
+++ trunk/coregrind/m_debuginfo/readelf.c Thu Aug 7 23:35:54 2014
@@ -241,7 +241,10 @@
Bool* from_opd_out, /* ppc64be-linux only: did we deref an
.opd entry? */
Bool* is_text_out, /* is this a text symbol? */
- Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/
+ Bool* is_ifunc, /* is this a STT_GNU_IFUNC function ?*/
+ Addr* sym_local_ep /* addr for local entry point. PPC64 LE
+ supports a local and global entry points.
+ Use this value to return the entry point. */
)
{
Bool plausible;
@@ -259,6 +262,8 @@
*sym_tocptr_out = 0; /* unknown/inapplicable */
*from_opd_out = False;
*is_ifunc = False;
+ *sym_local_ep = 0; /* unknown/inapplicable */
+
/* Get the symbol size, but restrict it to fit in a signed 32 bit
int. Also, deal with the stupid case of negative size by making
the size be 1. Note that sym->st_size has type UWord,
@@ -671,14 +676,57 @@
}
# if defined(VGP_ppc64be_linux)
- /* It's crucial that we never add symbol addresses in the .opd
- section. This would completely mess up function redirection and
- intercepting. This assert ensures that any symbols that make it
- into the symbol table on ppc64-linux don't point into .opd. */
if (di->opd_present && di->opd_size > 0) {
vg_assert(*sym_avma_out + *sym_size_out <= di->opd_avma
|| *sym_avma_out >= di->opd_avma + di->opd_size);
}
+#endif
+
+# if defined(VGP_ppc64le_linux)
+ /* PPC64 LE ABI uses three bits in the st_other field to indicate the number
+ * of instructions between the function's global and local entry points. An
+ * offset of 0 indicates that there is one entry point. The value must be:
+ *
+ * 0 - one entry point, local and global are the same
+ * 1 - reserved
+ * 2 - local entry point is one instruction after the global entry point
+ * 3 - local entry point is two instructions after the global entry point
+ * 4 - local entry point is four instructions after the global entry point
+ * 5 - local entry point is eight instructions after the global entry point
+ * 6 - local entry point is sixteen two instructions after the global entry point
+ * 7 - reserved
+ *
+ * The extract the three bit field from the other field.
+ * (other_field & STO_PPC64_LOCAL_MASK) >> STO_PPC_LOCAL_BIT
+ *
+ * where the #define values are given in include/elf/powerpc.h file for
+ * the PPC binutils.
+ *
+ * coversion of the three bit field to bytes is given by
+ *
+ * ((1 << bit_field) >> 2) << 2
+ */
+
+ #define STO_PPC64_LOCAL_BIT 5
+ #define STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT)
+ {
+ unsigned int bit_field, dist_to_local_entry;
+ /* extract the other filed */
+ bit_field = (sym->st_other & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT;
+
+ if ((bit_field > 0) && (bit_field < 7)) {
+ /* store the local entry point address */
+ dist_to_local_entry = ((1 << bit_field) >> 2) << 2;
+ *sym_local_ep = *sym_avma_out + dist_to_local_entry;
+
+ if (TRACE_SYMTAB_ENABLED) {
+ HChar* sym_name = ML_(img_strdup)(escn_strtab->img,
+ "di.gesi.5", sym_name_ioff);
+ VG_(printf)("Local entry point: %s at %#010x\n",
+ sym_name, (unsigned int)*sym_local_ep);
+ }
+ }
+ }
# endif
/* Acquire! */
@@ -687,7 +735,7 @@
/* Read an ELF symbol table (normal or dynamic). This one is for the
- "normal" case ({x86,amd64,ppc32,arm,mips32,mips64}-linux). */
+ "normal" case ({x86,amd64,ppc32,arm,mips32,mips64, ppc64le}-linux). */
static
__attribute__((unused)) /* not referred to on all targets */
void read_elf_symtab__normal(
@@ -726,6 +774,7 @@
Addr sym_avma_really = 0;
Int sym_size = 0;
Addr sym_tocptr = 0;
+ Addr local_ep = 0;
Bool from_opd = False, is_text = False, is_ifunc = False;
DiOffT sym_name_really = DiOffT_INVALID;
if (get_elf_symbol_info(di, &sym, sym_name, escn_strtab,
@@ -735,7 +784,8 @@
&sym_avma_really,
&sym_size,
&sym_tocptr,
- &from_opd, &is_text, &is_ifunc)) {
+ &from_opd, &is_text, &is_ifunc,
+ &local_ep)) {
DiSym disym;
VG_(memset)(&disym, 0, sizeof(disym));
@@ -743,6 +793,7 @@
"di.res__n.1", sym_name_really);
disym.addr = sym_avma_really;
disym.tocptr = sym_tocptr;
+ disym.local_ep = local_ep;
disym.pri_name = ML_(addStr) ( di, cstr, -1 );
disym.sec_names = NULL;
disym.size = sym_size;
@@ -750,7 +801,7 @@
disym.isIFunc = is_ifunc;
if (cstr) { ML_(dinfo_free)(cstr); cstr = NULL; }
vg_assert(disym.pri_name);
- vg_assert(disym.tocptr == 0); /* has no role except on ppc64-linux */
+ vg_assert(disym.tocptr == 0); /* has no role except on ppc64be-linux */
ML_(addSym) ( di, &disym );
if (TRACE_SYMTAB_ENABLED) {
@@ -762,6 +813,10 @@
(Int)disym.size,
(HChar*)disym.pri_name
);
+ if (local_ep != 0) {
+ TRACE_SYMTAB(" local entry point %#010lx\n",
+ local_ep)
+ }
}
}
@@ -857,6 +912,7 @@
Addr sym_avma_really = 0;
Int sym_size = 0;
Addr sym_tocptr = 0;
+ Addr sym_local_ep = 0;
Bool from_opd = False, is_text = False, is_ifunc = False;
DiOffT sym_name_really = DiOffT_INVALID;
DiSym disym;
@@ -868,7 +924,8 @@
&sym_avma_really,
&sym_size,
&sym_tocptr,
- &from_opd, &is_text, &is_ifunc)) {
+ &from_opd, &is_text, &is_ifunc,
+ &sym_local_ep)) {
/* Check if we've seen this (name,addr) key before. */
key.addr = sym_avma_really;
@@ -2825,6 +2882,7 @@
# if !defined(VGP_amd64_linux) \
&& !defined(VGP_s390x_linux) \
&& !defined(VGP_ppc64be_linux) \
+ && !defined(VGP_ppc64le_linux) \
&& !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGP_mips64_linux)
Modified: trunk/coregrind/m_debuginfo/readmacho.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readmacho.c (original)
+++ trunk/coregrind/m_debuginfo/readmacho.c Thu Aug 7 23:35:54 2014
@@ -199,6 +199,8 @@
Int cputype = CPU_TYPE_POWERPC;
# elif defined(VGA_ppc64be)
Int cputype = CPU_TYPE_POWERPC64BE;
+# elif defined(VGA_ppc64le)
+ Int cputype = CPU_TYPE_POWERPC64LE;
# elif defined(VGA_x86)
Int cputype = CPU_TYPE_X86;
# elif defined(VGA_amd64)
Modified: trunk/coregrind/m_debuginfo/storage.c
==============================================================================
--- trunk/coregrind/m_debuginfo/storage.c (original)
+++ trunk/coregrind/m_debuginfo/storage.c Thu Aug 7 23:35:54 2014
@@ -199,7 +199,7 @@
SHOW_HOW(si_m->r11_how, si_m->r11_off);
VG_(printf)(" R7=");
SHOW_HOW(si_m->r7_how, si_m->r7_off);
-# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64be)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGA_s390x) || defined(VGA_mips32) || defined(VGA_mips64)
VG_(printf)(" SP=");
SHOW_HOW(si_m->sp_how, si_m->sp_off);
Added: trunk/coregrind/m_dispatch/dispatch-ppc64be-linux.S
==============================================================================
--- trunk/coregrind/m_dispatch/dispatch-ppc64be-linux.S (added)
+++ trunk/coregrind/m_dispatch/dispatch-ppc64be-linux.S Thu Aug 7 23:35:54 2014
@@ -0,0 +1,537 @@
+
+/*--------------------------------------------------------------------*/
+/*--- The core dispatch loop, for jumping to a code address. ---*/
+/*--- dispatch-ppc64-linux.S ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2005-2013 Cerion Armour-Brown <ce...@op...>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGP_ppc64be_linux)
+
+#include "pub_core_basics_asm.h"
+#include "pub_core_dispatch_asm.h"
+#include "pub_core_transtab_asm.h"
+#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */
+
+
+/* References to globals via the TOC */
+
+/*
+ .globl vgPlain_tt_fast
+ .lcomm vgPlain_tt_fast,4,4
+ .type vgPlain_tt_fast, @object
+*/
+.section ".toc","aw"
+.tocent__vgPlain_tt_fast:
+ .tc vgPlain_tt_fast[TC],vgPlain_tt_fast
+.tocent__vgPlain_stats__n_xindirs_32:
+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32
+.tocent__vgPlain_stats__n_xindir_misses_32:
+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32
+.tocent__vgPlain_machine_ppc64_has_VMX:
+ .tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/*----------------------------------------------------*/
+/*--- Entry and preamble (set everything up) ---*/
+/*----------------------------------------------------*/
+
+/* signature:
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
+*/
+
+.section ".text"
+.align 2
+.globl VG_(disp_run_translations)
+.section ".opd","aw"
+.align 3
+VG_(disp_run_translations):
+.quad .VG_(disp_run_translations),.TOC.@tocbase,0
+.previous
+.type .VG_(disp_run_translations),@function
+.globl .VG_(disp_run_translations)
+.VG_(disp_run_translations):
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
+
+ /* ----- entry point to VG_(disp_run_translations) ----- */
+ /* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */
+
+ /* Save lr, cr */
+ mflr 6
+ std 6,16(1)
+ mfcr 6
+ std 6,8(1)
+
+ /* New stack frame */
+ stdu 1,-624(1) /* sp should maintain 16-byte alignment */
+
+ /* General reg save area : 152 bytes */
+ std 31,472(1)
+ std 30,464(1)
+ std 29,456(1)
+ std 28,448(1)
+ std 27,440(1)
+ std 26,432(1)
+ std 25,424(1)
+ std 24,416(1)
+ std 23,408(1)
+ std 22,400(1)
+ std 21,392(1)
+ std 20,384(1)
+ std 19,376(1)
+ std 18,368(1)
+ std 17,360(1)
+ std 16,352(1)
+ std 15,344(1)
+ std 14,336(1)
+ std 13,328(1)
+ std 3,104(1) /* save two_words for later */
+
+ /* Save callee-saved registers... */
+ /* Floating-point reg save area : 144 bytes */
+ stfd 31,616(1)
+ stfd 30,608(1)
+ stfd 29,600(1)
+ stfd 28,592(1)
+ stfd 27,584(1)
+ stfd 26,576(1)
+ stfd 25,568(1)
+ stfd 24,560(1)
+ stfd 23,552(1)
+ stfd 22,544(1)
+ stfd 21,536(1)
+ stfd 20,528(1)
+ stfd 19,520(1)
+ stfd 18,512(1)
+ stfd 17,504(1)
+ stfd 16,496(1)
+ stfd 15,488(1)
+ stfd 14,480(1)
+
+ /* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
+ The Linux kernel might not actually use VRSAVE for its intended
+ purpose, but it should be harmless to preserve anyway. */
+ /* r3, r4, r5 are live here, so use r6 */
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
+ beq .LafterVMX1
+
+ /* VRSAVE save word : 32 bytes */
+ mfspr 6,256 /* vrsave reg is spr number 256 */
+ stw 6,324(1)
+
+ /* Alignment padding : 4 bytes */
+
+ /* Vector reg save area (quadword aligned) : 192 bytes */
+ li 6,304
+ stvx 31,6,1
+ li 6,288
+ stvx 30,6,1
+ li 6,272
+ stvx 29,6,1
+ li 6,256
+ stvx 28,6,1
+ li 6,240
+ stvx 27,6,1
+ li 6,224
+ stvx 26,6,1
+ li 6,208
+ stvx 25,6,1
+ li 6,192
+ stvx 24,6,1
+ li 6,176
+ stvx 23,6,1
+ li 6,160
+ stvx 22,6,1
+ li 6,144
+ stvx 21,6,1
+ li 6,128
+ stvx 20,6,1
+.LafterVMX1:
+
+ /* Local variable space... */
+
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
+
+ /* 96(sp) used later to check FPSCR[RM] */
+ /* 88(sp) used later to load fpscr with zero */
+ /* 48:87(sp) free */
+
+ /* Linkage Area (reserved) BE ABI
+ 40(sp) : TOC
+ 32(sp) : link editor doubleword
+ 24(sp) : compiler doubleword
+ 16(sp) : LR
+ 8(sp) : CR
+ 0(sp) : back-chain
+ */
+
+ /* set host FPU control word to the default mode expected
+ by VEX-generated code. See comments in libvex.h for
+ more info. */
+ /* => get zero into f3 (tedious)
+ fsub 3,3,3 is not a reliable way to do this, since if
+ f3 holds a NaN or similar then we don't necessarily
+ wind up with zero. */
+ li 6,0
+ stw 6,88(1)
+ lfs 3,88(1)
+ mtfsf 0xFF,3 /* fpscr = lo32 of f3 */
+
+ /* set host AltiVec control word to the default mode expected
+ by VEX-generated code. */
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
+ beq .LafterVMX2
+
+ vspltisw 3,0x0 /* generate zero */
+ mtvscr 3
+.LafterVMX2:
+
+ /* make a stack frame for the code we are calling */
+ stdu 1,-48(1)
+
+ /* Set up the guest state ptr */
+ mr 31,4 /* r31 (generated code gsp) = r4 */
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ mtctr 5
+ bctr
+ /*NOTREACHED*/
+
+/*----------------------------------------------------*/
+/*--- Postamble and exit. ---*/
+/*----------------------------------------------------*/
+
+.postamble:
+ /* At this point, r6 and r7 contain two
+ words to be returned to the caller. r6
+ holds a TRC value, and r7 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* undo the "make a stack frame for the code we are calling" */
+ addi 1,1,48
+
+ /* We're leaving. Check that nobody messed with
+ VSCR or FPSCR in ways we don't expect. */
+ /* Using r11 - value used again further on, so don't trash! */
+ ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 11,0(11)
+
+ /* Set fpscr back to a known state, since vex-generated code
+ may have messed with fpscr[rm]. */
+ li 5,0
+ addi 1,1,-16
+ stw 5,0(1)
+ lfs 3,0(1)
+ addi 1,1,16
+ mtfsf 0xFF,3 /* fpscr = f3 */
+
+ cmpldi 11,0 /* Do we have altivec? */
+ beq .LafterVMX8
+
+ /* Check VSCR[NJ] == 1 */
+ /* first generate 4x 0x00010000 */
+ vspltisw 4,0x1 /* 4x 0x00000001 */
+ vspltisw 5,0x0 /* zero */
+ vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */
+ /* retrieve VSCR and mask wanted bits */
+ mfvscr 7
+ vand 7,7,6 /* gives NJ flag */
+ vspltw 7,7,0x3 /* flags-word to all lanes */
+ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
+ bt 24,.invariant_violation /* branch if all_equal */
+
+.LafterVMX8:
+ /* otherwise we're OK */
+ b .remove_frame
+
+.invariant_violation:
+ li 6,VG_TRC_INVARIANT_FAILED
+ li 7,0
+ /* fall through */
+
+.remove_frame:
+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */
+ cmplwi 11,0
+ beq .LafterVMX9
+
+ /* Restore Altivec regs.
+ Use r5 as scratch since r6/r7 are live. */
+ /* VRSAVE */
+ lwz 5,324(1)
+ mfspr 5,256 /* VRSAVE reg is spr number 256 */
+
+ /* Vector regs */
+ li 5,304
+ lvx 31,5,1
+ li 5,288
+ lvx 30,5,1
+ li 5,272
+ lvx 29,5,1
+ li 5,256
+ lvx 28,5,1
+ li 5,240
+ lvx 27,5,1
+ li 5,224
+ lvx 26,5,1
+ li 5,208
+ lvx 25,5,1
+ li 5,192
+ lvx 24,5,1
+ li 5,176
+ lvx 23,5,1
+ li 5,160
+ lvx 22,5,1
+ li 5,144
+ lvx 21,5,1
+ li 5,128
+ lvx 20,5,1
+.LafterVMX9:
+
+ /* Restore FP regs */
+ /* Floating-point regs */
+ lfd 31,616(1)
+ lfd 30,608(1)
+ lfd 29,600(1)
+ lfd 28,592(1)
+ lfd 27,584(1)
+ lfd 26,576(1)
+ lfd 25,568(1)
+ lfd 24,560(1)
+ lfd 23,552(1)
+ lfd 22,544(1)
+ lfd 21,536(1)
+ lfd 20,528(1)
+ lfd 19,520(1)
+ lfd 18,512(1)
+ lfd 17,504(1)
+ lfd 16,496(1)
+ lfd 15,488(1)
+ lfd 14,480(1)
+
+ /* restore int regs, including importantly r3 (two_words) */
+ ld 31,472(1)
+ ld 30,464(1)
+ ld 29,456(1)
+ ld 28,448(1)
+ ld 27,440(1)
+ ld 26,432(1)
+ ld 25,424(1)
+ ld 24,416(1)
+ ld 23,408(1)
+ ld 22,400(1)
+ ld 21,392(1)
+ ld 20,384(1)
+ ld 19,376(1)
+ ld 18,368(1)
+ ld 17,360(1)
+ ld 16,352(1)
+ ld 15,344(1)
+ ld 14,336(1)
+ ld 13,328(1)
+ ld 3,104(1)
+ /* Stash return values */
+ std 6,0(3)
+ std 7,8(3)
+
+ /* restore lr & sp, and leave */
+ ld 0,632(1) /* stack_size + 8 */
+ mtcr 0
+ ld 0,640(1) /* stack_size + 16 */
+ mtlr 0
+ addi 1,1,624 /* stack_size */
+ blr
+
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+
+/* ------ Chain me to slow entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_slowEP)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_slowEP):
+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_chain_me_to_slowEP),@function
+ .globl .VG_(disp_cp_chain_me_to_slowEP)
+.VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
+
+/* ------ Chain me to fast entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_fastEP)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_fastEP):
+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_chain_me_to_fastEP),@function
+ .globl .VG_(disp_cp_chain_me_to_fastEP)
+.VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
+
+/* ------ Indirect but boring jump ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_xindir)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xindir):
+ .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_xindir),@function
+ .globl .VG_(disp_cp_xindir)
+.VG_(disp_cp_xindir):
+ /* Where are we going? */
+ ld 3,OFFSET_ppc64_CIA(31)
+
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ /* r5 = &VG_(tt_fast) */
+ ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
+
+ /* try a fast lookup in the translation cache */
+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
+ rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
+ sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
+ add 5,5,4 /* & VG_(tt_fast)[entry#] */
+ ld 6,0(5) /* .guest */
+ ld 7,8(5) /* .host */
+ cmpd 3,6
+ bne .fast_lookup_failed
+
+ /* Found a match. Jump to .host. */
+ mtctr 7
+ bctr
+
+.fast_lookup_failed:
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ li 6,VG_TRC_INNER_FASTMISS
+ li 7,0
+ b .postamble
+ /*NOTREACHED*/
+
+/* ------ Assisted jump ------ */
+.section ".text"
+ .align 2
+ .globl VG_(disp_cp_xassisted)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xassisted):
+ .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_xassisted),@function
+ .globl .VG_(disp_cp_xassisted)
+.VG_(disp_cp_xassisted):
+ /* r31 contains the TRC */
+ mr 6,31
+ li 7,0
+ b .postamble
+
+/* ------ Event check failed ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_evcheck_fail)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_evcheck_fail):
+ .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_evcheck_fail),@function
+ .globl .VG_(disp_cp_evcheck_fail)
+.VG_(disp_cp_evcheck_fail):
+ li 6,VG_TRC_INNER_COUNTERZERO
+ li 7,0
+ b .postamble
+
+
+.size .VG_(disp_run_translations), .-.VG_(disp_run_translations)
+
+/* Let the linker know we don't need an executable stack */
+.section .note.GNU-stack,"",@progbits
+
+#endif // defined(VGP_ppc64be_linux)
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
Added: trunk/coregrind/m_dispatch/dispatch-ppc64le-linux.S
==============================================================================
--- trunk/coregrind/m_dispatch/dispatch-ppc64le-linux.S (added)
+++ trunk/coregrind/m_dispatch/dispatch-ppc64le-linux.S Thu Aug 7 23:35:54 2014
@@ -0,0 +1,630 @@
+
+/*--------------------------------------------------------------------*/
+/*--- The core dispatch loop, for jumping to a code address. ---*/
+/*--- dispatch-ppc64-linux.S ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2005-2013 Cerion Armour-Brown <ce...@op...>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGP_ppc64le_linux)
+
+#include "pub_core_basics_asm.h"
+#include "pub_core_dispatch_asm.h"
+#include "pub_core_transtab_asm.h"
+#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */
+
+/* NOTE: PPC64 supports Big Endian and Little Endian. It also supports the
+ ELF version 1 and ELF version 2 APIs.
+
+ Currently LE uses ELF version 2 and BE uses ELF version 1. However,
+ BE and LE may support the other ELF version in the future. So, the
+ _CALL_ELF is used in the assembly function to enable code for a
+ specific ELF version independently of the Enianess of the machine.
+ The test "#if _CALL_ELF == 2" checks if ELF version 2 is being used.
+*/
+
+/* References to globals via the TOC */
+
+/*
+ .globl vgPlain_tt_fast
+ .lcomm vgPlain_tt_fast,4,4
+ .type vgPlain_tt_fast, @object
+*/
+.section ".toc","aw"
+.tocent__vgPlain_tt_fast:
+ .tc vgPlain_tt_fast[TC],vgPlain_tt_fast
+.tocent__vgPlain_stats__n_xindirs_32:
+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32
+.tocent__vgPlain_stats__n_xindir_misses_32:
+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32
+.tocent__vgPlain_machine_ppc64_has_VMX:
+ .tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/*----------------------------------------------------*/
+/*--- Entry and preamble (set everything up) ---*/
+/*----------------------------------------------------*/
+
+/* signature:
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
+*/
+
+.section ".text"
+.align 2
+.globl VG_(disp_run_translations)
+#if _CALL_ELF == 2
+.type VG_(disp_run_translations),@function
+VG_(disp_run_translations):
+.type .VG_(disp_run_translations),@function
+#else
+.section ".opd","aw"
+.align 3
+VG_(disp_run_translations):
+.quad .VG_(disp_run_translations),.TOC.@tocbase,0
+.previous
+.type .VG_(disp_run_translations),@function
+#endif
+.globl .VG_(disp_run_translations)
+.VG_(disp_run_translations):
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_run_translations), .-VG_(disp_run_translations)
+#endif
+
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
+
+ /* ----- entry point to VG_(disp_run_translations) ----- */
+ /* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */
+
+ /* Save lr, cr */
+ mflr 6
+ std 6,16(1)
+ mfcr 6
+ std 6,8(1)
+
+ /* New stack frame */
+ stdu 1,-624(1) /* sp should maintain 16-byte alignment */
+
+ /* General reg save area : 152 bytes */
+ std 31,472(1)
+ std 30,464(1)
+ std 29,456(1)
+ std 28,448(1)
+ std 27,440(1)
+ std 26,432(1)
+ std 25,424(1)
+ std 24,416(1)
+ std 23,408(1)
+ std 22,400(1)
+ std 21,392(1)
+ std 20,384(1)
+ std 19,376(1)
+ std 18,368(1)
+ std 17,360(1)
+ std 16,352(1)
+ std 15,344(1)
+ std 14,336(1)
+ std 13,328(1)
+ std 3,104(1) /* save two_words for later */
+
+ /* Save callee-saved registers... */
+ /* Floating-point reg save area : 144 bytes */
+ stfd 31,616(1)
+ stfd 30,608(1)
+ stfd 29,600(1)
+ stfd 28,592(1)
+ stfd 27,584(1)
+ stfd 26,576(1)
+ stfd 25,568(1)
+ stfd 24,560(1)
+ stfd 23,552(1)
+ stfd 22,544(1)
+ stfd 21,536(1)
+ stfd 20,528(1)
+ stfd 19,520(1)
+ stfd 18,512(1)
+ stfd 17,504(1)
+ stfd 16,496(1)
+ stfd 15,488(1)
+ stfd 14,480(1)
+
+ /* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
+ The Linux kernel might not actually use VRSAVE for its intended
+ purpose, but it should be harmless to preserve anyway. */
+ /* r3, r4, r5 are live here, so use r6 */
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
+ beq .LafterVMX1
+
+ /* VRSAVE save word : 32 bytes */
+ mfspr 6,256 /* vrsave reg is spr number 256 */
+ stw 6,324(1)
+
+ /* Alignment padding : 4 bytes */
+
+ /* Vector reg save area (quadword aligned) : 192 bytes */
+ li 6,304
+ stvx 31,6,1
+ li 6,288
+ stvx 30,6,1
+ li 6,272
+ stvx 29,6,1
+ li 6,256
+ stvx 28,6,1
+ li 6,240
+ stvx 27,6,1
+ li 6,224
+ stvx 26,6,1
+ li 6,208
+ stvx 25,6,1
+ li 6,192
+ stvx 24,6,1
+ li 6,176
+ stvx 23,6,1
+ li 6,160
+ stvx 22,6,1
+ li 6,144
+ stvx 21,6,1
+ li 6,128
+ stvx 20,6,1
+.LafterVMX1:
+
+ /* Local variable space... */
+
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
+
+ /* 96(sp) used later to check FPSCR[RM] */
+ /* 88(sp) used later to load fpscr with zero */
+ /* 48:87(sp) free */
+
+ /* Linkage Area (reserved) BE ABI
+ 40(sp) : TOC
+ 32(sp) : link editor doubleword
+ 24(sp) : compiler doubleword
+ 16(sp) : LR
+ 8(sp) : CR
+ 0(sp) : back-chain
+ */
+
+ /* set host FPU control word to the default mode expected
+ by VEX-generated code. See comments in libvex.h for
+ more info. */
+ /* => get zero into f3 (tedious)
+ fsub 3,3,3 is not a reliable way to do this, since if
+ f3 holds a NaN or similar then we don't necessarily
+ wind up with zero. */
+ li 6,0
+ stw 6,88(1)
+ lfs 3,88(1)
+ mtfsf 0xFF,3 /* fpscr = lo32 of f3 */
+
+ /* set host AltiVec control word to the default mode expected
+ by VEX-generated code. */
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
+ beq .LafterVMX2
+
+ vspltisw 3,0x0 /* generate zero */
+ mtvscr 3
+.LafterVMX2:
+
+ /* make a stack frame for the code we are calling */
+ stdu 1,-48(1)
+
+ /* Set up the guest state ptr */
+ mr 31,4 /* r31 (generated code gsp) = r4 */
+#if _CALL_ELF == 2
+/* for the LE ABI need to setup r2 and r12 */
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+#endif
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ mtctr 5
+ bctr
+ /*NOTREACHED*/
+
+/*----------------------------------------------------*/
+/*--- Postamble and exit. ---*/
+/*----------------------------------------------------*/
+
+.postamble:
+ /* At this point, r6 and r7 contain two
+ words to be returned to the caller. r6
+ holds a TRC value, and r7 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* undo the "make a stack frame for the code we are calling" */
+ addi 1,1,48
+
+ /* We're leaving. Check that nobody messed with
+ VSCR or FPSCR in ways we don't expect. */
+ /* Using r11 - value used again further on, so don't trash! */
+ ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 11,0(11)
+
+ /* Set fpscr back to a known state, since vex-generated code
+ may have messed with fpscr[rm]. */
+ li 5,0
+ addi 1,1,-16
+ stw 5,0(1)
+ lfs 3,0(1)
+ addi 1,1,16
+ mtfsf 0xFF,3 /* fpscr = f3 */
+
+ cmpldi 11,0 /* Do we have altivec? */
+ beq .LafterVMX8
+
+ /* Check VSCR[NJ] == 1 */
+ /* first generate 4x 0x00010000 */
+ vspltisw 4,0x1 /* 4x 0x00000001 */
+ vspltisw 5,0x0 /* zero */
+ vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */
+ /* retrieve VSCR and mask wanted bits */
+ mfvscr 7
+ vand 7,7,6 /* gives NJ flag */
+ vspltw 7,7,0x3 /* flags-word to all lanes */
+ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
+ bt 24,.invariant_violation /* branch if all_equal */
+
+.LafterVMX8:
+ /* otherwise we're OK */
+ b .remove_frame
+
+.invariant_violation:
+ li 6,VG_TRC_INVARIANT_FAILED
+ li 7,0
+ /* fall through */
+
+.remove_frame:
+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */
+ cmplwi 11,0
+ beq .LafterVMX9
+
+ /* Restore Altivec regs.
+ Use r5 as scratch since r6/r7 are live. */
+ /* VRSAVE */
+ lwz 5,324(1)
+ mfspr 5,256 /* VRSAVE reg is spr number 256 */
+
+ /* Vector regs */
+ li 5,304
+ lvx 31,5,1
+ li 5,288
+ lvx 30,5,1
+ li 5,272
+ lvx 29,5,1
+ li 5,256
+ lvx 28,5,1
+ li 5,240
+ lvx 27,5,1
+ li 5,224
+ lvx 26,5,1
+ li 5,208
+ lvx 25,5,1
+ li 5,192
+ lvx 24,5,1
+ li 5,176
+ lvx 23,5,1
+ li 5,160
+ lvx 22,5,1
+ li 5,144
+ lvx 21,5,1
+ li 5,128
+ lvx 20,5,1
+.LafterVMX9:
+
+ /* Restore FP regs */
+ /* Floating-point regs */
+ lfd 31,616(1)
+ lfd 30,608(1)
+ lfd 29,600(1)
+ lfd 28,592(1)
+ lfd 27,584(1)
+ lfd 26,576(1)
+ lfd 25,568(1)
+ lfd 24,560(1)
+ lfd 23,552(1)
+ lfd 22,544(1)
+ lfd 21,536(1)
+ lfd 20,528(1)
+ lfd 19,520(1)
+ lfd 18,512(1)
+ lfd 17,504(1)
+ lfd 16,496(1)
+ lfd 15,488(1)
+ lfd 14,480(1)
+
+ /* restore int regs, including importantly r3 (two_words) */
+ ld 31,472(1)
+ ld 30,464(1)
+ ld 29,456(1)
+ ld 28,448(1)
+ ld 27,440(1)
+ ld 26,432(1)
+ ld 25,424(1)
+ ld 24,416(1)
+ ld 23,408(1)
+ ld 22,400(1)
+ ld 21,392(1)
+ ld 20,384(1)
+ ld 19,376(1)
+ ld 18,368(1)
+ ld 17,360(1)
+ ld 16,352(1)
+ ld 15,344(1)
+ ld 14,336(1)
+ ld 13,328(1)
+ ld 3,104(1)
+ /* Stash return values */
+ std 6,0(3)
+ std 7,8(3)
+
+ /* restore lr & sp, and leave */
+ ld 0,632(1) /* stack_size + 8 */
+ mtcr 0
+ ld 0,640(1) /* stack_size + 16 */
+ mtlr 0
+ addi 1,1,624 /* stack_size */
+ blr
+#if _CALL_ELF == 2
+ .size VG_(disp_run_translations),.-VG_(disp_run_translations)
+#endif
+
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+
+/* ------ Chain me to slow entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_slowEP)
+#if _CALL_ELF == 2
+ .type VG_(disp_cp_chain_me_to_slowEP),@function
+ VG_(disp_cp_chain_me_to_slowEP):
+#else
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_slowEP):
+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0
+ .previous
+#endif
+ .type .VG_(disp_cp_chain_me_to_slowEP),@function
+ .globl .VG_(disp_cp_chain_me_to_slowEP)
+.VG_(disp_cp_chain_me_to_slowEP):
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_cp_chain_me_to_slowEP), .-VG_(disp_cp_chain_me_to_slowEP)
+#endif
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
+#if _CALL_ELF == 2
+ .size VG_(disp_cp_chain_me_to_slowEP),.-VG_(disp_cp_chain_me_to_slowEP)
+#endif
+
+/* ------ Chain me to fast entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_fastEP)
+#if _CALL_ELF == 2
+ .type VG_(disp_cp_chain_me_to_fastEP),@function
+VG_(disp_cp_chain_me_to_fastEP):
+#else
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_fastEP):
+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0
+ .previous
+#endif
+ .type .VG_(disp_cp_chain_me_to_fastEP),@function
+ .globl .VG_(disp_cp_chain_me_to_fastEP)
+.VG_(disp_cp_chain_me_to_fastEP):
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_cp_chain_me_to_fastEP), .-VG_(disp_cp_chain_me_to_fastEP)
+#endif
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
+#if _CALL_ELF == 2
+ .size VG_(disp_cp_chain_me_to_fastEP),.-VG_(disp_cp_chain_me_to_fastEP)
+#endif
+
+/* ------ Indirect but boring jump ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_xindir)
+#if _CALL_ELF == 2
+ .type VG_(disp_cp_xindir),@function
+VG_(disp_cp_xindir):
+#else
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xindir):
+ .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0
+ .previous
+#endif
+ .type .VG_(disp_cp_xindir),@function
+ .globl .VG_(disp_cp_xindir)
+.VG_(disp_cp_xindir):
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_cp_xindir), .-VG_(disp_cp_xindir)
+#endif
+ /* Where are we going? */
+ ld 3,OFFSET_ppc64_CIA(31)
+
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ /* r5 = &VG_(tt_fast) */
+ ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
+
+ /* try a fast lookup in the translation cache */
+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
+ rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
+ sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
+ add 5,5,4 /* & VG_(tt_fast)[entry#] */
+ ld 6,0(5) /* .guest */
+ ld 7,8(5) /* .host */
+ cmpd 3,6
+ bne .fast_lookup_failed
+
+ /* Found a match. Jump to .host. */
+ mtctr 7
+ bctr
+#if _CALL_ELF == 2
+ .size VG_(disp_cp_xindir),.-VG_(disp_cp_xindir)
+#endif
+
+.fast_lookup_failed:
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ li 6,VG_TRC_INNER_FASTMISS
+ li 7,0
+ b .postamble
+ /*NOTREACHED*/
+
+/* ------ Assisted jump ------ */
+.section ".text"
+ .align 2
+ .globl VG_(disp_cp_xassisted)
+#if _CALL_ELF == 2
+ .type VG_(disp_cp_xassisted),@function
+VG_(disp_cp_xassisted):
+#else
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xassisted):
+ .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0
+ .previous
+#endif
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_cp_xassisted), .-VG_(disp_cp_xassisted)
+#endif
+ .type .VG_(disp_cp_xassisted),@function
+ .globl .VG_(disp_cp_xassisted)
+.VG_(disp_cp_xassisted):
+ /* r31 contains the TRC */
+ mr 6,31
+ li 7,0
+ b .postamble
+#if _CALL_ELF == 2
+ .size VG_(disp_cp_xassisted),.-VG_(disp_cp_xassisted)
+#endif
+
+/* ------ Event check failed ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_evcheck_fail)
+#if _CALL_ELF == 2
+ .type VG_(disp_cp_evcheck_fail),@function
+VG_(disp_cp_evcheck_fail):
+#else
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_evcheck_fail):
+ .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0
+ .previous
+#endif
+#if _CALL_ELF == 2
+0: addis 2, 12,.TOC.-0b@ha
+ addi 2,2,.TOC.-0b@l
+ .localentry VG_(disp_cp_evcheck_fail), .-VG_(disp_cp_evcheck_fail)
+#endif
+ .type .VG_(disp_cp_evcheck_fail),@function
+ .globl .VG_(disp_cp_evcheck_fail)
+.VG_(disp_cp_evcheck_fail):
+ li 6,VG_TRC_INNER_COUNTERZERO
+ li 7,0
+ b .postamble
+#if _CALL_ELF == 2
+ .size VG_(disp_cp_evcheck_fail),.-VG_(disp_cp_evcheck_fail)
+#endif
+
+.size .VG_(disp_run_translations), .-.VG_(disp_run_translations)
+
+/* Let the linker know we don't need an executable stack */
+.section .note.GNU-stack,"",@progbits
+
+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
Modified: trunk/coregrind/m_initimg/initimg-linux.c
==============================================================================
--- trunk/coregrind/m_initimg/initimg-linux.c (original)
+++ trunk/coregrind/m_initimg/initimg-linux.c Thu Aug 7 23:35:54 2014
@@ -1043,6 +1043,9 @@
arch->vex.guest_GPR1 = iifii.initial_client_SP;
arch->vex.guest_GPR2 = iifii.initial_client_TOC;
arch->vex.guest_CIA = iifii.initial_client_IP;
+#if defined(VGP_ppc64le_linux)
+ arch->vex.guest_GPR12 = iifii.initial_client_IP;
+#endif
# elif defined(VGP_arm_linux)
/* Zero out the initial state, and set up the simulated FPU in a
Modified: trunk/coregrind/m_libcsetjmp.c
==============================================================================
--- trunk/coregrind/m_libcsetjmp.c (original)
+++ trunk/coregrind/m_libcsetjmp.c Thu Aug 7 23:35:54 2014
@@ -158,7 +158,6 @@
".align 2" "\n"
".p2align 4,,15" "\n"
".globl VG_MINIMAL_SETJMP" "\n"
-
".section \".opd\",\"aw\"" "\n"
".align 3" "\n"
"VG_MINIMAL_SETJMP:" "\n"
@@ -267,9 +266,114 @@
"" "\n"
".previous" "\n"
-".previous" "\n"
);
+#elif defined(VGP_ppc64le_linux)
+__asm__(
+".section \".toc\",\"aw\"" "\n"
+
+".section \".text\"" "\n"
+".align 2" "\n"
+".p2align 4,,15" "\n"
+".globl VG_MINIMAL_SETJMP" "\n"
+".type VG_MINIMAL_SETJMP,@function" "\n"
+"VG_MINIMAL_SETJMP:" "\n"
+" .localentry VG_MINIMAL_SETJMP, .-VG_MINIMAL_SETJMP" "\n"
+" std 0, 0(3)" "\n"
+" std 1, 8(3)" "\n"
+" std 2, 16(3)" "\n"
+" std 3, 24(3)" "\n"
+" std 4, 32(3)" "\n"
+" std 5, 40(3)" "\n"
+" std 6, 48(3)" "\n"
+" std 7, 56(3)" "\n"
+" std 8, 64(3)" "\n"
+" std 9, 72(3)" "\n"
+" std 10, 80(3)" "\n"
+" std 11, 88(3)" "\n"
+" std 12, 96(3)" "\n"
+" std 13, 104(3)" "\n"
+" std 14, 112(3)" "\n"
+" std 15, 120(3)" "\n"
+" std 16, 128(3)" "\n"
+" std 17, 136(3)" "\n"
+" std 18, 144(3)" "\n"
+" std 19, 152(3)" "\n"
+" std 20, 160(3)" "\n"
+" std 21, 168(3)" "\n"
+" std 22, 176(3)" "\n"
+" std 23, 184(3)" "\n"
+" std 24, 192(3)" "\n"
+" std 25, 200(3)" "\n"
+" std 26, 208(3)" "\n"
+" std 27, 216(3)" "\n"
+" std 28, 224(3)" "\n"
+" std 29, 232(3)" "\n"
+" std 30, 240(3)" "\n"
+" std 31, 248(3)" "\n"
+// must use a caller-save register here as scratch, hence r4
+" mflr 4" "\n"
+" std 4, 256(3)" "\n"
+" mfcr 4" "\n"
+" std 4, 264(3)" "\n"
+" li 3, 0" "\n"
+" blr" "\n"
+"" "\n"
+
+
+".globl VG_MINIMAL_LONGJMP" "\n"
+".type VG_MINIMAL_LONGJMP, @function" "\n"
+"VG_MINIMAL_LONGJMP:" "\n"
+" .localentry VG_MINIMAL_LONGJMP, .-VG_MINIMAL_LONGJMP" "\n"
+ // do r4 = 1
+ // and park it in the restore slot for r3 (the ret reg)
+" li 4, 1" "\n"
+" std 4, 24(3)" "\n"
+ // restore everything except r3
+ // then r3 last of all
+ // then blr
+" ld 0, 256(3)" "\n"
+" mtlr 0" "\n"
+" ld 0, 264(3)" "\n"
+" mtcr 0" "\n"
+" ld 0, 0(3)" "\n"
+" ld 1, 8(3)" "\n"
+" ld 2, 16(3)" "\n"
+ // r3 is done at the end
+" ld 4, 32(3)" "\n"
+" ld 5, 40(3)" "\n"
+" ld 6, 48(3)" "\n"
+" ld 7, 56(3)" "\n"
+" ld 8, 64(3)" "\n"
+" ld 9, 72(3)" "\n"
+" ld 10, 80(3)" "\n"
+" ld 11, 88(3)" "\n"
+" ld 12, 96(3)" "\n"
+" ld 13, 104(3)" "\n"
+" ld 14, 112(3)" "\n"
+" ld 15, 120(3)" "\n"
+" ld 16, 128(3)" "\n"
+" ld 17, 136(3)" "\n"
+" ld 18, 144(3)" "\n"
+" ld 19, 152(3)" "\n"
+" ld 20, 160(3)" "\n"
+" ld 21, 168(3)" "\n"
+" ld 22, 176(3)" "\n"
+" ld 23, 184(3)" "\n"
+" ld 24, 192(3)" "\n"
+" ld 25, 200(3)" "\n"
+" ld 26, 208(3)" "\n"
+" ld 27, 216(3)" "\n"
+" ld 28, 224(3)" "\n"
+" ld 29, 232(3)" "\n"
+" ld 30, 240(3)" "\n"
+" ld 31, 248(3)" "\n"
+" ld 3, 24(3)" "\n"
+" blr" "\n"
+"" "\n"
+
+".previous" "\n"
+);
#endif /* VGP_ppc64be_linux */
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Thu Aug 7 23:35:54 2014
@@ -1188,9 +1188,13 @@
VG_(mac...
[truncated message content] |
|
From: <sv...@va...> - 2014-08-07 23:25:46
|
Author: carll
Date: Thu Aug 7 23:25:23 2014
New Revision: 2914
Log:
This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334384 and 334836.
POWER PC, add the functional Little Endian support, patch 2 VEX part
The IBM POWER processor now supports both Big Endian and Little Endian.
The ABI for Little Endian also changes. Specifically, the function
descriptor is not used, the stack size changed, accessing the TOC
changed. Functions now have a local and a global entry point. Register
r2 contains the TOC for local calls and register r12 contains the TOC
for global calls. This patch makes the functional changes to the
Valgrind tool. The patch makes the changes needed for the
none/tests/ppc32 and none/tests/ppc64 Makefile.am. A number of the
ppc specific tests have Endian dependencies that are not fixed in
this patch. They are fixed in the next patch.
Per Julian's comments renamed coregrind/m_dispatch/dispatch-ppc64-linux.S
to coregrind/m_dispatch/dispatch-ppc64be-linux.S Created new file for LE
coregrind/m_dispatch/dispatch-ppc64le-linux.S. The same was done for
coregrind/m_syswrap/syscall-ppc-linux.S.
Signed-off-by: Carl Love <ca...@us...>
Modified:
trunk/priv/guest_ppc_defs.h
trunk/priv/guest_ppc_helpers.c
trunk/priv/guest_ppc_toIR.c
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_isel.c
trunk/priv/main_main.c
Modified: trunk/priv/guest_ppc_defs.h
==============================================================================
--- trunk/priv/guest_ppc_defs.h (original)
+++ trunk/priv/guest_ppc_defs.h Thu Aug 7 23:25:23 2014
@@ -161,7 +161,8 @@
extern void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
UInt vD_idx, UInt sh,
- UInt shift_right );
+ UInt shift_right,
+ UInt endness );
#endif /* ndef __VEX_GUEST_PPC_DEFS_H */
Modified: trunk/priv/guest_ppc_helpers.c
==============================================================================
--- trunk/priv/guest_ppc_helpers.c (original)
+++ trunk/priv/guest_ppc_helpers.c Thu Aug 7 23:25:23 2014
@@ -153,10 +153,12 @@
/* CALLED FROM GENERATED CODE */
/* DIRTY HELPER (reads guest state, writes guest mem) */
void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
- UInt vD_off, UInt sh, UInt shift_right )
+ UInt vD_off, UInt sh, UInt shift_right,
+ UInt endness )
{
UChar ref[32];
ULong i;
+ Int k;
/* ref[] used to be a static const array, but this doesn't work on
ppc64 because VEX doesn't load the TOC pointer for the call here,
and so we wind up picking up some totally random other data.
@@ -179,10 +181,19 @@
pU128_src = (U128*)&ref[sh];
pU128_dst = (U128*)( ((UChar*)gst) + vD_off );
- (*pU128_dst)[0] = (*pU128_src)[0];
- (*pU128_dst)[1] = (*pU128_src)[1];
- (*pU128_dst)[2] = (*pU128_src)[2];
- (*pU128_dst)[3] = (*pU128_src)[3];
+ if ((0x1 & endness) == 0x0) {
+ /* Little endian */
+ unsigned char *srcp, *dstp;
+ srcp = (unsigned char *)pU128_src;
+ dstp = (unsigned char *)pU128_dst;
+ for (k = 15; k >= 0; k--, srcp++)
+ dstp[k] = *srcp;
+ } else {
+ (*pU128_dst)[0] = (*pU128_src)[0];
+ (*pU128_dst)[1] = (*pU128_src)[1];
+ (*pU128_dst)[2] = (*pU128_src)[2];
+ (*pU128_dst)[3] = (*pU128_src)[3];
+ }
}
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Thu Aug 7 23:25:23 2014
@@ -97,7 +97,8 @@
7C210B78 (or 1,1,1) %R3 = client_request ( %R4 )
7C421378 (or 2,2,2) %R3 = guest_NRADDR
- 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11
+ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 Big endian
+ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R12 Little endian
7C842378 (or 4,4,4) %R3 = guest_NRADDR_GPR2
7CA52B78 (or 5,5,5) IR injection
@@ -107,7 +108,55 @@
fragments designed for Valgrind to catch.
*/
-
+/* Little Endian notes */
+/*
+ * Vector operations in little Endian mode behave in non-obvious ways at times.
+ * Below is an attempt at explaining this.
+ *
+ * LE/BE vector example
+ * With a vector of unsigned ints declared as follows:
+ * vector unsigned int vec_inA =
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 };
+ * The '0x11111111' word is word zero in both LE and BE format. But the
+ * loaded vector register will have word zero on the far left in BE mode and
+ * on the far right in LE mode. The lvx and stvx instructions work naturally
+ * for whatever endianness is in effect. For example, in LE mode, the stvx
+ * stores word zero (far right word) of the vector at the lowest memory
+ * address of the EA; in BE mode, stvx still stores word zero at the lowest
+ * memory address, but with word zero interpreted as the one at the far left
+ * of the register.
+ *
+ * The lxvd2x and stxvd2x instructions are not so well suited for LE mode.
+ * When the compiler generates an lxvd2x instruction to load the
+ * above-declared vector of unsigned integers, it loads the vector as two
+ * double words, but they are in BE word-wise format. To put the vector in
+ * the right order for LE, the compiler also generates an xxswapd after the
+ * load, which puts it in proper LE format. Similarly, the stxvd2x
+ * instruction has a BE bias, storing the vector in BE word-wise format. But
+ * the compiler also generates an xxswapd prior to the store, thus ensuring
+ * the vector is stored in memory in the correct LE order.
+ *
+ * Vector-flavored Iops, such Iop_V128Hito64, reference the hi and lo parts
+ * of a double words and words within a vector. Because of the reverse order
+ * of numbering for LE as described above, the high part refers to word 1 in
+ * LE format. When input data is saved to a guest state vector register
+ * (e.g., via Iop_64HLtoV128), it is first saved to memory and then the
+ * register is loaded via PPCInstr_AvLdSt, which does an lvx instruction.
+ * The saving of the data to memory must be done in proper LE order. For the
+ * inverse operation of extracting data from a vector register (e.g.,
+ * Iop_V128Hito64), the register is first saved (by PPCInstr_AvLdSt resulting
+ * in stvx), and then integer registers are loaded from the memory location
+ * from where the vector register was saved. Again, this must be done in
+ * proper LE order. So for these various vector Iops, we have LE-specific
+ * code in host_ppc_isel.c
+ *
+ * Another unique behavior of vectors in LE mode is with the vector scalar
+ * (VSX) operations that operate on "double word 0" of the source register,
+ * storing the result in "double word 0" of the output vector register. For
+ * these operations, "double word 0" is interpreted as "high half of the
+ * register" (i.e, the part on the left side).
+ *
+ */
/* Translates PPC32/64 code to IR. */
/* References
@@ -143,7 +192,6 @@
#include "guest_generic_bb_to_IR.h"
#include "guest_ppc_defs.h"
-
/*------------------------------------------------------------*/
/*--- Globals ---*/
/*------------------------------------------------------------*/
@@ -503,15 +551,22 @@
return (ULong)((((Long)x) << 32) >> 32);
}
-/* Do a big-endian load of a 32-bit word, regardless of the endianness
+/* Do a proper-endian load of a 32-bit word, regardless of the endianness
of the underlying host. */
-static UInt getUIntBigendianly ( UChar* p )
+static UInt getUIntPPCendianly ( UChar* p )
{
UInt w = 0;
- w = (w << 8) | p[0];
- w = (w << 8) | p[1];
- w = (w << 8) | p[2];
- w = (w << 8) | p[3];
+ if (host_endness == VexEndnessBE) {
+ w = (w << 8) | p[0];
+ w = (w << 8) | p[1];
+ w = (w << 8) | p[2];
+ w = (w << 8) | p[3];
+ } else {
+ w = (w << 8) | p[3];
+ w = (w << 8) | p[2];
+ w = (w << 8) | p[1];
+ w = (w << 8) | p[0];
+ }
return w;
}
@@ -526,11 +581,15 @@
}
/* This generates a normal (non store-conditional) store. */
-static void storeBE ( IRExpr* addr, IRExpr* data )
+static void store ( IRExpr* addr, IRExpr* data )
{
IRType tyA = typeOfIRExpr(irsb->tyenv, addr);
vassert(tyA == Ity_I32 || tyA == Ity_I64);
- stmt( IRStmt_Store(Iend_BE, addr, data) );
+
+ if (host_endness == VexEndnessBE)
+ stmt( IRStmt_Store(Iend_BE, addr, data) );
+ else
+ stmt( IRStmt_Store(Iend_LE, addr, data) );
}
static IRExpr* unop ( IROp op, IRExpr* a )
@@ -586,9 +645,21 @@
}
/* This generates a normal (non load-linked) load. */
-static IRExpr* loadBE ( IRType ty, IRExpr* addr )
+static IRExpr* load ( IRType ty, IRExpr* addr )
{
- return IRExpr_Load(Iend_BE, ty, addr);
+ if (host_endness == VexEndnessBE)
+ return IRExpr_Load(Iend_BE, ty, addr);
+ else
+ return IRExpr_Load(Iend_LE, ty, addr);
+}
+
+static IRStmt* stmt_load ( IRTemp result,
+ IRExpr* addr, IRExpr* storedata )
+{
+ if (host_endness == VexEndnessBE)
+ return IRStmt_LLSC(Iend_BE, result, addr, storedata);
+ else
+ return IRStmt_LLSC(Iend_LE, result, addr, storedata);
}
static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 )
@@ -1039,7 +1110,6 @@
// jrs: probably not necessary; only matters if we reference sub-parts
// of the ppc registers, but that isn't the case
// later: this might affect Altivec though?
- vassert(host_endness == VexEndnessBE);
switch (archreg) {
case 0: return offsetofPPCGuestState(guest_GPR0);
@@ -1101,40 +1171,78 @@
{
vassert(archreg < 32);
- switch (archreg) {
- case 0: return offsetofPPCGuestState(guest_VSR0);
- case 1: return offsetofPPCGuestState(guest_VSR1);
- case 2: return offsetofPPCGuestState(guest_VSR2);
- case 3: return offsetofPPCGuestState(guest_VSR3);
- case 4: return offsetofPPCGuestState(guest_VSR4);
- case 5: return offsetofPPCGuestState(guest_VSR5);
- case 6: return offsetofPPCGuestState(guest_VSR6);
- case 7: return offsetofPPCGuestState(guest_VSR7);
- case 8: return offsetofPPCGuestState(guest_VSR8);
- case 9: return offsetofPPCGuestState(guest_VSR9);
- case 10: return offsetofPPCGuestState(guest_VSR10);
- case 11: return offsetofPPCGuestState(guest_VSR11);
- case 12: return offsetofPPCGuestState(guest_VSR12);
- case 13: return offsetofPPCGuestState(guest_VSR13);
- case 14: return offsetofPPCGuestState(guest_VSR14);
- case 15: return offsetofPPCGuestState(guest_VSR15);
- case 16: return offsetofPPCGuestState(guest_VSR16);
- case 17: return offsetofPPCGuestState(guest_VSR17);
- case 18: return offsetofPPCGuestState(guest_VSR18);
- case 19: return offsetofPPCGuestState(guest_VSR19);
- case 20: return offsetofPPCGuestState(guest_VSR20);
- case 21: return offsetofPPCGuestState(guest_VSR21);
- case 22: return offsetofPPCGuestState(guest_VSR22);
- case 23: return offsetofPPCGuestState(guest_VSR23);
- case 24: return offsetofPPCGuestState(guest_VSR24);
- case 25: return offsetofPPCGuestState(guest_VSR25);
- case 26: return offsetofPPCGuestState(guest_VSR26);
- case 27: return offsetofPPCGuestState(guest_VSR27);
- case 28: return offsetofPPCGuestState(guest_VSR28);
- case 29: return offsetofPPCGuestState(guest_VSR29);
- case 30: return offsetofPPCGuestState(guest_VSR30);
- case 31: return offsetofPPCGuestState(guest_VSR31);
- default: break;
+ if (host_endness == VexEndnessLE) {
+ switch (archreg) {
+ case 0: return offsetofPPCGuestState(guest_VSR0 + 8);
+ case 1: return offsetofPPCGuestState(guest_VSR1 + 8);
+ case 2: return offsetofPPCGuestState(guest_VSR2 + 8);
+ case 3: return offsetofPPCGuestState(guest_VSR3 + 8);
+ case 4: return offsetofPPCGuestState(guest_VSR4 + 8);
+ case 5: return offsetofPPCGuestState(guest_VSR5 + 8);
+ case 6: return offsetofPPCGuestState(guest_VSR6 + 8);
+ case 7: return offsetofPPCGuestState(guest_VSR7 + 8);
+ case 8: return offsetofPPCGuestState(guest_VSR8 + 8);
+ case 9: return offsetofPPCGuestState(guest_VSR9 + 8);
+ case 10: return offsetofPPCGuestState(guest_VSR10 + 8);
+ case 11: return offsetofPPCGuestState(guest_VSR11 + 8);
+ case 12: return offsetofPPCGuestState(guest_VSR12 + 8);
+ case 13: return offsetofPPCGuestState(guest_VSR13 + 8);
+ case 14: return offsetofPPCGuestState(guest_VSR14 + 8);
+ case 15: return offsetofPPCGuestState(guest_VSR15 + 8);
+ case 16: return offsetofPPCGuestState(guest_VSR16 + 8);
+ case 17: return offsetofPPCGuestState(guest_VSR17 + 8);
+ case 18: return offsetofPPCGuestState(guest_VSR18 + 8);
+ case 19: return offsetofPPCGuestState(guest_VSR19 + 8);
+ case 20: return offsetofPPCGuestState(guest_VSR20 + 8);
+ case 21: return offsetofPPCGuestState(guest_VSR21 + 8);
+ case 22: return offsetofPPCGuestState(guest_VSR22 + 8);
+ case 23: return offsetofPPCGuestState(guest_VSR23 + 8);
+ case 24: return offsetofPPCGuestState(guest_VSR24 + 8);
+ case 25: return offsetofPPCGuestState(guest_VSR25 + 8);
+ case 26: return offsetofPPCGuestState(guest_VSR26 + 8);
+ case 27: return offsetofPPCGuestState(guest_VSR27 + 8);
+ case 28: return offsetofPPCGuestState(guest_VSR28 + 8);
+ case 29: return offsetofPPCGuestState(guest_VSR29 + 8);
+ case 30: return offsetofPPCGuestState(guest_VSR30 + 8);
+ case 31: return offsetofPPCGuestState(guest_VSR31 + 8);
+ default: break;
+ }
+ } else {
+ switch (archreg) {
+ case 0: return offsetofPPCGuestState(guest_VSR0);
+ case 1: return offsetofPPCGuestState(guest_VSR1);
+ case 2: return offsetofPPCGuestState(guest_VSR2);
+ case 3: return offsetofPPCGuestState(guest_VSR3);
+ case 4: return offsetofPPCGuestState(guest_VSR4);
+ case 5: return offsetofPPCGuestState(guest_VSR5);
+ case 6: return offsetofPPCGuestState(guest_VSR6);
+ case 7: return offsetofPPCGuestState(guest_VSR7);
+ case 8: return offsetofPPCGuestState(guest_VSR8);
+ case 9: return offsetofPPCGuestState(guest_VSR9);
+ case 10: return offsetofPPCGuestState(guest_VSR10);
+ case 11: return offsetofPPCGuestState(guest_VSR11);
+ case 12: return offsetofPPCGuestState(guest_VSR12);
+ case 13: return offsetofPPCGuestState(guest_VSR13);
+ case 14: return offsetofPPCGuestState(guest_VSR14);
+ case 15: return offsetofPPCGuestState(guest_VSR15);
+ case 16: return offsetofPPCGuestState(guest_VSR16);
+ case 17: return offsetofPPCGuestState(guest_VSR17);
+ case 18: return offsetofPPCGuestState(guest_VSR18);
+ case 19: return offsetofPPCGuestState(guest_VSR19);
+ case 20: return offsetofPPCGuestState(guest_VSR20);
+ case 21: return offsetofPPCGuestState(guest_VSR21);
+ case 22: return offsetofPPCGuestState(guest_VSR22);
+ case 23: return offsetofPPCGuestState(guest_VSR23);
+ case 24: return offsetofPPCGuestState(guest_VSR24);
+ case 25: return offsetofPPCGuestState(guest_VSR25);
+ case 26: return offsetofPPCGuestState(guest_VSR26);
+ case 27: return offsetofPPCGuestState(guest_VSR27);
+ case 28: return offsetofPPCGuestState(guest_VSR28);
+ case 29: return offsetofPPCGuestState(guest_VSR29);
+ case 30: return offsetofPPCGuestState(guest_VSR30);
+ case 31: return offsetofPPCGuestState(guest_VSR31);
+ default: break;
+ }
}
vpanic("floatGuestRegOffset(ppc)"); /*notreached*/
}
@@ -4758,7 +4866,7 @@
switch (opc1) {
case 0x22: // lbz (Load B & Zero, PPC32 p433)
DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I8, mkexpr(EA));
+ val = load(Ity_I8, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
break;
@@ -4768,14 +4876,14 @@
return False;
}
DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I8, mkexpr(EA));
+ val = load(Ity_I8, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x2A: // lha (Load HW Alg, PPC32 p445)
DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
break;
@@ -4785,14 +4893,14 @@
return False;
}
DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x28: // lhz (Load HW & Zero, PPC32 p450)
DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
break;
@@ -4802,14 +4910,14 @@
return False;
}
DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x20: // lwz (Load W & Zero, PPC32 p460)
DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I32, mkexpr(EA));
+ val = load(Ity_I32, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
break;
@@ -4819,7 +4927,7 @@
return False;
}
DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
- val = loadBE(Ity_I32, mkexpr(EA));
+ val = load(Ity_I32, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
@@ -4838,14 +4946,14 @@
vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n");
return False;
}
- val = loadBE(Ity_I8, mkexpr(EA));
+ val = load(Ity_I8, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436)
DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I8, mkexpr(EA));
+ val = load(Ity_I8, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
break;
@@ -4855,14 +4963,14 @@
return False;
}
DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448)
DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
break;
@@ -4872,14 +4980,14 @@
return False;
}
DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453)
DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I16, mkexpr(EA));
+ val = load(Ity_I16, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
break;
@@ -4889,14 +4997,14 @@
return False;
}
DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I32, mkexpr(EA));
+ val = load(Ity_I32, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463)
DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- val = loadBE(Ity_I32, mkexpr(EA));
+ val = load(Ity_I32, mkexpr(EA));
putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
break;
@@ -4908,13 +5016,13 @@
return False;
}
DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x015: // ldx (Load DWord, Indexed, PPC64 p476)
DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
break;
case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501)
@@ -4924,14 +5032,14 @@
}
DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
putIReg( rD_addr,
- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502)
DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
putIReg( rD_addr,
- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
break;
default:
@@ -4946,7 +5054,7 @@
switch ((b1<<1) | b0) {
case 0x0: // ld (Load DWord, PPC64 p472)
DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
break;
case 0x1: // ldu (Load DWord, Update, PPC64 p474)
@@ -4955,14 +5063,14 @@
return False;
}
DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x2: // lwa (Load Word Alg, PPC64 p499)
DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
putIReg( rD_addr,
- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
break;
default:
@@ -4981,17 +5089,17 @@
*/
// trap if EA misaligned on 16 byte address
if (mode64) {
- assign(high, loadBE(ty, mkexpr( EA ) ) );
- assign(low, loadBE(ty, binop( Iop_Add64,
- mkexpr( EA ),
- mkU64( 8 ) ) ) );
+ assign(high, load(ty, mkexpr( EA ) ) );
+ assign(low, load(ty, binop( Iop_Add64,
+ mkexpr( EA ),
+ mkU64( 8 ) ) ) );
} else {
- assign(high, loadBE(ty, binop( Iop_Add32,
- mkexpr( EA ),
- mkU32( 4 ) ) ) );
- assign(low, loadBE(ty, binop( Iop_Add32,
- mkexpr( EA ),
- mkU32( 12 ) ) ) );
+ assign(high, load(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+ mkU32( 4 ) ) ) );
+ assign(low, load(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+ mkU32( 12 ) ) ) );
}
gen_SIGBUS_if_misaligned( EA, 16 );
putIReg( rD_addr, mkexpr( high) );
@@ -5046,7 +5154,7 @@
switch (opc1) {
case 0x26: // stb (Store B, PPC32 p509)
DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
break;
case 0x27: // stbu (Store B, Update, PPC32 p510)
@@ -5056,12 +5164,12 @@
}
DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
break;
case 0x2C: // sth (Store HW, PPC32 p522)
DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
break;
case 0x2D: // sthu (Store HW, Update, PPC32 p524)
@@ -5071,12 +5179,12 @@
}
DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
break;
case 0x24: // stw (Store W, PPC32 p530)
DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
break;
case 0x25: // stwu (Store W, Update, PPC32 p534)
@@ -5086,7 +5194,7 @@
}
DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
break;
/* X Form : all these use EA_indexed */
@@ -5104,12 +5212,12 @@
}
DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
break;
case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
break;
case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525)
@@ -5119,12 +5227,12 @@
}
DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
break;
case 0x197: // sthx (Store HW Indexed, PPC32 p526)
DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
break;
case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535)
@@ -5134,12 +5242,12 @@
}
DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
break;
case 0x097: // stwx (Store W Indexed, PPC32 p536)
DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
break;
@@ -5151,12 +5259,12 @@
}
DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkexpr(rS) );
+ store( mkexpr(EA), mkexpr(rS) );
break;
case 0x095: // stdx (Store DWord Indexed, PPC64 p585)
DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
- storeBE( mkexpr(EA), mkexpr(rS) );
+ store( mkexpr(EA), mkexpr(rS) );
break;
default:
@@ -5174,7 +5282,7 @@
return False;
DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
- storeBE( mkexpr(EA), mkexpr(rS) );
+ store( mkexpr(EA), mkexpr(rS) );
break;
case 0x1: // stdu (Store DWord, Update, PPC64 p583)
@@ -5183,7 +5291,7 @@
DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
putIReg( rA_addr, mkexpr(EA) );
- storeBE( mkexpr(EA), mkexpr(rS) );
+ store( mkexpr(EA), mkexpr(rS) );
break;
case 0x2: { // stq (Store QuadWord, Update, PPC64 p583)
@@ -5205,9 +5313,9 @@
assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) );
}
putIReg( rA_addr, mkexpr(EA_hi) );
- storeBE( mkexpr(EA_hi), mkexpr(rS) );
+ store( mkexpr(EA_hi), mkexpr(rS) );
putIReg( rA_addr, mkexpr( EA_lo) );
- storeBE( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
+ store( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
break;
}
default:
@@ -5256,7 +5364,7 @@
DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
for (r = rD_addr; r <= 31; r++) {
irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
- putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ),
+ putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ),
False) );
ea_off += 4;
}
@@ -5266,7 +5374,7 @@
DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
for (r = rS_addr; r <= 31; r++) {
irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
- storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) );
+ store( irx_addr, mkNarrowTo32(ty, getIReg(r)) );
ea_off += 4;
}
break;
@@ -5321,8 +5429,9 @@
Iop_Shl32,
unop(
Iop_8Uto32,
- loadBE(Ity_I8,
- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)))
+ load( Ity_I8,
+ binop( mkSzOp(ty,Iop_Add8),
+ e_EA, mkSzImm(ty,i)))
),
mkU8(toUChar(shift))
)
@@ -5360,12 +5469,12 @@
}
/* *(EA+i) = 32to8(rS >> shift) */
vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
- storeBE(
- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),
- unop(Iop_32to8,
- binop(Iop_Shr32,
- mkNarrowTo32(ty, getIReg(rS)),
- mkU8(toUChar(shift))))
+ store(
+ binop( mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),
+ unop( Iop_32to8,
+ binop( Iop_Shr32,
+ mkNarrowTo32( ty, getIReg(rS) ),
+ mkU8( toUChar(shift) )))
);
shift -= 8;
}
@@ -5404,10 +5513,10 @@
/* Special case hack */
/* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */
putIReg( rD_addr,
- loadBE(Ity_I32, mkexpr(t_EA)) );
+ load(Ity_I32, mkexpr(t_EA)) );
putIReg( (rD_addr+1) % 32,
- loadBE(Ity_I32,
- binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );
+ load(Ity_I32,
+ binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );
} else {
t_nbytes = newTemp(Ity_I32);
assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
@@ -5439,10 +5548,10 @@
if (NumBytes == 8 && !mode64) {
/* Special case hack */
/* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */
- storeBE( mkexpr(t_EA),
- getIReg(rD_addr) );
- storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
- getIReg((rD_addr+1) % 32) );
+ store( mkexpr(t_EA),
+ getIReg(rD_addr) );
+ store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
+ getIReg((rD_addr+1) % 32) );
} else {
t_nbytes = newTemp(Ity_I32);
assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
@@ -6143,7 +6252,7 @@
// and actually do the load
res = newTemp(Ity_I32);
- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );
+ stmt( stmt_load(res, mkexpr(EA), NULL/*this is a load*/) );
putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) );
break;
@@ -6169,7 +6278,7 @@
// Do the store, and get success/failure bit into resSC
resSC = newTemp(Ity_I1);
- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) );
// Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
// Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
@@ -6236,7 +6345,7 @@
// and actually do the load
res = newTemp(Ity_I64);
- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );
+ stmt( stmt_load( res, mkexpr(EA), NULL/*this is a load*/) );
putIReg( rD_addr, mkexpr(res) );
break;
@@ -6262,7 +6371,7 @@
// Do the store, and get success/failure bit into resSC
resSC = newTemp(Ity_I1);
- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) );
// Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
// Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
@@ -6292,18 +6401,18 @@
// and actually do the load
if (mode64) {
- stmt( IRStmt_LLSC( Iend_BE, res_hi,
- mkexpr(EA), NULL/*this is a load*/) );
- stmt( IRStmt_LLSC( Iend_BE, res_lo,
- binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
- NULL/*this is a load*/) );
+ stmt( stmt_load( res_hi,
+ mkexpr(EA), NULL/*this is a load*/) );
+ stmt( stmt_load( res_lo,
+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+ NULL/*this is a load*/) );
} else {
- stmt( IRStmt_LLSC( Iend_BE, res_hi,
- binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
- NULL/*this is a load*/) );
- stmt( IRStmt_LLSC( Iend_BE, res_lo,
- binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
- NULL/*this is a load*/) );
+ stmt( stmt_load( res_hi,
+ binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
+ NULL/*this is a load*/) );
+ stmt( stmt_load( res_lo,
+ binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
+ NULL/*this is a load*/) );
}
putIReg( rD_addr, mkexpr(res_hi) );
putIReg( rD_addr+1, mkexpr(res_lo) );
@@ -6332,14 +6441,14 @@
resSC = newTemp(Ity_I1);
if (mode64) {
- stmt( IRStmt_LLSC( Iend_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
- storeBE(binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
} else {
- stmt( IRStmt_LLSC( Iend_BE, resSC, binop( Iop_Add32,
- mkexpr(EA),
- mkU32(4) ),
- mkexpr(rS_hi) ) );
- storeBE(binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
+ stmt( stmt_load( resSC, binop( Iop_Add32,
+ mkexpr(EA),
+ mkU32(4) ),
+ mkexpr(rS_hi) ) );
+ store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
}
// Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
@@ -6662,7 +6771,7 @@
case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449)
DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- assign( w1, unop(Iop_16Uto32, loadBE(Ity_I16, mkexpr(EA))) );
+ assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) );
assign( w2, gen_byterev16(w1) );
putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
/* Signed */False) );
@@ -6670,7 +6779,7 @@
case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459)
DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- assign( w1, loadBE(Ity_I32, mkexpr(EA)) );
+ assign( w1, load(Ity_I32, mkexpr(EA)) );
assign( w2, gen_byterev32(w1) );
putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
/* Signed */False) );
@@ -6682,26 +6791,29 @@
IRTemp w3 = newTemp( Ity_I32 );
IRTemp w4 = newTemp( Ity_I32 );
DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
- assign( w1, loadBE( Ity_I32, mkexpr( EA ) ) );
+ assign( w1, load( Ity_I32, mkexpr( EA ) ) );
assign( w2, gen_byterev32( w1 ) );
nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
- assign( w3, loadBE( Ity_I32, nextAddr ) );
+ assign( w3, load( Ity_I32, nextAddr ) );
assign( w4, gen_byterev32( w3 ) );
- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
+ if (host_endness == VexEndnessLE)
+ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) );
+ else
+ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
break;
}
case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523)
DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
- storeBE( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );
+ store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );
break;
case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531)
DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
- storeBE( mkexpr(EA), gen_byterev32(w1) );
+ store( mkexpr(EA), gen_byterev32(w1) );
break;
case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed)
@@ -6713,8 +6825,9 @@
DIP("stdbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
assign(lo, unop(Iop_64HIto32, mkexpr(rS)));
assign(hi, unop(Iop_64to32, mkexpr(rS)));
- storeBE( mkexpr( EA ),
- binop( Iop_32HLto64, gen_byterev32( hi ), gen_byterev32( lo ) ) );
+ store( mkexpr( EA ),
+ binop( Iop_32HLto64, gen_byterev32( hi ),
+ gen_byterev32( lo ) ) );
break;
}
@@ -7232,7 +7345,7 @@
for (i = 0; i < clearszB / 8; i++) {
irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) );
- storeBE( irx_addr, mkU64(0) );
+ store( irx_addr, mkU64(0) );
}
} else {
/* Round EA down to the start of the containing block. */
@@ -7242,7 +7355,7 @@
for (i = 0; i < clearszB / 4; i++) {
irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );
- storeBE( irx_addr, mkU32(0) );
+ store( irx_addr, mkU32(0) );
}
}
break;
@@ -7462,7 +7575,7 @@
DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
assign( EA, ea_rAor0_simm(rA_addr, simm16) );
putFReg( frD_addr,
- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
break;
case 0x31: // lfsu (Load Float Single, Update, PPC32 p442)
@@ -7471,14 +7584,14 @@
DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
assign( EA, ea_rA_simm(rA_addr, simm16) );
putFReg( frD_addr,
- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x32: // lfd (Load Float Double, PPC32 p437)
DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
assign( EA, ea_rAor0_simm(rA_addr, simm16) );
- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
break;
case 0x33: // lfdu (Load Float Double, Update, PPC32 p438)
@@ -7486,7 +7599,7 @@
return False;
DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
assign( EA, ea_rA_simm(rA_addr, simm16) );
- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
break;
@@ -7501,7 +7614,7 @@
DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
putFReg( frD_addr, unop( Iop_F32toF64,
- loadBE(Ity_F32, mkexpr(EA))) );
+ load(Ity_F32, mkexpr(EA))) );
break;
case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443)
@@ -7510,14 +7623,14 @@
DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
putFReg( frD_addr,
- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440)
DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
break;
case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439)
@@ -7525,14 +7638,14 @@
return False;
DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120)
DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) );
+ assign( iLo, load(Ity_I32, mkexpr(EA)) );
assign( iHi, binop(Iop_Sub32,
mkU32(0),
binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) );
@@ -7545,7 +7658,7 @@
IRTemp dw = newTemp( Ity_I64 );
DIP("lfiwzx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) );
+ assign( iLo, load(Ity_I32, mkexpr(EA)) );
assign( dw, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( iLo ) ) );
putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ) );
break;
@@ -7604,8 +7717,7 @@
/* Use Iop_TruncF64asF32 to truncate and possible denormalise
the value to be stored in the correct way, without any
rounding. */
- storeBE( mkexpr(EA),
- unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
break;
case 0x35: // stfsu (Store Float Single, Update, PPC32 p519)
@@ -7614,15 +7726,14 @@
DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
assign( EA, ea_rA_simm(rA_addr, simm16) );
/* See comment for stfs */
- storeBE( mkexpr(EA),
- unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x36: // stfd (Store Float Double, PPC32 p513)
DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
assign( EA, ea_rAor0_simm(rA_addr, simm16) );
- storeBE( mkexpr(EA), mkexpr(frS) );
+ store( mkexpr(EA), mkexpr(frS) );
break;
case 0x37: // stfdu (Store Float Double, Update, PPC32 p514)
@@ -7630,7 +7741,7 @@
return False;
DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
assign( EA, ea_rA_simm(rA_addr, simm16) );
- storeBE( mkexpr(EA), mkexpr(frS) );
+ store( mkexpr(EA), mkexpr(frS) );
putIReg( rA_addr, mkexpr(EA) );
break;
@@ -7644,8 +7755,8 @@
DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
/* See note for stfs */
- storeBE( mkexpr(EA),
- unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ store( mkexpr(EA),
+ unop(Iop_TruncF64asF32, mkexpr(frS)) );
break;
case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520)
@@ -7654,15 +7765,14 @@
DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
/* See note for stfs */
- storeBE( mkexpr(EA),
- unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
putIReg( rA_addr, mkexpr(EA) );
break;
case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516)
DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
- storeBE( mkexpr(EA), mkexpr(frS) );
+ store( mkexpr(EA), mkexpr(frS) );
break;
case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515)
@@ -7670,7 +7780,7 @@
return False;
DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
- storeBE( mkexpr(EA), mkexpr(frS) );
+ store( mkexpr(EA), mkexpr(frS) );
putIReg( rA_addr, mkexpr(EA) );
break;
@@ -7678,8 +7788,8 @@
// NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX)
DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
- storeBE( mkexpr(EA),
- unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) );
+ store( mkexpr(EA),
+ unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) );
break;
default:
@@ -8865,11 +8975,11 @@
assign( frT_lo, getFReg(frT_lo_addr) );
if (is_load) {
- putFReg( frT_hi_addr, loadBE(Ity_F64, mkexpr(EA_hi)) );
- putFReg( frT_lo_addr, loadBE(Ity_F64, mkexpr(EA_lo)) );
+ putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi)) );
+ putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo)) );
} else {
- storeBE( mkexpr(EA_hi), mkexpr(frT_hi) );
- storeBE( mkexpr(EA_lo), mkexpr(frT_lo) );
+ store( mkexpr(EA_hi), mkexpr(frT_hi) );
+ store( mkexpr(EA_lo), mkexpr(frT_lo) );
}
return True;
@@ -14767,6 +14877,7 @@
static Bool
dis_vxs_misc( UInt theInstr, UInt opc2 )
{
+#define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL
/* XX3-Form and XX2-Form */
UChar opc1 = ifieldOPC( theInstr );
UChar XT = ifieldRegXT ( theInstr );
@@ -14793,7 +14904,20 @@
{
/* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */
IRTemp absVal = newTemp(Ity_V128);
- assign(absVal, binop(Iop_ShrV128, binop(Iop_ShlV128, mkexpr(vB), mkU8(1)), mkU8(1)));
+ if (host_endness == VexEndnessLE) {
+ IRTemp hi64 = newTemp(Ity_I64);
+ IRTemp lo64 = newTemp(Ity_I64);
+ assign( hi64, unop( Iop_V128HIto64, mkexpr(vB) ) );
+ assign( lo64, unop( Iop_V128to64, mkexpr(vB) ) );
+ assign( absVal, binop( Iop_64HLtoV128,
+ binop( Iop_And64, mkexpr(hi64),
+ mkU64(VG_PPC_SIGN_MASK) ),
+ mkexpr(lo64) ) );
+ } else {
+ assign(absVal, binop(Iop_ShrV128,
+ binop(Iop_ShlV128, mkexpr(vB),
+ mkU8(1)), mkU8(1)));
+ }
DIP("xsabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
putVSReg(XT, mkexpr(absVal));
break;
@@ -14801,51 +14925,73 @@
case 0x2C0: // xscpsgndp
{
/* Scalar copy sign double-precision */
- IRTemp vecA_signbit = newTemp(Ity_V128);
- IRTemp vecB_no_signbit = newTemp(Ity_V128);
+ IRTemp vecA_signed = newTemp(Ity_I64);
+ IRTemp vecB_unsigned = newTemp(Ity_I64);
IRTemp vec_result = newTemp(Ity_V128);
DIP("xscpsgndp v%d,v%d v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128,
- mkexpr( vB ),
- mkU8( 1 ) ),
- mkU8( 1 ) ) );
- assign( vecA_signbit, binop( Iop_ShlV128, binop( Iop_ShrV128,
- mkexpr( vA ),
- mkU8( 127 ) ),
- mkU8( 127 ) ) );
- assign( vec_result, binop( Iop_OrV128, mkexpr(vecA_signbit), mkexpr( vecB_no_signbit ) ) );
+ assign( vecA_signed, binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr(vA)),
+ mkU64(~VG_PPC_SIGN_MASK) ) );
+ assign( vecB_unsigned, binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr(vB) ),
+ mkU64(VG_PPC_SIGN_MASK) ) );
+ assign( vec_result, binop( Iop_64HLtoV128,
+ binop( Iop_Or64,
+ mkexpr(vecA_signed),
+ mkexpr(vecB_unsigned) ),
+ mkU64(0x0ULL)));
putVSReg(XT, mkexpr(vec_result));
break;
}
case 0x2D2: // xsnabsdp
{
/* Scalar negative absolute value double-precision */
- IRTemp vec_neg_signbit = newTemp(Ity_V128);
+ IRTemp BHi_signed = newTemp(Ity_I64);
DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
- assign( vec_neg_signbit, unop( Iop_NotV128, binop( Iop_ShrV128,
- mkV128( 0xffff ),
- mkU8( 1 ) ) ) );
- putVSReg(XT, binop(Iop_OrV128, mkexpr(vec_neg_signbit), mkexpr(vB)));
+ assign( BHi_signed, binop( Iop_Or64,
+ unop( Iop_V128HIto64,
+ mkexpr(vB) ),
+ mkU64(~VG_PPC_SIGN_MASK) ) );
+ putVSReg(XT, binop( Iop_64HLtoV128,
+ mkexpr(BHi_signed), mkU64(0x0ULL) ) );
break;
}
case 0x2F2: // xsnegdp
{
/* Scalar negate double-precision */
- IRTemp vecB_no_signbit = newTemp(Ity_V128);
- IRTemp vecB_signbit_comp = newTemp(Ity_V128);
+ IRTemp BHi_signed = newTemp(Ity_I64);
+ IRTemp BHi_unsigned = newTemp(Ity_I64);
+ IRTemp BHi_negated = newTemp(Ity_I64);
+ IRTemp BHi_negated_signbit = newTemp(Ity_I1);
+ IRTemp vec_result = newTemp(Ity_V128);
DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128,
- mkexpr( vB ),
- mkU8( 1 ) ),
- mkU8( 1 ) ) );
- assign( vecB_signbit_comp, binop( Iop_ShlV128,
- unop( Iop_NotV128,
- binop( Iop_ShrV128,
- mkexpr( vB ),
- mkU8( 127 ) ) ),
- mkU8( 127 ) ) );
- putVSReg( XT, binop( Iop_OrV128, mkexpr( vecB_no_signbit ),
- mkexpr( vecB_signbit_comp ) ) );
+ assign( BHi_signed, unop( Iop_V128HIto64, mkexpr(vB) ) );
+ assign( BHi_unsigned, binop( Iop_And64, mkexpr(BHi_signed),
+ mkU64(VG_PPC_SIGN_MASK) ) );
+ assign( BHi_negated_signbit,
+ unop( Iop_Not1,
+ unop( Iop_32to1,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32,
+ binop( Iop_And64,
+ mkexpr(BHi_signed),
+ mkU64(~VG_PPC_SIGN_MASK) )
+ ),
+ mkU8(31) ) ) ) );
+ assign( BHi_negated,
+ binop( Iop_Or64,
+ binop( Iop_32HLto64,
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32,
+ mkexpr(BHi_negated_signbit) ),
+ mkU8(31) ),
+ mkU32(0) ),
+ mkexpr(BHi_unsigned) ) );
+ assign( vec_result, binop( Iop_64HLtoV128, mkexpr(BHi_negated),
+ mkU64(0x0ULL)));
+ putVSReg( XT, mkexpr(vec_result));
break;
}
case 0x280: // xsmaxdp (VSX Scalar Maximum Double-Precision)
@@ -15070,7 +15216,7 @@
{
IRExpr * exp;
DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) );
+ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
putVSReg( XT, binop( Iop_64HLtoV128,
unop( Iop_32Uto64, exp),
mkU64(0) ) );
@@ -15080,7 +15226,7 @@
{
IRExpr * exp;
DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) );
+ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
putVSReg( XT, binop( Iop_64HLtoV128,
unop( Iop_32Sto64, exp),
mkU64(0) ) );
@@ -15097,8 +15243,7 @@
exp = unop( Iop_ReinterpF64asI64,
unop( Iop_F32toF64,
unop( Iop_ReinterpI32asF32,
- unop( Iop_64HIto32,
- loadBE( Ity_I64, mkexpr( EA ) ) ) ) ) );
+ load( Ity_I32, mkexpr( EA ) ) ) ) );
putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) );
break;
@@ -15107,7 +15252,7 @@
{
IRExpr * exp;
DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- exp = loadBE( Ity_I64, mkexpr( EA ) );
+ exp = load( Ity_I64, mkexpr( EA ) );
// We need to pass an expression of type Ity_V128 with putVSReg, but the load
// we just performed is only a DW. But since the contents of VSR[XT] element 1
// are undefined after this operation, we can just do a splat op.
@@ -15121,10 +15266,10 @@
ULong ea_off = 8;
IRExpr* high_addr;
DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- high = loadBE( Ity_I64, mkexpr( EA ) );
+ high = load( Ity_I64, mkexpr( EA ) );
high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
: mkU32( ea_off ) );
- low = loadBE( Ity_I64, high_addr );
+ low = load( Ity_I64, high_addr );
putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
break;
}
@@ -15132,7 +15277,7 @@
{
IRTemp data = newTemp(Ity_I64);
DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- assign( data, loadBE( Ity_I64, mkexpr( EA ) ) );
+ assign( data, load( Ity_I64, mkexpr( EA ) ) );
putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) );
break;
}
@@ -15143,19 +15288,19 @@
IRExpr* irx_addr;
DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- t3 = loadBE( Ity_I32, mkexpr( EA ) );
+ t3 = load( Ity_I32, mkexpr( EA ) );
ea_off += 4;
irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- t2 = loadBE( Ity_I32, irx_addr );
+ t2 = load( Ity_I32, irx_addr );
ea_off += 4;
irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- t1 = loadBE( Ity_I32, irx_addr );
+ t1 = load( Ity_I32, irx_addr );
ea_off += 4;
irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- t0 = loadBE( Ity_I32, irx_addr );
+ t0 = load( Ity_I32, irx_addr );
putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ),
binop( Iop_32HLto64, t1, t0 ) ) );
break;
@@ -15203,7 +15348,7 @@
DIP("stxsiwx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
low32 = unop( Iop_64to32, high64 );
- storeBE( mkexpr( EA ), low32 );
+ store( mkexpr( EA ), low32 );
break;
}
case 0x28C:
@@ -15216,7 +15361,7 @@
assign(val32, unop( Iop_ReinterpF32asI32,
unop( Iop_TruncF64asF32,
mkexpr(high64) ) ) );
- storeBE( mkexpr( EA ), mkexpr( val32 ) );
+ store( mkexpr( EA ), mkexpr( val32 ) );
break;
}
case 0x2CC:
@@ -15224,7 +15369,7 @@
IRExpr * high64;
DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
- storeBE( mkexpr( EA ), high64 );
+ store( mkexpr( EA ), high64 );
break;
}
case 0x3CC:
@@ -15233,9 +15378,9 @@
DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
low64 = unop( Iop_V128to64, mkexpr( vS ) );
- storeBE( mkexpr( EA ), high64 );
- storeBE( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), ty == Ity_I64 ? mkU64( 8 )
- : mkU32( 8 ) ), low64 );
+ store( mkexpr( EA ), high64 );
+ store( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64 );
break;
}
case 0x38C:
@@ -15251,20 +15396,19 @@
// quad-word aligned. Th...
[truncated message content] |
Author: carll
Date: Thu Aug 7 23:17:29 2014
New Revision: 14238
Log:
This commit is for Bugzilla 334384. The Bugzilla contains patch 1 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334834 and 334836. The commit does not have a VEX commit associated with it.
POWER PC, add initial Little Endian support
The IBM POWER processor now supports both Big Endian and Little Endian.
This patch renames the #defines with the name ppc64 to ppc64be for the BE
specific code. This patch adds the Little Endian #define ppc64le to the
Additionally, a few functions are renamed to remove BE from the name if the
function is used by BE and LE. Functions that are BE specific have BE put
in the name.
The goals of this patch is to make sure #defines, function names and
variables consistently use PPC64/ppc64 if it refers to BE and LE,
PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE
specific. The patch does not break the code for PPC64 Big Endian.
The test files memcheck/tests/atomic_incs.c, tests/power_insn_available.c
and tests/power_insn_available.c are also updated to the new #define
definition for PPC64 BE.
Signed-off-by: Carl Love <ca...@us...>
Modified:
trunk/Makefile.all.am
trunk/Makefile.tool.am
trunk/cachegrind/cg_arch.c
trunk/cachegrind/cg_branchpred.c
trunk/configure.ac
trunk/coregrind/launcher-darwin.c
trunk/coregrind/launcher-linux.c
trunk/coregrind/m_aspacemgr/aspacemgr-common.c
trunk/coregrind/m_cache.c
trunk/coregrind/m_coredump/coredump-elf.c
trunk/coregrind/m_debugger.c
trunk/coregrind/m_debuginfo/d3basics.c
trunk/coregrind/m_debuginfo/debuginfo.c
trunk/coregrind/m_debuginfo/priv_storage.h
trunk/coregrind/m_debuginfo/readdwarf.c
trunk/coregrind/m_debuginfo/readelf.c
trunk/coregrind/m_debuginfo/readmacho.c
trunk/coregrind/m_debuginfo/storage.c
trunk/coregrind/m_debuglog.c
trunk/coregrind/m_dispatch/dispatch-ppc64-linux.S
trunk/coregrind/m_gdbserver/target.c
trunk/coregrind/m_initimg/initimg-linux.c
trunk/coregrind/m_libcassert.c
trunk/coregrind/m_libcfile.c
trunk/coregrind/m_libcproc.c
trunk/coregrind/m_libcsetjmp.c
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_redir.c
trunk/coregrind/m_scheduler/scheduler.c
trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c
trunk/coregrind/m_signals.c
trunk/coregrind/m_stacktrace.c
trunk/coregrind/m_syscall.c
trunk/coregrind/m_syswrap/priv_types_n_macros.h
trunk/coregrind/m_syswrap/syscall-ppc64-linux.S
trunk/coregrind/m_syswrap/syswrap-linux.c
trunk/coregrind/m_syswrap/syswrap-main.c
trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
trunk/coregrind/m_trampoline.S
trunk/coregrind/m_translate.c
trunk/coregrind/m_ume/elf.c
trunk/coregrind/m_ume/macho.c
trunk/coregrind/m_vki.c
trunk/coregrind/pub_core_aspacemgr.h
trunk/coregrind/pub_core_basics.h
trunk/coregrind/pub_core_debuginfo.h
trunk/coregrind/pub_core_machine.h
trunk/coregrind/pub_core_mallocfree.h
trunk/coregrind/pub_core_threadstate.h
trunk/coregrind/pub_core_trampoline.h
trunk/coregrind/pub_core_transtab_asm.h
trunk/coregrind/vgdb-invoker-ptrace.c
trunk/drd/drd_bitmap.h
trunk/drd/drd_load_store.c
trunk/drd/tests/unit_bitmap.c
trunk/helgrind/tests/annotate_hbefore.c
trunk/include/pub_tool_basics.h
trunk/include/pub_tool_libcsetjmp.h
trunk/include/pub_tool_machine.h
trunk/include/pub_tool_vkiscnums_asm.h
trunk/include/valgrind.h
trunk/include/vki/vki-linux.h
trunk/memcheck/mc_machine.c
trunk/memcheck/tests/atomic_incs.c
trunk/memcheck/tests/unit_libcbase.c
trunk/tests/arch_test.c
trunk/tests/power_insn_available.c
Modified: trunk/Makefile.all.am
==============================================================================
--- trunk/Makefile.all.am (original)
+++ trunk/Makefile.all.am Thu Aug 7 23:17:29 2014
@@ -229,15 +229,16 @@
PRELOAD_LDFLAGS_COMMON_LINUX += -nostdlib
endif
-PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
-PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
-PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
-PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
Modified: trunk/Makefile.tool.am
==============================================================================
--- trunk/Makefile.tool.am (original)
+++ trunk/Makefile.tool.am Thu Aug 7 23:17:29 2014
@@ -46,7 +46,10 @@
TOOL_LDFLAGS_PPC32_LINUX = \
$(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
-TOOL_LDFLAGS_PPC64_LINUX = \
+TOOL_LDFLAGS_PPC64BE_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC64LE_LINUX = \
$(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
TOOL_LDFLAGS_ARM_LINUX = \
@@ -102,8 +105,11 @@
LIBREPLACEMALLOC_PPC32_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
-LIBREPLACEMALLOC_PPC64_LINUX = \
- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+LIBREPLACEMALLOC_PPC64BE_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64be-linux.a
+
+LIBREPLACEMALLOC_PPC64LE_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64le-linux.a
LIBREPLACEMALLOC_ARM_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
@@ -141,9 +147,14 @@
$(LIBREPLACEMALLOC_PPC32_LINUX) \
-Wl,--no-whole-archive
-LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+LIBREPLACEMALLOC_LDFLAGS_PPC64BE_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64BE_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64LE_LINUX = \
-Wl,--whole-archive \
- $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ $(LIBREPLACEMALLOC_PPC64LE_LINUX) \
-Wl,--no-whole-archive
LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
Modified: trunk/cachegrind/cg_arch.c
==============================================================================
--- trunk/cachegrind/cg_arch.c (original)
+++ trunk/cachegrind/cg_arch.c Thu Aug 7 23:17:29 2014
@@ -353,7 +353,7 @@
*D1c = (cache_t) { 65536, 2, 64 };
*LLc = (cache_t) { 262144, 8, 64 };
-#elif defined(VGA_ppc64)
+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
// Default cache configuration
*I1c = (cache_t) { 65536, 2, 64 };
Modified: trunk/cachegrind/cg_branchpred.c
==============================================================================
--- trunk/cachegrind/cg_branchpred.c (original)
+++ trunk/cachegrind/cg_branchpred.c Thu Aug 7 23:17:29 2014
@@ -44,7 +44,7 @@
/* How many bits at the bottom of an instruction address are
guaranteed to be zero? */
-#if defined(VGA_ppc32) || defined(VGA_ppc64) \
+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
|| defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
# define N_IADDR_LO_ZERO_BITS 2
#elif defined(VGA_x86) || defined(VGA_amd64)
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Thu Aug 7 23:17:29 2014
@@ -163,6 +163,18 @@
# is a 64-bit capable PowerPC, then it must be set to ppc64 and not ppc32.
# Ditto for amd64. It is used for more configuration below, but is not used
# outside this file.
+#
+# Power PC returns powerpc for Big Endian. This was not changed when Little
+# Endian support was added to the 64-bit architecture. The 64-bit Little
+# Endian systems explicitly state le in the host_cpu. For clarity in the
+# Valgrind code, the ARCH_MAX name will state LE or BE for the endianess of
+# the 64-bit system. Big Endian is the only mode supported on 32-bit Power PC.
+# The abreviation PPC or ppc refers to 32-bit and 64-bit systems with either
+# Endianess. The name PPC64 or ppc64 to 64-bit systems of either Endianess.
+# The names ppc64be or PPC64BE refer to only 64-bit systems that are Big
+# Endian. Similarly, ppc64le or PPC64LE refer to only 64-bit systems that are
+# Little Endian.
+
case "${host_cpu}" in
i?86)
AC_MSG_RESULT([ok (${host_cpu})])
@@ -175,8 +187,15 @@
;;
powerpc64)
+ # this only referrs to 64-bit Big Endian
AC_MSG_RESULT([ok (${host_cpu})])
- ARCH_MAX="ppc64"
+ ARCH_MAX="ppc64be"
+ ;;
+
+ powerpc64le)
+ # this only referrs to 64-bit Little Endian
+ AC_MSG_RESULT([ok (${host_cpu})])
+ ARCH_MAX="ppc64le"
;;
powerpc)
@@ -378,7 +397,7 @@
# does not support building 32 bit programs
case "$ARCH_MAX-$VGCONF_OS" in
- amd64-linux|ppc64-linux)
+ amd64-linux|ppc64be-linux)
AC_MSG_CHECKING([for 32 bit build support])
safe_CFLAGS=$CFLAGS
CFLAGS="-m32"
@@ -496,13 +515,13 @@
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
- ppc64-linux)
+ ppc64be-linux)
valt_load_address_sec_norml="0xUNSET"
valt_load_address_sec_inner="0xUNSET"
if test x$vg_cv_only64bit = xyes; then
- VGCONF_ARCH_PRI="ppc64"
+ VGCONF_ARCH_PRI="ppc64be"
VGCONF_ARCH_SEC=""
- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
+ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS=""
valt_load_address_pri_norml="0x38000000"
valt_load_address_pri_inner="0x28000000"
@@ -514,9 +533,9 @@
valt_load_address_pri_norml="0x38000000"
valt_load_address_pri_inner="0x28000000"
else
- VGCONF_ARCH_PRI="ppc64"
+ VGCONF_ARCH_PRI="ppc64be"
VGCONF_ARCH_SEC="ppc32"
- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
+ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
valt_load_address_pri_norml="0x38000000"
valt_load_address_pri_inner="0x28000000"
@@ -525,6 +544,18 @@
fi
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
+ ppc64le-linux)
+ # Little Endian is only supported on PPC64
+ valt_load_address_sec_norml="0xUNSET"
+ valt_load_address_sec_inner="0xUNSET"
+ VGCONF_ARCH_PRI="ppc64le"
+ VGCONF_ARCH_SEC=""
+ VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX"
+ VGCONF_PLATFORM_SEC_CAPS=""
+ valt_load_address_pri_norml="0x38000000"
+ valt_load_address_pri_inner="0x28000000"
+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
+ ;;
# Darwin gets identified as 32-bit even when it supports 64-bit.
# (Not sure why, possibly because 'uname' returns "i386"?) Just about
# all Macs support both 32-bit and 64-bit, so we just build both. If
@@ -663,7 +694,8 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
-o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX )
AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64,
- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX )
+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX )
AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM,
test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
-o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX )
@@ -686,8 +718,10 @@
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX,
test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
-o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX)
-AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX,
- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX)
+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX)
+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64LE_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX)
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX,
test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
-o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX)
@@ -714,7 +748,8 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \
Modified: trunk/coregrind/launcher-darwin.c
==============================================================================
--- trunk/coregrind/launcher-darwin.c (original)
+++ trunk/coregrind/launcher-darwin.c Thu Aug 7 23:17:29 2014
@@ -59,11 +59,11 @@
const char *apple_name; // e.g. x86_64
const char *valgrind_name; // e.g. amd64
} valid_archs[] = {
- { CPU_TYPE_X86, "i386", "x86" },
- { CPU_TYPE_X86_64, "x86_64", "amd64" },
- { CPU_TYPE_ARM, "arm", "arm" },
- { CPU_TYPE_POWERPC, "ppc", "ppc32" },
- { CPU_TYPE_POWERPC64, "ppc64", "ppc64" },
+ { CPU_TYPE_X86, "i386", "x86" },
+ { CPU_TYPE_X86_64, "x86_64", "amd64" },
+ { CPU_TYPE_ARM, "arm", "arm" },
+ { CPU_TYPE_POWERPC, "ppc", "ppc32" },
+ { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
};
static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
Modified: trunk/coregrind/launcher-linux.c
==============================================================================
--- trunk/coregrind/launcher-linux.c (original)
+++ trunk/coregrind/launcher-linux.c Thu Aug 7 23:17:29 2014
@@ -236,7 +236,7 @@
if (ehdr->e_machine == EM_PPC64 &&
(ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
- platform = "ppc64-linux";
+ platform = "ppc64be-linux";
}
else
if (ehdr->e_machine == EM_S390 &&
@@ -320,7 +320,7 @@
if ((0==strcmp(VG_PLATFORM,"x86-linux")) ||
(0==strcmp(VG_PLATFORM,"amd64-linux")) ||
(0==strcmp(VG_PLATFORM,"ppc32-linux")) ||
- (0==strcmp(VG_PLATFORM,"ppc64-linux")) ||
+ (0==strcmp(VG_PLATFORM,"ppc64be-linux")) ||
(0==strcmp(VG_PLATFORM,"arm-linux")) ||
(0==strcmp(VG_PLATFORM,"arm64-linux")) ||
(0==strcmp(VG_PLATFORM,"s390x-linux")) ||
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-common.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-common.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-common.c Thu Aug 7 23:17:29 2014
@@ -155,7 +155,8 @@
aspacem_assert((offset % 4096) == 0);
res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length,
prot, flags, fd, offset / 4096);
-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
+# elif defined(VGP_amd64_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
|| defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length,
Modified: trunk/coregrind/m_cache.c
==============================================================================
--- trunk/coregrind/m_cache.c (original)
+++ trunk/coregrind/m_cache.c Thu Aug 7 23:17:29 2014
@@ -538,7 +538,8 @@
return ret == 0 ? True : False;
}
-#elif defined(VGA_arm) || defined(VGA_ppc32) || defined(VGA_ppc64) || \
+#elif defined(VGA_arm) || defined(VGA_ppc32) || \
+ defined(VGA_ppc64be) || defined(VGA_ppc64le) || \
defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
static Bool
Modified: trunk/coregrind/m_coredump/coredump-elf.c
==============================================================================
--- trunk/coregrind/m_coredump/coredump-elf.c (original)
+++ trunk/coregrind/m_coredump/coredump-elf.c Thu Aug 7 23:17:29 2014
@@ -322,7 +322,7 @@
regs->dsisr = 0;
regs->result = 0;
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux)
# define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n
DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
@@ -458,7 +458,7 @@
DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
# undef DO
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/* The guest state has the FPR fields declared as ULongs, so need
to fish out the values without converting them.
NOTE: The 32 FP registers map to the first 32 VSX registers.*/
Modified: trunk/coregrind/m_debugger.c
==============================================================================
--- trunk/coregrind/m_debugger.c (original)
+++ trunk/coregrind/m_debugger.c Thu Aug 7 23:17:29 2014
@@ -152,7 +152,7 @@
(void*)LibVEX_GuestPPC32_get_XER(vex));
return rc;
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
Int rc = 0;
/* FRJ: copied nearly verbatim from the ppc32 case. I compared the
vki-ppc64-linux.h with its ppc32 counterpart and saw no
Modified: trunk/coregrind/m_debuginfo/d3basics.c
==============================================================================
--- trunk/coregrind/m_debuginfo/d3basics.c (original)
+++ trunk/coregrind/m_debuginfo/d3basics.c Thu Aug 7 23:17:29 2014
@@ -406,7 +406,7 @@
if (regno == 7/*RSP*/) { *a = regs->sp; return True; }
# elif defined(VGP_ppc32_linux)
if (regno == 1/*SP*/) { *a = regs->sp; return True; }
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
if (regno == 1/*SP*/) { *a = regs->sp; return True; }
# elif defined(VGP_arm_linux)
if (regno == 13) { *a = regs->sp; return True; }
@@ -863,7 +863,8 @@
if (!regs)
FAIL("evaluate_Dwarf3_Expr: "
"DW_OP_call_frame_cfa but no reg info");
-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
/* Valgrind on ppc32/ppc64 currently doesn't use unwind info. */
uw1 = ML_(read_Addr)((UChar*)regs->sp);
#else
Modified: trunk/coregrind/m_debuginfo/debuginfo.c
==============================================================================
--- trunk/coregrind/m_debuginfo/debuginfo.c (original)
+++ trunk/coregrind/m_debuginfo/debuginfo.c Thu Aug 7 23:17:29 2014
@@ -836,8 +836,8 @@
|| defined(VGA_mips64)
is_rx_map = seg->hasR && seg->hasX;
is_rw_map = seg->hasR && seg->hasW;
-# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) \
- || defined(VGA_arm64)
+# elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
+ || defined(VGA_arm) || defined(VGA_arm64)
is_rx_map = seg->hasR && seg->hasX && !seg->hasW;
is_rw_map = seg->hasR && seg->hasW && !seg->hasX;
# elif defined(VGP_s390x_linux)
@@ -1678,7 +1678,7 @@
return True;
}
-/* ppc64-linux only: find the TOC pointer (R2 value) that should be in
+/* ppc64be-linux only: find the TOC pointer (R2 value) that should be in
force at the entry point address of the function containing
guest_code_addr. Returns 0 if not known. */
Addr VG_(get_tocptr) ( Addr guest_code_addr )
@@ -2389,7 +2389,8 @@
case Creg_IA_SP: return eec->uregs->sp;
case Creg_IA_BP: return eec->uregs->fp;
case Creg_MIPS_RA: return eec->uregs->ra;
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
+ || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
case Creg_ARM64_X30: return eec->uregs->x30;
# else
@@ -2639,7 +2640,7 @@
case CFIC_IA_BPREL:
cfa = cfsi_m->cfa_off + uregs->fp;
break;
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
case CFIC_ARM64_SPREL:
cfa = cfsi_m->cfa_off + uregs->sp;
@@ -2747,7 +2748,7 @@
ipHere = uregsHere->ia;
# elif defined(VGA_mips32) || defined(VGA_mips64)
ipHere = uregsHere->pc;
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
ipHere = uregsHere->pc;
# else
@@ -2829,7 +2830,7 @@
COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off);
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
Modified: trunk/coregrind/m_debuginfo/priv_storage.h
==============================================================================
--- trunk/coregrind/m_debuginfo/priv_storage.h (original)
+++ trunk/coregrind/m_debuginfo/priv_storage.h Thu Aug 7 23:17:29 2014
@@ -293,7 +293,7 @@
Int x29_off;
}
DiCfSI_m;
-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* Just have a struct with the common fields in, so that code that
processes the common fields doesn't have to be ifdef'd against
VGP_/VGA_ symbols. These are not used in any way on ppc32/64-linux
Modified: trunk/coregrind/m_debuginfo/readdwarf.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readdwarf.c (original)
+++ trunk/coregrind/m_debuginfo/readdwarf.c Thu Aug 7 23:17:29 2014
@@ -1735,7 +1735,7 @@
# define FP_REG 1
# define SP_REG 1
# define RA_REG_DEFAULT 65
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
# define FP_REG 1
# define SP_REG 1
# define RA_REG_DEFAULT 65
@@ -1775,8 +1775,9 @@
arm-linux (320) seems ludicrously high, but the ARM IHI 0040A page
7 (DWARF for the ARM Architecture) specifies that values up to 320
might exist, for Neon/VFP-v3. */
-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \
+ || defined(VGP_mips64_linux)
# define N_CFI_REGS 72
#elif defined(VGP_arm_linux)
# define N_CFI_REGS 320
@@ -2393,7 +2394,7 @@
return True;
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* These don't use CFI based unwinding (is that really true?) */
# else
@@ -2487,7 +2488,8 @@
return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP );
# elif defined(VGA_arm64)
I_die_here;
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
+ || defined(VGA_ppc64le)
# else
# error "Unknown arch"
# endif
@@ -3658,7 +3660,8 @@
if (!is_ehframe)
vg_assert(frame_avma == 0);
-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
/* These targets don't use CFI-based stack unwinding. */
return;
# endif
Modified: trunk/coregrind/m_debuginfo/readelf.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readelf.c (original)
+++ trunk/coregrind/m_debuginfo/readelf.c Thu Aug 7 23:17:29 2014
@@ -205,19 +205,19 @@
.data, size of .data + size of .bss). I don't know if this is
really correct/justifiable, or not.
- For ppc64-linux it's more complex. If the symbol is seen to be in
+ For ppc64be-linux it's more complex. If the symbol is seen to be in
the .opd section, it is taken to be a function descriptor, and so
a dereference is attempted, in order to get hold of the real entry
point address. Also as part of the dereference, there is an attempt
to calculate the TOC pointer (R2 value) associated with the symbol.
- To support the ppc64-linux pre-"dotless" ABI (prior to gcc 4.0.0),
+ To support the ppc64be-linux pre-"dotless" ABI (prior to gcc 4.0.0),
if the symbol is seen to be outside the .opd section and its name
starts with a dot, an .opd deference is not attempted, and no TOC
pointer is calculated, but the the leading dot is removed from the
name.
- As a result, on ppc64-linux, the caller of this function may have
+ As a result, on ppc64be-linux, the caller of this function may have
to piece together the real size, address, name of the symbol from
multiple calls to this function. Ugly and confusing.
*/
@@ -230,22 +230,22 @@
DiSlice* escn_strtab, /* holds the name */
Addr sym_svma, /* address as stated in the object file */
Bool symtab_in_debug, /* symbol table is in the debug file */
- DiSlice* escn_opd, /* the .opd (ppc64-linux only) */
+ DiSlice* escn_opd, /* the .opd (ppc64be-linux only) */
PtrdiffT opd_bias, /* for biasing AVMAs found in .opd */
/* OUTPUTS */
DiOffT* sym_name_out_ioff, /* name (in strtab) we should record */
Addr* sym_avma_out, /* addr we should record */
Int* sym_size_out, /* symbol size */
- Addr* sym_tocptr_out, /* ppc64-linux only: R2 value to be
+ Addr* sym_tocptr_out, /* ppc64be-linux only: R2 value to be
used on entry */
- Bool* from_opd_out, /* ppc64-linux only: did we deref an
+ Bool* from_opd_out, /* ppc64be-linux only: did we deref an
.opd entry? */
Bool* is_text_out, /* is this a text symbol? */
Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/
)
{
Bool plausible;
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
Bool is_in_opd;
# endif
Bool in_text, in_data, in_sdata, in_rodata, in_bss, in_sbss;
@@ -375,9 +375,9 @@
}
# endif
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
/* Allow STT_NOTYPE in the very special case where we're running on
- ppc64-linux and the symbol is one which the .opd-chasing hack
+ ppc64be-linux and the symbol is one which the .opd-chasing hack
below will chase. */
if (!plausible
&& *is_text_out
@@ -474,7 +474,7 @@
return False;
}
- /* ppc64-linux nasty hack: if the symbol is in an .opd section,
+ /* ppc64be-linux nasty hack: if the symbol is in an .opd section,
then really what we have is the address of a function
descriptor. So use the first word of that as the function's
text.
@@ -482,7 +482,8 @@
See thread starting at
http://gcc.gnu.org/ml/gcc-patches/2004-08/msg00557.html
*/
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
+ /* Host and guest may have different Endianess, used by BE only */
is_in_opd = False;
# endif
@@ -490,7 +491,7 @@
&& di->opd_size > 0
&& *sym_avma_out >= di->opd_avma
&& *sym_avma_out < di->opd_avma + di->opd_size) {
-# if !defined(VGP_ppc64_linux)
+# if !defined(VGP_ppc64be_linux)
if (TRACE_SYMTAB_ENABLED) {
HChar* sym_name = ML_(img_strdup)(escn_strtab->img,
"di.gesi.6", sym_name_ioff);
@@ -585,7 +586,7 @@
/* Here's yet another ppc64-linux hack. Get rid of leading dot if
the symbol is outside .opd. */
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
if (di->opd_size > 0
&& !is_in_opd
&& *sym_name_out_ioff != DiOffT_INVALID
@@ -669,7 +670,7 @@
}
}
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
/* It's crucial that we never add symbol addresses in the .opd
section. This would completely mess up function redirection and
intercepting. This assert ensures that any symbols that make it
@@ -693,7 +694,7 @@
struct _DebugInfo* di, const HChar* tab_name,
DiSlice* escn_symtab,
DiSlice* escn_strtab,
- DiSlice* escn_opd, /* ppc64-linux only */
+ DiSlice* escn_opd, /* ppc64be-linux only */
Bool symtab_in_debug
)
{
@@ -769,7 +770,7 @@
/* Read an ELF symbol table (normal or dynamic). This one is for
- ppc64-linux, which requires special treatment. */
+ ppc64be-linux, which requires special treatment. */
typedef
struct {
@@ -807,7 +808,7 @@
static
__attribute__((unused)) /* not referred to on all targets */
-void read_elf_symtab__ppc64_linux(
+void read_elf_symtab__ppc64be_linux(
struct _DebugInfo* di, const HChar* tab_name,
DiSlice* escn_symtab,
DiSlice* escn_strtab,
@@ -831,7 +832,7 @@
return;
}
- TRACE_SYMTAB("\n--- Reading (ELF, ppc64-linux) %s (%lld entries) ---\n",
+ TRACE_SYMTAB("\n--- Reading (ELF, ppc64be-linux) %s (%lld entries) ---\n",
tab_name, escn_symtab->szB/sizeof(ElfXX_Sym) );
oset = VG_(OSetGen_Create)( offsetof(TempSym,key),
@@ -2118,7 +2119,7 @@
BAD(".plt");
}
}
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/* Accept .plt where mapped as rw (data), or unmapped */
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrw && !di->plt_present) {
@@ -2275,7 +2276,7 @@
DiSlice dwarf1d_escn = DiSlice_INVALID; // .debug (dwarf1)
DiSlice dwarf1l_escn = DiSlice_INVALID; // .line (dwarf1)
DiSlice opd_escn = DiSlice_INVALID; // .opd (dwarf2,
- // ppc64-linux)
+ // ppc64be-linux)
DiSlice ehframe_escn[N_EHFRAME_SECTS]; // .eh_frame (dwarf2)
for (i = 0; i < N_EHFRAME_SECTS; i++)
@@ -2780,8 +2781,8 @@
void (*read_elf_symtab)(struct _DebugInfo*, const HChar*,
DiSlice*, DiSlice*, DiSlice*, Bool);
Bool symtab_in_debug;
-# if defined(VGP_ppc64_linux)
- read_elf_symtab = read_elf_symtab__ppc64_linux;
+# if defined(VGP_ppc64be_linux)
+ read_elf_symtab = read_elf_symtab__ppc64be_linux;
# else
read_elf_symtab = read_elf_symtab__normal;
# endif
@@ -2823,7 +2824,7 @@
seems OK though. Also skip on Android. */
# if !defined(VGP_amd64_linux) \
&& !defined(VGP_s390x_linux) \
- && !defined(VGP_ppc64_linux) \
+ && !defined(VGP_ppc64be_linux) \
&& !defined(VGPV_arm_linux_android) \
&& !defined(VGPV_x86_linux_android) \
&& !defined(VGP_mips64_linux)
Modified: trunk/coregrind/m_debuginfo/readmacho.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readmacho.c (original)
+++ trunk/coregrind/m_debuginfo/readmacho.c Thu Aug 7 23:17:29 2014
@@ -197,8 +197,8 @@
f++, arch_be_ioff += sizeof(struct fat_arch)) {
# if defined(VGA_ppc)
Int cputype = CPU_TYPE_POWERPC;
-# elif defined(VGA_ppc64)
- Int cputype = CPU_TYPE_POWERPC64;
+# elif defined(VGA_ppc64be)
+ Int cputype = CPU_TYPE_POWERPC64BE;
# elif defined(VGA_x86)
Int cputype = CPU_TYPE_X86;
# elif defined(VGA_amd64)
Modified: trunk/coregrind/m_debuginfo/storage.c
==============================================================================
--- trunk/coregrind/m_debuginfo/storage.c (original)
+++ trunk/coregrind/m_debuginfo/storage.c Thu Aug 7 23:17:29 2014
@@ -199,7 +199,7 @@
SHOW_HOW(si_m->r11_how, si_m->r11_off);
VG_(printf)(" R7=");
SHOW_HOW(si_m->r7_how, si_m->r7_off);
-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64be)
# elif defined(VGA_s390x) || defined(VGA_mips32) || defined(VGA_mips64)
VG_(printf)(" SP=");
SHOW_HOW(si_m->sp_how, si_m->sp_off);
Modified: trunk/coregrind/m_debuglog.c
==============================================================================
--- trunk/coregrind/m_debuglog.c (original)
+++ trunk/coregrind/m_debuglog.c Thu Aug 7 23:17:29 2014
@@ -189,7 +189,7 @@
return __res;
}
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
static UInt local_sys_write_stderr ( const HChar* buf, Int n )
{
Modified: trunk/coregrind/m_dispatch/dispatch-ppc64-linux.S
==============================================================================
--- trunk/coregrind/m_dispatch/dispatch-ppc64-linux.S (original)
+++ trunk/coregrind/m_dispatch/dispatch-ppc64-linux.S Thu Aug 7 23:17:29 2014
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-#if defined(VGP_ppc64_linux)
+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
#include "pub_core_basics_asm.h"
#include "pub_core_dispatch_asm.h"
@@ -193,7 +193,7 @@
/* 88(sp) used later to load fpscr with zero */
/* 48:87(sp) free */
- /* Linkage Area (reserved)
+ /* Linkage Area (reserved) BE ABI
40(sp) : TOC
32(sp) : link editor doubleword
24(sp) : compiler doubleword
@@ -530,7 +530,7 @@
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
-#endif // defined(VGP_ppc64_linux)
+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/*--------------------------------------------------------------------*/
/*--- end ---*/
Modified: trunk/coregrind/m_gdbserver/target.c
==============================================================================
--- trunk/coregrind/m_gdbserver/target.c (original)
+++ trunk/coregrind/m_gdbserver/target.c Thu Aug 7 23:17:29 2014
@@ -657,7 +657,7 @@
arm64_init_architecture(&the_low_target);
#elif defined(VGA_ppc32)
ppc32_init_architecture(&the_low_target);
-#elif defined(VGA_ppc64)
+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
ppc64_init_architecture(&the_low_target);
#elif defined(VGA_s390x)
s390x_init_architecture(&the_low_target);
Modified: trunk/coregrind/m_initimg/initimg-linux.c
==============================================================================
--- trunk/coregrind/m_initimg/initimg-linux.c (original)
+++ trunk/coregrind/m_initimg/initimg-linux.c Thu Aug 7 23:17:29 2014
@@ -366,7 +366,7 @@
sp++;
sp++;
-#if defined(VGA_ppc32) || defined(VGA_ppc64)
+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# if defined AT_IGNOREPPC
while (*sp == AT_IGNOREPPC) // skip AT_IGNOREPPC entries
sp += 2;
@@ -457,7 +457,8 @@
auxsize += sizeof(*cauxv);
}
-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
auxsize += 2 * sizeof(*cauxv);
# endif
@@ -614,7 +615,8 @@
// We do not take ULong* (as ULong 8 bytes on a 32 bits),
// => we take UWord*
-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
auxv[0].a_type = AT_IGNOREPPC;
auxv[0].u.a_val = AT_IGNOREPPC;
auxv[1].a_type = AT_IGNOREPPC;
@@ -707,7 +709,7 @@
"PPC32 icache line size %u (type %u)\n",
(UInt)auxv->u.a_val, (UInt)auxv->a_type );
}
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/* acquire cache info */
if (auxv->u.a_val > 0) {
VG_(machine_ppc64_set_clszB)( auxv->u.a_val );
@@ -718,7 +720,8 @@
# endif
break;
-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
case AT_IGNOREPPC:
break;
# endif
@@ -738,7 +741,8 @@
auxv->a_type = AT_IGNORE;
break;
-# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64_linux)
+# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64be_linux) \
+ && !defined(VGP_ppc64le_linux)
case AT_SYSINFO_EHDR: {
/* Trash this, because we don't reproduce it */
const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr);
@@ -1024,7 +1028,7 @@
arch->vex.guest_GPR1 = iifii.initial_client_SP;
arch->vex.guest_CIA = iifii.initial_client_IP;
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
vg_assert(0 == sizeof(VexGuestPPC64State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
Modified: trunk/coregrind/m_libcassert.c
==============================================================================
--- trunk/coregrind/m_libcassert.c (original)
+++ trunk/coregrind/m_libcassert.c Thu Aug 7 23:17:29 2014
@@ -98,7 +98,7 @@
(srP)->r_sp = (ULong)r1; \
(srP)->misc.PPC32.r_lr = lr; \
}
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
# define GET_STARTREGS(srP) \
{ ULong cia, r1, lr; \
__asm__ __volatile__( \
Modified: trunk/coregrind/m_libcfile.c
==============================================================================
--- trunk/coregrind/m_libcfile.c (original)
+++ trunk/coregrind/m_libcfile.c Thu Aug 7 23:17:29 2014
@@ -677,8 +677,8 @@
res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count,
0, 0, offset);
return res;
-# elif defined(VGP_amd64_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
+# elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_mips64_linux) \
|| defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset);
@@ -923,7 +923,8 @@
Int VG_(socket) ( Int domain, Int type, Int protocol )
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux)
SysRes res;
UWord args[3];
args[0] = domain;
@@ -963,7 +964,8 @@
Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen )
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux)
SysRes res;
UWord args[3];
args[0] = sockfd;
@@ -1002,7 +1004,8 @@
SIGPIPE */
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux)
SysRes res;
UWord args[4];
args[0] = sd;
@@ -1033,7 +1036,8 @@
Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux) \
|| defined(VGP_mips32_linux)
SysRes res;
UWord args[3];
@@ -1064,7 +1068,8 @@
Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux) \
|| defined(VGP_mips32_linux)
SysRes res;
UWord args[3];
@@ -1096,7 +1101,8 @@
Int *optlen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux)
SysRes res;
UWord args[5];
args[0] = sd;
@@ -1133,7 +1139,8 @@
Int optlen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux)
SysRes res;
UWord args[5];
args[0] = sd;
Modified: trunk/coregrind/m_libcproc.c
==============================================================================
--- trunk/coregrind/m_libcproc.c (original)
+++ trunk/coregrind/m_libcproc.c Thu Aug 7 23:17:29 2014
@@ -555,8 +555,8 @@
list[i] = (UInt)list16[i];
return sr_Res(sres);
-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
- || defined(VGP_arm_linux) \
+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGO_darwin) || defined(VGP_s390x_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_arm64_linux)
SysRes sres;
@@ -741,7 +741,7 @@
// If I-caches are coherent, nothing needs to be done here
if (vai.hwcache_info.icaches_maintain_coherence) return;
-# if defined(VGA_ppc32) || defined(VGA_ppc64)
+# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
Addr startaddr = (Addr) ptr;
Addr endaddr = startaddr + nbytes;
Addr cls;
Modified: trunk/coregrind/m_libcsetjmp.c
==============================================================================
--- trunk/coregrind/m_libcsetjmp.c (original)
+++ trunk/coregrind/m_libcsetjmp.c Thu Aug 7 23:17:29 2014
@@ -149,7 +149,7 @@
/* ------------ ppc64-linux ------------ */
-#if defined(VGP_ppc64_linux)
+#if defined(VGP_ppc64be_linux)
__asm__(
".section \".toc\",\"aw\"" "\n"
@@ -270,7 +270,7 @@
".previous" "\n"
);
-#endif /* VGP_ppc64_linux */
+#endif /* VGP_ppc64be_linux */
/* ------------ amd64-{linux,darwin} ------------ */
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Thu Aug 7 23:17:29 2014
@@ -81,7 +81,7 @@
regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_GPR1;
regs->misc.PPC32.r_lr
= VG_(threads)[tid].arch.vex.guest_LR;
-# elif defined(VGA_ppc64)
+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
regs->r_pc = VG_(threads)[tid].arch.vex.guest_CIA;
regs->r_sp = VG_(threads)[tid].arch.vex.guest_GPR1;
regs->misc.PPC64.r_lr
@@ -212,7 +212,7 @@
(*f)(tid, "R13", vex->guest_R13);
(*f)(tid, "R14", vex->guest_R14);
(*f)(tid, "R15", vex->guest_R15);
-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
(*f)(tid, "GPR0" , vex->guest_GPR0 );
(*f)(tid, "GPR1" , vex->guest_GPR1 );
(*f)(tid, "GPR2" , vex->guest_GPR2 );
@@ -442,7 +442,7 @@
UInt VG_(machine_ppc32_has_FP) = 0;
UInt VG_(machine_ppc32_has_VMX) = 0;
#endif
-#if defined(VGA_ppc64)
+#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
ULong VG_(machine_ppc64_has_VMX) = 0;
#endif
#if defined(VGA_arm)
@@ -452,7 +452,7 @@
/* For hwcaps detection on ppc32/64, s390x, and arm we'll need to do SIGILL
testing, so we need a VG_MINIMAL_JMP_BUF. */
-#if defined(VGA_ppc32) || defined(VGA_ppc64) \
+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
|| defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32)
#include "pub_core_libcsetjmp.h"
static VG_MINIMAL_JMP_BUF(env_unsup_insn);
@@ -470,7 +470,7 @@
* Not very defensive: assumes that as long as the dcbz/dcbzl
* instructions don't raise a SIGILL, that they will zero an aligned,
* contiguous block of memory of a sensible size. */
-#if defined(VGA_ppc32) || defined(VGA_ppc64)
+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
static void find_ppc_dcbz_sz(VexArchInfo *arch_info)
{
Int dcbz_szB = 0;
@@ -523,7 +523,7 @@
dcbz_szB, dcbzl_szB);
# undef MAX_DCBZL_SZB
}
-#endif /* defined(VGA_ppc32) || defined(VGA_ppc64) */
+#endif /* defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) */
#ifdef VGA_s390x
@@ -1067,7 +1067,7 @@
return True;
}
-#elif defined(VGA_ppc64)
+#elif defined(VGA_ppc64be)|| defined(VGA_ppc64le)
{
/* Same instruction set detection algorithm as for ppc32. */
vki_sigset_t saved_set, tmp_set;
@@ -1181,7 +1181,7 @@
(Int)have_F, (Int)have_V, (Int)have_FX,
(Int)have_GX, (Int)have_VX, (Int)have_DFP,
(Int)have_isa_2_07);
- /* on ppc64, if we don't even have FP, just give up. */
+ /* on ppc64be, if we don't even have FP, just give up. */
if (!have_F)
return False;
@@ -1624,7 +1624,7 @@
/* Notify host cpu instruction cache line size. */
-#if defined(VGA_ppc64)
+#if defined(VGA_ppc64be)|| defined(VGA_ppc64le)
void VG_(machine_ppc64_set_clszB)( Int szB )
{
vg_assert(hwcaps_done);
@@ -1706,7 +1706,7 @@
if (vai.hwcaps & VEX_HWCAPS_PPC32_DFP) return 16;
return 8;
-# elif defined(VGA_ppc64)
+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* 8 if boring; 16 if signs of Altivec or other exotic stuff */
if (vai.hwcaps & VEX_HWCAPS_PPC64_V) return 16;
if (vai.hwcaps & VEX_HWCAPS_PPC64_VX) return 16;
@@ -1744,12 +1744,12 @@
void* VG_(fnptr_to_fnentry)( void* f )
{
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
- || defined(VGP_arm_linux) \
- || defined(VGP_ppc32_linux) || defined(VGO_darwin) \
+ || defined(VGP_arm_linux) || defined(VGO_darwin) \
+ || defined(VGP_ppc32_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
|| defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
return f;
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux)
/* ppc64-linux uses the AIX scheme, in which f is a pointer to a
3-word function descriptor, of which the first word is the entry
address. */
Modified: trunk/coregrind/m_main.c
==============================================================================
--- trunk/coregrind/m_main.c (original)
+++ trunk/coregrind/m_main.c Thu Aug 7 23:17:29 2014
@@ -2024,7 +2024,8 @@
# if defined(VGP_x86_linux)
iters = 10;
-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux)
+# elif defined(VGP_amd64_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
iters = 10;
# elif defined(VGP_ppc32_linux)
iters = 5;
@@ -2603,7 +2604,7 @@
static void final_tidyup(ThreadId tid)
{
#if !defined(VGO_darwin)
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
Addr r2;
# endif
Addr __libc_freeres_wrapper = VG_(client___libc_freeres_wrapper);
@@ -2615,7 +2616,7 @@
0 == __libc_freeres_wrapper )
return; /* can't/won't do it */
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
r2 = VG_(get_tocptr)( __libc_freeres_wrapper );
if (r2 == 0) {
VG_(message)(Vg_UserMsg,
@@ -2633,12 +2634,12 @@
"Caught __NR_exit; running __libc_freeres()\n");
/* set thread context to point to libc_freeres_wrapper */
- /* ppc64-linux note: __libc_freeres_wrapper gives us the real
+ /* ppc64be-linux note: __libc_freeres_wrapper gives us the real
function entry point, not a fn descriptor, so can use it
directly. However, we need to set R2 (the toc pointer)
appropriately. */
VG_(set_IP)(tid, __libc_freeres_wrapper);
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux)
VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
# endif
/* mips-linux note: we need to set t9 */
@@ -2835,7 +2836,7 @@
"\ttrap\n"
".previous\n"
);
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux)
asm("\n"
/* PPC64 ELF ABI says '_start' points to a function descriptor.
So we must have one, and that is what goes into the .opd section. */
@@ -3094,10 +3095,10 @@
the_iicii.sp_at_startup = (Addr)pArgc;
-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
- || defined(VGP_arm64_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux)
{
- /* ppc/ppc64 can be configured with different page sizes.
+ /* ppc32/ppc64 can be configured with different page sizes.
Determine this early. This is an ugly hack and really should
be moved into valgrind_main. */
UWord *sp = &pArgc[1+argc+1];
Modified: trunk/coregrind/m_redir.c
==============================================================================
--- trunk/coregrind/m_redir.c (original)
+++ trunk/coregrind/m_redir.c Thu Aug 7 23:17:29 2014
@@ -1278,7 +1278,7 @@
);
}
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux)
/* If we're using memcheck, use these intercepts right from
the start, otherwise ld.so makes a lot of noise. */
if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
Modified: trunk/coregrind/m_scheduler/scheduler.c
==============================================================================
--- trunk/coregrind/m_scheduler/scheduler.c (original)
+++ trunk/coregrind/m_scheduler/scheduler.c Thu Aug 7 23:17:29 2014
@@ -768,7 +768,7 @@
vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_RIP)));
# endif
-# if defined(VGA_ppc32) || defined(VGA_ppc64)
+# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* ppc guest_state vector regs must be 16 byte aligned for
loads/stores. This is important! */
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VSR0));
@@ -1622,7 +1622,7 @@
#elif defined(VGA_amd64)
# define VG_CLREQ_ARGS guest_RAX
# define VG_CLREQ_RET guest_RDX
-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# define VG_CLREQ_ARGS guest_GPR4
# define VG_CLREQ_RET guest_GPR3
#elif defined(VGA_arm)
Modified: trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c
==============================================================================
--- trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c (original)
+++ trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c Thu Aug 7 23:17:29 2014
@@ -31,7 +31,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-#if defined(VGP_ppc64_linux)
+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
#include "pub_core_basics.h"
#include "pub_core_vki.h"
@@ -388,7 +388,7 @@
VG_TRACK( post_deliver_signal, tid, sigNo );
}
-#endif // defined(VGP_ppc64_linux)
+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/*--------------------------------------------------------------------*/
/*--- end ---*/
Modified: trunk/coregrind/m_signals.c
==============================================================================
--- trunk/coregrind/m_signals.c (original)
+++ trunk/coregrind/m_signals.c Thu Aug 7 23:17:29 2014
@@ -348,7 +348,7 @@
(srP)->misc.PPC32.r_lr = (uc)->uc_regs->mc_gregs[VKI_PT_LNK]; \
}
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
# define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_NIP])
# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1])
/* Dubious hack: if there is an error, only consider the lowest 8
@@ -851,7 +851,7 @@
" sc\n" \
".previous\n"
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux)
# define _MY_SIGRETURN(name) \
".align 2\n" \
".globl my_sigreturn\n" \
Modified: trunk/coregrind/m_stacktrace.c
==============================================================================
--- trunk/coregrind/m_stacktrace.c (original)
+++ trunk/coregrind/m_stacktrace.c Thu Aug 7 23:17:29 2014
@@ -622,7 +622,8 @@
/* -----------------------ppc32/64 ---------------------- */
-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
/*OUT*/Addr* ips, UInt max_n_ips,
@@ -631,7 +632,7 @@
Addr fp_max_orig )
{
Bool lr_is_first_RA = False;
-# if defined(VG_PLAT_USES_PPCTOC)
+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
Word redir_stack_size = 0;
Word redirs_used = 0;
# endif
@@ -650,7 +651,7 @@
Addr fp = sp;
# if defined(VGP_ppc32_linux)
Addr lr = startRegs->misc.PPC32.r_lr;
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
Addr lr = startRegs->misc.PPC64.r_lr;
# endif
Addr fp_min = sp;
@@ -686,7 +687,7 @@
/* fp is %r1. ip is %cia. Note, ppc uses r1 as both the stack and
frame pointers. */
-# if defined(VGP_ppc64_linux)
+# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
redir_stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE;
redirs_used = 0;
# endif
@@ -742,7 +743,7 @@
/* On ppc64-linux (ppc64-elf, really), the lr save
slot is 2 words back from sp, whereas on ppc32-elf(?) it's
only one word back. */
-# if defined(VG_PLAT_USES_PPCTOC)
+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
const Int lr_offset = 2;
# else
const Int lr_offset = 1;
@@ -761,7 +762,7 @@
else
ip = (((UWord*)fp)[lr_offset]);
-# if defined(VG_PLAT_USES_PPCTOC)
+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
/* Nasty hack to do with function replacement/wrapping on
ppc64-linux. If LR points to our magic return stub,
then we are in a wrapped or intercepted function, in
Modified: trunk/coregrind/m_syscall.c
==============================================================================
--- trunk/coregrind/m_syscall.c (original)
+++ trunk/coregrind/m_syscall.c Thu Aug 7 23:17:29 2014
@@ -386,7 +386,7 @@
".previous\n"
);
-#elif defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc64be_linux)
/* Due to the need to return 65 bits of result, this is completely
different from the ppc32 case. The single arg register points to a
7-word block containing the syscall # and the 6 args. The syscall
@@ -720,7 +720,7 @@
UInt cr0so = (UInt)(ret);
return VG_(mk_SysRes_ppc32_linux)( val, cr0so );
-# elif defined(VGP_ppc64_linux)
+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
ULong argblock[7];
argblock[0] = sysno;
argblock[1] = a1;
Modified: trunk/coregrind/m_syswrap/priv_types_n_macros.h
==============================================================================
--- trunk/coregrind/m_syswrap/priv_types_n_macros.h (original)
+++ trunk/coregrind/m_syswrap/priv_types_n_macros.h Thu Aug 7 23:17:29 2014
@@ -90,7 +90,8 @@
// field names), the s_arg value is the offset from the stack pointer.
Int o_sysno;
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
- || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+ || defined(VGP_ppc32_linux) \
+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_arm_linux) || defined(VGP_s390x_linux) \
|| defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
Int o_arg1;
Modified: trunk/coregrind/m_syswrap/syscall-ppc64-linux.S
==============================================================================
--- trunk/coregrind/m_syswrap/syscall-ppc64-linux.S (original)
+++ trunk/coregrind/m_syswrap/syscall-ppc64-linux.S Thu Aug 7 23:17:29 2014
@@ -27,7 +27,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-#if defined(VGP_ppc64_linux)
+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
#include "pub_core_basics_asm.h"
#include "pub_core_vkiscnums_asm.h"
@@ -165,7 +165,7 @@
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
-#endif // defined(VGP_ppc64_linux)
+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
/*--------------------------------------------------------------------*/
/*--- end ---*/
Modified: trunk/coregrind/m_syswrap/syswrap-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-linux.c Thu Aug 7 23:17:29 2014
@@ -244,7 +244,8 @@
: "n" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
: "rax", "rdi"
);
-#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
+ || defined(VGP_ppc64le_linux)
{ UInt vgts_empty = (UInt)VgTs_Empty;
asm volatile (
"stw %1,%0\n\t" /* set tst->status = VgTs_Empty */
@@ -385,7 +386,7 @@
sp -= 16;
sp &= ~0xF;
*(UWord *)sp = 0;
-#elif defined(VGP_ppc64_linux)
+#eli...
[truncated message content] |
|
From: Petar J. <mip...@gm...> - 2014-08-07 17:20:07
|
Hi Sasi, Support for Cavium specific extensions in Valgrind is not complete today. If you want to use Valgrind on a Cavium board, I suggest you put vanilla MIPS64 rootfs and build Valgrind with a standard GCC for MIPS64. That environment has been tested and has no known issues (so far). However, if you still want to stick with Cavium specific toolchain and rootfs, be aware that you are likely to come across issues specific to Cavium extensions that are - as I previously said - not fully supported yet. In that case, I suggest you: 1. create a Bugzilla issue [1] and report your findings, 2. be able to provide feedback and - wait till the issue is fixed. That would be all. Regards, Petar [1] KDE Bugzilla, https://bugs.kde.org/ On Thu, Aug 7, 2014 at 10:26 AM, Sasikanth babu <sas...@gm...> wrote: > Hi all, > > I had checked-out latest valgrind code from svn repo and cross-compiled > it for octeon. Looks the instruction errors seems fixed but I still > see the following issue. And Libc has the debugging symbols. > > /lib64/libc-2.11.1.so: ELF 64-bit MSB shared object, MIPS, MIPS64 rel2 > version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux > 2.6.34, not stripped > > Any suggestions? > > valgrind --run-libc-freeres=no ./a.out 1 > ==1409== Memcheck, a memory error detector > ==1409== Copyright (C) 2002-2013, and GNU GPL'd, by Julian Seward et al. > ==1409== Using Valgrind-3.10.0.SVN and LibVEX; rerun with -h for copyright > info > ==1409== Command: ./a.out 1 > ==1409== > 1409: > ==1409== > ==1409== Process terminating with default action of signal 11 (SIGSEGV) > ==1409== Access not within mapped region at address 0x50 > ==1409== at 0x400D148: _dl_relocate_object (dl-machine.h:713) > ==1409== by 0x4004B50: dl_main (rtld.c:2227) > ==1409== by 0x4019188: _dl_sysdep_start (dl-sysdep.c:243) > ==1409== by 0x40021A4: _dl_start_final (rtld.c:333) > ==1409== by 0x40023E4: _dl_start (rtld.c:561) > ==1409== by 0x4001C0C: __start (in /lib64/ld-2.11.1.so) > ==1409== If you believe this happened as a result of a stack > ==1409== overflow in your program's main thread (unlikely but > ==1409== possible), you can try to increase the size of the > ==1409== main thread stack using the --main-stacksize= flag. > ==1409== The main thread stack size used in this run was 8388608. > ==1409== > ==1409== HEAP SUMMARY: > ==1409== in use at exit: 0 bytes in 0 blocks > ==1409== total heap usage: 0 allocs, 0 frees, 0 bytes allocated > ==1409== > ==1409== All heap blocks were freed -- no leaks are possible > ==1409== > ==1409== For counts of detected and suppressed errors, rerun with: -v > ==1409== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 4 from 4) > Segmentation fault > > > > ------------------------------------------------------------------------------ > Infragistics Professional > Build stunning WinForms apps today! > Reboot your WinForms applications with our WinForms controls. > Build a bridge from your legacy apps to the future. > > http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > > |
|
From: Sasikanth b. <sas...@gm...> - 2014-08-07 08:26:31
|
Hi all,
I had checked-out latest valgrind code from svn repo and cross-compiled
it for octeon. Looks the instruction errors seems fixed but I still
see the following issue. And Libc has the debugging symbols.
/lib64/libc-2.11.1.so: ELF 64-bit MSB shared object, MIPS, MIPS64 rel2
version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux
2.6.34, not stripped
Any suggestions?
valgrind --run-libc-freeres=no ./a.out 1
==1409== Memcheck, a memory error detector
==1409== Copyright (C) 2002-2013, and GNU GPL'd, by Julian Seward et al.
==1409== Using Valgrind-3.10.0.SVN and LibVEX; rerun with -h for copyright
info
==1409== Command: ./a.out 1
==1409==
1409:
==1409==
==1409== Process terminating with default action of signal 11 (SIGSEGV)
==1409== Access not within mapped region at address 0x50
==1409== at 0x400D148: _dl_relocate_object (dl-machine.h:713)
==1409== by 0x4004B50: dl_main (rtld.c:2227)
==1409== by 0x4019188: _dl_sysdep_start (dl-sysdep.c:243)
==1409== by 0x40021A4: _dl_start_final (rtld.c:333)
==1409== by 0x40023E4: _dl_start (rtld.c:561)
==1409== by 0x4001C0C: __start (in /lib64/ld-2.11.1.so)
==1409== If you believe this happened as a result of a stack
==1409== overflow in your program's main thread (unlikely but
==1409== possible), you can try to increase the size of the
==1409== main thread stack using the --main-stacksize= flag.
==1409== The main thread stack size used in this run was 8388608.
==1409==
==1409== HEAP SUMMARY:
==1409== in use at exit: 0 bytes in 0 blocks
==1409== total heap usage: 0 allocs, 0 frees, 0 bytes allocated
==1409==
==1409== All heap blocks were freed -- no leaks are possible
==1409==
==1409== For counts of detected and suppressed errors, rerun with: -v
==1409== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 4 from 4)
Segmentation fault
|
|
From: Rich C. <rc...@wi...> - 2014-08-07 05:03:07
|
valgrind revision: 14237
VEX revision: 2913
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-08-06 19:22:01 CDT
Ended at 2014-08-07 00:02:57 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 607 tests, 6 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
memcheck/tests/vbit-test/vbit-test (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
--tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old
+ perl perf/vg_perf --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old perf
-- Running tests in perf ----------------------------------------------
-- bigcode1 --
bigcode1 valgrind-new:0.48s no: 7.8s (16.3x, -----) me:15.0s (31.3x, -----) ca:61.1s (127.3x, -----) he: 8.9s (18.6x, -----) ca:25.5s (53.2x, -----) dr: 8.7s (18.2x, -----) ma: 9.1s (19.0x, -----)
bigcode1 valgrind-old:0.48s no: 7.8s (16.3x, 0.1%) me:15.1s (31.4x, -0.1%) ca:61.1s (127.4x, -0.0%) he: 8.9s (18.6x, -0.4%) ca:25.5s (53.1x, 0.0%) dr: 8.8s (18.2x, -0.1%) ma: 9.1s (19.0x, 0.1%)
-- bigcode2 --
bigcode2 valgrind-new:0.49s no:18.7s (38.2x, -----) me:38.5s (78.6x, -----) ca:105.2s (214.6x, -----) he:22.4s (45.6x, -----) ca:40.9s (83.4x, -----) dr:21.3s (43.4x, -----) ma:21.6s (44.0x, -----)
bigcode2 valgrind-old:0.49s no:18.7s (38.1x, 0.2%) me:38.6s (78.9x, -0.3%) ca:105.2s (214.8x, -0.1%) he:22.5s (45.9x, -0.6%) ca:40.8s (83.3x, 0.1%) dr:21.3s (43.5x, -0.1%) ma:21.6s (44.0x, 0.0%)
-- bz2 --
bz2 valgrind-new:2.32s no:10.2s ( 4.4x, -----) me:27.2s (11.7x, -----) ca:59.6s (25.7x, -----) he:40.3s (17.4x, -----) ca:75.4s (32.5x, -----) dr:57.9s (25.0x, -----) ma: 9.8s ( 4.2x, -----)
bz2 valgrind-old:2.32s no:10.2s ( 4.4x, -0.5%) me:27.3s (11.8x, -0.1%) ca:59.6s (25.7x, -0.0%) he:40.3s (17.4x, 0.1%) ca:75.5s (32.5x, -0.0%) dr:57.9s (25.0x, 0.1%) ma: 9.8s ( 4.2x, -0.1%)
-- fbench --
fbench valgrind-new:1.44s no: 5.4s ( 3.8x, -----) me:17.9s (12.4x, -----) ca:26.6s (18.4x, -----) he:13.0s ( 9.0x, -----) ca:21.5s (14.9x, -----) dr:12.9s ( 9.0x, -----) ma: 5.6s ( 3.9x, -----)
fbench valgrind-old:1.44s no: 5.4s ( 3.8x, 0.0%) me:17.9s (12.4x, 0.2%) ca:27.0s (18.8x, -1.7%) he:13.0s ( 9.1x, -0.2%) ca:21.6s (15.0x, -0.2%) dr:12.9s ( 9.0x, 0.0%) ma: 5.6s ( 3.9x, -0.2%)
-- ffbench --
ffbench valgrind-new:1.00s no: 3.7s ( 3.7x, -----) me:12.1s (12.1x, -----) ca: 8.2s ( 8.2x, -----) he:21.3s (21.3x, -----) ca:27.6s (27.6x, -----) dr:17.1s (17.1x, -----) ma: 3.7s ( 3.7x, -----)
ffbench valgrind-old:1.00s no: 3.7s ( 3.7x, 0.3%) me:12.1s (12.1x, -0.1%) ca: 8.2s ( 8.2x, 0.0%) he:21.4s (21.4x, -0.3%) ca:27.6s (27.6x, 0.0%) dr:17.1s (17.1x, 0.1%) ma: 3.7s ( 3.7x, -0.3%)
-- heap --
heap valgrind-new:0.41s no: 3.3s ( 8.1x, -----) me:21.7s (52.9x, -----) ca:31.0s (75.6x, -----) he:30.6s (74.7x, -----) ca:22.9s (55.9x, -----) dr:19.9s (48.5x, -----) ma:21.9s (53.5x, -----)
heap valgrind-old:0.41s no: 3.3s ( 8.1x, 0.3%) me:21.8s (53.0x, -0.2%) ca:31.0s (75.5x, 0.1%) he:30.8s (75.2x, -0.6%) ca:22.9s (55.9x, 0.0%) dr:19.9s (48.4x, 0.2%) ma:22.2s (54.2x, -1.4%)
-- heap_pdb4 --
heap_pdb4 valgrind-new:0.55s no: 3.6s ( 6.6x, -----) me:41.4s (75.3x, -----) ca:33.7s (61.2x, -----) he:35.8s (65.2x, -----) ca:24.7s (45.0x, -----) dr:22.4s (40.7x, -----) ma:23.4s (42.5x, -----)
heap_pdb4 valgrind-old:0.55s no: 3.6s ( 6.6x, 0.3%) me:41.5s (75.5x, -0.2%) ca:33.7s (61.2x, 0.1%) he:35.9s (65.3x, -0.3%) ca:24.7s (45.0x, 0.0%) dr:22.3s (40.6x, 0.1%) ma:23.5s (42.8x, -0.7%)
-- many-loss-records --
many-loss-records valgrind-new:0.05s no: 1.2s (25.0x, -----) me: 5.8s (116.2x, -----) ca: 5.1s (102.0x, -----) he: 5.2s (104.6x, -----) ca: 4.1s (81.4x, -----) dr: 4.7s (93.0x, -----) ma: 4.7s (93.6x, -----)
many-loss-records valgrind-old:0.05s no: 1.2s (24.8x, 0.8%) me: 5.8s (116.4x, -0.2%) ca: 5.1s (101.8x, 0.2%) he: 5.3s (105.2x, -0.6%) ca: 4.1s (81.2x, 0.2%) dr: 4.7s (93.2x, -0.2%) ma: 4.7s (93.8x, -0.2%)
-- many-xpts --
many-xpts valgrind-new:0.15s no: 1.6s (10.3x, -----) me: 7.2s (48.1x, -----) ca:12.9s (86.3x, -----) he:10.1s (67.1x, -----) ca: 5.8s (38.9x, -----) dr: 6.2s (41.3x, -----) ma: 7.4s (49.5x, -----)
many-xpts valgrind-old:0.15s no: 1.5s (10.3x, 0.6%) me: 7.2s (48.2x, -0.1%) ca:13.0s (86.5x, -0.2%) he:10.1s (67.3x, -0.2%) ca: 5.8s (38.9x, -0.2%) dr: 6.2s (41.3x, -0.2%) ma: 7.4s (49.5x, 0.0%)
-- sarp --
sarp valgrind-new:0.10s no: 1.5s (14.8x, -----) me: 8.8s (87.6x, -----) ca: 8.4s (84.0x, -----) he:30.7s (307.2x, -----) ca: 5.6s (55.8x, -----) dr: 4.1s (40.8x, -----) ma: 1.5s (15.4x, -----)
sarp valgrind-old:0.10s no: 1.5s (14.7x, 0.7%) me: 8.8s (87.5x, 0.1%) ca: 8.4s (84.1x, -0.1%) he:30.5s (304.9x, 0.7%) ca: 5.6s (55.7x, 0.2%) dr: 4.1s (40.7x, 0.2%) ma: 1.5s (15.4x, 0.0%)
-- tinycc --
tinycc valgrind-new:0.76s no: 7.6s (10.0x, -----) me:37.6s (49.5x, -----) ca:47.5s (62.5x, -----) he:45.5s (59.9x, -----) ca:45.0s (59.2x, -----) dr:38.4s (50.6x, -----) ma:12.1s (15.9x, -----)
tinycc valgrind-old:0.76s no: 7.6s (10.0x, 0.1%) me:37.6s (49.5x, -0.1%) ca:47.5s (62.5x, -0.0%) he:45.5s (59.9x, -0.1%) ca:45.0s (59.2x, 0.0%) dr:38.4s (50.5x, 0.1%) ma:12.1s (15.9x, 0.0%)
-- Finished tests in perf ----------------------------------------------
== 11 programs, 154 timings =================
real 162m3.143s
user 160m8.473s
sys 1m48.467s
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-08-06 20:21:49.306585201 -0500
+++ hackedbz2.stderr.out 2014-08-06 21:19:44.161463762 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-08-06 20:21:19.223242170 -0500
+++ err_disable3.stderr.out 2014-08-06 20:40:40.437459808 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-08-06 20:21:21.015262608 -0500
+++ err_disable4.stderr.out 2014-08-06 20:40:44.732508609 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-08-06 20:21:21.048262984 -0500
+++ threadname.stderr.out 2014-08-06 20:46:51.554674487 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-08-06 20:21:19.255242535 -0500
+++ threadname_xml.stderr.out 2014-08-06 20:46:53.601697723 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-new/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-08-06 20:21:22.827283274 -0500
+++ vbit-test.stderr.out 2014-08-06 20:49:01.101144734 -0500
@@ -0,0 +1 @@
+unknown opcode 5918
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-08-06 19:22:40.279420610 -0500
+++ hackedbz2.stderr.out 2014-08-06 20:19:54.588276708 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-08-06 19:22:31.392321426 -0500
+++ err_disable3.stderr.out 2014-08-06 19:41:00.662801115 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-08-06 19:22:31.834326359 -0500
+++ err_disable4.stderr.out 2014-08-06 19:41:05.037850322 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-08-06 19:22:31.868326738 -0500
+++ threadname.stderr.out 2014-08-06 19:47:10.096953682 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-08-06 19:22:31.429321839 -0500
+++ threadname_xml.stderr.out 2014-08-06 19:47:12.143976677 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/memcheck/tests/vbit-test/vbit-test.stderr.diff
=================================================
--- vbit-test.stderr.exp 2014-08-06 19:22:28.692291292 -0500
+++ vbit-test.stderr.out 2014-08-06 19:49:19.500407023 -0500
@@ -0,0 +1 @@
+unknown opcode 5918
|
|
From: Christian B. <bor...@de...> - 2014-08-07 04:11:57
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.31-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-08-07 03:45:01 CEST Ended at 2014-08-07 06:11:42 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 657 tests, 4 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 5.0s (21.7x, -----) me: 6.3s (27.3x, -----) ca:26.6s (115.5x, -----) he: 5.5s (23.9x, -----) ca: 9.1s (39.7x, -----) dr: 4.9s (21.3x, -----) ma: 3.9s (17.1x, -----) bigcode1 valgrind-old:0.23s no: 4.9s (21.1x, 2.8%) me: 6.3s (27.4x, -0.5%) ca:26.5s (115.3x, 0.2%) he: 5.5s (23.9x, -0.2%) ca: 9.2s (39.9x, -0.4%) dr: 4.8s (21.0x, 1.4%) ma: 3.9s (17.1x, 0.3%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.8s (32.7x, -----) me:13.1s (54.7x, -----) ca:39.9s (166.1x, -----) he:10.6s (44.0x, -----) ca:14.2s (59.2x, -----) dr: 9.0s (37.3x, -----) ma: 7.5s (31.2x, -----) bigcode2 valgrind-old:0.24s no: 7.9s (33.0x, -1.1%) me:13.3s (55.4x, -1.2%) ca:39.5s (164.7x, 0.9%) he:10.7s (44.6x, -1.2%) ca:14.3s (59.6x, -0.7%) dr: 9.0s (37.5x, -0.3%) ma: 7.3s (30.6x, 1.9%) -- bz2 -- bz2 valgrind-new:0.70s no: 6.7s ( 9.5x, -----) me:12.8s (18.2x, -----) ca:30.7s (43.9x, -----) he:19.9s (28.4x, -----) ca:34.3s (49.0x, -----) dr:29.9s (42.8x, -----) ma: 4.2s ( 6.0x, -----) bz2 valgrind-old:0.70s no: 6.6s ( 9.5x, 0.2%) me:12.7s (18.2x, 0.1%) ca:30.8s (43.9x, -0.0%) he:19.9s (28.4x, 0.0%) ca:34.3s (49.0x, 0.0%) dr:29.5s (42.2x, 1.3%) ma: 4.2s ( 5.9x, 1.9%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 4.0x, -----) me: 4.3s (10.4x, -----) ca: 9.4s (22.9x, -----) he: 6.3s (15.3x, -----) ca: 7.2s (17.7x, -----) dr: 5.6s (13.7x, -----) ma: 1.6s ( 4.0x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, 0.6%) me: 4.3s (10.5x, -0.2%) ca: 9.3s (22.8x, 0.4%) he: 6.3s (15.3x, 0.2%) ca: 7.2s (17.7x, 0.0%) dr: 5.6s (13.6x, 0.7%) ma: 1.6s ( 4.0x, 0.0%) -- ffbench -- ffbench valgrind-new:0.21s no: 1.2s ( 5.7x, -----) me: 3.0s (14.1x, -----) ca: 3.0s (14.4x, -----) he:44.5s (211.9x, -----) ca: 9.6s (45.8x, -----) dr: 6.9s (33.0x, -----) ma: 1.0s ( 4.6x, -----) ffbench valgrind-old:0.21s no: 1.2s ( 5.6x, 0.8%) me: 3.0s (14.1x, -0.3%) ca: 3.0s (14.4x, 0.0%) he:44.5s (212.0x, -0.1%) ca: 9.7s (46.1x, -0.8%) dr: 6.9s (33.0x, -0.1%) ma: 1.0s ( 4.6x, 0.0%) -- heap -- heap valgrind-new:0.23s no: 2.4s (10.3x, -----) me: 8.8s (38.2x, -----) ca:13.3s (57.7x, -----) he:13.1s (56.8x, -----) ca:11.4s (49.7x, -----) dr: 7.9s (34.2x, -----) ma: 8.0s (34.7x, -----) heap valgrind-old:0.23s no: 2.4s (10.3x, 0.8%) me: 9.0s (39.2x, -2.5%) ca:13.2s (57.5x, 0.3%) he:12.9s (56.2x, 1.0%) ca:11.4s (49.7x, -0.1%) dr: 7.8s (34.1x, 0.3%) ma: 8.1s (35.0x, -0.9%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.6s (11.9x, -----) me:13.0s (59.2x, -----) ca:14.4s (65.4x, -----) he:14.4s (65.4x, -----) ca:12.5s (56.7x, -----) dr: 9.1s (41.5x, -----) ma: 8.1s (37.0x, -----) heap_pdb4 valgrind-old:0.22s no: 2.6s (11.9x, 0.4%) me:13.3s (60.5x, -2.1%) ca:14.3s (65.2x, 0.3%) he:14.4s (65.6x, -0.3%) ca:12.4s (56.5x, 0.2%) dr: 8.8s (40.2x, 3.2%) ma: 8.2s (37.4x, -1.2%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (27.0x, -----) me: 2.1s (105.0x, -----) ca: 2.0s (98.0x, -----) he: 2.1s (107.5x, -----) ca: 1.9s (96.0x, -----) dr: 1.8s (87.5x, -----) ma: 1.7s (83.0x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (26.5x, 1.9%) me: 2.1s (107.5x, -2.4%) ca: 1.9s (97.0x, 1.0%) he: 2.2s (108.0x, -0.5%) ca: 1.9s (96.0x, 0.0%) dr: 1.8s (87.5x, 0.0%) ma: 1.7s (83.5x, -0.6%) -- many-xpts -- many-xpts valgrind-new:0.07s no: 0.7s ( 9.9x, -----) me: 3.1s (45.0x, -----) ca:373.9s (5341.3x, -----) he: 6.6s (94.0x, -----) ca: 2.8s (40.1x, -----) dr: 2.5s (36.0x, -----) ma: 2.6s (36.9x, -----) many-xpts valgrind-old:0.07s no: 0.7s ( 9.7x, 1.4%) me: 3.2s (45.7x, -1.6%) ca:372.7s (5324.1x, 0.3%) he: 6.6s (94.4x, -0.5%) ca: 2.8s (40.0x, 0.4%) dr: 2.5s (35.9x, 0.4%) ma: 2.6s (37.3x, -1.2%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (20.3x, -----) me: 3.5s (115.3x, -----) ca: 3.1s (105.0x, -----) he:17.2s (574.0x, -----) ca: 2.0s (68.3x, -----) dr: 1.4s (45.0x, -----) ma: 0.5s (16.0x, -----) sarp valgrind-old:0.03s no: 0.6s (20.7x, -1.6%) me: 3.5s (115.7x, -0.3%) ca: 3.2s (107.0x, -1.9%) he:17.6s (587.3x, -2.3%) ca: 2.0s (68.0x, 0.5%) dr: 1.4s (45.0x, 0.0%) ma: 0.5s (16.3x, -2.1%) -- tinycc -- tinycc valgrind-new:0.22s no: 3.2s (14.4x, -----) me:14.6s (66.4x, -----) ca:30.2s (137.2x, -----) he:28.1s (127.9x, -----) ca:21.3s (96.7x, -----) dr:20.8s (94.7x, -----) ma: 3.9s (17.7x, -----) tinycc valgrind-old:0.22s no: 3.2s (14.4x, 0.3%) me:14.6s (66.4x, -0.1%) ca:30.0s (136.3x, 0.6%) he:28.1s (127.7x, 0.1%) ca:21.3s (96.7x, 0.0%) dr:20.7s (94.2x, 0.5%) ma: 4.0s (18.1x, -2.6%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 112m57.857s user 111m59.784s sys 0m45.223s |
|
From: Tom H. <to...@co...> - 2014-08-07 03:30:46
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-08-07 03:22:49 BST Ended at 2014-08-07 04:30:30 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 660 tests, 3 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) none/tests/amd64/sse4-64 (stdout) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.7s (15.7x, -----) me: 3.3s (30.4x, -----) ca:14.0s (127.5x, -----) he: 2.0s (18.1x, -----) ca: 4.4s (39.8x, -----) dr: 1.9s (17.6x, -----) ma: 2.0s (18.2x, -----) bigcode1 valgrind-old:0.11s no: 1.7s (15.6x, 0.6%) me: 3.3s (30.2x, 0.6%) ca:14.0s (127.5x, -0.1%) he: 2.0s (18.2x, -0.5%) ca: 4.4s (39.8x, 0.0%) dr: 1.9s (17.6x, 0.0%) ma: 2.0s (18.5x, -1.5%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 4.3s (39.2x, -----) me: 8.9s (81.1x, -----) ca:26.6s (242.3x, -----) he: 5.2s (47.4x, -----) ca: 8.1s (73.6x, -----) dr: 4.8s (44.1x, -----) ma: 4.8s (43.8x, -----) bigcode2 valgrind-old:0.11s no: 4.3s (38.8x, 0.9%) me: 8.9s (81.1x, 0.0%) ca:25.6s (232.5x, 4.1%) he: 5.2s (47.2x, 0.4%) ca: 8.1s (73.5x, 0.1%) dr: 4.8s (44.0x, 0.2%) ma: 4.9s (44.9x, -2.5%) -- bz2 -- bz2 valgrind-new:0.59s no: 1.7s ( 2.9x, -----) me: 5.7s ( 9.7x, -----) ca:17.4s (29.6x, -----) he: 8.5s (14.3x, -----) ca:12.4s (21.1x, -----) dr:12.9s (21.9x, -----) ma: 1.8s ( 3.0x, -----) bz2 valgrind-old:0.59s no: 1.7s ( 2.9x, 1.7%) me: 5.7s ( 9.7x, 0.2%) ca:17.5s (29.6x, -0.1%) he: 8.4s (14.2x, 0.7%) ca:12.4s (21.1x, -0.2%) dr:12.8s (21.7x, 0.9%) ma: 1.8s ( 3.0x, -0.6%) -- fbench -- fbench valgrind-new:0.22s no: 1.1s ( 4.8x, -----) me: 3.6s (16.3x, -----) ca: 5.8s (26.5x, -----) he: 3.0s (13.4x, -----) ca: 3.6s (16.5x, -----) dr: 2.8s (12.8x, -----) ma: 1.1s ( 5.0x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.7x, 1.0%) me: 3.6s (16.2x, 0.6%) ca: 5.8s (26.5x, 0.3%) he: 3.0s (13.4x, 0.0%) ca: 3.7s (16.6x, -0.5%) dr: 2.9s (13.0x, -1.1%) ma: 1.1s ( 5.0x, 0.0%) -- ffbench -- ffbench valgrind-new:0.22s no: 1.2s ( 5.4x, -----) me: 3.1s (14.1x, -----) ca: 2.1s ( 9.8x, -----) he: 5.1s (23.2x, -----) ca: 5.0s (22.6x, -----) dr: 3.6s (16.3x, -----) ma: 1.1s ( 5.2x, -----) ffbench valgrind-old:0.22s no: 1.2s ( 5.5x, -0.8%) me: 3.1s (14.1x, 0.0%) ca: 2.2s ( 9.9x, -0.9%) he: 5.6s (25.5x,-10.2%) ca: 5.0s (22.9x, -1.2%) dr: 3.6s (16.3x, -0.3%) ma: 1.1s ( 5.2x, 0.0%) -- heap -- heap valgrind-new:0.07s no: 0.6s ( 8.9x, -----) me: 5.3s (75.3x, -----) ca: 5.9s (84.1x, -----) he: 7.1s (101.0x, -----) ca: 3.6s (51.3x, -----) dr: 4.4s (62.6x, -----) ma: 4.7s (66.6x, -----) heap valgrind-old:0.07s no: 0.6s ( 8.7x, 1.6%) me: 5.2s (74.9x, 0.6%) ca: 5.9s (84.1x, 0.0%) he: 7.0s (99.6x, 1.4%) ca: 3.6s (50.9x, 0.8%) dr: 4.3s (61.9x, 1.1%) ma: 4.6s (66.1x, 0.6%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.10s no: 0.7s ( 6.5x, -----) me: 8.6s (85.8x, -----) ca: 6.3s (63.0x, -----) he: 7.8s (78.5x, -----) ca: 3.7s (37.0x, -----) dr: 4.8s (48.4x, -----) ma: 4.9s (48.8x, -----) heap_pdb4 valgrind-old:0.10s no: 0.7s ( 6.5x, 0.0%) me: 8.5s (84.9x, 1.0%) ca: 6.4s (64.0x, -1.6%) he: 7.8s (78.4x, 0.1%) ca: 3.7s (36.9x, 0.3%) dr: 4.8s (48.4x, 0.0%) ma: 4.9s (49.1x, -0.6%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.2s (22.0x, -----) me: 1.2s (123.0x, -----) ca: 0.9s (93.0x, -----) he: 1.1s (108.0x, -----) ca: 0.6s (62.0x, -----) dr: 0.9s (90.0x, -----) ma: 0.9s (93.0x, -----) many-loss-records valgrind-old:0.01s no: 0.2s (22.0x, 0.0%) me: 1.2s (122.0x, 0.8%) ca: 0.9s (93.0x, 0.0%) he: 1.1s (109.0x, -0.9%) ca: 0.6s (63.0x, -1.6%) dr: 0.9s (89.0x, 1.1%) ma: 0.9s (93.0x, 0.0%) -- many-xpts -- many-xpts valgrind-new:0.04s no: 0.3s ( 7.8x, -----) me: 1.7s (42.5x, -----) ca: 2.9s (73.0x, -----) he: 2.2s (54.8x, -----) ca: 1.1s (27.8x, -----) dr: 1.3s (31.8x, -----) ma: 1.4s (34.8x, -----) many-xpts valgrind-old:0.04s no: 0.3s ( 7.8x, 0.0%) me: 1.7s (43.2x, -1.8%) ca: 2.9s (73.0x, 0.0%) he: 2.1s (53.8x, 1.8%) ca: 1.1s (27.8x, 0.0%) dr: 1.3s (32.2x, -1.6%) ma: 1.4s (34.5x, 0.7%) -- sarp -- sarp valgrind-new:0.02s no: 0.2s (12.0x, -----) me: 2.2s (108.5x, -----) ca: 1.7s (87.0x, -----) he: 7.4s (372.0x, -----) ca: 1.0s (48.5x, -----) dr: 0.8s (39.0x, -----) ma: 0.3s (13.0x, -----) sarp valgrind-old:0.02s no: 0.2s (12.0x, 0.0%) me: 2.2s (108.0x, 0.5%) ca: 1.7s (86.5x, 0.6%) he: 8.7s (435.0x,-16.9%) ca: 1.0s (49.0x, -1.0%) dr: 0.8s (42.0x, -7.7%) ma: 0.3s (13.0x, 0.0%) -- tinycc -- tinycc valgrind-new:0.17s no: 1.3s ( 7.8x, -----) me: 8.7s (50.9x, -----) ca:11.0s (64.9x, -----) he:10.9s (64.1x, -----) ca: 8.8s (52.1x, -----) dr: 8.8s (51.5x, -----) ma: 2.5s (14.5x, -----) tinycc valgrind-old:0.17s no: 1.4s ( 8.2x, -5.3%) me: 9.3s (54.8x, -7.7%) ca:11.3s (66.4x, -2.4%) he:10.9s (64.1x, 0.1%) ca: 8.8s (51.9x, 0.3%) dr: 8.8s (51.6x, -0.1%) ma: 2.5s (14.4x, 0.8%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 36m18.793s user 35m27.853s sys 0m21.489s |
|
From: Tom H. <to...@co...> - 2014-08-07 03:26:15
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-08-07 03:14:35 BST Ended at 2014-08-07 04:26:00 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.6s (14.8x, -----) me: 3.2s (29.2x, -----) ca:14.2s (128.8x, -----) he: 1.9s (17.3x, -----) ca: 3.9s (35.4x, -----) dr: 1.9s (17.0x, -----) ma: 1.9s (17.5x, -----) bigcode1 valgrind-old:0.11s no: 1.6s (14.9x, -0.6%) me: 3.2s (28.7x, 1.6%) ca:14.3s (130.0x, -0.9%) he: 1.9s (17.4x, -0.5%) ca: 3.9s (35.3x, 0.3%) dr: 1.9s (16.9x, 0.5%) ma: 1.9s (17.6x, -0.5%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 3.9s (35.5x, -----) me: 8.2s (74.4x, -----) ca:26.0s (236.4x, -----) he: 4.8s (43.6x, -----) ca: 7.2s (65.5x, -----) dr: 4.5s (40.8x, -----) ma: 4.5s (40.7x, -----) bigcode2 valgrind-old:0.11s no: 3.9s (35.5x, 0.0%) me: 8.2s (74.6x, -0.4%) ca:26.4s (240.3x, -1.7%) he: 4.8s (43.6x, 0.0%) ca: 7.3s (66.4x, -1.4%) dr: 4.5s (40.8x, 0.0%) ma: 4.5s (41.2x, -1.1%) -- bz2 -- bz2 valgrind-new:0.53s no: 2.1s ( 4.0x, -----) me: 6.1s (11.5x, -----) ca:13.7s (25.8x, -----) he: 8.8s (16.6x, -----) ca:11.7s (22.1x, -----) dr:11.1s (21.0x, -----) ma: 2.1s ( 3.9x, -----) bz2 valgrind-old:0.53s no: 2.1s ( 4.0x, -0.5%) me: 6.1s (11.6x, -0.5%) ca:13.6s (25.7x, 0.6%) he: 8.7s (16.5x, 0.9%) ca:11.6s (21.9x, 0.9%) dr:11.3s (21.3x, -1.3%) ma: 2.1s ( 3.9x, 0.0%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.6x, -----) me: 3.6s (16.4x, -----) ca: 5.5s (24.8x, -----) he: 2.8s (12.6x, -----) ca: 3.1s (14.3x, -----) dr: 2.5s (11.4x, -----) ma: 1.1s ( 4.9x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.6x, 0.0%) me: 3.6s (16.4x, 0.0%) ca: 5.5s (25.0x, -0.7%) he: 2.8s (12.9x, -1.8%) ca: 3.1s (14.2x, 0.3%) dr: 2.5s (11.5x, -1.2%) ma: 1.1s ( 4.8x, 0.9%) -- ffbench -- ffbench valgrind-new:0.21s no: 0.9s ( 4.4x, -----) me: 2.7s (13.0x, -----) ca: 1.9s ( 8.8x, -----) he: 5.8s (27.4x, -----) ca: 4.2s (20.1x, -----) dr: 3.3s (15.9x, -----) ma: 0.9s ( 4.2x, -----) ffbench valgrind-old:0.21s no: 0.9s ( 4.4x, 0.0%) me: 2.7s (13.0x, -0.0%) ca: 1.9s ( 8.8x, 0.0%) he: 5.6s (26.6x, 2.8%) ca: 4.1s (19.7x, 1.9%) dr: 3.4s (16.0x, -0.6%) ma: 0.9s ( 4.2x, 0.0%) -- heap -- heap valgrind-new:0.07s no: 0.6s ( 8.6x, -----) me: 5.1s (73.0x, -----) ca: 6.3s (89.4x, -----) he: 6.8s (97.0x, -----) ca: 3.3s (46.7x, -----) dr: 4.2s (60.4x, -----) ma: 4.9s (69.6x, -----) heap valgrind-old:0.07s no: 0.6s ( 8.6x, 0.0%) me: 5.1s (72.9x, 0.2%) ca: 6.2s (89.1x, 0.3%) he: 6.8s (97.9x, -0.9%) ca: 3.3s (46.7x, 0.0%) dr: 4.2s (60.6x, -0.2%) ma: 4.8s (68.6x, 1.4%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.11s no: 0.7s ( 6.0x, -----) me: 8.7s (78.8x, -----) ca: 7.0s (63.4x, -----) he: 8.0s (72.3x, -----) ca: 3.6s (32.9x, -----) dr: 4.8s (44.1x, -----) ma: 5.1s (46.5x, -----) heap_pdb4 valgrind-old:0.11s no: 0.7s ( 6.1x, -1.5%) me: 8.7s (79.1x, -0.3%) ca: 7.0s (63.7x, -0.6%) he: 8.0s (72.3x, 0.0%) ca: 3.6s (32.9x, 0.0%) dr: 4.8s (43.4x, 1.6%) ma: 5.0s (45.5x, 2.3%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.2s (24.0x, -----) me: 1.2s (123.0x, -----) ca: 1.0s (99.0x, -----) he: 1.1s (105.0x, -----) ca: 0.7s (66.0x, -----) dr: 0.9s (91.0x, -----) ma: 1.0s (96.0x, -----) many-loss-records valgrind-old:0.01s no: 0.2s (24.0x, 0.0%) me: 1.2s (124.0x, -0.8%) ca: 1.0s (101.0x, -2.0%) he: 1.1s (105.0x, 0.0%) ca: 0.7s (66.0x, 0.0%) dr: 0.9s (91.0x, 0.0%) ma: 0.9s (95.0x, 1.0%) -- many-xpts -- many-xpts valgrind-new:0.03s no: 0.3s (10.3x, -----) me: 1.8s (58.3x, -----) ca: 2.6s (87.3x, -----) he: 2.1s (70.3x, -----) ca: 0.9s (30.3x, -----) dr: 1.3s (44.0x, -----) ma: 1.4s (48.3x, -----) many-xpts valgrind-old:0.03s no: 0.3s (10.0x, 3.2%) me: 1.8s (58.3x, 0.0%) ca: 2.6s (86.7x, 0.8%) he: 2.1s (70.3x, 0.0%) ca: 0.9s (30.3x, 0.0%) dr: 1.3s (43.7x, 0.8%) ma: 1.4s (47.3x, 2.1%) -- sarp -- sarp valgrind-new:0.02s no: 0.3s (13.0x, -----) me: 2.4s (120.5x, -----) ca: 1.7s (83.5x, -----) he: 6.4s (319.0x, -----) ca: 0.9s (45.5x, -----) dr: 0.8s (40.5x, -----) ma: 0.3s (13.5x, -----) sarp valgrind-old:0.02s no: 0.3s (13.0x, 0.0%) me: 2.4s (120.5x, 0.0%) ca: 1.7s (85.5x, -2.4%) he: 6.5s (326.5x, -2.4%) ca: 0.9s (44.5x, 2.2%) dr: 0.8s (41.0x, -1.2%) ma: 0.3s (14.0x, -3.7%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.4s ( 8.5x, -----) me: 8.5s (53.1x, -----) ca:10.7s (66.6x, -----) he: 9.3s (58.4x, -----) ca: 7.9s (49.2x, -----) dr: 7.8s (48.5x, -----) ma: 2.4s (15.1x, -----) tinycc valgrind-old:0.16s no: 1.4s ( 8.5x, -0.0%) me: 8.6s (53.9x, -1.5%) ca:10.7s (67.0x, -0.7%) he: 9.5s (59.4x, -1.6%) ca: 7.8s (48.6x, 1.3%) dr: 7.9s (49.3x, -1.7%) ma: 2.4s (14.9x, 1.7%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 34m39.875s user 33m47.705s sys 0m20.817s |
|
From: Tom H. <to...@co...> - 2014-08-07 03:17:12
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-08-07 03:04:26 BST Ended at 2014-08-07 04:16:59 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.7s (15.1x, -----) me: 3.2s (29.2x, -----) ca:14.4s (131.3x, -----) he: 1.9s (17.5x, -----) ca: 4.0s (36.1x, -----) dr: 1.9s (17.5x, -----) ma: 2.0s (18.1x, -----) bigcode1 valgrind-old:0.11s no: 1.7s (15.1x, 0.0%) me: 3.2s (29.5x, -0.9%) ca:14.4s (130.6x, 0.5%) he: 1.9s (17.5x, 0.0%) ca: 4.0s (35.9x, 0.5%) dr: 1.9s (17.0x, 2.6%) ma: 2.0s (17.9x, 1.0%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 4.0s (36.2x, -----) me: 8.3s (75.9x, -----) ca:27.4s (248.7x, -----) he: 4.9s (44.8x, -----) ca: 7.3s (66.1x, -----) dr: 4.5s (41.4x, -----) ma: 4.6s (41.7x, -----) bigcode2 valgrind-old:0.11s no: 3.9s (35.5x, 2.0%) me: 8.2s (74.8x, 1.4%) ca:26.5s (240.7x, 3.2%) he: 4.8s (44.0x, 1.8%) ca: 7.3s (66.0x, 0.1%) dr: 4.5s (41.2x, 0.4%) ma: 4.5s (41.0x, 1.7%) -- bz2 -- bz2 valgrind-new:0.52s no: 2.2s ( 4.2x, -----) me: 6.2s (11.8x, -----) ca:13.8s (26.4x, -----) he: 8.9s (17.2x, -----) ca:11.8s (22.8x, -----) dr:11.3s (21.7x, -----) ma: 2.1s ( 4.1x, -----) bz2 valgrind-old:0.52s no: 2.1s ( 4.1x, 4.1%) me: 6.1s (11.8x, 0.5%) ca:13.7s (26.3x, 0.4%) he: 9.0s (17.3x, -0.7%) ca:11.8s (22.7x, 0.3%) dr:11.3s (21.8x, -0.1%) ma: 2.1s ( 4.0x, 0.5%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.7x, -----) me: 3.6s (16.5x, -----) ca: 5.5s (25.2x, -----) he: 2.7s (12.3x, -----) ca: 3.2s (14.6x, -----) dr: 2.5s (11.4x, -----) ma: 1.1s ( 4.9x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.7x, 0.0%) me: 3.6s (16.4x, 0.8%) ca: 5.5s (25.2x, 0.2%) he: 2.7s (12.4x, -0.7%) ca: 3.2s (14.7x, -0.3%) dr: 2.5s (11.4x, 0.0%) ma: 1.1s ( 4.9x, 0.9%) -- ffbench -- ffbench valgrind-new:0.22s no: 0.9s ( 4.3x, -----) me: 2.8s (12.8x, -----) ca: 1.9s ( 8.6x, -----) he: 6.1s (27.7x, -----) ca: 4.2s (18.9x, -----) dr: 3.3s (14.9x, -----) ma: 0.9s ( 4.0x, -----) ffbench valgrind-old:0.22s no: 0.9s ( 4.3x, 0.0%) me: 2.7s (12.5x, 2.5%) ca: 1.9s ( 8.5x, 1.6%) he: 5.5s (24.8x, 10.5%) ca: 4.2s (19.0x, -1.0%) dr: 3.3s (14.9x, -0.3%) ma: 0.9s ( 4.0x, -1.1%) -- heap -- heap valgrind-new:0.09s no: 0.7s ( 7.2x, -----) me: 5.2s (57.8x, -----) ca: 6.6s (73.4x, -----) he: 7.1s (79.3x, -----) ca: 3.3s (37.0x, -----) dr: 4.3s (47.3x, -----) ma: 4.8s (53.7x, -----) heap valgrind-old:0.09s no: 0.6s ( 7.1x, 1.5%) me: 5.2s (57.7x, 0.2%) ca: 6.6s (73.7x, -0.3%) he: 7.1s (78.9x, 0.6%) ca: 3.4s (38.0x, -2.7%) dr: 4.2s (47.1x, 0.5%) ma: 4.8s (53.1x, 1.0%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.11s no: 0.7s ( 6.4x, -----) me: 8.6s (78.5x, -----) ca: 7.2s (65.7x, -----) he: 7.9s (71.5x, -----) ca: 3.6s (32.9x, -----) dr: 5.0s (45.6x, -----) ma: 5.2s (46.8x, -----) heap_pdb4 valgrind-old:0.11s no: 0.7s ( 6.4x, 0.0%) me: 8.6s (78.4x, 0.1%) ca: 7.2s (65.7x, 0.0%) he: 7.8s (71.1x, 0.5%) ca: 3.6s (33.2x, -0.8%) dr: 5.0s (45.4x, 0.6%) ma: 5.0s (45.9x, 1.9%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.3s (26.0x, -----) me: 1.3s (129.0x, -----) ca: 1.1s (108.0x, -----) he: 1.1s (109.0x, -----) ca: 0.7s (68.0x, -----) dr: 0.9s (95.0x, -----) ma: 1.0s (99.0x, -----) many-loss-records valgrind-old:0.01s no: 0.3s (26.0x, 0.0%) me: 1.3s (127.0x, 1.6%) ca: 1.1s (108.0x, 0.0%) he: 1.1s (107.0x, 1.8%) ca: 0.7s (69.0x, -1.5%) dr: 0.9s (95.0x, 0.0%) ma: 1.0s (97.0x, 2.0%) -- many-xpts -- many-xpts valgrind-new:0.03s no: 0.3s (10.7x, -----) me: 1.8s (59.7x, -----) ca: 2.8s (92.3x, -----) he: 2.1s (71.7x, -----) ca: 1.0s (32.3x, -----) dr: 1.3s (44.7x, -----) ma: 1.4s (48.3x, -----) many-xpts valgrind-old:0.03s no: 0.3s (10.7x, 0.0%) me: 1.8s (59.7x, 0.0%) ca: 2.8s (92.7x, -0.4%) he: 2.1s (71.7x, 0.0%) ca: 1.0s (33.0x, -2.1%) dr: 1.3s (44.3x, 0.7%) ma: 1.4s (47.7x, 1.4%) -- sarp -- sarp valgrind-new:0.02s no: 0.3s (14.0x, -----) me: 2.4s (117.5x, -----) ca: 1.7s (86.0x, -----) he: 6.5s (327.5x, -----) ca: 1.0s (49.0x, -----) dr: 0.9s (46.5x, -----) ma: 0.3s (14.5x, -----) sarp valgrind-old:0.02s no: 0.3s (13.5x, 3.6%) me: 2.4s (118.0x, -0.4%) ca: 1.7s (86.0x, 0.0%) he: 6.6s (328.5x, -0.3%) ca: 1.0s (49.0x, 0.0%) dr: 0.9s (46.5x, 0.0%) ma: 0.3s (14.5x, 0.0%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.4s ( 8.8x, -----) me: 8.7s (54.3x, -----) ca:11.0s (68.6x, -----) he: 9.5s (59.2x, -----) ca: 8.1s (50.4x, -----) dr: 7.8s (48.7x, -----) ma: 2.5s (15.4x, -----) tinycc valgrind-old:0.16s no: 1.4s ( 8.6x, 2.8%) me: 8.7s (54.3x, 0.0%) ca:11.0s (68.6x, 0.0%) he: 9.5s (59.6x, -0.5%) ca: 7.8s (48.9x, 3.0%) dr: 7.9s (49.6x, -1.8%) ma: 2.5s (15.4x, 0.0%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 35m1.620s user 34m2.529s sys 0m22.610s |
|
From: Tom H. <to...@co...> - 2014-08-07 03:07:12
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-08-07 02:53:50 BST Ended at 2014-08-07 04:06:47 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 6 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.6s (14.6x, -----) me: 3.3s (29.8x, -----) ca:13.4s (122.0x, -----) he: 1.9s (17.3x, -----) ca: 4.0s (36.1x, -----) dr: 1.9s (17.7x, -----) ma: 1.9s (17.5x, -----) bigcode1 valgrind-old:0.11s no: 1.6s (14.6x, -0.0%) me: 3.4s (31.3x, -4.9%) ca:14.0s (126.9x, -4.0%) he: 2.0s (18.3x, -5.8%) ca: 3.7s (33.8x, 6.3%) dr: 1.8s (16.7x, 5.6%) ma: 2.2s (20.2x,-15.0%) -- bigcode2 -- bigcode2 valgrind-new:0.14s no: 3.9s (27.8x, -----) me: 8.3s (59.6x, -----) ca:26.1s (186.6x, -----) he: 4.7s (33.6x, -----) ca: 7.0s (50.1x, -----) dr: 4.5s (32.4x, -----) ma: 4.4s (31.7x, -----) bigcode2 valgrind-old:0.14s no: 3.8s (27.4x, 1.3%) me: 8.3s (59.4x, 0.4%) ca:25.1s (179.4x, 3.8%) he: 4.9s (35.2x, -4.7%) ca: 7.1s (50.7x, -1.1%) dr: 4.5s (32.0x, 1.3%) ma: 4.6s (32.6x, -2.7%) -- bz2 -- bz2 valgrind-new:0.52s no: 2.1s ( 4.1x, -----) me: 6.3s (12.1x, -----) ca:12.9s (24.7x, -----) he: 8.9s (17.2x, -----) ca:12.1s (23.2x, -----) dr:11.7s (22.4x, -----) ma: 2.1s ( 4.0x, -----) bz2 valgrind-old:0.52s no: 2.1s ( 4.0x, 1.9%) me: 6.3s (12.0x, 0.6%) ca:12.9s (24.7x, 0.0%) he: 9.0s (17.4x, -1.1%) ca:11.9s (22.9x, 1.2%) dr:11.6s (22.3x, 0.5%) ma: 2.1s ( 4.1x, -1.4%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.7x, -----) me: 3.5s (15.8x, -----) ca: 5.5s (25.1x, -----) he: 2.7s (12.1x, -----) ca: 3.0s (13.4x, -----) dr: 2.4s (10.8x, -----) ma: 1.1s ( 4.8x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.6x, 1.0%) me: 3.4s (15.6x, 0.9%) ca: 5.5s (25.0x, 0.2%) he: 2.7s (12.1x, -0.4%) ca: 3.0s (13.5x, -0.3%) dr: 2.4s (10.8x, -0.4%) ma: 1.1s ( 4.9x, -0.9%) -- ffbench -- ffbench valgrind-new:0.21s no: 0.9s ( 4.5x, -----) me: 2.8s (13.3x, -----) ca: 1.9s ( 8.9x, -----) he: 7.3s (35.0x, -----) ca: 4.2s (19.9x, -----) dr: 3.3s (15.8x, -----) ma: 0.9s ( 4.2x, -----) ffbench valgrind-old:0.21s no: 0.9s ( 4.5x, 0.0%) me: 2.8s (13.5x, -1.1%) ca: 1.9s ( 8.8x, 1.1%) he: 6.9s (32.7x, 6.7%) ca: 4.0s (19.3x, 2.9%) dr: 3.3s (15.9x, -0.6%) ma: 0.9s ( 4.2x, 0.0%) -- heap -- heap valgrind-new:0.08s no: 0.6s ( 7.8x, -----) me: 5.4s (67.6x, -----) ca: 6.0s (74.4x, -----) he: 6.8s (84.6x, -----) ca: 3.2s (40.1x, -----) dr: 4.3s (54.2x, -----) ma: 4.9s (61.1x, -----) heap valgrind-old:0.08s no: 0.6s ( 7.9x, -1.6%) me: 5.4s (67.8x, -0.2%) ca: 6.0s (74.8x, -0.5%) he: 6.8s (84.5x, 0.1%) ca: 3.2s (39.8x, 0.9%) dr: 4.3s (54.4x, -0.2%) ma: 4.9s (61.2x, -0.2%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.10s no: 0.7s ( 6.8x, -----) me: 8.9s (88.8x, -----) ca: 6.6s (65.7x, -----) he: 8.1s (80.6x, -----) ca: 3.6s (35.8x, -----) dr: 5.0s (49.6x, -----) ma: 5.2s (52.0x, -----) heap_pdb4 valgrind-old:0.10s no: 0.7s ( 6.9x, -1.5%) me: 8.8s (88.2x, 0.7%) ca: 6.6s (65.6x, 0.2%) he: 8.0s (80.3x, 0.4%) ca: 3.6s (36.0x, -0.6%) dr: 4.9s (49.3x, 0.6%) ma: 5.2s (51.6x, 0.8%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.2s (25.0x, -----) me: 1.3s (131.0x, -----) ca: 1.0s (101.0x, -----) he: 1.1s (110.0x, -----) ca: 0.7s (65.0x, -----) dr: 1.0s (100.0x, -----) ma: 1.1s (105.0x, -----) many-loss-records valgrind-old:0.01s no: 0.2s (25.0x, 0.0%) me: 1.3s (134.0x, -2.3%) ca: 1.0s (101.0x, 0.0%) he: 1.1s (110.0x, 0.0%) ca: 0.7s (65.0x, 0.0%) dr: 1.0s (99.0x, 1.0%) ma: 1.0s (104.0x, 1.0%) -- many-xpts -- many-xpts valgrind-new:0.04s no: 0.3s ( 7.8x, -----) me: 1.8s (44.8x, -----) ca: 2.6s (65.2x, -----) he: 2.2s (55.2x, -----) ca: 0.9s (22.8x, -----) dr: 1.4s (36.0x, -----) ma: 1.5s (38.5x, -----) many-xpts valgrind-old:0.04s no: 0.3s ( 7.8x, 0.0%) me: 1.8s (44.5x, 0.6%) ca: 2.6s (64.8x, 0.8%) he: 2.2s (54.8x, 0.9%) ca: 0.9s (23.0x, -1.1%) dr: 1.4s (35.8x, 0.7%) ma: 1.6s (38.8x, -0.6%) -- sarp -- sarp valgrind-new:0.02s no: 0.3s (14.0x, -----) me: 2.3s (113.5x, -----) ca: 1.7s (86.0x, -----) he: 7.3s (367.5x, -----) ca: 0.9s (44.0x, -----) dr: 0.9s (44.0x, -----) ma: 0.3s (15.0x, -----) sarp valgrind-old:0.02s no: 0.3s (13.5x, 3.6%) me: 2.3s (113.0x, 0.4%) ca: 1.7s (86.0x, 0.0%) he: 7.4s (368.5x, -0.3%) ca: 0.9s (44.0x, 0.0%) dr: 0.9s (44.0x, 0.0%) ma: 0.3s (15.0x, 0.0%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.3s ( 8.3x, -----) me: 8.4s (52.6x, -----) ca:10.7s (67.0x, -----) he: 9.9s (62.1x, -----) ca: 7.6s (47.5x, -----) dr: 7.5s (46.9x, -----) ma: 2.4s (14.9x, -----) tinycc valgrind-old:0.16s no: 1.4s ( 8.5x, -2.3%) me: 8.3s (52.2x, 0.8%) ca:10.8s (67.8x, -1.1%) he: 9.9s (62.1x, 0.0%) ca: 7.5s (46.6x, 1.8%) dr: 7.5s (46.9x, 0.1%) ma: 2.4s (15.1x, -0.8%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 35m15.383s user 34m10.141s sys 0m23.372s |
|
From: Tom H. <to...@co...> - 2014-08-07 02:57:53
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-08-07 02:43:41 BST Ended at 2014-08-07 03:57:37 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 3 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.6s (15.0x, -----) me: 3.2s (29.3x, -----) ca:13.3s (120.5x, -----) he: 1.9s (17.5x, -----) ca: 3.7s (33.7x, -----) dr: 1.9s (17.2x, -----) ma: 1.9s (17.6x, -----) bigcode1 valgrind-old:0.11s no: 1.6s (15.0x, 0.0%) me: 3.3s (29.9x, -2.2%) ca:13.5s (122.8x, -1.9%) he: 2.0s (18.0x, -2.6%) ca: 3.9s (35.4x, -4.9%) dr: 1.9s (17.0x, 1.1%) ma: 1.9s (17.5x, 0.5%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 4.2s (38.6x, -----) me: 9.3s (84.3x, -----) ca:29.1s (265.0x, -----) he: 5.2s (47.5x, -----) ca: 7.1s (64.5x, -----) dr: 4.5s (41.2x, -----) ma: 4.6s (41.5x, -----) bigcode2 valgrind-old:0.11s no: 3.9s (35.4x, 8.5%) me: 8.3s (75.8x, 10.0%) ca:27.5s (249.9x, 5.7%) he: 4.8s (43.5x, 8.2%) ca: 7.8s (71.1x,-10.3%) dr: 4.6s (41.9x, -1.8%) ma: 4.5s (41.1x, 1.1%) -- bz2 -- bz2 valgrind-new:0.53s no: 2.2s ( 4.2x, -----) me: 6.8s (12.8x, -----) ca:14.5s (27.3x, -----) he: 9.2s (17.5x, -----) ca:11.7s (22.1x, -----) dr:12.4s (23.5x, -----) ma: 2.1s ( 4.0x, -----) bz2 valgrind-old:0.53s no: 2.2s ( 4.2x, 0.0%) me: 6.3s (11.8x, 7.4%) ca:12.9s (24.3x, 10.9%) he: 9.0s (16.9x, 3.1%) ca:11.8s (22.2x, -0.5%) dr:11.5s (21.6x, 7.8%) ma: 2.1s ( 4.0x, 0.0%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.6x, -----) me: 3.5s (15.8x, -----) ca: 5.5s (24.9x, -----) he: 2.7s (12.3x, -----) ca: 3.0s (13.8x, -----) dr: 2.4s (11.1x, -----) ma: 1.1s ( 4.8x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.6x, 0.0%) me: 3.5s (15.9x, -0.3%) ca: 5.5s (25.0x, -0.4%) he: 2.7s (12.2x, 0.7%) ca: 3.0s (13.9x, -0.7%) dr: 2.4s (11.0x, 0.4%) ma: 1.1s ( 4.8x, 0.0%) -- ffbench -- ffbench valgrind-new:0.24s no: 0.9s ( 4.0x, -----) me: 2.8s (11.7x, -----) ca: 1.9s ( 7.8x, -----) he: 7.7s (31.9x, -----) ca: 4.2s (17.6x, -----) dr: 3.2s (13.5x, -----) ma: 0.9s ( 3.8x, -----) ffbench valgrind-old:0.24s no: 0.9s ( 3.9x, 2.1%) me: 2.8s (11.7x, 0.0%) ca: 1.9s ( 7.7x, 1.6%) he: 7.4s (30.7x, 3.9%) ca: 4.2s (17.3x, 1.7%) dr: 3.2s (13.5x, 0.0%) ma: 0.9s ( 3.7x, 2.2%) -- heap -- heap valgrind-new:0.08s no: 0.6s ( 8.0x, -----) me: 5.3s (66.8x, -----) ca: 6.2s (77.1x, -----) he: 6.8s (84.8x, -----) ca: 3.2s (40.5x, -----) dr: 4.5s (55.9x, -----) ma: 5.0s (62.9x, -----) heap valgrind-old:0.08s no: 0.7s ( 8.1x, -1.6%) me: 5.2s (65.5x, 1.9%) ca: 6.1s (76.5x, 0.8%) he: 6.8s (84.6x, 0.1%) ca: 3.2s (40.4x, 0.3%) dr: 4.5s (56.1x, -0.4%) ma: 5.0s (62.0x, 1.4%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.11s no: 0.7s ( 6.3x, -----) me: 8.9s (81.1x, -----) ca: 6.8s (61.4x, -----) he: 8.2s (74.5x, -----) ca: 3.6s (33.1x, -----) dr: 5.2s (47.4x, -----) ma: 5.3s (48.3x, -----) heap_pdb4 valgrind-old:0.11s no: 0.7s ( 6.3x, -0.0%) me: 8.8s (80.0x, 1.3%) ca: 6.8s (61.4x, 0.0%) he: 8.1s (73.2x, 1.7%) ca: 3.6s (32.6x, 1.4%) dr: 5.2s (47.0x, 0.8%) ma: 5.2s (47.5x, 1.5%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.2s (25.0x, -----) me: 1.3s (134.0x, -----) ca: 1.0s (100.0x, -----) he: 1.1s (115.0x, -----) ca: 0.7s (67.0x, -----) dr: 1.0s (103.0x, -----) ma: 1.1s (107.0x, -----) many-loss-records valgrind-old:0.01s no: 0.3s (26.0x, -4.0%) me: 1.4s (135.0x, -0.7%) ca: 1.0s (102.0x, -2.0%) he: 1.1s (113.0x, 1.7%) ca: 0.7s (67.0x, 0.0%) dr: 1.0s (101.0x, 1.9%) ma: 1.1s (105.0x, 1.9%) -- many-xpts -- many-xpts valgrind-new:0.03s no: 0.3s (10.0x, -----) me: 1.8s (59.3x, -----) ca: 2.6s (88.3x, -----) he: 2.2s (74.0x, -----) ca: 0.9s (30.0x, -----) dr: 1.4s (48.3x, -----) ma: 1.6s (52.3x, -----) many-xpts valgrind-old:0.03s no: 0.3s (10.3x, -3.3%) me: 1.8s (60.0x, -1.1%) ca: 2.6s (88.3x, 0.0%) he: 2.2s (73.0x, 1.4%) ca: 0.9s (30.7x, -2.2%) dr: 1.5s (48.7x, -0.7%) ma: 1.6s (52.0x, 0.6%) -- sarp -- sarp valgrind-new:0.01s no: 0.3s (28.0x, -----) me: 2.0s (205.0x, -----) ca: 1.7s (174.0x, -----) he: 7.3s (730.0x, -----) ca: 0.9s (89.0x, -----) dr: 0.9s (89.0x, -----) ma: 0.3s (29.0x, -----) sarp valgrind-old:0.01s no: 0.3s (28.0x, 0.0%) me: 2.1s (206.0x, -0.5%) ca: 1.7s (172.0x, 1.1%) he: 7.3s (730.0x, 0.0%) ca: 0.9s (89.0x, 0.0%) dr: 0.9s (90.0x, -1.1%) ma: 0.3s (30.0x, -3.4%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.4s ( 8.6x, -----) me: 8.4s (52.7x, -----) ca:10.7s (67.0x, -----) he: 9.7s (60.8x, -----) ca: 7.6s (47.7x, -----) dr: 7.5s (47.1x, -----) ma: 2.4s (15.2x, -----) tinycc valgrind-old:0.16s no: 1.4s ( 8.5x, 1.4%) me: 8.6s (53.6x, -1.7%) ca:10.6s (66.4x, 0.8%) he: 9.8s (61.1x, -0.5%) ca: 7.7s (48.0x, -0.7%) dr: 8.5s (52.9x,-12.5%) ma: 2.5s (15.3x, -0.8%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 36m17.909s user 35m5.707s sys 0m24.903s |
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From: Tom H. <to...@co...> - 2014-08-07 02:47:48
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.8.3 20140624 (Red Hat 4.8.3-1) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-08-07 02:33:27 BST Ended at 2014-08-07 03:47:13 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/hackedbz2 (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.6s (14.8x, -----) me: 3.2s (28.9x, -----) ca:13.3s (121.2x, -----) he: 1.9s (17.2x, -----) ca: 3.8s (34.5x, -----) dr: 1.8s (16.7x, -----) ma: 1.9s (17.5x, -----) bigcode1 valgrind-old:0.11s no: 1.6s (14.8x, 0.0%) me: 3.2s (29.1x, -0.6%) ca:13.3s (121.2x, 0.0%) he: 1.9s (17.3x, -0.5%) ca: 3.7s (33.9x, 1.6%) dr: 1.9s (16.8x, -0.5%) ma: 1.9s (17.4x, 1.0%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 3.8s (34.9x, -----) me: 8.2s (74.1x, -----) ca:26.5s (240.8x, -----) he: 4.7s (42.5x, -----) ca: 7.2s (65.0x, -----) dr: 4.5s (41.0x, -----) ma: 4.5s (40.6x, -----) bigcode2 valgrind-old:0.11s no: 3.8s (34.6x, 0.8%) me: 8.2s (74.7x, -0.9%) ca:26.5s (240.8x, 0.0%) he: 4.7s (43.1x, -1.3%) ca: 7.0s (64.1x, 1.4%) dr: 4.4s (39.8x, 2.9%) ma: 4.6s (41.7x, -2.7%) -- bz2 -- bz2 valgrind-new:0.50s no: 2.1s ( 4.2x, -----) me: 6.1s (12.3x, -----) ca:13.5s (26.9x, -----) he: 9.3s (18.5x, -----) ca:11.0s (22.0x, -----) dr:11.4s (22.8x, -----) ma: 2.1s ( 4.2x, -----) bz2 valgrind-old:0.50s no: 2.1s ( 4.2x, -1.0%) me: 6.4s (12.7x, -3.8%) ca:14.2s (28.3x, -5.2%) he:10.5s (21.0x,-13.3%) ca:11.8s (23.6x, -7.1%) dr:12.0s (24.1x, -5.7%) ma: 2.2s ( 4.4x, -3.8%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.7x, -----) me: 3.5s (15.7x, -----) ca: 5.8s (26.1x, -----) he: 2.6s (11.9x, -----) ca: 3.1s (14.3x, -----) dr: 2.4s (10.8x, -----) ma: 1.1s ( 5.0x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.7x, -1.0%) me: 3.4s (15.5x, 1.4%) ca: 5.8s (26.2x, -0.2%) he: 2.5s (11.4x, 4.2%) ca: 3.2s (14.5x, -1.0%) dr: 2.6s (11.9x,-10.1%) ma: 1.1s ( 4.9x, 2.7%) -- ffbench -- ffbench valgrind-new:0.27s no: 1.0s ( 3.7x, -----) me: 3.0s (11.0x, -----) ca: 1.9s ( 7.0x, -----) he: 7.3s (27.0x, -----) ca: 4.7s (17.3x, -----) dr: 3.3s (12.3x, -----) ma: 0.9s ( 3.4x, -----) ffbench valgrind-old:0.27s no: 1.1s ( 4.1x,-13.1%) me: 2.8s (10.5x, 4.1%) ca: 1.9s ( 7.1x, -2.7%) he: 6.9s (25.4x, 5.8%) ca: 4.7s (17.4x, -0.6%) dr: 3.3s (12.4x, -0.9%) ma: 0.9s ( 3.4x, -1.1%) -- heap -- heap valgrind-new:0.08s no: 0.7s ( 8.1x, -----) me: 5.4s (67.8x, -----) ca: 6.2s (77.1x, -----) he: 6.8s (85.6x, -----) ca: 3.3s (40.8x, -----) dr: 4.5s (56.0x, -----) ma: 4.9s (61.6x, -----) heap valgrind-old:0.08s no: 0.7s ( 8.2x, -1.5%) me: 5.1s (63.4x, 6.5%) ca: 6.3s (79.1x, -2.6%) he: 7.3s (90.8x, -6.0%) ca: 3.2s (40.4x, 0.9%) dr: 4.3s (54.4x, 2.9%) ma: 4.8s (60.6x, 1.6%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.10s no: 0.7s ( 7.0x, -----) me: 9.1s (90.8x, -----) ca: 6.7s (67.1x, -----) he: 7.8s (77.9x, -----) ca: 3.5s (35.5x, -----) dr: 5.0s (50.4x, -----) ma: 5.0s (50.1x, -----) heap_pdb4 valgrind-old:0.10s no: 0.7s ( 7.0x, 0.0%) me: 8.8s (87.8x, 3.3%) ca: 7.1s (70.6x, -5.2%) he: 7.8s (78.1x, -0.3%) ca: 3.5s (35.2x, 0.8%) dr: 5.0s (50.5x, -0.2%) ma: 5.0s (49.6x, 1.0%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.3s (27.0x, -----) me: 1.3s (133.0x, -----) ca: 1.0s (99.0x, -----) he: 1.1s (109.0x, -----) ca: 0.7s (66.0x, -----) dr: 1.0s (97.0x, -----) ma: 1.0s (102.0x, -----) many-loss-records valgrind-old:0.01s no: 0.3s (26.0x, 3.7%) me: 1.3s (133.0x, 0.0%) ca: 1.0s (99.0x, 0.0%) he: 1.1s (109.0x, 0.0%) ca: 0.7s (66.0x, 0.0%) dr: 1.0s (98.0x, -1.0%) ma: 1.1s (105.0x, -2.9%) -- many-xpts -- many-xpts valgrind-new:0.03s no: 0.3s (10.7x, -----) me: 1.5s (49.0x, -----) ca: 2.5s (85.0x, -----) he: 2.1s (69.7x, -----) ca: 1.0s (32.0x, -----) dr: 1.4s (47.3x, -----) ma: 1.6s (52.7x, -----) many-xpts valgrind-old:0.03s no: 0.3s (11.0x, -3.1%) me: 1.5s (49.0x, 0.0%) ca: 2.7s (88.7x, -4.3%) he: 2.1s (68.7x, 1.4%) ca: 0.9s (31.3x, 2.1%) dr: 1.4s (46.0x, 2.8%) ma: 1.6s (52.0x, 1.3%) -- sarp -- sarp valgrind-new:0.02s no: 0.3s (14.5x, -----) me: 2.1s (106.5x, -----) ca: 1.7s (87.0x, -----) he: 6.0s (301.5x, -----) ca: 0.9s (46.5x, -----) dr: 0.9s (46.0x, -----) ma: 0.3s (15.0x, -----) sarp valgrind-old:0.02s no: 0.3s (14.0x, 3.4%) me: 2.1s (106.0x, 0.5%) ca: 1.7s (86.0x, 1.1%) he: 6.0s (300.0x, 0.5%) ca: 0.9s (46.5x, 0.0%) dr: 0.9s (47.5x, -3.3%) ma: 0.3s (16.5x,-10.0%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.4s ( 8.7x, -----) me: 7.8s (48.9x, -----) ca:10.9s (68.0x, -----) he: 9.8s (61.1x, -----) ca: 7.8s (48.7x, -----) dr: 7.9s (49.1x, -----) ma: 2.4s (14.9x, -----) tinycc valgrind-old:0.16s no: 1.4s ( 8.6x, 0.7%) me: 8.1s (50.7x, -3.7%) ca:11.0s (68.8x, -1.1%) he: 9.8s (61.1x, 0.0%) ca: 8.0s (50.2x, -3.2%) dr: 7.9s (49.4x, -0.5%) ma: 2.4s (15.0x, -0.4%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 36m12.004s user 34m44.366s sys 0m25.111s |
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From: Tom H. <to...@co...> - 2014-08-07 02:35:14
|
valgrind revision: 14237 VEX revision: 2913 C compiler: gcc (GCC) 4.8.3 20140624 (Red Hat 4.8.3-1) GDB: GNU gdb (GDB) Fedora 7.7.1-17.fc20 Assembler: GNU assembler version 2.23.2 C library: GNU C Library (GNU libc) stable release version 2.18 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 20 (Heisenbug) Nightly build on bristol ( x86_64, Fedora 20 ) Started at 2014-08-07 02:21:20 BST Ended at 2014-08-07 03:34:53 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) memcheck/tests/vbit-test/vbit-test (stderr) exp-sgcheck/tests/hackedbz2 (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.11s no: 1.6s (14.8x, -----) me: 3.1s (28.3x, -----) ca:13.2s (120.3x, -----) he: 1.9s (17.1x, -----) ca: 3.8s (34.1x, -----) dr: 1.8s (16.5x, -----) ma: 1.9s (17.5x, -----) bigcode1 valgrind-old:0.11s no: 1.6s (14.6x, 1.2%) me: 3.1s (28.5x, -1.0%) ca:13.3s (120.7x, -0.4%) he: 1.9s (17.0x, 0.5%) ca: 3.8s (34.2x, -0.3%) dr: 1.8s (16.7x, -1.1%) ma: 1.9s (17.4x, 0.5%) -- bigcode2 -- bigcode2 valgrind-new:0.11s no: 3.8s (34.5x, -----) me: 8.1s (73.7x, -----) ca:25.6s (232.8x, -----) he: 4.7s (42.5x, -----) ca: 7.0s (63.8x, -----) dr: 4.4s (40.3x, -----) ma: 4.5s (40.5x, -----) bigcode2 valgrind-old:0.11s no: 3.8s (34.7x, -0.8%) me: 8.2s (74.6x, -1.2%) ca:26.7s (243.0x, -4.4%) he: 4.7s (42.5x, 0.2%) ca: 7.0s (64.1x, -0.4%) dr: 4.4s (39.9x, 0.9%) ma: 4.5s (40.5x, 0.0%) -- bz2 -- bz2 valgrind-new:0.49s no: 2.1s ( 4.2x, -----) me: 6.1s (12.4x, -----) ca:13.0s (26.6x, -----) he: 8.8s (18.1x, -----) ca:11.0s (22.4x, -----) dr:11.1s (22.7x, -----) ma: 2.1s ( 4.3x, -----) bz2 valgrind-old:0.49s no: 2.1s ( 4.2x, 0.0%) me: 6.0s (12.3x, 1.0%) ca:13.0s (26.5x, 0.2%) he: 8.9s (18.2x, -0.6%) ca:10.8s (22.1x, 1.1%) dr:11.2s (22.9x, -0.5%) ma: 2.1s ( 4.3x, -1.0%) -- fbench -- fbench valgrind-new:0.22s no: 1.0s ( 4.6x, -----) me: 3.4s (15.6x, -----) ca: 5.4s (24.7x, -----) he: 2.6s (11.6x, -----) ca: 3.1s (14.3x, -----) dr: 2.4s (10.7x, -----) ma: 1.1s ( 4.8x, -----) fbench valgrind-old:0.22s no: 1.0s ( 4.7x, -2.0%) me: 3.5s (15.7x, -0.6%) ca: 5.5s (25.0x, -1.3%) he: 2.6s (11.7x, -0.8%) ca: 3.2s (14.4x, -1.0%) dr: 2.4s (10.9x, -1.3%) ma: 1.1s ( 4.9x, -0.9%) -- ffbench -- ffbench valgrind-new:0.24s no: 1.0s ( 4.0x, -----) me: 2.9s (11.9x, -----) ca: 1.9s ( 8.1x, -----) he: 6.6s (27.5x, -----) ca: 4.6s (19.3x, -----) dr: 3.2s (13.5x, -----) ma: 0.9s ( 3.8x, -----) ffbench valgrind-old:0.24s no: 1.0s ( 4.0x, 0.0%) me: 2.8s (11.8x, 1.4%) ca: 1.9s ( 8.0x, 1.0%) he: 6.6s (27.4x, 0.6%) ca: 4.6s (19.1x, 1.1%) dr: 3.2s (13.5x, 0.6%) ma: 0.9s ( 3.8x, -1.1%) -- heap -- heap valgrind-new:0.08s no: 0.6s ( 8.0x, -----) me: 5.1s (63.2x, -----) ca: 6.3s (78.6x, -----) he: 6.7s (83.5x, -----) ca: 3.2s (40.6x, -----) dr: 4.3s (53.2x, -----) ma: 4.8s (59.4x, -----) heap valgrind-old:0.08s no: 0.7s ( 8.1x, -1.6%) me: 5.1s (64.1x, -1.4%) ca: 6.2s (78.0x, 0.8%) he: 6.8s (84.6x, -1.3%) ca: 3.2s (40.4x, 0.6%) dr: 4.4s (55.4x, -4.0%) ma: 4.8s (59.9x, -0.8%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.10s no: 0.7s ( 6.8x, -----) me: 8.7s (86.9x, -----) ca: 6.9s (68.8x, -----) he: 7.7s (76.8x, -----) ca: 3.7s (37.1x, -----) dr: 5.1s (51.1x, -----) ma: 5.0s (50.1x, -----) heap_pdb4 valgrind-old:0.10s no: 0.7s ( 6.9x, -1.5%) me: 9.0s (90.3x, -3.9%) ca: 7.0s (70.5x, -2.5%) he: 8.5s (85.3x,-11.1%) ca: 4.0s (39.9x, -7.5%) dr: 4.8s (48.5x, 5.1%) ma: 5.6s (55.9x,-11.6%) -- many-loss-records -- many-loss-records valgrind-new:0.01s no: 0.3s (27.0x, -----) me: 1.3s (127.0x, -----) ca: 1.0s (102.0x, -----) he: 1.1s (114.0x, -----) ca: 0.7s (69.0x, -----) dr: 1.0s (100.0x, -----) ma: 1.1s (105.0x, -----) many-loss-records valgrind-old:0.01s no: 0.3s (26.0x, 3.7%) me: 1.3s (130.0x, -2.4%) ca: 1.1s (108.0x, -5.9%) he: 1.1s (114.0x, 0.0%) ca: 0.7s (70.0x, -1.4%) dr: 1.0s (101.0x, -1.0%) ma: 1.1s (109.0x, -3.8%) -- many-xpts -- many-xpts valgrind-new:0.03s no: 0.3s (11.0x, -----) me: 1.5s (49.3x, -----) ca: 2.6s (88.3x, -----) he: 2.1s (69.7x, -----) ca: 0.9s (31.3x, -----) dr: 1.4s (47.0x, -----) ma: 1.6s (52.3x, -----) many-xpts valgrind-old:0.03s no: 0.3s (10.3x, 6.1%) me: 1.4s (48.0x, 2.7%) ca: 2.7s (89.7x, -1.5%) he: 2.1s (70.0x, -0.5%) ca: 0.9s (31.0x, 1.1%) dr: 1.4s (46.7x, 0.7%) ma: 1.6s (52.7x, -0.6%) -- sarp -- sarp valgrind-new:0.03s no: 0.3s ( 9.7x, -----) me: 2.1s (71.0x, -----) ca: 1.7s (57.7x, -----) he: 5.9s (197.3x, -----) ca: 1.0s (32.7x, -----) dr: 0.9s (31.0x, -----) ma: 0.3s (10.3x, -----) sarp valgrind-old:0.03s no: 0.3s ( 9.3x, 3.4%) me: 2.1s (70.7x, 0.5%) ca: 1.8s (58.7x, -1.7%) he: 5.9s (196.3x, 0.5%) ca: 0.9s (30.7x, 6.1%) dr: 0.9s (31.0x, 0.0%) ma: 0.3s (10.3x, 0.0%) -- tinycc -- tinycc valgrind-new:0.16s no: 1.4s ( 8.8x, -----) me: 8.6s (54.0x, -----) ca:11.8s (73.4x, -----) he: 9.6s (60.1x, -----) ca: 8.8s (54.7x, -----) dr: 9.2s (57.5x, -----) ma: 2.5s (15.3x, -----) tinycc valgrind-old:0.16s no: 1.5s ( 9.3x, -6.4%) me: 8.3s (52.1x, 3.5%) ca:12.5s (78.2x, -6.5%) he:10.5s (65.4x, -8.8%) ca: 7.8s (48.8x, 10.9%) dr: 8.1s (50.8x, 11.6%) ma: 2.5s (15.5x, -1.2%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 35m35.586s user 34m19.167s sys 0m25.098s |